CYPRESS SEMICONDUCTOR PSoC Creator 213: Multi-Byte Datapath Components PSoC Creator 213: Multi-Byte Datapath Components Cypress Blogs • Latest posts: www.cypress.com/go/blogs • PSoC Sensei: www.cypress.com/go/psocsensei Online Training • http://www.cypress.com/go/training www.cypress.com/go/psoc3 www.cypress.com/go/psoc5 Chip Documentation • Datasheets and Technical Reference Manuals • Available on the web: Help->Documentation->Component Author Guide Software Documentation • From within PSoC Creator select: Various aspects of component development are documented in the following locations Component Development Documentation 2 PSoC Creator 213: Multi-Byte Datapath Components PSoC Development Kit (CY8CKIT-001) is used for all examples Shown using the PSoC 3 processor module All examples can also use the PSoC 5 processor module Many of the examples could also be run on: • PSoC 3 FirstTouch Starter Kit (CY8CKIT-003) • PSoC 5 FirstTouch Starter Kit (CY8CKIT-014) Development Kit wired as follows: P0_2 – SW1 P0_3 – SW2 P0_4 – LED1 P0_5 – LED2 P0_6 – LED3 P0_7 – LED4 Development Kit Setup for Examples 3 PSoC Creator 213: Multi-Byte Datapath Components For each datapath element in the instance there is a separate set of configuration parameters Labeled with _a for the LSB, _b for the next, … The datapath configuration tool will show the configuration for each separately Usually each byte configuration will be similar • The dynamic configuration will rarely be different cy_psoc3_dp8: 8-bits cy_psoc3_dp16: 16-bits cy_psoc3_dp24: 24-bits cy_psoc3_dp32: 32-bits Datapath elements in the UDBs are designed to be chained together to form 8, 16, 24 and 32 bit datapaths Various width datapaths are instanced using the following Verilog modules: Multi-Byte Datapath Elements 4 PSoC Creator 213: Multi-Byte Datapath Components Typically the signals from either the first of last datapath in the chain will be connected outside the component Multi-byte datapath modules make available the control signals and status outputs for each of the datapaths in the module PSoC Creator will place multi-byte datapaths so that this chaining is available Multi-byte datapath modules automatically chain the 8-bit datapaths together The PSoC hardware supports dedicated paths for this chaining to provide single cycle chained operation Multi-Byte Datapath Connectivity 5 PSoC Creator 213: Multi-Byte Datapath Components For Right Shift and CMSB (CRC and Pseudo Random generation) operations Enable chaining in all datapaths except for the MSB Use the output from the LSB For all others Enable chaining in all datapaths except for the LSB Use the output from the MSB Chaining Architecture 6 PSoC Creator 213: Multi-Byte Datapath Components The Datapath Configuration Tool has copy and paste capability to make configuring Multi-Byte datapaths easier Typical Configuration Flow Configure the LSB datapath Copy and Paste that configuration to all other datapaths in the chain Modify the static chaining configuration appropriately Updating the dynamic configuration if it changes Update the dynamic configuration in one datapath Copy that updated datapath Paste just the dynamic portion to all other bytes in the chain Configuring Multi-Byte Datapaths 7 CRC Comparison Arithmetic Shift PSoC Creator 213: Multi-Byte Datapath Components Datapath Chaining Configuration 8 LSB configured the same as a single byte DP All others CHAIN MSB configured the same as a single byte DP All others CHAIN PSoC Creator 213: Multi-Byte Datapath Components CRC Chain (CHAIN CMSB / CHAIN FB) CRC functionality not covered here Comparison Chain (CHAIN 0 / 1) LSB no chaining (NOCHN) All others chain (CHNED) • • Right Shifting • • Shift In Select (SI SELA / B) Left Shifting Carry In Select (CI SELA / B) LSB configured the same as a single byte DP All others CHAIN Chained Configuration 9 PSoC Creator 213: Multi-Byte Datapath Components 1 input: clock 1 output: pwm (glitch-free) CPU controllable enable Implement using: • Two Chained Datapaths • Single Control register • Verilog logic 16-bit One Output PWM Walkthrough Example 10 DP ce1 cl0_reg cs_addr[0] Disable A0<D0 (D1+1) A0==D1 D0 Config 000 001 010 011 Disable A D1 D0 A1 A0 Count A+1 D1 D0 A1 A0 Reset A^B D1 D0 A1 A0 Description Control register disabled Control register disabled Increment counter Clear counter • Config[0] = (A0 == D1) • Config[1] = Ctrl[0] Name Disable Disable Count Reset PSoC Creator 213: Multi-Byte Datapath Components pwm • “Period” is the upper count of the PWM counter • Counter counts from 0 to Period for a clock period of (D1 + 1) Register Usage A0 Counter D0 Limit (Low pulse width) D1 Period PWM Design 11