DC1586A - Schematic

1
2
3
4
5
6
7
8
REVISION HISTORY
INTVCC
ECO
VIN
REV
2
R2
20.0K
1%
JP2
1
2
3
4
JP1
MODE
PS
R1
OPT
RUN1
1
2
3
ON
BM
OFF
INTVCC
C1
OPT
DATE
JIAN L.
4-13-10
JP3
R3
OPT
90 DEG
60 DEG
R4
10K
A
A
E1
R5
0
CLKOUT
VIN
R9
127K
1%
R8
10
E3
1
R7
10
VIN
C3
1nF
S1-
S1+
ITEMP1
R29
0
31
R32
OPT
R33
10
VOUT1
COUT2
10uF
6.3V
6
7
4
BG1
R19
2.2
Q1A
Si4816BDY
VIN
25
E6
+ COUT5
OPT.
VOUT1
3.3V /
5A
C8
1uF
6.3V
E7
EXTVCC
23
C13
1uF
35V
C14
4.7uF
10V
22
21
VIN
BG2
R24
0
TG2
D2
CMDSH-3
INTVCC
CIN3
4.7uF
50V
R26
OPT
C17
0.1uF
1
TG2
Q2B
Si4816BDY
L2
2.2uH
R28
OPT
RS2
0.005
1206
VOUT2
TDK RLF7030-2R2M
COUT4
10uF
6.3V
R30
OPT
INTVCC
4
+ COUT3
220uF
4V
E9
+ COUT6
OPT.
VOUT2
2.5V /
5A
C19
1uF
6.3V
Q2A
Si4816BDY
E10
GND
2
3
C
R37
10
INTVCC
R38
10
E13
DIFFP
R41
100K
1%
OPTIONAL JUMPERS FOR
SINGLE OUTPUT / DUAL PHASE
OPERATION
VIN
TEMPERATURE COMPENSATION NETWORK FOR DCR SENSING
R43
OPT
ITEMP1
R44
OPT
ITH1
R40
OPT
ITEMP2
Q3A
OPT
FDS698SAS
ITH2
R45
OPT
D
C22
OPT
R46
OPT
C23
OPT
TG1
R48
OPT
1
R51
OPT
RN2
OPT
3
Q3B
OPT
R49
OPT
Q4B
OPT
FDS698SAS
BG1
RUN2
CIN5
OPT
CUSTOMER NOTICE
4
SW2
2
BG2
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
1
2
3
4
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HZ
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
JIAN LI
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
FDS698SAS
1
RUN1
RN1
OPT
1
TRK/SS2
TG2
7
8
R50
OPT
TRK/SS1
2
SW1
2
VFB2
Q4A
OPT
FDS698SAS
4
R47
OPT
VFB1
VIN
CIN4
OPT
5
6
PGOOD2
3
PGOOD1
E16
INTVCC
7
8
E15
ILIM1
1
PGOOD2
VO2_SNS+
R39
OPT
5
6
PGOOD1
VO2_SNS-
E14
R42
100K
1%
B
GND
INTVCC
24
E11
E12
GND
2
3
26
C21
1uF
GND
+ COUT1
220uF
4V
S1-
27
R36
OPT
EXTVCC
E4
28
ILIM2
R34
10
VIN
4.5V 25V
RS1
0.005
R16
OPT
5
INTVCC
8
32
CLKOUT
SW1
33
34
FREQ
PHSASMD
35
36
38
39
37
ITEMP2
ITEMP1
MODE/PLLIN
29
R35
OPT
R31
OPT
R13
OPT
TDK RLF7030-2R2M
RUN2
C20
OPT
L1
2.2uH
1206
D1
CMDSH-3
SW2
1
2
3
EXTVCC
BOOST2
R17
0
5
ON
R25
63.4K
1%
Q1B
Si4816BDY
6
7
R27
OPT
JP4
RUN2
OFF
SGND
VIN
C18
OPT
PGND2
DIFFP
41
C16
0.1uF
BG2
SENSE2-
SW2
R23
OPT
40
SENSE2+
10
E8
EXTVCC
30
20
9
TK/SS2
NC
8
S2-
INTVCC
19
S2+
VIN
ITH2
PGOOD2
C15
1nF
VFB2
18
TRK/SS2
7
17
6
PGOOD1
R22
0
ITH2
16
R20
OPT
C12
OPT
C11
1500pF
5
BG1
ILIM2
R21
23.2K
1%
VFB2
PGND1
15
C10
150pF
BOOST1
SGND
1
C4
0.1uF
TG1
TG1
VFB1
4
R18
20.0K
ILIM1
3
B
14
VFB1
ITH1
RUN2
2
13
ITH1
TK/SS1
RUN1
1
TRK/SS1
C9
OPT
VOUT1
SENSE1-
C7
68pF
SENSE1+
R14
29.4K
1%
R15
20.0K
DIFFOUT
C6
1nF
DIFFN
C5
0.1uF
U1
LTC3855EUJ
12
R12
OPT
TRK/SS2
R11
OPT
SW1
E5
11
TRK/SS1
CIN2
4.7uF
50V
8
ITEMP2
R10
0
CIN1
+ 22uF
35V
2
R6
91K
S1+
C2
OPT
S2+
E2
CLKOUT
S2-
PLLIN
C
APPROVED
PHASMD
120 DEG
1
2
3
4
RUN1
FCM
DESCRIPTION
PRODUCTION
5
6
TECHNOLOGY
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
TITLE: SCHEMATIC
DUAL OUTPUT SYNCHRONOUS BUCK CONVERTER
SIZE
IC NO.
A
DATE:
Tuesday, January 17, 2012
7
REV
LTC3855EUJ
DEMO CIRCUIT 1586A
2
SHEET
8
1 OF 1
D
A
B
C
D
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