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Synchronous
y
SRAMs
What is an Synchronous SRAM?
Address
Reg
Control
Clock
15
Async SRAM
Data In/Out
Register
•
•
A Register is an element which is capable of storing binary data.
A clock is a stream of p
positive and negative
g
p
pulses occurring
g at regular
g
intervals.
Positive pulse is always preceded or succeeded by a negative pulse.
•
A register can be activated only at the edges of the clock.
Data Out
Data In
Clock
Rising
Positive
d
pulse
Negative edge
pulse
Register
g
Data In
clock
Data Out
• A combinatorial signal doesn’t pass through registers.
registers
• A combinatorial logic responds to any change in the inputs.
inputs It is not
controlled byy a clock.
16
Falling
edge
d
Sync.
y
SRAM Overview
Sync SRAM
Std Sync
Std.
NoBL,
NoBL
ZBT
FT
FT
PL(SCD)
PL(DCD)
PL(DCD)
QDR
DDR
QDR
B2
DDR
B2
QDR
B4
DDR
B4
QDR-II &
II+ B2
DDR-II &
II+ B2
QDR-II
& II+B4
DDR-II
&II+ B4
DDR
DDRII&II+
SIO (B2)
17
Sync. SRAM Overview
•Each Family has numerous options as well:
Density & Organization
•Density
•
•
1 Mb – 72 Mb
X18, X36 (X8, X9, X32, X72)
• Speed Grades
•
400MHz,300MHz,250MHz, 167MHz, …etc.
• Timing Options-> eg Read Latency
•
1 5cycle 2cycles
1.5cycle,
2cycles, 2
2.5cycles
5cycles
• Burst Options
•
Interleaved, Linear,Burst 2,Burst4
• Core
C
V
Voltage
lt
•
•
3.3V, 2.5V, 1.8V
• I/O Voltage
g
•
•
18
LVTTL: 3.3V, 2.5V, 1.8V,1.5V
HSTL, Variable impedance
Sync. SRAM Overview
•Each Family has even more options:
• Packages
•
100 TQFP, 165 fBGA, 119 BGA, 209 BGA
• Temperature
p
Ranges
g
•
Commercial, Industrial,Automotive
• Chip Enables
•
•
2 CE vs 3 CE options
Address Locations
• JTAG
•
With EXTEST,
EXTEST No EXTEST
• Names
•
•
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NoBL = ZBT = NtRAM = ZBL = ZERO SB = Etc.
QDR SigmaRAM
QDR,
Sync SRAM Family
Sync SRAMs
Standard Sync
NoBL
QDR/QDRII/QDRII+
• Standard Sync SRAMs
• NoBL SRAMs
• QDR /QDR II/QDRII+
• DDR /DDR
/
II/DDRII+
/
20
DDR/DDRII/DDRII+
Standard Sync SRAM
Sync SRAMs
Standard Sync
Flowthrough
Pipelined
SCD
21
NoBL
DCD
QDR/QDRII/QDRII+ DDR/DDRII/DDRII+
Synchronous SRAM
Standard Sync SRAM
•Sync SRAM = Async SRAM + (Clock + Registers)
•Common I/O
•Offered in both Pipeline
p
and Flowthrough
g
•Single cycle deselect SCD ( Flowthrough and Pipeline)
•Double Cycle Deselect DCD ( Pipeline Only!)
•Best for either dominated Reads or Writes
22
Flowthrough Timing Diagram
OE#
Address
Write
Reg.
Memory
Core
I/O
Logic
Control
Add. Decod
de
•
Clk
Flowthrough SRAM = Sync SRAM with only a register on I/P
Read
Write
Clock
Add
Address
W2
R1
WE#
Data
23
OUT1
IN2
Pipelined Timing Diagram
OE#
Logic
Control
Memory
Core
Outtput Reg.
•
Add. Decode
e
Address
Write
Reg.
I/O
Clk
Pipelined SRAM = Flowthrough SRAM + Output register
Read
Write
Clock
Address
W3
R1
WE#
Data
Data is pushed out one cycle due to the
output register
24
OUT1
IN3
SCD v/s DCD
• SCD – Single
Single--Cycle Deselect
• One clock cycle until chip deselects
• Available in Pipelined and Flowthrough
• DCD – Double
Double--Cycle Deselect
• Two clock cycles until chip deselects
• Available in Pipelined only
Clock
Chip
Chi D
Deselected
l t d
CE#
I/O Disabled within one clock
cycle after deselect
SCD Data
OUT1
OUT2
OUT3
DCD Data
OUT1
OUT2
OUT3
OUT4
I/O Disabled within two clock
cycle after deselect
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Flowthrough vs. Pipeline
• Pipeline operates at higher frequency than Flowthrough
• Flowthrough is used where the initial latency is a critical
issue and a Pipeline SRAM is used where the speed is a
critical issue.
• Write operations can take a single clock ccycle
cle to complete
for both Flowthrough and Pipeline.
• Read operations
p
take 2 clock cycles
y
in flowthrough
g and 3
clock cycles in Pipeline.
• In networking applications where read/write is balanced
(Ratio ~1)
~1), both pipeline and flowthrough SRAMs are not
as efficient.
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NoBL™ SRAMs
Sync SRAMs
Std Sync
Pipelined
NoBL
QDR/QDRII/QDRII+ DDR/DDRII/DDRII+
Flowthough
No Bus Latency (NoBLTM)
•Also Known as ZBTTM
•No dead cycles between reads and writes
•Optimized
O ti i d for
f 50% reads
d and
d 50% writes
it
•Best for Networking Applications
•Offered in both Pipelined and Flowthrough modes
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NoBL™ SRAMs
No Operation. (Dead Cycles!)
Standard Pipelined SRAM
Write A
Now a write is possible here
Read B
Write C
Clock
D I/O
Data
A
B
C
NoBL Pipelined SRAM = Read and Write on Every Cycle!
Write A
Read B
Write C
Read
Write
Clock
Data I/O
28
A
B
C
What is NOBL ?
NoBL SRAMs = Stand Sync SRAMs(FL or PL) + NoBL logic
/OE
/OE
NoBL
“Flow Through”
29
Control
Memory
Core
NoBL
L
Logicc
NoB
BL
Logic
Clk
I/O
Write
Reg.
Clk
NoBL
N
BL
“Pipeline”
O
Output
Reg.
Memory
Core
Address
Add. Deco
ode
Add. Deccode
Write
Reg.
I/O
Flowthrough NoBL Operation
No Dead Cycles between Reads and Writes
Clock
Write
Read
A
B
Write
Read
Write
D
E
/WE
/CE
/CE
Address
F/T Data I/O
A
Data in
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C
B
Data out
C
Data in
D
Data out
Pipelined NoBL Operation
Clock
Write
i
Readd
A
B
Wi
Write
Read
Wi
Write
D
E
/WE
/CE
Address
C
Data in
P/L Data I/O
A
Data in
31
B
Data out
C
Data in
D
Data out
Standard Sync Vs NoBL
•STANDARD SYNC
• MOST EFFECTIVE FOR BURST
READS OR WRITES FOR L2 CACHE
• IDEAL FOR NETWORK APPLICATIONS
• IDEAL FOR DOMINANT READ OR
WRITE
• ENABLES FASTER MEMORY
PERFORMANCE - ELIMINATES THE
LATENCY CYCLE
• LATENCY OCCURS WHEN
SWITCHING FROM WRITE TO READ
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•NOBL
NOBL
• IDEAL FOR READ/WRITE RATIO OF 1
• 2X BANDWIDTH IN HEAVY READ / WRITE
APPLICATIONS
QDR
Sync SRAMs
Std Sync
NoBL
QDR/QDRII/QDRII+ DDR/DDRII/DDRII+
QDR I
QDR II/II+
QDR = Quad Data Rate
•Joint effort between Cypress and Other Industry Leaders
•Optimum for balanced Read/ Write Applications
•Separate Input and Output Ports = No bus contention
•Double Data Rate on Separate Ports = 4X Bandwidth
•HSTL(High Speed Transceiver Logic) I/O Levels
•Programmable output Impedance using ZQ pin
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QDRI Burst of 2
BLOCK DIAGRAM
•2 Word Burst QDR SRAM
•Separate Read and Write control signals
•Vref signal due to HSTL I/O
34
QDRI Burst of 2
Read Operation
Read
Read
Read
K
/K
/WPS
/RPS
Add.
Data Out
C
/C
35
A
B
C
E
D
Q(A)
Q(A)+1
F
Q(C)
G
H
Q(C)+1
Q(E)
QDRI Burst of 2
Write Operation
Write
Address B
Write
Address D
Write
Address F
K
/K
/WPS
/RPS
B
Add.
Data In
C
/C
36
D(B)
D(B)+1
D
D(D)
D(D)+1
F
D(F)
D(F)+1
H
D(H)
D(H)+1
QDRI Burst of 4
BLOCK DIAGRAM
•4 Word Burst QDR SRAM
•Burst of 2 and 4 are two different parts
Data Flows in one direction
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QDRI Burst of 4
p
Read Operation
Read
Read
K
/K
/WPS
/RPS
Add.
Data Out
C
/C
38
A
B
C
Q(A)
Q(A)+1
D
Q(A)+2 Q(A)+3 Q(C)
QDRI Burst of 4
p
Write Operation
Write
Address B
K
/K
/WPS
/RPS
Add.
Data In
C
/C
39
A
B
D
C
D(B)
D(B)+1
D(B)+2 D(B)+3
QDR Advantages
• 4x Network Performance
•
Features
• * Simultaneous Accesses
Bandwidth(~2x)
Benefits
* Improved
• * DDR Interface on Both Ports
Bandwidth(~2x)
(
)
• * Pipeline Output
* Low Initial Latency
p
Input/Output
p
p Ports
• * Separate
Contention
40
• * 165 FBGA Package
* Improved
* No Bus
* Reduced Board Area
QDR to QDR-II Transition
Address
D
Q
/RPS
/WPS
DLL
CQ
Q
CQb
/BWS
B
Benefits
fit
K Kb
41
Doff C Cb
•Provides Echo Clock
•Allows higher speed operation
QDR-II Features
• QDR II Purpose:
• Extend QDR Solution to 250MHz (From 166MHz)
• QDR
QDR--II Has Internal DLL (Delay Lock Loop)
• Shorten ClockClock-Valid,
Valid Lengthen Data Hold
• Source Synchronous Clocks (Echo Clock) Added
• Echo Clock Outputs From SRAM
• Guaranteed Relationship to Valid Data
• Additional 1/2 Clock of Latency
42
QDR-II Block Diagram
Data Flows in one direction
43
QDRII Burst of 2
Operation
•
Read/Write Access
Read
Write
Read Write
Read Write
K
/K
/WPS
/RPS
Address
DataIn (D)
DataOut (Q)
A
B
D(B)
D(B+1)
C
D(D)
D
D(D+1)
E
F
D(F)
D(F+1)
Q(A)
C
/C
Extra ½ cycle of latency
44
Q(A+1)
G
D(G)
Q(C)
D(G+1)
Q(C+1)
Q(E)
Q(E+1)
QDRII Burst of 4
p
Operation
•
Read/Write Access
Read
R d
W it
Write
A
B
Read
R d
W it
Write
C
D
K
/K
/WPS
/RPS
Address
DataIn (D)
D(B)
D(B+1)
D(B+2)
D(B+3)
D(D)
D(D+1)
D(D+2)
D(D+3)
DataOut (Q)
Q(A)
Q(A+1)
Q(A+2)
Q(A+3)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
C
/C
45
QDR-II Advantages
The 2nd Generation
Features
46
Benefits
* 300Mhz Fmax
* Higher
g
Bandwidth
* 1.5 Clock cycle Pipeline
* Low Initial Latency
* 18Mb / 36Mb / 72Mb
* Higher Density
* Echo clocks
* SourceSource-Sync. Output Data
* DLL
* Faster Data Capture
* 1.8V Power Supply
* Lower Power
* Same 165FBGA Package
* Compatibility
QDR vs QDR-II
Summary of Differences
QDR
QDR-II
Maximum Frequency
Burst of 2: 167MHz
Burst of 4: 200 MHz
Burst of 2: 167 MHz
Burst of 4: 300 MHz
Frequency
q
y Minimum
(DLL Constraint)
N/A
100 MHz
MH
Data Valid Window
1.4ns @ 167MHz
1.9ns @ 167MHz
1.4ns @ 250MHz
Initial Latency
1 clock cycles*
1.5 clock cycles*
Echo Clocks
No echo clocks
Echo clocks
Density
9Mb / 18Mb / 36Mb
18Mb / 36Mb / 72Mb+
Power Supply
2.5V
1.8V
* By adding an ½ clock cycle of latency to QDR-II, the access time is reduced to 0.45ns from QDR’s 2.5 ns.
47
DDR
Sync SRAMs
Std Sync
NoBL
QDR/QDRII/QDRII+
DDR I
DDR/DDRII/DDRII+
DDR II/II+
DDR II/II+ SIO
DDR = “Double Data Rate”
•Shared Input and Output Buses
•Optimized for Dominant Reads OR Writes
•Double Data Rate Interface
•Commonly referred to as “Networking” DDR and DDR
DDR--II
•Data transferred on both edges of the clock
•Two
T and
d Four
F
Word
W d Burst
B t Devices
D i
48
QDR vs. DDR
Address
D
RPS
WPS
Q
QDR
DDR Characteristics
•Double Data Rate
•Common I/O
BW
K
Kb
C
Cb
QDR Characteristics
•Double Data Rate
•Simultaneous R/W Access
possible
•Separate
p
Input
p and Output
p ports
p
Address
D/Q
DDR
CE
R/W
BW
K
49
Kb
C
Cb
DDR Block Diagram
Input Data
Register
R
Register
R
Address Decode /
Control Logic
Address/
Control
Memory Array
Output Data
Clock
NOP – “No Opp” Cycle – to
prevent bus contention
Write
Read
Clock
Address
Data
50
W2
R1
OUT1
OUT2
OUT3
OUT4
IN1
DDR II
• •Changes
from DDR
• Internal DLL
• Higher clock frequency
• Latency increased by half a cycle
• Increase Data Valid Window
Write
Read
Clock
Address
W2
R1
Data
OUT1
OU
Latency increase
by half cycle
51
OUT2
OUT3
OUT4
IN1
DDR-II Block Diagram
Input Data
Reegister
Memory Array
Input Clock
Internal DLL
52
Regiister
Address D
Add
Decode
d /
Control Logic
Address/
Control
Output Data
Output Clock
DDR & DDR-II
2 Reads OR 2 Writes / Clock Cycle = DDR & DDR-II
I/O Bus is the Only Major Difference From QDR & QDR-II
Feature
Benefit
DDR Interfaces
Higher Mb/s
DDR: 200MHz
DDR II 300MH
DDR-II:
300MHz
Higher
g
Mb/s
Count
Shared I/O bus
((DDR & DDR-II CIO))
Reduces ball count
Bus Contention
Split I/O buses
(DDR-II SIO)
Eliminates bus
contention
(B2 @ > 200MHz)
200MH )
Single address per
clock cycle
Reduced address rate
relative to QDR
Bandwidth
Package Pin/Ball
53
DDR II SIO
Re
egister
Input Data
Memory Array
Input Clock
Internal DLL
54
Register
Address D
Add
Decode
d /
Control Logic
Address/
Control
Output Data
Output Clock
DDR II SIO
•DDR-Separate I/O (SIO)
• • Separate Input and Output Buses
• Only
O l O
One Operation
O
ti Per
P Clock
Cl k
• Can Not Perform Data Forwarding Feature
•Eliminates Bus Contention
•Two
T
Word
W d Burst
B
Only
O l
Read
Write
Clock
Address
55
R1
W2
Write
Port
IN1
Read
Data
OUT1
IN2
OUT2
QDR & DDR SRAM
Architectures
• QDRTM / QDRIITM
• Separate Input and Output Buses
• Double Data Rate Interface on Both Buses
• 4X Increase in Bandwidth From NoBLTM
• DDRTM / DDRIITM
• Single I/O Bus
• Double Data Rate Interface
• 2X Increase in Bandwidth, Reduces ASIC/FPGA Pin Count
• DDRII Separate I/O
• Operates like a QDRIIQDRII-burst of 2 device with access on only
one port per clock cycle
• Separate Input and Output Buses
• Double Data Rate Interface on Both Buses
• 2X Increase in Bandwidth From NoBLTM
56
QDR - DDR Summary
• QDR and QDRII are optimized for systems with Balanced
READ and WRITE operations
• Packet memory
• Linked-list
• Lookup
Look p Table
• Statistics Storage
• DDR and DDRII are optimized for data streaming operations
or READ/WRITE unbalanced systems
• L2 Cache
• Microprocessor,
c op ocesso , network
et o p
processor,
ocesso , DSP
S memory
e oy
• DDR Separate I/O optimized for 1 address/clock 2-word burst
systems
• Minimized
Mi i i d b
bus llatency,
t
maximized
i i d ffrequency
57
QDRII+/DDRII+ Overview
What is it?
• Latest QDR Consortium Defined QDR SRAM
Why do you care?
• Frequency Support up to 500MHz
• S
Simplify
p y Board
oa d Design
es g
What are the Main Differences to QDRII?
• Read Latency of 2.0 Offered for Latency Critical Applications
• Read
R dL
Latency
t
off 2
2.5
5 Off
Offered
d ffor F
Frequency C
Critical
iti l A
Applications
li ti
• Data Valid Pin
What Densities? Speeds?
• 18M, 36M, 72M, 144M
•
Maximum CY Frequency
Technology
58
2.0 Cycle Latency
2.5 Cycle Latency
90-nm
375MHz
400MHz
65-nm
400MHz
500MHz
QDRII+/DDRII+ Overview
QDRII+/DDRII+ Differences to QDRII/DDRII
QDR II / DDRII
Frequency (DLL ON) 119MHz~333MHz
QDRII+ / DDRII+
300MHz~500MHz
Organization
VDD
VDDQ
Read Latency
x9, x18, x36
1.8V +/-0.1V
1.5V +/-0.1V
2.0 & 2.5 clocks
x8, x9, x18, x36
1.8V +/-0.1V
1.8V+/-0.1V or 1.5V+/-0.1V
1.5 clocks
Input Clocks
Single Ended (K,K#)
Output Clocks(C,C#) Yes
Single Ended (K,K#)
No
A0 ((DDR B2))
Echo Clock Number
No
1 Pair
Yes
1 Pair
PKG
165 ball FBGA
Individual Byte Write Yes
(BWa#,BWb#)
QVLD
No
59
Remark
QDRII+ read latency is not user
selectable. Offered as two different
selectable
devices.
Echo Clocks are Single Ended.
165 ball FBGA
Yes
Yes
Edge Aligned with Echo Clocks
Guide to Support QDRII/DDRII &
QDRII+/DDRII+
QDR & DDR Pinout
• P6 – Design to use as C Clock or QVLD
• R6 – Design
D i tto use as C# Cl
Clock
k or N
No C
Connectt
DDR B2 Specific Pinout
• Design Controller to Always Start the Access/Burst with A0 = 0
• A0 Becomes a No Connect with DDRII+
I/O Voltage
• Use 1.5V HSTL I/O
Host Design
• Design to Support 1.5, 2.0 and 2.5 Cycles for Read Latencies
• Write Latency Remains 1.0 Cycle for QDRII & QDRII+
• Recommend to use Echo Clocks to Latch Read Data
Board Design
• Design to Take Advantage of QValid Output
• Analyze Timing up to 400MHz
60
QDRII+ (x18) Pinout Differences
QDRII - B4
QDRII+ - B4
61
DDRII+ (x18) Pinout Differences
DDRII - B2
DDRII+ - B2
62
Architecture Comparison
*
Parameter
Std. Sync
NoBLTM,
DDR / DDRII/DDRII+
QDRTM / QDRTM-II/
QDRTM-II+
D t Rate
Data
R t
Si l
Single
Si l
Single
D bl
Double
D bl
Double
Data Bus
Common I/O
Common I/O
Common I/O* &
Separate I/O**
Separate I/O
Data Bus
Utilization
NOP between
reads & writes
100%***
NOP between
reads* / 50% of
Separate I/Os**
100% reading &
100% writing
VDD
3.3V / 2.5V
3.3V / 2.5V
2.5V / 1.8V
2.5V / 1.8V
VDDQ
LVTTL
3.3V / 2.5V
LVTTL
3.3V / 2.5V / 1.8V
HSTL
(1.5V / 1.8V)
HSTL
(1.5V / 1.8V)
Clock
q
y
Frequency
250 MHz
250 MHz
200 MHz /
300 MHz/400MHz
200 MHz /
300 MHz/400MHz
DDR & DDR-II CIO have a common bus and require 1-2 NOP(s) between reads and writes.
** DDR-II SIO has separate input and output buses. Because only one bus can be used at a time, bus
utilization is exactlyy 50%.
*** Applies to clock frequency < 166 MHz. Clock frequencies above this typically requires an NOP.
63
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