User's Guide SLVU551I – October 2011 – Revised September 2014 Powering the AM335x with the TPS65217x This User’s Guide is a reference for connectivity between the TPS65217 power management IC and the AM335x processor. For detailed information about TPS65217 and AM335x, see the respective data sheets. 1 TPS65217 Overview The TPS65217 is an optimized and highly integrated power management solution for the AM335x processor. Features of the TPS65217 include: • Power path management for Lithium-ion battery, USB, and AC inputs • Linear Battery Charger • 3 DC/DC Step-Down Converters • 2 LDOs • 2 Load Switches (configure as LDOs) • White LED driver capable of driving up to 20 LEDs There are four versions of the TPS65217: TPS65217A is used for the AM335x processor in the ZCE package. In this package, the VDD_MPU and VDD_CORE nodes are shorted together and will only use a single power rail. TPS65217B is used for the AM335x processor in the ZCZ package. In this package, the VDD_MPU and VDD_CORE rails are separate and can use separate power rails. TPS65217C is also targeted at the AM335x processor in the ZCZ package, but the DCDC1 output voltage is set to 1.5 V to supply DDR3 memory. This version does not support AM335x RTC-only operation. TPS65217D is identical to TPS65217C, except DCDC1 is set to 1.35 V to support DDR3L. PMIC Processor Memory TPS65217A AM335xZCE DDR2 DDR2 TPS65217B AM335xZCZ TPS65217C AM335xZCZ DDR3 TPS65217D AM335xZCZ DDR3L All trademarks are the property of their respective owners. SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Powering the AM335x with the TPS65217x Copyright © 2011–2014, Texas Instruments Incorporated 1 Connection Diagram for TPS65217A and AM335x 2 www.ti.com Connection Diagram for TPS65217A and AM335x The block diagram shown in Figure 1 illustrates the connections between TPS65217A and AM335x. Power rails as well as the digital and analog signals are shown. The power rails may be used to power additional parts of the system (DCDC1 powers DDR2 memory). AC SYS from AC connector To system load 4.7µF USB BAT Single cell Li+ Battery Power Path and Charger from USB connector 4.7µF VDDS_PLL_MPU VDDS_PLL_CORE_LCD VDDS_SRAM_MPU_BB INT_LDO 100nF BYPASS BAT_SENSE 10µF TS 75k VDDS_SRAM_CORE_BG VDDA1P8V_USB0 VDDS_DDR 10k NTC VDDS 10µF L1 VIN_DCDC1 VDDS_OSC VDDS_PLL_DDR 22µF DCDC1 VDDSHVx(1.8) (1.8V) VDCDC1 VDDA_ADC 10µF DDR2 10µF L2 VIN_DCDC2 DCDC2 (3.3V) VDCDC2 VDDSHVx(3.3) 10µF VDDA3P3V_USB0 10µF SYS L3 VIN_DCDC3 DCDC3 (1.1V) VDCDC3 VDD_CORE 10µF VDD_MPU 10µF VIN_LDO VLDO1 LDO1 (1.8V) VDDS_RTC 2.2uF 4.7µF AGND VLDO2 LDO2 (3.3V) 2.2uF PGND LS1_IN LS1_OUT LS1/LDO3 SYS or VDCDCx 10uF LS2_IN LS2_OUT LS2/LDO4 SYS or VDCDCx 10uF MUX_IN (0..3.3V) VBAT VSYS VICHARGE VTS Any system power needs Any system power needs MUX_OUT AIN4 MUX 100nF Any system voltage Always-on supply Always-on supply 100k 100k PB_IN nRESET 4.7k VDDSHV6 4.7k VDDSHV6 No Connect SCL VIO VLDO1 Any system power needs I2C0_SCL SDA 18uH L4 I2C0_SDA PWR_EN PMIC_PWR_EN SYS PGOOD FB_WLED PWRONRSTN LDO_PGOOD 4.7µF WLED Driver 10k VDDSHV6 100k VLDO1 RTC_PWRONRSTN nINT EXTINTn nWAKEUP ISINK1 EXT_WAKEUP ISINK2 ISET1 ISET2 Power Pad (TM) TPS65217A AM335x Figure 1. Connection Diagram for TPS65217A and AM335x 2 Powering the AM335x with the TPS65217x SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Power Rails for TPS65217A and AM335x www.ti.com 3 Power Rails for TPS65217A and AM335x Table 1 matches the AM335x power terminals with the appropriate power rail from the TPS65217A. Table 1. Power Rails for TPS65217A and AM335x TPS65217A Voltage (V) AM335x VDDS_DDR VDDS VDDSHVx(1.8 V) VDDS_SRAM_CORE_BG VDDS_SRAM_MPU_BB DCDC1 1.8 VDD_PLL_DDR VDDS_PLL_CORE_LCD VDDS_PLL_MPU VDDS_OSC VDDA1P8V_USB0/1 VDDA_ADC VDDSHVx(3.3 V) DCDC2 3.3 DCDC3 Defaults to 1.1 V. Controlled by I2C. LDO1 1.8 VDDS_RTC VDDA3P3V_USB0/1 VDD_CORE VDD_MPU LDO2 3.3 n/a LDO3/LS1 Load Switch n/a LDO4/LS2 Load Switch n/a Each output voltage may be changed dynamically while the TPS65217 is in active mode. This requires use of I2C commands to the TPS65217. SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Powering the AM335x with the TPS65217x Copyright © 2011–2014, Texas Instruments Incorporated 3 Power-Up Sequence for TPS65217A 4 www.ti.com Power-Up Sequence for TPS65217A Figure 2 and Table 2 describe the power-up sequence of the TPS65217A. This sequence is optimized specifically for the AM335x processor. NOTE: The power-down sequence follows the reverse of the power-up sequence. STROBE 15 STROBE 1 STROBE 2 DLY 1 5ms STROBE 3 DLY 2 1ms STROBE 4 DLY 3 1ms VSYS WAKEUP (1) PWR_EN (DG) (2) (3) LDO1 LDO2 DCDC1 DCDC2 DCDC3 LS1 LS2 PGDLY 20 ms PGOOD (1) Wakeup↓ events are PB_IN↓ or AC↑ or USB↑ (2) DG = Deglitched (3) LDO1 turns on as soon as VSYS is present LDO_PGOOD↑ 20 ms after LDO1↑ Figure 2. Power-Up Sequence Timing Diagram, TPS65217A Table 2. TPS65217A, Power-Up Sequence STROBE 15 STROBE 1 STROBE 2 4 LDO1 DCDC1 LS1 DCDC2 LDO2 STROBE 3 DCDC3 STROBE 4 LS2 Powering the AM335x with the TPS65217x SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Connections Diagram for TPS65217B and AM335x www.ti.com 5 Connections Diagram for TPS65217B and AM335x The block diagram shown in Figure 3 illustrates the connections between TPS65217B and AM335x. Power rails as well as the digital and analog signals are shown. The power rails may be used to power additional parts of the system (DCDC1 powers DDR2 memory). AC SYS USB BAT from AC connector To system load 4.7µF Single cell Li+ Battery Power Path and Charger from USB connector 4.7µF VDDS_PLL_MPU VDDS_PLL_CORE_LCD VDDS_SRAM_MPU_BB INT_LDO 100nF BYPASS BAT_SENSE 10µF TS 75k VDDS_SRAM_CORE_BG VDDA1P8V_USB0 VDDS_DDR 10k NTC VDDS 10µF DCDC1 VDDSHVx(1.8) (1.8V) L1 VIN_DCDC1 VDDS_OSC VDDS_PLL_DDR 22µF VDCDC1 VDDA_ADC 10µF DDR2 10µF L2 VIN_DCDC2 DCDC2 (1.1V) VDCDC2 VDD_MPU 10µF 10µF SYS L3 VIN_DCDC3 DCDC3 (1.1V) VDCDC3 VDD_CORE 10µF 10µF VIN_LDO (1.8V) VLDO1 LDO1 VDDS_RTC 2.2uF 4.7µF AGND VLDO2 LDO2 (3.3V) 2.2uF PGND LS1_IN (3.3V) LS1_OUT LS1/LDO3 SYS VDDSHVx(3.3) 10uF LS2_IN VDDA3P3V_USB0 (3.3V) LS2_OUT LS2/LDO4 SYS VDDSHVx(3.3) 10uF MUX_IN (0..3.3V) VBAT VSYS VICHARGE VTS MUX_OUT AIN4 MUX 100nF Any system voltage Always-on supply Always-on supply 100k 100k PB_IN nRESET 4.7k VDDSHV6 4.7k VDDSHV6 No Connect SCL VIO VLDO1 Any system power needs I2C0_SCL SDA 18uH L4 I2C0_SDA PWR_EN PMIC_PWR_EN SYS PGOOD FB_WLED PWRONRSTN LDO_PGOOD 4.7µF WLED Driver 10k VDDSHV6 100k VLDO1 RTC_PWRONRSTN nINT EXTINTn nWAKEUP ISINK1 EXT_WAKEUP ISINK2 ISET1 ISET2 Power Pad (TM) TPS65217B AM335x Figure 3. Connection Diagram for TPS65217B and AM335x SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Powering the AM335x with the TPS65217x Copyright © 2011–2014, Texas Instruments Incorporated 5 Power Rails Connections for TPS65217B and AM335x 6 www.ti.com Power Rails Connections for TPS65217B and AM335x Table 3 matches the AM335x power terminals with the appropriate power rail from the TPS65217B. Table 3. Power Rails for TPS65217B and AM335x TPS65217B Voltage (V) AM335x VDDS_DDR VDDS VDDSHVx(1.8 V) VDDS_SRAM_CORE_BG VDDS_SRAM_MPU_BB DCDC1 1.8 VDD_PLL_DDR VDDS_PLL_CORE_LCD VDDS_PLL_MPU VDDS_OSC VDDA1P8V_USB0/1 VDDA_ADC 2 DCDC2 Defaults to 1.1 V. Controlled by I C. VDD_MPU DCDC3 Defaults to 1.1 V. Controlled by I2C. VDD_CORE LDO1 1.8 VDDS_RTC LDO2 3.3 LDO3/LS1 3.3 (LDO) LDO4/LS2 3.3 (LDO) n/a VDDSHVx(3.3 V) VDDA3P3V_USB0/1 VDDSHVx(3.3 V) Each output voltage may be changed dynamically while the TPS65217 is in active mode. This requires use of I2C commands to the TPS65217. 6 Powering the AM335x with the TPS65217x SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Power-Up Sequence for TPS65217B www.ti.com 7 Power-Up Sequence for TPS65217B Figure 4 and Table 4 describe the power-up sequence of the TPS65217B. This sequence is optimized specifically for the AM335x processor. NOTE: The power-down sequence follows the reverse of the power-up sequence. STROBE 15 STROBE 1 STROBE 2 DLY 1 5ms STROBE 3 DLY 2 1ms STROBE 4 DLY 3 1ms STROBE 5 DLY 4 1ms VSYS WAKEUP (1) PWR_EN (DG) (2) LDO1 (3) LDO2 DCDC1 DCDC2 DCDC3 LDO3 LDO4 PGDLY PGOOD 20 ms (1) Wakeup↓ events are PB_IN↓ or AC↑ or USB↑ (2) DG = Deglitched (3) LDO1 turns on as soon as VSYS is present LDO_PGOOD↑ 20 ms after LDO1↑ Figure 4. Power-Up Sequence Timing Diagram, TPS65217B Table 4. TPS65217B Power-Up Sequence STROBE 15 LDO1 STROBE 1 DCDC1 STROBE 2 LDO2 STROBE 3 LDO3 STROBE 4 STROBE 5 SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback LDO4 DCDC2 DCDC3 Powering the AM335x with the TPS65217x Copyright © 2011–2014, Texas Instruments Incorporated 7 Connections Diagram for TPS65217C and AM335x 8 www.ti.com Connections Diagram for TPS65217C and AM335x The block diagram shown in Figure 5 illustrates the connections between TPS65217C and AM335x. Power rails as well as the digital and analog signals are shown. The power rails may be used to power additional parts of the system (DCDC1 powers DDR3 memory). AC SYS from AC connector To system load 4.7µF USB BAT 22µF Single cell Li+ Battery Power Path and Charger from USB connector 4.7µF INT_LDO 100nF BYPASS BAT_SENSE 10µF TS 75k 10k NTC 10µF VIN_DCDC1 L1 VDCDC1 DCDC1 (1.5V) VDDS_DDR 10µF DDR3 10µF VIN_DCDC2 L2 VDCDC2 (1.1V) DCDC2 L3 VDCDC3 (1.1V) DCDC3 VLDO1 (1.8V) VDD_MPU 10µF 10µF SYS VIN_DCDC3 VDD_CORE 10µF 10µF VIN_LDO LDO1 VDDS VDDS_RTC 2.2µF 4.7µF (3.3V) VLDO2 LDO2 AGND Any system power needs 2.2µF PGND LS1_IN LS1_OUT LS1/LDO3 (1.8V) SYS 10µF LS2_IN LS2_OUT LS2/LDO4 (3.3V) SYS VDDSHVx(3.3) VDDA3P3V_USB0 10µF (0..3.3V) MUX_IN VBAT VSYS VICHARGE VTS MUX_OUT AIN4 MUX 100nF Any system voltage Always-on supply Always-on supply 100k 100k PB_IN nRESET No Connect 4.7k VDDSHV6 4.7k VDDSHV6 SCL VIO VLDO1 VDDA_ADC VDDS_OSC VDDS_PLL_DDR VDDS_PLL_MPU VDDS_PLL_CORE_LCD VDDS_SRAM_MPU_BB VDDS_SRAM_CORE_BG VDDA1P8V_USB0 VDDSHVx(1.8) I2C0_SCL SDA 18µH L4 I2C0_SDA PWR_EN PMIC_PWR_EN SYS PGOOD FB_WLED PWRONRSTN LDO_PGOOD 4.7µF WLED Driver RTC_PWRONRSTN 10k VDDSHV6 100k VLDO1 nINT EXTINTn nWAKEUP ISINK1 ISINK2 ISET1 ISET2 EXT_WAKEUP Power Pad (TM) TPS65217C AM335x Figure 5. Connection Diagram for TPS65217C and AM335x 8 Powering the AM335x with the TPS65217x SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Power Rails Connections for TPS65217C and AM335x www.ti.com 9 Power Rails Connections for TPS65217C and AM335x Table 5 matches the AM335x power terminals with the appropriate power rail from the TPS65217C. Table 5. Power Rails for TPS65217C and AM335x TPS65217C Voltage (V) AM335x DCDC1 1.5 VDDS_DDR DCDC2 Defaults to 1.1 V. Controlled by I2C. VDD_MPU DCDC3 Defaults to 1.1 V. Controlled by I2C. VDD_CORE LDO1 1.8 VDDS_RTC LDO2 3.3 n/a LDO3/LS1 1.8 VDDSHVx(1.8 V) VDDS VDDS_SRAM_CORE_BG VDDS_SRAM_MPU_BB VDDS_PLL_DDR VDDS_PLL_CORE_LCD VDDS_OSC VDDA1P8V_USB0/1 VDDA_ADC LDO4/LS2 3.3 VDDSHVx(3.3 V) VDDA3P3V_USV0/1 Each output voltage may be changed dynamically while the TPS65217 is in active mode. This requires use of I2C commands to the TPS65217. SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Powering the AM335x with the TPS65217x Copyright © 2011–2014, Texas Instruments Incorporated 9 Power-Up Sequence for TPS65217C 10 www.ti.com Power-Up Sequence for TPS65217C Figure 6 and Table 6 describe the power-up sequence of the TPS65217C. This sequence is optimized specifically for the AM335x processor. NOTE: The power-down sequence follows the reverse of the power-up sequence. STROBE 15 STROBE 1 STROBE 2 DLY 1 1ms STROBE 3 DLY 2 5ms STROBE 4 DLY 3 1ms STROBE 5 DLY 4 1ms VSYS WAKEUP (1) PWR_EN (DG) (2) LDO1 (3) LDO2 DCDC1 DCDC2 DCDC3 LDO3 LDO4 PGDLY PGOOD 20ms (1) Wakeup↓ events are PB_IN↓ or AC↑ or USB↑ (2) DG = Deglitched (3) LDO1 turns on as soon as VSYS is present LDO_PGOOD↑ 20 ms after LDO1↑ Figure 6. Power-Up Sequence Timing Diagram, TPS65217C Table 6. TPS65217C Power-Up Sequence STROBE 15 LDO1 STROBE 1 DCDC1 STROBE 2 LDO3 STROBE 3 LDO2 STROBE 4 LDO4 STROBE 5 10 Powering the AM335x with the TPS65217x DCDC2 DCDC3 SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated PGOOD and LDO_PGOOD Outputs www.ti.com 11 PGOOD and LDO_PGOOD Outputs PGOOD and LDO_PGOOD are push-pull outputs. These outputs are supplied by the VIO pin. During TPS65217 SLEEP mode, all power rails are typically turned off except for LDO1. In order for LDO_PGOOD to remain high during SLEEP mode, connect the VIO pin to LDO1. This allows the LDO_PGOOD signal to be valid even during SLEEP mode. With VIO connected to LDO1, PGOOD and LDO_PGOOD have an output high level of 1.8 V. This level meets the requirements of the PWRONRSTN and RTC_PWRONRSTN input signals of the AM335x processor. 12 MUX_OUT Scaling The AINx ADC input of the AM335x processor is powered by VDDA_ADC. Therefore the maximum voltage input to the ADC should be 1.8 V. If the output voltage of MUX_OUT will be higher than 1.8 V in your application, then add a resistor divider inbetween MUX_OUT and AINx, such that the voltage at AINx does not exceed 1.8 V. The resistor values must be large enough such that the load on MUX_OUT is low. However, the resistors should not be so large as to impact the performance of the ADC. TPS65217x MUX_OUT 20 k AM335x AINx 60 k Figure 7. MUX_OUT Scaling Example 13 Pull-Up Resistors There are four pull-up resistors on the connection diagrams; Figure 1, Figure 3, and Figure 5. nWAKEUP should be pulled up to VLDO1 so that the pull-up source is present even during SLEEP mode. A 100-kΩ pull-up resistor should be used for nWAKEUP to minimize the current load on LDO1. nINT, SCL, and SDA should be pulled up to the same supply that is connected to VDDSHV6. If VDDSHV6 is 1.8 V, then the 1.8-V supply should be used. If VDDSHV6 is 3.3 V, then the 3.3-V supply should be used. SCL and SDA use lower value pull-up resistors in order to decrease rise time of these nodes during I2C communication. Revision History Changes from G Revision (March 2013) to H Revision .................................................................................................. Page • • Changed connection diagram for TPS65217C and AM335x. ....................................................................... 8 Changed table contents in Power Rails for TPS65217C and AM335x. ............................................................ 9 Revision History Changes from H Revision (January 2014) to I Revision ................................................................................................ Page • Changed connection diagram for TPS65217C and AM335x. ....................................................................... 8 SLVU551I – October 2011 – Revised September 2014 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Revision History 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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