AN-D15

Supertex inc.
AN-D15
Application Note
Understanding MOSFET Data
The following outline explains how to read and use Supertex
MOSFET data sheets. The approach is simple and care has
been taken to avoid getting lost in a maze of technical jargon.
The VN3205 data sheet was chosen as an example because it has the largest choice of packages. The product
nomenclature shown applies only to Supertex proprietary
products.
VN3205
Supertex inc.
Type of Channel
Device Structure
Drain-to-Source Breakdown Voltage divided by 10.
►► N-Channel, or
V: Vertical DMOS (discretes & quads)
D: Vertical Depletion-Mode DMOS discretes
T: Low threshold vertical DMOS discretes
L: Lateral DMOS discretes
05:50V
►► P-Channel
Design
Supertex Family
Number
Advanced DMOS Technology
This enhancement-mode (normally-off) DMOS FET transistors utilize a vertical DMOS structure and Supertex’s wellproven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities
of bipolar transistors and with the high input impedance and
negative temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, these devices are free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where high
breakdown voltage, high input impedance, low input capacitance, and fast switching speed are desired.
N-Channel Enhancement-Mode
Vertical DMOS FETs
This section outlines main features of the product.
Ordering Information
Package Options
Device
VN3205
TO-92
14-Lead
PDIP
TO-243AA
(SOT-89)
Die
VN3205N3-G
VN3205P-G
VN3205N8-G
VN3205ND
Drain to source breakdown voltage
& drain to gate breakdown voltage.
Doc.# DSAN-AN-D15
A040213
BVDSS/BVDGS
(V)
50
Maximum resistance from drain to
source when device is fully turned on.
RDS(ON)
max
ID(ON)
min
0.3
3.0
(Ω)
(A)
Minimum drain current when
device is fully turned on.
Supertex inc.
www.supertex.com
AN-D15
Package Options
TO-92
SOT-89
►► Low power
►► Low profile
►► Plastic
►► Cost effective
►► Low θJC thermal
resistance
►► Mainly commercial applications
►► Commercial and
industrial applications
Ordering Information
Package Options
Device
VN3205
TO-92
14-Lead
PDIP
TO-243AA
(SOT-89)
Die
VN3205N3-G
VN3205P-G
VN3205N8-G
VN3205ND
14-Lead DIP
►► Dual in line plastic
►► 4 die in one package
►► Commercial and
industrial applications
Doc.# DSAN-AN-D15
A040213
Wafer
►► NW: Die in wafer form
►► 6 inch diameter wafers
►► Reject dice are inked
2
BVDSS/BVDGS
(V)
50
RDS(ON)
max
ID(ON)
min
0.3
3.0
(Ω)
(A)
Waffle Pack
►► ND: die in waffle pack
►► Die can be visually
inspected to commercial
(standard) or military
visual criteria (specify
while ordering)
Supertex inc.
www.supertex.com
AN-D15
Absolute Maximum Ratings
Absolute Maximum Ratings
Extreme conditions a device can be subjected
to electrically and thermally. Stress in excess
of these ratings will usually cause permanent
damage.
Parameter
Value
Drain-to-source voltage
BVDSS
Drain-to-gate voltage
BVDGS
Gate-to-source voltage
Operating and storage temperature
Ratings given in product summary.
Soldering temperature*
±20V
-55°C to +150°C
+300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
VGS
►► Most Supertex FETs are rated for ±20V.
*
Distance of 1.6mm from case for 10 seconds.
►► ±voltage handling capability allows quick
turn off by reversing bias.
►► External protection should be used
when there is a possibility of exceeding
this rating. Stress exceeding ±20V will
result in gate insulation degradation and
eventual failure.
Maximum allowable temperature at leads while
soldering, 1.6mm away from case for 10 seconds.
►► All Supertex devices can be stored and
operated satisfactorily within these junction temperature (TJ) limits.
►► Appropriate derating factors from curves
and change in parameters due to reduced/elevated temperatures have to
be considered when temperature is not
25°C.
►► Operation at TJ below maximum limit
can enhance operating life.
Doc.# DSAN-AN-D15
A040213
3
Supertex inc.
www.supertex.com
AN-D15
Thermal Characteristics
removed from device. Die size, RDS(ON) and packaging type
are the main factors determining these thermal limitations.
Device characteristics affecting limits of heat produced and
Thermal Characteristics
ID
ID
Power Dissipation
(continuous)*
(A)
(pulsed)
(A)
@TC = 25OC
(W)
θjc
θja
IDR†
IDRM
(OC/W)
(OC/W)
(A)
(A)
TO-92
1.2
8.0
1.0
125
170
1.2
8.0
14-Lead PDIP
1.5
8.0
3.0
41.6
83.3
1.5
8.0
TO-243AA
1.5
8.0
1.6 (TA = 25O)
1.5
8.0
Package
Notes:
* ID (continuous) is limited by max rated TJ, TA = 25OC.
† Total for package.
‡ Mounted on FR5 board, 25mm x 25mm x 1.57mm.
†
15
†
†
78‡
ID (continuous)
IDRM
Maximum continuous current carrying capability
of device.
300µs, 2% duty cycle pulsed. Current handling
capability of drain source diode.
►► Factors affecting value same as ID (pulsed).
Depends mainly on:
►► RDS(ON) - on state resistance.
►► PD - maximum power dissipation for package.
►► Die size.
►► Maximum junction temperature.
IDR
Continuous current handling capability of drain
to source diode.
►► Factors affecting value same as ID (continuous).
ID (pulsed)
Maximum non-continuous pulse current carrying
capability for a 300µs 2% duty cycle pulsed.
θJA
Depends mainly on:
►► RDS(ON).
►► PD max.
►► Diameter of bonding wire.
►► Die size.
►► Maximum junction temperature.
Thermal resistance from junction to air.
►► Depends mainly on package and die size.
θJC
Thermal resistance from junction to case.
►► Depends mainly on package and die size
►► To determine TJ use equation:
Power Dissipation
TJ = PD x θJC + TC
►► Maximum power package can dissipate
when case temperature is 25°C.
►► When case temperature is higher than
25°C, use PD vs. TC curve to determine dissipation permissible.
Doc.# DSAN-AN-D15
A040213
4
Supertex inc.
www.supertex.com
AN-D15
Electrical Characteristics
Electrical Characteristics (T
A
= 25OC unless otherwise specified)
Sym
Parameter
Min
Typ
Max
Units
BVDSS
Drain-to-source breakdown voltage
50
-
-
V
VGS = 0V, ID = 10mA
Conditions
VGS(th)
Gate threshold voltage
0.8
-
2.4
V
VGS = VDS, ID = 10mA
Change in VGS(th) with temperature
-
-4.3
-5.5
mV/OC
VGS = VDS, ID = 10mA
IGSS
Gate body leakage current
-
1.0
100
nA
VGS = ±20V, VDS = 0V
-
-
10
µA
IDSS
Zero gate voltage drain current
VGS = 0V,
VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON)
On-state drain current
3.0
14
-
A
-
-
0.45
ΔVGS(th)
RDS(ON)
ΔRDS(ON)
TO-92 and PDIP
Static
drain-tosource
on-state
resistance
TO-243AA
-
-
0.45
TO-92 and PDIP
-
-
0.3
TO-243AA
Change in RDS(ON) with temperature
-
-
0.3
0.85
1.2
%/OC
mho
GFS
Forward transconductance
1.0
1.5
-
Input capacitance
-
220
300
COSS
Common source output capacitance
-
70
120
CRSS
Reverse transfer capacitance
-
20
30
td(ON)
Turn-on delay time
-
-
10
Rise time
-
-
15
Turn-off delay time
-
-
25
Fall time
-
-
25
Diode forward voltage drop
-
-
Reverse recovery time
-
300
tr
td(OFF)
tf
VSD
trr
Ω
-
CISS
VGS = 10V, VDS = 5.0V
VGS = 4.5V, ID = 1.5A
VGS = 4.5V, ID = 0.75A
VGS = 10V, ID = 3.0A
VGS = 10V, ID = 1.5A
VGS = 10V, ID = 3.0A
VDS = 25V, ID = 2.0A
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
ns
VDD = 25V,
ID = 2.0A,
RGEN = 10Ω
1.6
V
VGS = 0V, ISD = 1.5A
-
ns
VGS = 0V, ISD = 1.0A
BVDSS
IGSS
►► Please see product summary (part I).
►► Positive temperature coefficient. See curve BVDSS vs. TJ.
►► Since the gate is insulated from the rest of device by a silicon dioxide insulating layer, this parameter depends on thick-ness/integ
rity of layer and size of device.
►► Measured at maximum permissible voltage from gate to source: ±20V.
►► Values of this parameter are often tens/hundreds of times less than pub lished maximum value. Electrical screening is done at
100nA since test equipment functions slowly
at lower values, which is not practical for
mass production. Consult factory for screening lower values.
VGS(TH)
►► Voltage required from gate to source to
turn on device to certain ID currentv a l u e
given in “condition” column.
►► ID measurement condition is low for small
die and higher for larger die.
ΔVGS(TH)
►► Threshold voltage reduces when temperature increases and vice versa.
►► Value at temperature other than 25OC can
be determined by VGS(TH) (normalized) vs. TJ
curve.
Doc.# DSAN-AN-D15
A040213
5
Supertex inc.
www.supertex.com
AN-D15
Electrical Characteristics
Electrical Characteristics (T
A
= 25OC unless otherwise specified)
Sym
Parameter
Min
Typ
Max
Units
BVDSS
Drain-to-source breakdown voltage
50
-
-
V
VGS = 0V, ID = 10mA
VGS(th)
Gate threshold voltage
ΔVGS(th)
IGSS
0.8
-
2.4
V
VGS = VDS, ID = 10mA
Change in VGS(th) with temperature
-
-4.3
-5.5
mV/OC
VGS = VDS, ID = 10mA
Gate body leakage current
-
1.0
100
nA
VGS = ±20V, VDS = 0V
-
-
10
µA
VGS = 0V,
VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
3.0
14
-
A
-
-
0.45
IDSS
Zero gate voltage drain current
ID(ON)
On-state drain current
RDS(ON)
ΔRDS(ON)
TO-92 and PDIP
Static
drain-tosource
on-state
resistance
TO-243AA
-
-
0.45
TO-92 and PDIP
-
-
0.3
TO-243AA
Change in RDS(ON) with temperature
-
0.3
1.2
%/OC
VGS = 10V, ID = 3.0A
mho
VDS = 25V, ID = 2.0A
1.0
1.5
-
Input capacitance
-
220
300
COSS
Common source output capacitance
-
70
120
CRSS
Reverse transfer capacitance
-
20
30
td(ON)
Turn-on delay time
-
-
10
Rise time
-
-
15
Turn-off delay time
-
-
25
Fall time
-
-
25
Diode forward voltage drop
-
-
Reverse recovery time
-
300
tf
trr
VGS = 4.5V, ID = 0.75A
VGS = 10V, ID = 3.0A
0.85
Forward transconductance
VSD
Ω
-
GFS
td(OFF)
VGS = 10V, VDS = 5.0V
VGS = 4.5V, ID = 1.5A
-
CISS
tr
Conditions
VGS = 10V, ID = 1.5A
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
ns
VDD = 25V,
ID = 2.0A,
RGEN = 10Ω
1.6
V
VGS = 0V, ISD = 1.5A
-
ns
VGS = 0V, ISD = 1.0A
IDSS
ΔRDS(ON)
►► This is the leakage current from drain to source
when device is fully turned off.
►► Measured by applying maximum permissible
voltage between drain and source (BVDSS)
and gate shorted to source (VGS = 0).
►► Special electrical screening possible at lower
values since max. published values are higher
to achieve practical testing speeds.
►► Positive temperature coefficient.
►► Enhances stability due to current sharing during
parallel operation.
RDS(ON)
►► Drain to source resistance measured when device is partially turned on at VGS = 4.5V, and fully
turned on at VGS = 10V.
►► Designers should use maximum values for
worst case condition.
►► When better turn on characteristics (ie., low
RDS(ON)) is required for logic level inputs, Supertex’s low threshold TN & TP devices may be
used.
►► Typical value of RDS(ON) can be calculated at
various VGS conditions by using output characteristics or saturation characteristics family of
curves (ID vs. VDS).
►► RDS(ON) increases with higher drain currents.
RDS(ON) curve has a slight slope for low values
of ID, but rises rapidly for high values.
ID(ON)
►► Defined as the minimum drain current when
device is turned on.
►► Supertex measures ID(ON) min. at VGS = 10V.
Although Supertex specifies a typical value of
ID(ON), the designer should use minimum value
as the worst case.
Doc.# DSAN-AN-D15
A040213
6
Supertex inc.
www.supertex.com
AN-D15
Switching Characteristics
Electrical Characteristics (T
A
►► Extremely fast switching compared to bipolar transistors, due
to absence of minority carrier
storage time during turn off.
►► Switching times depend almost
totally on interelectrode capacitance, RS (source impedance)
and RL (load impedance) as
shown on test circuit.
Sym
Parameter
Min
Typ
Max
Units
BVDSS
Drain-to-source breakdown voltage
50
-
-
V
VGS = 0V, ID = 10mA
VGS(th)
Gate threshold voltage
0.8
-
2.4
V
VGS = VDS, ID = 10mA
-
-4.3
-5.5
mV/OC
VGS = VDS, ID = 10mA
IGSS
Gate body leakage current
-
1.0
100
nA
VGS = ±20V, VDS = 0V
-
-
10
µA
IDSS
Zero gate voltage drain current
VGS = 0V,
VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON)
On-state drain current
3.0
14
-
A
-
-
0.45
ΔRDS(ON)
►► Represents gain of the device
and can be compared to HFE of
a bipolar transistor.
►► Value is the ratio of change in ID
for a change in VGS:
∆ID
GFS =
∆VGS
►► Rises rapidly with increasing ID,
and then becomes constant in
the satur-ation region. See GFS
vs. ID curve.
CGS
Doc.# DSAN-AN-D15
A040213
-
0.45
-
0.3
TO-243AA
-
0.3
0.85
1.2
%/OC
mho
1.0
1.5
-
Input capacitance
-
220
300
COSS
Common source output capacitance
-
70
120
CRSS
Reverse transfer capacitance
-
20
30
td(ON)
Turn-on delay time
-
-
10
Rise time
-
-
15
Turn-off delay time
-
-
25
Fall time
-
-
25
Diode forward voltage drop
-
-
Reverse recovery time
-
300
tr
td(OFF)
tf
VSD
trr
Ω
-
Forward transconductance
VGS = 10V, VDS = 5.0V
VGS = 4.5V, ID = 1.5A
-
GFS
VGS = 4.5V, ID = 0.75A
VGS = 10V, ID = 3.0A
VGS = 10V, ID = 1.5A
VGS = 10V, ID = 3.0A
VDS = 25V, ID = 2.0A
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
ns
VDD = 25V,
ID = 2.0A,
RGEN = 10Ω
1.6
V
VGS = 0V, ISD = 1.5A
-
ns
VGS = 0V, ISD = 1.0A
Td(ON)
During this period, the drive circuit charges CISS
up to VGS(TH). Since no drain current flows prior
to turn on, VDS and consequently CISS remain
constant. Region I on the VGS vs. QG curve
shows linear change in voltage with increasing
QG.
10
Gate Drive Dynamic Characteristics
VDS = 10V
VGS (volts)
8
DRAIN
GATE
-
CISS
CISS = CGS + (1+GFS • RL) CGD
CDS
TO-243AA
TO-92 and PDIP
Change in RDS(ON) with temperature
►► Supertex interdigitated structures have lowest CISS in
the industry for comparable die sizes and exhibit excellent switching characteristics.
►► Values of these capacitances are high at low voltages
across them. Please see capacitance vs VDS curves
for details.
►► Negligible effect of temperature on capacitances.
►► The following equation may be used for calculating
effective value of CISS with “Miller Effect.”
CGD
TO-92 and PDIP
Static
drain-tosource
on-state
resistance
CISS, CRSS, COSS
Conditions
Change in VGS(th) with temperature
ΔVGS(th)
RDS(ON)
GFS
= 25OC unless otherwise specified)
CISS = CGD + CGS
COSS = CGD + CDS
CRSS = CGD
6
I
II
VDS = 40V
325pF
III
4
2
0
SOURCE
7
215 pF
0
1
2
3
QG (nanocoulombs)
4
5
Supertex inc.
www.supertex.com
AN-D15
Switching Characteristics
tr
►► When CISS is driven to a voltage
exceeding VGS(TH), conduction
from drain source begins. GFS
increases causing increase in
CISS due to “Miller Effect” charge
requirements to Region II increase considerably. Gain stabilizes in Region III and “Miller
Effect” is nullified, resulting in a
linear change in VGS for increase
in QG.
td(OFF)
►► The sequence of events now begins to reverse. CISS discharges
through RGEN. The rise of VDS is
initially slowed by increase of
output capacitance.
Electrical Characteristics (T
A
= 25OC unless otherwise specified)
Sym
Parameter
Min
Typ
Max
Units
BVDSS
Drain-to-source breakdown voltage
50
-
-
V
VGS = 0V, ID = 10mA
Conditions
VGS(th)
Gate threshold voltage
0.8
-
2.4
V
VGS = VDS, ID = 10mA
Change in VGS(th) with temperature
-
-4.3
-5.5
mV/OC
VGS = VDS, ID = 10mA
IGSS
Gate body leakage current
-
1.0
100
nA
VGS = ±20V, VDS = 0V
-
-
10
µA
IDSS
Zero gate voltage drain current
VGS = 0V,
VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON)
On-state drain current
3.0
14
-
A
-
-
0.45
ΔVGS(th)
RDS(ON)
ΔRDS(ON)
Static
drain-tosource
on-state
resistance
TO-92 and PDIP
TO-243AA
-
-
0.45
TO-92 and PDIP
-
-
0.3
TO-243AA
Change in RDS(ON) with temperature
-
-
0.3
0.85
1.2
%/OC
mho
GFS
Forward transconductance
1.0
1.5
-
Input capacitance
-
220
300
COSS
Common source output capacitance
-
70
120
CRSS
Reverse transfer capacitance
-
20
30
td(ON)
Turn-on delay time
-
-
10
Rise time
-
-
15
Turn-off delay time
-
-
25
Fall time
-
-
25
Diode forward voltage drop
-
-
Reverse recovery time
-
300
tr
td(OFF)
tf
VSD
trr
Ω
-
CISS
VGS = 10V, VDS = 5.0V
VGS = 4.5V, ID = 1.5A
VGS = 4.5V, ID = 0.75A
VGS = 10V, ID = 3.0A
VGS = 10V, ID = 1.5A
VGS = 10V, ID = 3.0A
VDS = 25V, ID = 2.0A
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
ns
VDD = 25V,
ID = 2.0A,
RGEN = 10Ω
1.6
V
VGS = 0V, ISD = 1.5A
-
ns
VGS = 0V, ISD = 1.0A
trr
tf
►► The reverse recovery time is the time needed for
the carrier gradient, formed during forward biasing, to be depleted when the biasing is reversed.
►► An external fast recovery diode may be connected
from drain to source to improve recovery time.
►► VDS rises as the load resistor charges the
output capacitance.
VSD
►► This is the forward voltage drop of the parasitic diode between drain and source.
►► Diode may be used as a commutator in H
bridge configurations or in a synchronous
rectifier mode. Excessive fly back voltages
may be clamped by this diode in a totem
pole configuration.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSAN-AN-D15
A040213
8
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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