DC1996A - Schematic

5
4
3
2
1
REVISION HISTORY
VCCIO
C7
OPT
R6
0
3
R7
OPT
C8
OPT
2
U4A
LT1819CMS8
+
1
-
R8
49.9
4
2
04-01-14
R4
33
4
U3
NC7SZ04P5X
R10
1k
DATE
DOUG S.
5
2
R9
49.9
1206
C9 0.1uF
APPROVED
PRODUCTION
C2
0.1uF
5
R2
1k
C5
0.1uF
J1
CLK
200MHz MAX
2.5VPP
R3
OPT
DESCRIPTION
2
CLKIN
U2
NC7SZ04P5X
D
3
R5
0
C3
10uF
6.3V
8
J2
R1
1k
C6
10uF
6.3V
C1
0.1uF
C4 0.1uF
REV
C130
0.1uF
3
AIN2-
AIN1+
7
AIN1+
AIN1-
6
R30
0
U1
AIN1-
C35
OPT
28
V+ C29 0.1uF
R31
0
R32
OPT
5
C36
OPT
6
U5B
LT1819CMS8
+
7
-
C37 0.1uF
R28
OPT
R33
49.9
*
QFN28UFD-4X5
R29
OPT
R35 0
2
4
6
C40
OPT
R38
0 0402
CM1
R54
OPT
GND
2
5
D
CSB
1
2
3
OSC
OFF
ON
JP13
U7
NC7SZ04P5X
3
U6
NL17SZ74
5
Q
2
R20
33
C
SDO1+
SDO1-
SCK+
SCKCNVL
CLKOUT+
CLKOUT-
21
22
9
17
18
SCK+
SCK-
SDO2+
SDO2-
19
20
SDO2+
SDO2-
ADD 20 MIL SQUARE
PAD OPENING ON
TOP SOLDER MASK
LAYER ON THESE
CONNETIONS.
CLKOUT+
CLKOUT-
ADC
4
C54
10uF
8
R49
OPT
3
C47
10uF
6.3V
C51 V+
0.1uF
R44
49.9
1
R39
0
U10
LT6202CS5
U5A
LT1819CMS8
VCM_BIAS_1
R50
OPT
8
JP6
VREF_1
R43
0 0402
U9
LTC6655BHMS8-4.096 +9V/+10V
R36
OPT
3
2
1
+
1
-
C39
1uF
SHDN
1
7
VOUT_F VIN
2
6
VOUT_S GND
3
GND
4
5
GND
GND
CM2
EXT
ADC
C43
1uF
VREF_2
C42
2.2uF
R51
1k
C61
10uF
6.3V
R40
0
3
2
1
C49
10uF
6.3V
C52 V+
0.1uF
U21
LT6202CS5
3
VCM_BIAS_2
C55
4.7uF
U8
LTC6655BHMS8-4.096 +9V/+10V
R37
OPT
8
JP7
R46
1k
4
EXT_CM2
E2
+
1
-
SHDN
1
7
VOUT_F VIN
2
6
VOUT_S GND
3
GND
4
5
GND
GND
B
C45
1uF
C44
2.2uF
R47
1k
3
R52
1k
4
C56
4.7uF
C58
V0.1uF
C59
V0.1uF
3
2
1
C60
OPT
EOH
2
1
Q
4
2
J5
C53
10uF
6.3V
2
+
AIN10V - 4.096V
R48
1k
R42
301
EXT
C46
OPT
R45
150
C57
10uF
6.3V
+3V R121
10k
15
C38
1uF
C41
200pF
NP0
JP8
HD2X3-100
VCM_BIAS_1
R53
0
R41
301
-
C50
10uF
6.3V
3
C33 4.7uF
5
MODE
C48
10uF
6.3V
PR
7
R17
33
SDO1+ 16
SDO1-
C32
1uF
B
VCM_BIAS_1
8
EXT_CM1
E1
AC DC
DIFF 1
UNI 3
BIP 5
OUT
2
V-
R34 OPT
JP5
VREF_1
VCC
1
C31 4.7uF
C30
10uF
6.3V
3
2
1
+IN1
COUPLING
4
12
REFOUT1 26
REFOUT2
AIN2+
AIN2-
REFRTN1
REFRTN2
2
C13
0.1uF
R122
100
Y1
CB3LV
+3V
R123
OPT
11
27
AIN2+
C129
0.1uF
VCCIO
5
J4
CLR
VCC
REFOUT2
4
AIN1+
0V - 4.096V
6
GND
REFOUT1
R23
OPT
JP4
R27
1k
4
C23
0.1uF
JP3
U4B
LT1819CMS8
13
7
AC DC
C34
10uF
6.3V
C18
0.1uF
C22
0.1uF
1
2
3
LVDS
CMOS
C28
10uF
6.3V
VCM_BIAS_1
C17
10uF
6.3V
3
R18
49.9
8
-IN2
COUPLING
C19
0.1uF
VBYP1 24
VBYP2
R25
OPT
5
C25
10uF
C16
10uF
6.3V
DATA OUT
3
2
1
C27
OPT
R22
OPT
C15
1uF
1
C26
10uF
6.3V
C24
10uF
6.3V
R16
0 0402
25
C
R21
1k
6
VCCIO
4
5
10
23
29
VCM_BIAS_2
R24
0
C14
OPT
JP2
HD2X3-100
R19
150
VDD
C11
0.1uF
REFBG
C21
10uF
6.3V
4
C20
10uF
6.3V
8
VCM_BIAS_2
2
4
6
VCCIO
VDD1 8
VDD2
DIFF 1
UNI 3
BIP 5
R13
0 0402
C12
200pF
NP0
R15
301
+
VREF_2
AIN20V - 4.096V
C10
OPT
CP
R14
301
MODE
J3
R12 0
GND
GND
GND
GND
GND
R11 OPT
JP1
AC DC
-
+IN2
COUPLING
V-
LVDS 14
OVDD
3
2
1
4
D
AIN2+
0V - 4.096V
V+
ECO
VCCIO
3
VCM_BIAS_2
VCCIO
-IN1
COUPLING
JP9
AC DC
A
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0603.
ALL CAPACITORS ARE IN MICROFARADS, 0603
5
*
ASSY
A
B
C
D
E
F
4
U1
LTC2323CUFD-16
LTC2321CUFD-16
LTC2323CUFD-14
LTC2321CUFD-14
LTC2323CUFD-12
LTC2321CUFD-12
BITS
16
16
14
14
12
12
Msps
5
2
5
2
5
2
R67
R68
1k
OPT
OPT
1k
1k
OPT
R73
R74
1k
OPT
OPT
1k
CUSTOMER NOTICE
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
3
APPROVALS
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APP
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
2
TECHNOLOGY
KIM T.
DOUG S.
TITLE: SCHEMATIC
TRUE DIFFERENTIAL INPUT DUAL ADC
SIZE
B
SCALE = NONE
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
DATE:
IC NO.
LTC232XCUFD FAMILY
DEMO CIRCUIT 1996A
04/01/2014, 12:58 PM
REV.
2
SHEET 1
1
OF 3
A
5
4
E7
C62
47uF
16V
1210
C65
1uF
16V
5
IN
SHDN
GND
GND
GND
GND
8
V+
OUT
1
SEN
2
BYP
4
E5
C63
0.01uF
R56
3.92k
C66
10uF
10V
0805
U13
LT1763CS8
5
IN
SHDN
OUT
1
SEN
2
BYP
4
E8
C69
0.01uF
R59
499
3
2
1
VCCIO
1.8V
3
6
7
C68
1uF
16V
IN
SHDN
GND
GND
GND
5
OUT
SEN
2
BYP
4
C72
0.01uF
R62
3.09k
R63
4.02k
3
2
1
GND
GND
GND
IN
SHDN
IN
3
SHDN
ADJ
E3
5
R55
3.92k
4
R57
1k
C64
10uF
10V
0805
V-
V-
D
VCCIO
C73
10uF
10V
0805
VDD
VDD
C
3.3V
5V
JP11
+3V
OUT
1
SEN
2
BYP
4
E10
C75
0.01uF
R65
1.43k
C76
10uF
6.3V
+3V
R66
1k
3
6
7
5
2
OUT
R61
866
U15
LT1763CS8
C74
1uF
16V
C70
10uF
6.3V
E9
R64
1k
8
GND
VDD
1
3
6
7
C71
1uF
16V
C67
1uF
16V
1
2.5V
U14
LT1763CS8
8
V+
-9V/-10V
JP10
R60
1k
C
-9V/-10V
E6
VCCIO
GND
GND
GND
8
1
R58
1k
3
6
7
D
E4
2
U12
LT1964ES5-SD
U11
LT1763CS8
+9V/+10V
+9V/+10V
3
B
B
U16
LT1763CS8-2.5
5
SHDN
+2.5V
OUT
1
SEN
2
BYP
4
OUT
2
E11
C78
0.01uF
C79
10uF
6.3V
+2.5V
3
6
7
C77
1uF
16V
IN
GND
GND
GND
8
U17
LT3021ES8-1.2
SHDN
AGND
5
6
A
GND
C80
3.3uF
16V
IN
+1.2V
SEN
3
E12
VCCINT
C81
10uF
6.3V
+1.2V
CUSTOMER NOTICE
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
5
APPROVALS
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APP
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
4
8
4
3
2
TECHNOLOGY
KIM T.
DOUG S.
TITLE: SCHEMATIC
TRUE DIFFERENTIAL INPUT DUAL ADC
SIZE
B
SCALE = NONE
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
DATE:
IC NO.
LTC232XCUFD-16/-14 FAMILY
DEMO CIRCUIT 1996A
04/01/2014, 01:00 PM
SHEET 2
1
REV.
2
OF 3
A
5
4
U18B
U18C
BANK1
IO1
IO2
IO3
IO4
IO5_VREF1
IO6_DIFFL4P
IO7_DIFFL4N
CLK0
CLK1
D
3
R69
R70
R71
R72
R119
1
2
3
4
7
10
11
22
23
33
33
33
33
33
U18D
BANK2
DB12
DB13
DB14
CNVCLK
DB15
CLK2
CLK3
IO1
IO2
IO3_VREF2
IO4_RUP1
IO5_RDN1
IO6
SCK+
R26
OPT
2
IO1_DIFFIOB1P
IO2_DIFFIOB1N
IO3
IO4
IO5
IO6_VREF3
IO7_DIFFIOB9P
IO8_DIFFIOB9N
IO9
IO10_DIFFIOB11P
IO11_DIFFIOB11N
SCK-
P1
U18E
BANK3
24
25
28
30
31
32
33
34
1
DB15
DB14
BANK4
38
39
42
43
44
46
49
50
51
52
53
54
55
58
59
60
64
65
66
67
68
69
70
71
72
IO1_DIFFIOB12P
IO2_DIFFIOB12N
IO3
IO4_DIFFIOB16P
IO5_DIFFIOB16N
IO6
IO7_VREF4
IO8_RUP2
IO9_RDN2
IO10
IO11
IO12_DIFFIOB21P
IO13_DIFFIOB21N
IO14
SDO2-
R75
OPT
SDO2+
CLKIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DB13
DB12
CLKOUT-
R99
OPT
DB11
DB10
CLKOUT+
DB9
DB8
SDO1-
DB7
DB6
R76
OPT
DB5
DB4
SDO1+
DB3
DB2
DB1
DB0
CYCLONE3-EP3C5E144
CYCLONE3-EP3C5E144
CYCLONE3-EP3C5E144
CYCLONE3-EP3C5E144
U18F
U18G
U18H
U18I
C
33
33
33
BANK6
DA0
DA1
DA2
CLK5_DIFFCLK2N
CLK4_DIFFCLK2P
IO1
IO2
IO3_VREF6
IO4
CSB
R73
*
VCCIO
BANK7
90
91
100
104
105
106
R86
R89
33
33
DA3
DA4
R83
33
DA5
IO1
IO2
IO3
IO4
IO5_RUP4
IO6_RDN4
IO7_VREF7
IO8_DIFFIOT16N
IO9_DIFFIOT16P
IO10
IO11
IO12_DIFFIOT12N
IO13_DIFFIOT12P
R74
*
R67
*
110
111
112
113
114
115
119
120
121
124
125
126
127
BANK8
R78
R80
R87
R90
33
33
33
33
DA6
DA7
DA8
DA9
R93
R95
R97
R100
R102
R120
R104
33
33
33
33
33
33
33
DA10
DA11
DA12
DA13
DA14
DA15
DB0
128
129
132
133
135
136
137
138
141
142
143
144
IO1_DIFFIOT11N
IO2_DIFFIOT11P
IO3_DIFFIOT10N
IO4_DIFFIOT10P
IO5
IO6_VREF8
IO7
IO8
IO9
IO10
IO11_DIFFIOT01N
IO12_DIFFIOT01P
DA15
DA14
R79
R81
R88
R91
R82
33
33
33
33
33
DB1
DB2
DB3
DB4
DB5
R92
R94
R96
R98
R101
R103
33
33
33
33
33
33
DB6
DB7
DB8
DB9
DB10
DB11
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
VCCIO
DA3
DA2
R68
DA1
DA0
CYCLONE3-EP3C5E144
FPGA
PROGRAM
+3V
2
4
6
8
10
VCCIO
+1.2V
VCCIO
C93
0.1uF
C94
0.1uF
C95
0.1uF
C96
0.1uF
C97
0.1uF
C98
0.1uF
C99
0.1uF
C100
0.1uF
C101
0.1uF
C102 C103
0.1uF 0.1uF
C104
0.1uF
+2.5V
C105
47uF
0805
C106
4.7uF
0603
C107 C108 C109
0.01uF 0.1uF 1nF
C110
22nF
C111
22nF
C112
22nF
C113
4.7nF
A
C118 C119
470uF 4.7uF
7343 0603
6
8
9
12
13
14
15
16
18
20
21
86
87
92
94
96
97
98
99
101
103
IO1_DATA1
IO2_FLASH_NCE
N_STATUS
DCLK
IO3_DATA0
NCONFIG
TDI
TCK
TMS
TDO
NCE
IO4_DEV_OE
IO5_DEV_CLRN
CONF_DONE
MSEL0
MSEL1
MSEL2
IO6_INIT_DONE
IO7_CRC_ERROR
IO8_NCEO
IO9_CLKUSR
CYCLONE3-EP3C5E144
+1.2V
L1
BLM31PG391SN1L
VCCD_PLL
+
R109
10k
CONFIG
R110
10k
R111
10k
R112
10k
R114
10k
+3V
C120 C121 C122
0.01uF 0.01uF 0.1uF
C123
0.1uF
C124
0.1uF
C125
0.1uF
C126
0.1uF
C127
2.2nF
C128
4.7nF
+3V
+3V
8
NCS
VCC 7
DATA
VCC 6
VCC
DCLK 5
GND
ASDI
TDI
TCK
TMS
TDO
NCE
C91
0.1uF
0402
C92
0.1uF
0402
EPCS4SI8
R105
4.99k
0603
R107
4.99k
0603
R108
4.99k
0603
U20
24LC024-I /ST
SCL
SDA
WP
A2
A1
A0
6
5
7
3
2
1
B
EEPROM
1
2
3
WP
PROG
JP12
+2.5V
R115
10k
R116
10k
VCCIO
R117
10k
+3V
+3V
+3V
+3V
R118
1k
D1
BAT54WS
C114
10pF
JTAG
2
4
6
8
10
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS AND CAPACITORS ON THIS PAGE ARE 0402.
2. SEE ASSEMBLY TABLE ON PAGE 1 FOR R67, R68, R73, AND R74 VALUES.
4
U19
1
2
3
4
1
3
5
7
9
J7
HD2X5-100
5
R113
10k
8
C90
0.1uF
R106
4.99k
0603
4
C89
0.1uF
1
C88
0.1uF
1
C87
0.1uF
TCK
TDO
TMS
TDI
D2
BAT54WS
D3
BAT54WS
2
C86
0.1uF
1
C85
0.1uF
2
B
19
27
36
41
48
57
63
82
95
108
118
123
131
140
145
VCCINT
VCCINT
GND
VCCINT
GND
VCCINT
GNDA1 VCCINT
GND
VCCINT
GND
VCCINT
GND
VCCINT
GND
VCCIO1
GND
VCCIO2
GND
VCCIO3
GNDA2 VCCIO3
GND
VCCIO4
GND
VCCIO4
GND
VCCIO5
GND
VCCIO6
GND
VCCIO7
VCCIO7
VCCIO8
VCCIO8
VCCA1
VCCA2
VCCD_PLL1
VCCD_PLL2
CYCLONE3-EP3C5E144
C84
0.1uF
C82
0.1uF
0603
J6
HD2X5-100
2
PWR
U18J
C83
0.1uF
5
29
45
61
78
102
116
134
17
26
40
47
56
62
81
93
117
122
130
139
35
107
37
109
1
3
5
7
9
1
U18A
VCCIO
EDGE-CON-100
VCC
CYCLONE3-EP3C5E144
GND
CYCLONE3-EP3C5E144
C
C115
10pF
D4
BAT54WS
2
*
CYCLONE3-EP3C5E144
ARRAY
IO1
IO2
IO3
IO4_RUP3
IO4_RDN3
IO5
IO6_VREF5
IO7
IO8_DIFFIOR8N
IO9_DIFFIOR8P
CLK7_DIFFCLK3N
CLK6_DIFFCLK3P
R84
R85
R77
73
74
75
76
77
79
80
83
84
85
88
89
EEPROM
BANK5
CNVCLK
D
C116
10pF
C117
10pF
CUSTOMER NOTICE
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
3
APPROVALS
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APP
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
2
TECHNOLOGY
KIM T.
DOUG S.
TITLE: SCHEMATIC
TRUE DIFFERENTIAL INPUT DUAL ADC
SIZE
B
SCALE = NONE
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
DATE:
IC NO.
LTC232XCUFD-16/-14 FAMILY
DEMO CIRCUIT 1996A
04/01/2014, 12:59 PM
SHEET 3
1
REV.
2
OF 3
A
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