Dual 3 MHz, 1200 mA Buck Regulators with Two 300 mA LDOs ADP5034 Data Sheet FEATURES regulators operate in PWM mode when the load is above a predefined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. Main input voltage range: 2.3 V to 5.5 V Two 1200 mA buck regulators and two 300 mA LDOs 24-lead, 4 mm × 4 mm LFCSP or 28-lead TSSOP package Regulator accuracy: ±1.8% Factory programmable or external adjustable VOUTx 3 MHz buck operation with forced PWM and auto PWM/PSM modes BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V LDO1/LDO2: output voltage range from 0.8 V to 5.2 V LDO1/LDO2: input supply voltage from 1.7 V to 5.5 V LDO1/LDO2: high PSRR and low output noise Table 1. Family Models Model ADP5023 Channels 2 Buck,1 LDO ADP5024 2 Buck,1 LDO ADP5034 2 Buck,2 LDOs APPLICATIONS ADP5037 2 Buck,2 LDOs Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices ADP5033 2 Buck,2 LDOs with 2 EN pins Maximum Current 800 mA, 300 mA 1.2 A, 300 mA 1.2 A, 300 mA 800 mA, 300 mA 800 mA, 300 mA Package LFCSP (CP-24-10) LFCSP (CP-24-10) LFCSP (CP-24-10), TSSOP (RE-28-1) LFCSP (CP-24-10) WLCSP (CB-16-8) The ADP5034 combines two high performance buck regulators and two low dropout (LDO) regulators. It is available in either a 24-lead 4 mm × 4 mm LFCSP or a 28-lead TSSOP package. The two bucks operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5034 LDOs extend the battery life of portable devices. The ADP5034 LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set to high, the buck regulators operate in forced PWM mode. When the MODE pin is set to low, the buck Regulators in the ADP5034 are activated through dedicated enable pins. The default output voltages can be externally set in the adjustable version, or factory programmable to a wide range of preset values in the fixed voltage version. GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT AVIN CAVIN 0.1µF 2.3V TO 5.5V HOUSEKEEPING VOUT1 VIN1 SW1 C1 4.7µF ON OFF BUCK1 EN1 FB1 PGND1 EN1 L1 1µH C5 10µF R2 MODE PWM MODE MODE SW2 C2 4.7µF BUCK2 EN3 EN2 EN3 VIN3 1.7V TO 5.5V FB2 PGND2 R4 C6 10µF FB3 R5 VOUT3 AT 300mA C7 1µF VOUT4 EN4 LDO2 (DIGITAL) FB4 R7 R8 ADP5034 AGND VOUT4 AT 300mA C8 1µF 09703-001 EN4 VIN4 VOUT2 AT 1200mA R3 R6 OFF C4 1µF L2 1µH VOUT3 LDO1 (ANALOG) C3 1µF ON PSM/PWM VOUT2 VIN2 EN2 VOUT1 AT 1200mA R1 Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com ADP5034 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Power Management Unit........................................................... 16 General Description ......................................................................... 1 BUCK1 and BUCK2 .................................................................. 18 Typical Application Circuit ............................................................. 1 LDO1 and LDO2 ........................................................................ 19 Revision History ............................................................................... 3 Applications Information .............................................................. 20 Specifications..................................................................................... 4 Buck External Component Selection....................................... 20 General Specifications ................................................................. 4 LDO External Component Selection....................................... 22 BUCK1 and BUCK2 Specifications ........................................... 5 Power Dissipation and Thermal Considerations ....................... 23 LDO1 and LDO2 Specifications ................................................. 5 Buck Regulator Power Dissipation .......................................... 23 Input and Output Capacitor, Recommended Specifications .. 6 Junction Temperature ................................................................ 24 Absolute Maximum Ratings ............................................................ 7 PCB Layout Guidelines .................................................................. 25 Thermal Resistance ...................................................................... 7 Typical Application Schematics .................................................... 26 ESD Caution .................................................................................. 7 Bill of Materials ........................................................................... 26 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 27 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 28 Rev. E | Page 2 of 28 Data Sheet ADP5034 REVISION HISTORY 5/13—Rev. D to Rev. E Added Table 1; Renumbered Sequentially ..................................... 1 Changes to Figure 1........................................................................... 1 Changes to NC Pin Description ...................................................... 8 Changes to Figure 49 ......................................................................19 Changes to Figure 51 ......................................................................21 Changes to Figure 53 and Figure 54 .............................................26 1/13—Rev. C to Rev. D Changes to Ordering Guide ...........................................................28 11/12—Rev. B to Rev. C Changes to Ordering Guide ...........................................................28 7/12—Rev. A to Rev. B Added 28-Lead TSSOP Package Throughout ............................... 1 Changes to Output Voltage Accuracy Parameter, Added TSSOP SW On Resistance Specifications, Changes to Voltage Feedback Minimum and Maximum Values, and Changes to Active PullDown Conditions; Table 2 ............................................................... 5 Changes to Output Voltage Accuracy Parameter and Voltage Feedback Minimum and Maximum Values in Table 3; Changes to Table 4 ............................................................................................ 6 Added Thermal Resistance Values for TSSOP Package, Table 6 ..7 Added Figure 3 and TSSOP Pins to Table 7 .................................. 8 Changes to Figure 7, Figure 8, and Figure 9 .................................. 9 Changes to Figure 10 ......................................................................10 Changes to Figure 18 Caption .......................................................11 Changes to Figure 31 and Figure 32 .............................................13 Changes to Figure 35 and Figure 39 Caption ..............................14 Changes to Undervoltage Lockout Section..................................17 Changes to Table 8 ..........................................................................20 Changes to Table 9 and Table 11 ...................................................21 Changes to Equation 9 and Following Paragraph .......................23 Added UG-349 to PCB Layout Guidelines Section ....................25 Changes to Table 12 ........................................................................26 Updated Outline Dimensions ........................................................27 Changes to Ordering Guide ...........................................................28 10/11—Rev. 0 to Rev. A Change to Features Section .............................................................. 1 Changes to General Description Section ....................................... 1 Changes to Figure 1........................................................................... 1 Change to Table 1, Low UVLO Input Voltage Falling Parameter, Symbol Column................................................................................. 3 Change to Table 2, Output Voltage Accuracy Parameter, Test Conditions/Comment Column ....................................................... 4 Change to Table 2, Line Regulation Parameter, Symbols Column ............................................................................................... 4 Change to Table 2, Load Regulation Parameter, Symbols Column ............................................................................................... 4 Changes to Table 2, Reversed the RPFET and RNFET Symbols for the SW On Resistance Parameter and Changes to Typ and Max Columns ............................................................................................. 4 Changes to Table 3, Output Accuracy Parameter, Test Conditions/Comments Column ..................................................... 4 Changes to Table 3, Line Regulation Parameter, Symbols Column and Test Conditions/Comments Column ...................... 4 Change to Table 3, Changes to Dropout Voltage Parameter and Added Specification to Dropout Voltage Parameter .................... 5 Change to Table 3, Endnote 3 .......................................................... 5 Change to Table 4, BUCK1, BUCK2 Output Capacitor Parameter, Min Column Value ........................................................ 5 Change to Table 4, Endnote 1 .......................................................... 5 Changes to Absolute Maximum Ratings, Table 5 ......................... 6 Changes to Table 7, Pin Function Descriptions ............................ 7 Changes to TPC Section................................................................... 8 Moved Power Dissipation and Thermal Considerations Section .............................................................................................. 22 Change to Equation 5 Where Statement ...................................... 22 Change to Equation 6 ..................................................................... 22 Change to Undervoltage Lockout Section ................................... 16 Changes to Figure 46 ...................................................................... 16 Change to Figure 47 ........................................................................ 17 Changes to LDO1/LDO2 Section ................................................. 18 Changes to Output Capacitor Section and Table 8..................... 19 Change to VRIPPLE Equation, Table 9, and Figure 50.................... 20 Changes to Input and Output Capacitor Properties Section .... 21 Changes to Equation 3.................................................................... 22 Changes to Junction Temperature Section .................................. 23 Changes to LDO Regulator Power Dissipation Section ............. 23 Changes to Figure 52 and Figure 53 ............................................. 25 Moved Bill of Materials Section .................................................... 25 Changes to Ordering Guide ........................................................... 26 6/11—Revision 0: Initial Version Rev. E | Page 3 of 28 ADP5034 Data Sheet SPECIFICATIONS GENERAL SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; VIN3 = VIN4 = 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter INPUT VOLTAGE RANGE THERMAL SHUTDOWN Threshold Hysteresis START-UP TIME 1 BUCK1, LDO1, LDO2 BUCK2 EN1, EN2, EN3, EN4, MODE INPUTS Input Logic High Input Logic Low Input Leakage Current INPUT CURRENT All Channels Enabled All Channels Disabled VIN1 UNDERVOLTAGE LOCKOUT High UVLO Input Voltage Rising High UVLO Input Voltage Falling Low UVLO Input Voltage Rising Low UVLO Input Voltage Falling 1 Symbol VAVIN, VIN1, VIN2 Test Conditions/Comments TSSD TSSD-HYS TJ rising Min 2.3 tSTART1 tSTART2 VIH VIL VI-LEAKAGE ISTBY-NOSW ISHUTDOWN Typ Max 5.5 150 20 °C °C 250 300 µs µs 1.1 No load, no buck switching TJ = −40°C to +85°C UVLOVIN1RISE UVLOVIN1FALL UVLOVIN1RISE UVLOVIN1FALL 0.05 0.4 1 V V µA 108 0.3 175 1 µA µA 3.9 V V V V 3.1 2.275 1.95 Unit V Start-up time is defined as the time from EN1 = EN2 = EN3 = EN4 from 0 V to VAVIN to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information. Rev. E | Page 4 of 28 Data Sheet ADP5034 BUCK1 AND BUCK2 SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1 Table 3. Parameter OUTPUT CHARACTERISTICS Output Voltage Accuracy Line Regulation Load Regulation VOLTAGE FEEDBACK OPERATING SUPPLY CURRENT BUCK1 Only Test Conditions/Comments Min ΔVOUT1/VOUT1, ΔVOUT2/VOUT2 (ΔVOUT1/VOUT1)/ΔVIN1, (ΔVOUT2/VOUT2)/ΔVIN2 (ΔVOUT1/VOUT1)/ΔIOUT1, (ΔVOUT2/VOUT2)/ΔIOUT2 VFB1, VFB2 PWM mode; ILOAD1 = ILOAD2 = 0 mA −1.8 IIN BUCK2 Only IIN BUCK1 and BUCK2 IIN PSM CURRENT THRESHOLD SW CHARACTERISTICS SW On Resistance Current Limit ACTIVE PULL-DOWN OSCILLATOR FREQUENCY 1 Symbol IPSM RNFET RPFET RNFET RPFET RNFET RPFET RNFET RPFET ILIMIT1, ILIMIT2 RPDWN-B fSW Typ Max Unit +1.8 % PWM mode −0.05 %/V ILOAD = 0 mA to 1200 mA, PWM mode −0.1 %/A Models with adjustable outputs MODE = ground ILOAD1 = 0 mA, device not switching, all other channels disabled ILOAD2 = 0 mA, device not switching, all other channels disabled ILOAD1 = ILOAD2 = 0 mA, device not switching, LDO channels disabled PSM to PWM operation VIN1 = VIN2 = 3.6 V; LFCSP package VIN1 = VIN2 = 3.6 V; LFCSP package VIN1 = VIN2 = 5.5 V; LFCSP package VIN1 = VIN2 = 5.5 V; LFCSP package VIN1 = VIN2 = 3.6 V; TSSOP package VIN1 = VIN2 = 3.6 V; TSSOP package VIN1 = VIN2 = 5.5 V; TSSOP package VIN1 = VIN2 = 5.5 V; TSSOP package pFET switch peak current limit VIN1= VIN2 = 3.6 V; Channel disabled 0.491 0.5 0.509 44 μA 55 μA 67 μA 100 mA 155 205 137 162 156 194 137 154 1950 75 3.0 1600 2.5 V 240 310 204 243 237 270 202 212 2300 3.5 mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mA Ω MHz All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO1 AND LDO2 SPECIFICATIONS VIN3 = (VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, VIN4 = (VOUT4 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT = 1 µF; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1 Table 4. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Bias Current per LDO 2 Total System Input Current LDO1 or LDO2 Only LDO1 and LDO2 Only Symbol VIN3, VIN4 Test Conditions/Comments IVIN3BIAS/IVIN4BIAS IOUT3 = IOUT4 = 0 µA IOUT3 = IOUT4 = 10 mA IOUT3 = IOUT4 = 300 mA Includes all current into AVIN, VIN1, VIN2, VIN3, and VIN4 IOUT3 = IOUT4 = 0 µA, all other channels disabled IOUT3 = IOUT4 = 0 µA, buck channels disabled IIN Rev. E | Page 5 of 28 Min 1.7 Typ Max 5.5 Unit V 10 60 165 30 100 245 µA µA µA 53 74 µA µA ADP5034 Parameter OUTPUT CHARACTERISTICS Output Voltage Accuracy Line Regulation Load Regulation 3 VOLTAGE FEEDBACK DROPOUT VOLTAGE 4 CURRENT-LIMIT THRESHOLD 5 ACTIVE PULL-DOWN OUTPUT NOISE Regulator LDO1 Regulator LDO2 POWER SUPPLY REJECTION RATIO Regulator LDO1 Data Sheet Symbol Test Conditions/Comments Min ΔVOUT3/VOUT3, ΔVOUT4/VOUT4 (ΔVOUT3/VOUT3)/ΔVIN3, (ΔVOUT4/VOUT4)/ΔVIN4 (ΔVOUT3/VOUT3)/ΔIOUT3, (ΔVOUT4/VOUT4)/ΔIOUT4 100 µA < IOUT3 < 300 mA, 100 µA < IOUT4 < 300 mA IOUT3 = IOUT4 = 1 mA Max Unit −1.8 +1.8 % −0.03 +0.03 %/V 0.001 0.003 %/mA 0.509 Channel disabled 0.5 50 75 100 180 600 600 V mV mV mV mV mA Ω 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 10 Hz to 100 kHz, VIN4 = 5 V, VOUT4 = 1.2 V 100 60 µV rms µV rms 10 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 1 MHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 10 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 100 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 1 MHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA 60 62 63 54 57 64 dB dB dB dB dB dB IOUT3 = IOUT4 = 1 mA to 300 mA VFB3, VFB4 VDROPOUT ILIMIT3, ILIMIT4 RPDWN-L NOISELDO1 NOISELDO2 PSRR Regulator LDO2 0.491 VOUT3 = VOUT4 = 5.2 V, IOUT3 = IOUT4 = 300 mA VOUT3 = VOUT4 = 3.3 V, IOUT3 = IOUT4 = 300 mA VOUT3 = VOUT4 = 2.5 V, IOUT3 = IOUT4 = 300 mA VOUT3 = VOUT4 = 1.8 V, IOUT3 = IOUT4 = 300 mA 335 Typ 140 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). This is the input current into VIN3/VIN4, which is not delivered to the output load. 3 Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. 1 2 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS TA = −40°C to +125°C, unless otherwise specified. Table 5. Parameter NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2 Input Capacitor Ratings BUCK1, BUCK2 Output Capacitor Ratings LDO1, LDO2 1 Input and Output Capacitor Ratings CAPACITOR ESR 1 Symbol Min CMIN1, CMIN2 CMIN1, CMIN2 CMIN3, CMIN4 RESR 4.7 10 1.0 0.001 Typ Max Unit 40 40 µF µF µF Ω 1 The minimum input and output capacitance should be greater than 1.0 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics. Rev. E | Page 6 of 28 Data Sheet ADP5034 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVIN to AGND VIN1, VIN2 to AVIN PGND1, PGND2 to AGND VIN3, VIN4, VOUT1, VOUT2, FB1, FB2, FB3, FB4, EN1, EN2, EN3, EN4, MODE to AGND VOUT3 to AGND VOUT4 to AGND SW1 to PGND1 SW2 to PGND2 Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to (AVIN + 0.3 V) −0.3 V to (VIN3 + 0.3 V) −0.3 V to (VIN4 + 0.3 V) −0.3 V to (VIN1 + 0.3 V) −0.3 V to (VIN2 + 0.3 V) −65°C to +150°C −40°C to +125°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type 24-Lead, 0.5 mm pitch LFCSP 28-Lead TSSOP ESD CAUTION JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For detailed information on power dissipation, see the Power Dissipation and Thermal Considerations section. Rev. E | Page 7 of 28 θJA 35 36 θJC 3 5 Unit °C/W °C/W ADP5034 Data Sheet 1 2 3 4 5 6 PIN 1 INDICATOR ADP5034 TOP VIEW (Not to Scale) 18 17 16 15 14 13 AGND AVIN VIN1 SW1 PGND1 MODE EN2 FB2 VOUT2 VOUT1 FB1 EN1 7 8 9 10 11 12 FB4 EN4 VIN2 SW2 PGND2 NC 28 VIN3 27 VOUT3 VOUT4 3 26 FB3 NC 4 25 NC FB4 5 ADP5034 24 AGND EN4 6 TOP VIEW (Not to Scale) 23 AVIN VIN2 7 22 VIN1 SW2 8 21 SW1 PGND2 9 20 PGND1 NC 10 19 MODE NC 11 18 NC EN2 12 17 EN1 FB2 13 16 FB1 VOUT2 14 15 VOUT1 NOTES 1. NC = NOT INTERNALLY CONNECTED. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE. 09703-003 NOTES 1. NC = NOT INTERNALLY CONNECTED. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE. EN3 1 VIN4 2 Figure 2. LFCSP Pin Configuration—View from the Top of the Die 09703-100 24 23 22 21 20 19 VOUT4 VIN4 EN3 VIN3 VOUT3 FB3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. TSSOP Pin Configuration—View from the Top of the Die Table 8. Pin Function Descriptions LFCSP 1 2 3 4 5 6 Pin No. TSSOP 5 Mnemonic FB4 EN4 VIN2 SW2 PGND2 NC 7 8 6 7 8 9 4, 10, 11, 18, 25 12 13 9 10 11 14 15 16 VOUT2 VOUT1 FB1 12 13 17 19 EN1 MODE 14 15 16 17 18 19 20 21 22 23 24 26 PGND1 SW1 VIN1 AVIN AGND FB3 20 21 22 23 24 EPAD 27 28 1 2 3 EPAD VOUT3 VIN3 EN3 VIN4 VOUT4 EP EN2 FB2 Description LDO2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the LDO2 resistor divider. For device models with a factory programmed output voltage, connect FB4 to the top of the capacitor on VOUT4. LDO2 Enable Pin. High level turns on this regulator, and low level turns it off. BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN. BUCK2 Switching Node. Dedicated Power Ground for BUCK2. No Connect. Leave this pin unconnected or connect to ground. BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off. BUCK2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2. BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1. BUCK1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off. BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation. Dedicated Power Ground for BUCK1. BUCK1 Switching Node. BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN. Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2. Analog Ground. LDO1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the LDO1 resistor divider. For device models with a factory programmed output voltage, connect FB3 to the top of the capacitor on VOUT3. LDO1 Output Voltage. LDO1 Input Supply (1.7 V to 5.5 V). LDO1 Enable Pin. High level turns on this regulator, and low level turns it off. LDO2 Input Supply (1.7 V to 5.5 V). LDO2 Output Voltage. Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane. Rev. E | Page 8 of 28 Data Sheet ADP5034 TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3= VIN4 = 3.6 V, TA = 25°C, unless otherwise noted. 3.320 3.315 3.310 120 TA = –40°C 3.305 100 VOUT (V) QUIESCENT CURRENT (µA) 140 80 60 3.300 TA = +25°C 3.295 3.290 3.285 TA = +85°C 40 3.280 20 3.3 3.8 4.3 4.8 5.3 INPUT VOLTAGE (V) 3.270 0.2 0 0.4 0.6 0.8 1.0 1.2 IOUT (A) Figure 4. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.2 V, VOUT4 = 3.3 V, All Channels Unloaded 09703-101 2.8 09703-039 3.275 0 2.3 Figure 7. BUCK1 Load Regulation Across Temperature, VIN = 4.2 V, VOUT1 = 3.3 V, PWM Mode 1.812 T 1.810 TA = –40°C SW 4 1.808 IOUT 2 VOUT (V) TA = +25°C VOUT 1.806 1.804 1 EN 1.802 TA = +85°C BW BW CH2 50.0mA Ω BW M 40.0µs BW CH4 5.00V T 11.20% A CH3 2.2V 1.798 09703-049 CH1 2.00V CH3 5.00V 0 0.2 0.4 0.6 0.8 1.0 1.2 IOUT (A) Figure 5. BUCK1 Startup, VOUT1 = 1.8 V, IOUT1 = 5 mA 09703-102 1.800 3 Figure 8. BUCK2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT2 = 1.8 V, PWM Mode 0.808 T 0.807 SW 4 0.806 VOUT (V) IOUT 2 VOUT 1 TA = +25°C 0.805 TA = –40°C TA = +85°C 0.804 EN 0.803 BW BW CH2 50.0mA Ω BW M 40.0µs BW CH4 5.00V T 11.20% A CH3 2.2V 0.802 09703-048 CH1 2.00V CH3 5.00V 0 0.2 0.4 0.6 0.8 1.0 IOUT (A) Figure 9. BUCK1 Load Regulation Across Input Voltage, VIN = 3.6 V, VOUT1 = 0.8 V, PWM Mode Figure 6. BUCK2 Startup, VOUT2 = 3.3 V, IOUT2 = 10 mA Rev. E | Page 9 of 28 1.2 09703-103 3 ADP5034 100 VIN = 3.9V 80 80 VIN = 4.2V VIN = 2.3V 70 50 40 20 20 10 10 0 0.001 09703-104 0.1 1 ILOAD (A) 100 90 90 80 80 VIN = 5.5V 70 EFFICIENCY(%) VIN = 3.9V 60 50 40 60 50 VIN = 5.5V VIN = 2.3V VIN = 3.6V 40 20 20 VIN = 4.2V 10 0.01 1 0.1 IOUT (A) 0 0.001 09703-018 0 0.001 100 90 90 80 80 VIN = 2.3V 70 VIN = 5.5V EFFICIENCY (%) VIN = 4.2V VIN = 3.6V 50 40 20 10 10 0 0.001 09703-020 IOUT (A) VIN = 5.5V 40 20 1 VIN = 2.3V 50 30 0.1 1 VIN = 3.6V 60 30 0.01 0.1 Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, Auto Mode 100 70 0.01 IOUT (A) Figure 11. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode 0 0.001 VIN = 4.2V 30 30 60 1 0.1 Figure 13. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, PWM Mode 100 10 0.01 IOUT (A) Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Auto Mode EFFICIENCY (%) 40 30 0.01 VIN = 4.2V 50 30 0 0.001 EFFICIENCY (%) VIN = 5.5V 60 09703-015 EFFICIENCY (%) VIN = 5.5V 60 09703-016 EFFICIENCY (%) 70 70 VIN = 3.6V 90 90 VIN = 4.2V 0.01 0.1 IOUT (A) 1 09703-017 100 Data Sheet Figure 15. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, PWM Mode Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, Auto Mode Rev. E | Page 10 of 28 Data Sheet ADP5034 100 3.3 –40°C 90 3.2 +25°C SCOPE FREQUENCY (MHz) 80 EFFICIENCY (%) 70 60 50 40 30 3.1 3.0 +85°C 2.9 2.8 2.7 20 +25°C +85°C –40°C 2.6 0.1 0.01 1 IOUT (A) 0 0.2 0.4 0.6 0.8 1.0 09703-031 2.5 0 0.001 09703-028 10 1.2 IOUT (A) Figure 19. BUCK2 Switching Frequency vs. Output Current, Across Temperature, VOUT2 = 1.8 V, PWM Mode Figure 16. BUCK1 Efficiency vs. Load Current, Across Temperature, VIN = 3.9 V, VOUT1 = 3.3 V, Auto Mode 100 T 90 +25°C +85°C VOUT 80 1 EFFICIENCY (%) 70 –40°C ISW 60 50 2 40 SW 30 20 10 1 0.1 IOUT (A) Figure 17. BUCK2 Efficiency vs. Load Current, Across Temperature, VOUT2 = 1.8 V, Auto Mode CH2 500mA Ω CH4 2.00V CH1 50.0mV A CH2 240mA T 28.40% Figure 20. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode 100 T +25°C 90 M 4.00µs 09703-051 0.01 09703-030 4 0 0.001 VOUT 80 1 EFFICIENCY (%) 70 +85°C –40°C 60 ISW 50 2 40 30 SW 20 10 0.1 1 IOUT (A) Figure 18. BUCK1 Efficiency vs. Load Current, Across Temperature, VOUT1 = 0.8 V, Auto Mode CH1 50.0mV BW CH2 500mA Ω M 4.00µs A CH2 BW CH4 2.00V T 28.40% 220mA 09703-050 0.01 09703-029 4 0 0.001 Figure 21. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Auto Mode Rev. E | Page 11 of 28 ADP5034 Data Sheet T T VOUT 1 VIN ISW VOUT 2 1 SW SW 4 3 CH2 500mA Ω M 400ns A CH2 BW CH4 2.00V T 28.40% BW 220mA CH1 50.0mV CH3 1.00V BW BW M 1.00ms CH4 2.00V A CH3 4.80V BW T 30.40% Figure 22. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode 09703-041 CH1 50mV 09703-053 4 Figure 25. BUCK2 Response to Line Transient, VIN2 = 4.5 V to 5.0 V, VOUT2 = 1.8 V, PWM Mode T T SW VOUT 1 4 ISW 2 VOUT 1 SW IOUT 4 M 400ns A CH2 CH2 500mA Ω BW CH4 2.00V T 28.40% BW 220mA CH1 50.0mV Figure 23. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode BW CH2 50.0mA Ω BW M 20.0µs A CH2 BW T 60.000µs CH4 5.00V 356mA 09703-044 CH1 50mV 09703-052 2 Figure 26. BUCK1 Response to Load Transient, IOUT1 from 1 mA to 50 mA, VOUT1 = 3.3 V, Auto Mode T T SW 4 VIN VOUT VOUT 1 1 SW IOUT 3 BW BW M 1.00ms CH4 2.00V BW T 30.40% A CH3 4.80V CH1 50.0mV Figure 24. BUCK1 Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, PWM Mode BW CH2 50.0mA Ω BW M 20.0µs A CH2 BW CH4 5.00V T 22.20% 379mA 09703-043 CH1 50.0mV CH3 1.00V 09703-040 2 Figure 27. BUCK2 Response to Load Transient, IOUT2 from 1 mA to 50 mA, VOUT2 = 1.8 V, Auto Mode Rev. E | Page 12 of 28 Data Sheet ADP5034 T SW EN 4 2 VOUT 1 VOUT 3 IOUT IIN 2 BW CH2 200mA Ω CH4 5.00V BW M 20.0µs A CH2 408mA BW T 20.40% CH1 100mA CH2 5V CH3 1V M40µs 2.50GS/s T 159.40µs A CH2 4.20V 09703-105 CH1 50.0mV 09703-045 1 Figure 31. LDO Startup, VOUT3 = 1.8 V Figure 28. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA, VOUT1 = 3.3 V, Auto Mode 3.3160 T 3.3155 SW 3.3150 4 VIN = 5.5V VOUT (V) 3.3145 VOUT 1 3.3140 3.3135 VIN = 4.2V 3.3130 3.3125 IOUT VIN = 3.8V 3.3120 2 3.3115 CH2 200mA Ω CH4 5.00V BW M 20.0µs A CH2 88.0mA BW T 19.20% 0 09703-046 BW 50 100 150 200 250 09703-106 3.3110 CH1 100mV 300 IOUT (mA) Figure 32. LDO Load Regulation Across Input Voltage, VOUT3 = 3.3 V Figure 29. BUCK2 Response to Load Transient, IOUT2 from 20 mA to 180 mA, VOUT2 = 1.8 V, Auto Mode 400 T VOUT2 350 2 300 SW1 RDSON (mΩ) +125°C 3 VOUT1 1 250 +25°C 200 150 –40°C SW2 100 BW BW CH2 5.00V CH4 5.00V BW M 400ns BW T 50.00% A CH4 1.90V 0 2.3 09703-060 CH1 5.00V CH3 5.00V 2.8 3.3 3.8 4.3 INPUT VOLTAGE (V) Figure 30. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode Showing Out-of-Phase Operation 4.8 5.3 09703-037 50 4 Figure 33. LFCSP NMOS RDSON vs. Input Voltage Across Temperature Rev. E | Page 13 of 28 ADP5034 Data Sheet 250 50 45 200 40 +125°C GROUND CURRENT (µA) RDSON (mΩ) +25°C 150 –40°C 100 35 30 25 20 15 50 10 3.3 3.8 4.3 4.8 5.3 INPUT VOLTAGE (V) 0 09703-038 2.8 0 0.10 0.05 0.15 0.20 09703-036 5 0 2.3 0.25 LOAD CURRENT (A) Figure 34. LFCSP PMOS RDSON vs. Input Voltage Across Temperature Figure 37. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V 1.802 T 1.801 TA = –40°C 1.800 IOUT VOUT (V) 1.799 2 1.798 TA = +25°C 1.797 1.796 1 VOUT 1.795 1.794 TA = +85°C 0 50 150 100 200 250 300 IOUT (mA) CH1 100mV 2.5 VOUT (V) 2.0 IOUT = 10mA CH2 100mA Ω BW M 40.0µs A CH2 52.0mA T 19.20% Figure 35. LDO Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 1.8 V 3.0 BW 09703-047 1.792 09703-107 1.793 Figure 38. LDO Response to Load Transient, IOUT3 from 1 mA to 80 mA, VOUT3 = 2.8 V IOUT = 100µA T IOUT = 1mA IOUT = 100mA IOUT = 150mA IOUT = 300mA VIN 1.5 VOUT 1 2 1.0 0.5 VIN (V) Figure 36. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V CH1 20.0mV CH3 1.00V M 100µs T 28.40% A CH3 4.80V 09703-042 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 09703-034 3 Figure 39. LDO Response to Line Transient, Input Voltage from 4.5 V to 5 V, VOUT3 = 2.8 V Rev. E | Page 14 of 28 Data Sheet ADP5034 60 0 VIN = 5V 55 –20 VIN = 3.3V –40 PSRR (dB) 45 40 –60 –80 35 –100 30 0.01 0.1 1 10 –120 10 09703-055 25 0.001 100 ILOAD (mA) Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 2.8 V 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 43. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V 0 65 VIN = 5V 60 –20 VIN = 3.3V 55 100µA 1mA 10mA 50mA 100mA 150mA –40 50 PSRR (dB) RMS NOISE (µV) 100µA 1mA 10mA 50mA 100mA 150mA 09703-058 RMS NOISE (µV) 50 45 40 –60 –80 35 0.01 0.1 1 ILOAD (mA) 10 –120 10 09703-056 100 Figure 41. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 3.0 V –20 10k 100k FREQUENCY (Hz) 1M 10M 0 100µA 1mA 10mA 50mA 100mA 150mA –10 –20 –30 PSRR (dB) –40 –50 –60 –50 –60 –70 –80 –80 –90 –90 –100 10 –100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 42. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V 100µA 1mA 10mA 50mA 100mA 150mA –40 –70 09703-057 PSRR (dB) –30 1k Figure 44. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2.8 V 0 –10 100 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 45. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V Rev. E | Page 15 of 28 09703-061 25 0.001 09703-059 –100 30 ADP5034 Data Sheet THEORY OF OPERATION VOUT1 FB1 FB2 VOUT2 GM ERROR AMP AVIN ENBK1 75Ω 75Ω ENBK2 GM ERROR AMP PWM COMP PWM COMP VIN1 SOFT START SOFT START PSM COMP PSM COMP VIN2 ILIMIT ILIMIT LOW CURRENT PWM/ PSM CONTROL BUCK2 PWM/ PSM CONTROL BUCK1 LOW CURRENT SW2 SW1 OSCILLATOR DRIVER AND ANTISHOOT THROUGH DRIVER AND OP ANTISHOOT MODE THROUGH SYSTEM UNDERVOLTAGE LOCKOUT SEL THERMAL SHUTDOWN PGND1 Y B PGND2 MODE2 ENLDO2 600Ω A MODE EN2 EN3 EN4 ENBK1 ENABLE AND MODE CONTROL ENBK2 LDO UNDERVOLTAGE LOCKOUT ENLDO1 ENLDO2 LDO UNDERVOLTAGE LOCKOUT R1 AVIN R3 LDO CONTROL AVIN R2 ADP5034 VIN3 AGND 600Ω FB3 VOUT3 VIN4 LDO CONTROL ENLDO1 R4 FB4 VOUT4 09703-005 EN1 Figure 46. Functional Block Diagram POWER MANAGEMENT UNIT The ADP5034 is a micropower management unit (micro PMU) combining two step-down (buck) dc-to-dc converters and two low dropout linear regulators (LDOs). The high switching frequency and tiny 24-lead LFCSP package allow for a small power management solution. To combine these high performance regulators into the micro PMU, there is a system controller allowing them to operate together. The buck regulators can operate in forced PWM mode if the MODE pin is at a logic high level. In forced PWM mode, the buck switching frequency is always constant and does not change with the load current. If the MODE pin is at logic low level, the switching regulators operate in auto PWM/PSM mode. In this mode, the regulators operate at fixed PWM frequency when the load current is above the PSM current threshold. When the load current falls below the PSM current threshold, the regulator in question enters PSM, where the switching occurs in bursts. The burst repetition rate is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. The auto PWM/PSM mode transition is controlled independently for each buck regulator. The two bucks operate synchronized to each other. The ADP5034 has individual enable pins (EN1 to EN4) controlling the activation of each regulator. The regulators are activated by a logic level high applied to the respective EN pin. EN1 controls BUCK1, EN2 controls BUCK2, EN3 controls LDO1, and EN4 controls LDO2. Regulator output voltages are set through external resistor dividers or can be optionally factory programmed to default values (see the Ordering Guide section). When a regulator is turned on, the output voltage ramp rate is controlled through a soft start circuit to avoid a large inrush current due to the charging of the output capacitors. Rev. E | Page 16 of 28 Data Sheet ADP5034 Thermal Protection In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off all the regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20°C hysteresis is included so that when thermal shutdown occurs, the regulators do not return to operation until the on-chip temperature drops below 130°C. When coming out of thermal shutdown, all regulators restart with soft start control. Undervoltage Lockout To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated into the system. If the input voltage on AVIN drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for 5 V supply applications. For these models, the device reaches the turn-off threshold when the input supply drops to 3.65 V typical. In case of a thermal or UVLO event, the active pull-downs (if factory enabled) are enabled to discharge the output capacitors quickly. The pull-down resistors remain engaged until the thermal fault event is no longer present or the input supply voltage falls below the VPOR voltage level. The typical value of VPOR is approximately 1 V. Enable/Shutdown The ADP5034 has an individual control pin for each regulator. A logic level high applied to the ENx pin activates a regulator, whereas a logic level low turns off a regulator. Figure 47 shows the regulator activation timings for the ADP5034 when all enable pins are connected to AVIN. Also shown is the active pull-down activation. VUVLO AVIN VPOR VOUT1 VOUT3 VOUT4 VOUT2 30µs (MIN) 30µs (MIN) 50µs (MIN) 50µs (MIN) BUCK1, LDO1, LDO2 PULL-DOWNS 09703-006 BUCK2 PULL-DOWN Figure 47. Regulator Sequencing on the ADP5034 (EN1 = EN2 = EN3 = EN4 = VAVIN) Rev. E | Page 17 of 28 ADP5034 Data Sheet BUCK1 AND BUCK2 The buck uses a fixed frequency and high speed current mode architecture. The buck operates with an input voltage of 2.3 V to 5.5 V. The buck output voltage is set through external resistor dividers, shown in Figure 48 for BUCK1. The output voltage can optionally be factory programmed to default values as indicated in the Ordering Guide section. In this event, R1 and R2 are not needed, and FB1 can be left unconnected. In all cases, VOUT1 must be connected to the output capacitor. FB1 is 0.5 V. VOUT1 VIN1 SW1 L1 1µH VOUT1 BUCK AGND R1 C5 10µF R1 +1 VOUT1 = VFB1 R2 The ADP5034 has a dedicated MODE pin controlling the PSM and PWM operation. A high logic level applied to the MODE pin forces both bucks to operate in PWM mode. A logic level low sets the bucks to operate in auto PSM/PWM. PSM Current Threshold The PSM current threshold is set to100 mA. The bucks employ a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to and exit from the PSM. The PSM current threshold is optimized for excellent efficiency over all load currents. Oscillator/Phasing of Inductor Switching R2 The ADP5034 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. 09703-008 FB1 drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold. Figure 48. BUCK1 External Output Voltage Setting Control Scheme The bucks operate with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency but shift to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. PWM Mode In PWM mode, the bucks operate at a fixed frequency of 3 MHz set by an internal oscillator. At the start of each oscillator cycle, the pFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pFET switch and turns on the nFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold. Power Save Mode (PSM) The bucks smoothly transition to PSM operation when the load current decreases below the PSM current threshold. When either of the bucks enters PSM, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device Additionally, the ADP5034 ensures that when both bucks are in PWM mode, they operate out of phase, whereby the Buck2 pFET starts conducting exactly half a clock period after the BUCK1 pFET starts conducting. Short-Circuit Protection The bucks include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. Soft Start The bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Current Limit Each buck has protection circuitry to limit the amount of positive current flowing through the pFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% Duty Operation With a drop in input voltage, or with an increase in load current, the buck may reach a limit where, even with the pFET switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the pFET switch stays on 100% of the time. When Rev. E | Page 18 of 28 Data Sheet ADP5034 Active Pull-Downs All regulators have optional, factory programmable, active pulldown resistors discharging the respective output capacitors when the regulators are disabled. The pull-down resistors are connected between VOUTx and AGND. Active pull-downs are disabled when the regulators are turned on. The typical value of the pull-down resistor is 600 Ω for the LDOs and 75 Ω for the bucks. Figure 47 shows the activation timings for the active pull-downs during regulator activation and deactivation. Each LDO output voltage is set through external resistor dividers as shown in Figure 49 for LDO1. The output voltage can optionally be factory programmed to default values as indicated in the Ordering Guide section. In this event, Ra and Rb are not needed, and FB3 must be connected to the top of the capacitor on VOUT3. VOUT3 VIN3 LDO1 VOUT3 = VFB3 Each LDO operates with an input voltage of 1.7 V to 5.5 V. The wide operating range makes these LDOs suitable for cascading configurations where the LDO supply voltage is provided from one of the buck regulators. Ra Rb LDO1 AND LDO2 The ADP5034 contains two LDOs with low quiescent current and low dropout linear regulators, and provides up to 300 mA of output current. Drawing a low 10 μA quiescent current (typical) at no load makes the LDO ideal for battery-operated portable equipment. FB3 VOUT3 C7 1µF Ra +1 Rb 09703-009 the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. Figure 49. LDO1 External Output Voltage Setting The LDOs also provide high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with only a small 1 µF ceramic input and output capacitor. LDO1 is optimized to supply analog circuits because it offers better noise performance compared to LDO2. LDO1 should be used in applications where noise performance is critical. Rev. E | Page 19 of 28 ADP5034 Data Sheet APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure 1. Feedback Resistors For the adjustable model, referring to Figure 50 the total combined resistance for R1 and R2 is not to exceed 400 kΩ. Inductor The high switching frequency of the ADP5034 bucks allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 9. The peak-to-peak inductor current ripple is calculated using the following equation: I RIPPLE = VOUT × (VIN − VOUT ) VIN × f SW × L The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COUT × (1 − TEMPCO) × (1 − TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is 9.2 μF at 1.8 V, as shown in Figure 50. where: fSW is the switching frequency. L is the inductor value. The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation: I PEAK = I LOAD( MAX ) + Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. I RIPPLE 2 Substituting these values in the equation yields CEFF = 9.2 μF × (1 − 0.15) × (1 − 0.1) ≈ 7.0 μF To guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 12 Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the bucks are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI. CAPACITANCE (µF) 10 8 6 4 Output Capacitor Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. 0 0 1 2 3 4 5 DC BIAS VOLTAGE (V) 6 09703-010 2 Figure 50. Capacitance vs. Voltage Characteristic Table 9. Suggested 1.0 μH Inductors Vendor Murata Murata Murata Taiyo Yuden Coilcraft® Coilcraft Toko Model LQM2MPN1R0NG0B LQM2HPN1R0MJ0L LQH32PN1R0NN0 CBC3225T1R0MR XFL4020-102ME XPL2010-102ML MDT2520-CN Dimensions (mm) 2.0 × 1.6 × 0.9 2.5× 2.0 × 1.1 3.2 × 2.5 × 1.6 3.2 × 2.5 × 2.5 4.0 × 4.0 × 2.1 1.9 × 2.0 × 1.0 2.5 × 2.0 × 1.2 Rev. E | Page 20 of 28 ISAT (mA) 1400 1500 2300 2000 5400 1800 1350 DCR (mΩ) 85 90 45 71 11 89 85 Data Sheet ADP5034 To minimize supply noise, place the input capacitor as close as possible to the VINx pin of the buck. As with the output capacitor, a low ESR capacitor is recommended. The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 µF and a maximum of 10 µF. A list of suggested capacitors is shown in Table 10 and Table 11. VIN I RIPPLE ≈ 8 × f SW × COUT (2π × f SW )2 × L × COUT Capacitors with lower effective series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: ESRCOUT ≤ Table 10. Suggested 10 μF Capacitors VRIPPLE I RIPPLE Vendor Murata TDK Taiyo Yuden Panasonic The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 µF and a maximum of 40 µF. The buck regulators require 10 µF output capacitors to guarantee stability and response to rapid load variations and to transition into and out of the PWM/PSM modes. A list of suggested capacitors is shown in Table 10. In certain applications where one or both buck regulator powers a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 µF to 4.7 µF because the regulator does not expect a large load variation when working in PSM mode (see Figure 51). Vendor Murata Taiyo Yuden Panasonic Vendor Murata Murata TDK Panasonic Taiyo Yuden VOUT (VIN − VOUT ) VIN AVIN 2.3V TO 5.5V Type X5R X5R X5R X5R X5R SW1 BUCK1 EN1 EN1 FB1 PGND1 L1 1µH R1 R2 MODE MODE SW2 C2 4.7µF BUCK2 EN2 ON EN3 EN2 EN3 VIN3 C3 1µF ON OFF VIN4 C4 1µF PSM/PWM FB2 PGND2 L2 1µH VOUT2 @ 1200mA R3 R4 C6 10µF VOUT3 LDO1 (ANALOG) FB3 R5 R6 EN4 VOUT1 @ 1200mA C5 10µF VOUT2 VIN2 1.7V TO 5.5V Model GRM155B30J105K GRM155R61A105KE15D C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F PWM MODE OFF Model GRM188R60J475ME19D JMK107BJ475 ECJ-0EB0J475M VOUT1 C1 4.7µF ON Type X5R X5R X5R HOUSEKEEPING VIN1 OFF Voltage Rating (V) 6.3 6.3 6.3 6.3 Case Size 0402 0402 0402 Voltage Rating (V) 6.3 6.3 6.3 Case Size 0402 0402 0402 0402 0402 Voltage Rating (V) 6.3 10.0 6.3 6.3 10.0 Table 12. Suggested 1.0 μF Capacitors Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: CAVIN 0.1µF Model GRM188R60J106 C1608JB0J106K JMK107BJ106MA-T ECJ1VB0J106M Case Size 0603 0603 0603 0603 Table 11. Suggested 4.7 μF Capacitors Input Capacitor I CIN ≥ I LOAD( MAX ) Type X5R X5R X5R X5R VOUT3 @ 300mA C7 1µF VOUT4 EN4 LDO2 (DIGITAL) FB4 R7 R8 VOUT4 @ 300mA C8 1µF ADP5034 AGND Figure 51. Processor System Power Management with PSM/PWM Control Rev. E | Page 21 of 28 09703-021 VRIPPLE = ADP5034 Data Sheet LDO EXTERNAL COMPONENT SELECTION 1.2 Feedback Resistors The ADP5034 LDOs are designed for operation with small, spacesaving ceramic capacitors, but function with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended to ensure that stability of the ADP5034. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP5034 to large changes in load current. Input Bypass Capacitor Connecting a 1 µF capacitor from VIN3 and VIN4 to ground reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance is encountered. If greater than 1 µF of output capacitance is required, increase the input capacitor to match it. Input and Output Capacitor Properties Use any good quality ceramic capacitors with the ADP5034 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 52 depicts the capacitance vs. voltage bias characteristic of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating. 0.8 0.6 0.4 0.2 0 0 1 2 3 4 DC BIAS VOLTAGE (V) 5 6 09703-012 Output Capacitor CAPACITANCE (µF) 1.0 For the adjustable model, the maximum value of Rb is not to exceed 200 kΩ (see Figure 49). Figure 52. Capacitance vs. Voltage Characteristic Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage: CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.85 μF at 1.8 V as shown in Figure 52. Substituting these values into the following equation, CEFF = 0.85 μF × (1 − 0.15) × (1 − 0.1) = 0.65 μF Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5034, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Rev. E | Page 22 of 28 Data Sheet ADP5034 POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5034 is a highly efficient µPMU, and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach the maximum allowable operating limit (125°C). When the temperature exceeds 150°C, the ADP5034 turns off all the regulators, allowing the device to cool down. When the die temperature falls below 130°C, the ADP5034 resumes normal operation. This section provides guidelines to calculate the power dissipated in the device and ensure that the ADP5034 operates below the maximum allowable junction temperature. The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (3) where: PDBUCK is the power dissipation on one of the ADP5034 buck regulators. PL is the inductor power losses. The inductor losses are external to the device, and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by PL ≈ IOUT1(RMS)2 × DCRL The efficiency for each regulator on the ADP5034 is given by P η = OUT × 100% PIN BUCK REGULATOR POWER DISSIPATION (1) where: η is the efficiency. PIN is the input power. POUT is the output power. (4) where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator. I OUT 1( RMS ) = I OUT1 × 1 + r 12 (5) where r is the normalized inductor ripple current. r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) Power loss is given by PLOSS = PIN − POUT (2a) PLOSS = POUT (1− η)/η (2b) or Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and all the outputs. Perform the measurements at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor and, from this, use Equation 3 to calculate the power dissipation in the ADP5034 buck converter. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, and the power lost on each LDO can be calculated using Equation 12. When the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor, use Equation 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the two LDOs to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. (6) where: L is the inductance. fSW is the switching frequency. D is the duty cycle. D = VOUT1/VIN1 (7) ADP5034 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator. PDBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the P-MOSFET and the N-MOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT1(RMS)2 (9) where RDSON-P is approximately 0.2 Ω, and RDSON-N is approximately 0.16 Ω at 25°C junction temperature and VIN1 = VIN2 = 3.6 V. At VIN1 = VIN2 = 2.3 V, these values change to 0.31 Ω and 0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V, the values are 0.16 Ω and 0.14 Ω, respectively. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDO provided by Equation 12. Rev. E | Page 23 of 28 ADP5034 Data Sheet Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) where: CGATE-P is the P-MOSFET gate capacitance. CGATE-N is the N-MOSFET gate capacitance. The transition losses occur because the P-channel power MOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near VOUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW. For the ADP5034, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, a sufficient safety margin should be included in the estimate. LDO Regulator Power Dissipation The power loss of a LDO regulator is given by PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND) In cases where the board temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) For the ADP5034, the total of (CGATE-P + CGATE-N) is approximately 150 pF. PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW JUNCTION TEMPERATURE (12) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Refer to Table 7 for the thermal resistance values of the LFCSP and TSSOP packages. A very important factor to consider is that θJA is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. It is important to maximize the copper used to remove the heat from the device. Copper exposed to air dissipates heat better than copper used in the inner layers. The exposed pad should be connected to the ground plane with several vias. If the case temperature can be measured, the junction temperature is calculated by TJ = TC + (PD × θJC) (15) where TC is the case temperature and θJC is the junction-to-case thermal resistance provided in Table 7. When designing an application for a particular ambient temperature range, calculate the expected ADP5034 power dissipation (PD) due to the losses of all channels by using the Equation 8 to Equation 13. From this power calculation, the junction temperature, TJ, can be estimated using Equation 14. The reliable operation of the converter and the two LDO regulators can be achieved only if the estimated die junction temperature of the ADP5034 (Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) are highly affected by increasing the junction temperature. Additional information about product reliability can be found from the ADI Reliability Handbook, which can be found at www.analog.com/reliability_handbook. Power dissipation due to the ground current is small and it can be ignored. The total power dissipation in the ADP5034 simplifies to PD = PDBUCK1 + PDBUCK2 + PDLDO1 + PDLDO2 (14) (13) Rev. E | Page 24 of 28 Data Sheet ADP5034 PCB LAYOUT GUIDELINES Poor layout can affect ADP5034 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to the UG-271 and UG-439 user guide. • • • • • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Rev. E | Page 25 of 28 Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Connect VIN1, VIN2, and AVIN together close to the IC using short tracks. ADP5034 Data Sheet TYPICAL APPLICATION SCHEMATICS AVIN CAVIN 0.1µF HOUSEKEEPING VOUT1 VIN1 2.3V TO 5.5V SW1 C1 4.7µF ON OFF BUCK1 EN1 EN1 L1 1µH C5 10µF PGND1 MODE PWM MODE MODE SW2 C2 4.7µF BUCK2 EN2 ON EN3 EN2 EN3 VIN3 1.7V TO 5.5V PSM/PWM VOUT2 VIN2 OFF L2 1µH R3 FB2 PGND2 VOUT3 @ 300mA FB3 C7 1µF EN4 C4 1µF VOUT4 EN4 LDO2 (DIGITAL) VIN4 VOUT4 @ 300mA FB4 C8 1µF 09703-022 ON VOUT2 @ 1200mA C6 10µF VOUT3 LDO1 (ANALOG) C3 1µF OFF VOUT1 @ 1200mA FB1 ADP5034 AGND Figure 53. ADP5034 Fixed Output Voltages with Enable Pins AVIN CAVIN 0.1µF HOUSEKEEPING VOUT1 VIN1 2.3V TO 5.5V SW1 C1 4.7µF ON OFF BUCK1 EN1 EN1 FB1 PGND1 L1 1µH R1 R2 MODE PWM MODE MODE SW2 C2 4.7µF BUCK2 EN2 ON EN3 EN2 EN3 VIN3 C3 1µF ON PGND2 VIN4 VOUT2 @ 1200mA R3 R4 C6 10µF VOUT3 LDO1 (ANALOG) FB3 R5 R6 EN4 OFF C4 1µF FB2 L2 1µH VOUT3 @ 300mA C7 1µF VOUT4 EN4 LDO2 (DIGITAL) FB4 R7 R8 VOUT4 @ 300mA C8 1µF 09703-023 1.7V TO 5.5V PSM/PWM VOUT2 VIN2 OFF VOUT1 @ 1200mA C5 10µF ADP5034 AGND Figure 54. ADP5034 Adjustable Output Voltages with Enable Pins BILL OF MATERIALS Table 13. Reference CAVIN C3, C4, C7, C8 C1, C2 C5, C6 L1, L2 IC1 Value 0.1 µF, X5R, 6.3 V 1 µF, X5R, 6.3 V 4.7 µF, X5R, 6.3 V 10 µF, X5R, 6.3 V 1 µH, 0.18 Ω, 850 mA 1 µH, 0.085 Ω, 1400 mA 1 µH, 0.09 Ω, 1500 mA 1 µH, 0.059 Ω, 900 mA 1 µH, 0.086 Ω, 1350 mA Four-regulator micro PMU Part Number JMK105BJ104MV-F LMK105BJ105MV-F ECJ-0EB0J475M JMK107BJ106MA-T BRC1608T1R0M LQM2MPN1R0NG0B LQM2HPN1R0MJ0L EPL2014-102ML MDT2520-CN ADP5034 Rev. E | Page 26 of 28 Vendor Taiyo-Yuden Taiyo-Yuden Panasonic-ECG Taiyo-Yuden Taiyo-Yuden Murata Murata Coilcraft Toko Analog Devices Package or Dimension (mm) 0402 0402 0402 0603 0603 2.0 × 1.6 × 0.9 2.5 × 2.0 × 1.1 2.0 × 2.0 × 1.4 2.5 × 2.0 × 1.2 24-lead LFCSP Data Sheet ADP5034 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 13 12 2.20 2.10 SQ 2.00 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-11-2012-A COPLANARITY 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. Figure 55. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-10) Dimensions shown in millimeters 9.80 9.70 9.60 3.55 3.50 3.45 15 28 4.50 4.40 4.30 1 14 BOTTOM VIEW 1.05 1.00 0.80 1.20 MAX SEATING PLANE COPLANARITY 0.10 0.65 BSC 0.30 0.19 8° 0° 0.20 0.09 0.75 0.60 0.45 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-153-AET Figure 55. 28-Lead Thin Shrink Small Outline with Exposed Pad Package [TSSOP_EP] 9.7 mm × 6.4 mm Body, (RE-28-1) Dimensions shown in millimeters Rev. E | Page 27 of 28 02-23-2012-A TOP VIEW 0.15 0.05 3.05 3.00 2.95 EXPOSED PAD (Pins Up) 6.40 BSC ADP5034 Data Sheet ORDERING GUIDE Model 1 ADP5034ACPZ-R2 Temperature Range −40°C to +125°C Output Voltage (V) 2 Adjustable UVLO 3 Low ADP5034ACPZ-R7 −40°C to +125°C Adjustable Low ADP5034ACPZ-1-R7 −40°C to +125°C Low ADP5034ACPZ-2-R7 −40°C to +125°C VOUT1 = 1.2 V VOUT2 = 3.3 V VOUT3 = 2.8 V VOUT4 = 1.8 V Adjustable High ADP5034ACPZ-3-R7 −40°C to +125°C Adjustable High ADP5034AREZ −40°C to +125°C Adjustable Low ADP5034AREZ-R7 −40°C to +125°C Adjustable Low ADP5034AREZ-1 −40°C to +125°C Adjustable High ADP5034AREZ-1-R7 −40°C to +125°C Adjustable High Active PullDown 4 Enabled on buck channels only Enabled on buck channels only Enabled on buck channels only Enabled on buck channels only Enabled on all channels Enabled on all channels Enabled on all channels Enabled on all channels Enabled on all channels ADP5034-1-EVALZ ADP5034RE-EVALZ Package Description 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-24-10 CP-24-10 28-Lead TSSOP Package (TSSOP_EP) RE-28-1 28-Lead TSSOP Package (TSSOP_EP) RE-28-1 28-Lead TSSOP Package (TSSOP_EP) RE-28-1 1 Z = RoHS Compliant Part. 2 For additional options, contact a local sales or distribution representative. Additional options available are: BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, or adjustable. LDO1 and LDO2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2.0 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, 0.8 V, or adjustable. 3 UVLO: low or high. 4 BUCK1, BUCK2, both LDO1 and LDO2: Active pull-down resistor is programmable to be either enabled or disabled. Rev. E | Page 28 of 28 CP-24-10 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 24-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 28-Lead TSSOP Package (TSSOP_EP) Evaluation Board for ADP5034ACPZ-R7 Evaluation Board for ADP5034AREZ-R7 ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09703-0-5/13(E) Package Option CP-24-10 CP-24-10 RE-28-1