Supertex inc. HV9113 High-Voltage, Current-Mode PWM Controller General Description Features ► ► ► ► ► ► ► The Supertex HV9113 is a BiCMOS/DMOS single-output, pulse width modulator IC intended for use in high-speed, high-efficiency switch mode power supplies. It provides all the functions necessary to implement a single-switch current mode PWM, in any topology, with a minimum of external parts. 10 to 120V input voltage range Current-mode control High efficiency Up to 1.0MHz internal oscillator Internal start-up circuit Low internal noise 99% maximum duty cycle Because the HV9113 utilizes Supertex’s proprietary BiCMOS/DMOS technology, it requires less than one tenth of the operating power of conventional bipolar PWM ICs, and can operate at more than twice their switching frequency. The dynamic range for regulation is also increased, to approximately 8 times that of similar bipolar parts. It starts directly from any DC input voltage between 10 and 120VDC, requiring no external power resistor. The output stage is push-pull CMOS and thus requires no clamping diodes for protection, even when significant lead length exists between the output and the external MOSFET. The clock frequency is set with a single external resistor. Applications ► ► ► ► ► DC/DC converters Distributed power systems ISDN equipment PBX systems Modems Accessory functions are included to permit fast remote shutdown (latching or non-latching) and under voltage shutdown. For similar ICs intended to operate directly from up to 450VDC input, please consult the data sheets for the HV9120 and HV9123. For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24. Functional Block Diagram 14 FB COMP 13 DISCHARGE 9 OSC IN 8 OSC OUT 7 Error Amplifier VREF + VDD +VIN 1 2V 4V REF GEN BIAS OSC – 10 Modulator Comparator – + S + To Internal Circuits Current Sources 6 8.1V 8.6V Q 4 5 3 1.2V – + To VDD Current Limit Comparator – 2 – R + OUTPUT -VIN SENSE VDD Undervoltage Comparator Q S R 11 12 SHUTDOWN RESET Pre-regulator/Startup Doc.# DSFP-HV9112 A031314 Supertex inc. www.supertex.com HV9113 Ordering Information Pin Configuration Part Number Package Options Packing HV9112NG-G 14-Lead SOIC (Narrow Body) 53/Tube HV9112NG-G M905 14-Lead SOIC (Narrow Body) 2500/Reel -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value Input voltage, VIN 120V Logic voltage, VDD 15.5V Logic linear input, FB and sense input voltage 14-Lead SOIC (Narrow Body) Product Marking -0.3V to VDD +0.3V Top Marking HV9113NG Operating temperature range -55°C to +125°C YWW Storage temperature range -65°C to +150°C Bottom Marking 750mW CCCCCCCCC AAA Power dissipation LLLLLLLL Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package may or may not include the following marks: Si or 14-Lead SOIC (Narrow Body) Typical Thermal Resistance Package θja 14-Lead Narrow Body SOIC 75°C/W Electrical Characteristics (Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390kΩ, ROSC = 330kΩ, TA = 25°C.) Sym Parameter # Min Typ Max - 3.92 4.00 4.08 - 3.82 4.00 4.16 Units Conditions Reference VREF Output voltage ZOUT Output impedance # 15 30 ISHORT Short circuit current - - ΔVREF Change in VREF with temperature # fMAX Oscillator frequency fOSC Initial accuracy1 - RL = 10MΩ V RL = 10MΩ, TA = -55°C to +125°C 45 kΩ --- 125 250 μA VREF = -VIN - 0.25 - mV/°C - 1.0 3.0 - MHz - 80 100 120 - 160 200 240 Voltage stability - - - 15 % Temperature coefficient # - 170 - ppm/°C TA = -55°C to +125°C Oscillator kHz ROSC = 0Ω ROSC = 330kΩ ROSC = 150kΩ 9.5V< VDD <13.5V TA = -55°C to +125°C Note: # Guaranteed by design. 1. Stray capacitance on OSC In pin must be ≤5pF. Doc.# DSFP-HV9113 A031314 2 Supertex inc. www.supertex.com HV9113 Electrical Characteristics (cont.) (Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390kΩ, ROSC = 330kΩ, TA = 25°C.) Sym Parameter # Min Typ Max Units Conditions Maximum duty cycle # 95 97 99 % --- Deadtime # - 225 - ns --- Minimum duty cycle - - - 0 % --- Maximum pulse width before pulse drops out # - 80 125 ns --- Maximum input signal - 1.0 1.2 1.4 V VFB = 0V Delay to output # - 80 120 ns VSENSE = 1.5V, VCOMP ≤ 2.0V PWM DMAX DMIN Current Limit tD Error Amplifier VFB Feedback voltage - 3.96 4.00 4.04 V VFB shorted to COMP IIN Input bias current - - 25 500 nA VFB = 4.0V VOS Input offset voltage - nulled during trim AVOL Open loop voltage gain # 60 80 GB Unity gain bandwidth # 1.0 1.3 ZOUT Out impedance # Output source current - -1.4 -2.0 - mA VFB = 3.4V Output sink current - 0.12 0.15 - mA VFB = 4.5V Power supply rejection # dB --- ISOURCE ISINK PSRR - --- - dB --- - MHz --- Ω --- see Fig. 1 see Fig. 2 Pre-regulator/Startup +VIN Input voltage - 10 - 120 V IIN < 10µA; VCC > 9.4V +IIN Input leakage current - - - 10 μA VDD > 9.4V VTH Vdd pre-regulator turn-off threshold voltage - 8.0 8.7 9.4 V IPREREG = 10µA Undervoltage lockout - 7.0 8.1 8.9 V --- IDD Supply current - - 0.75 1.0 mA CL < 75pF IQ Quiescent supply current - - 0.55 - mA SHUTDOWN = -VIN IBIAS Nominal bias current - - 20 - μA --- VDD Operating range - 9.0 - 13.5 V --- VLOCK Supply Note: # Guaranteed by design. Not subject to production test. Doc.# DSFP-HV9113 A031314 3 Supertex inc. www.supertex.com HV9113 Electrical Characteristics (cont.) (Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390kΩ, ROSC = 330kΩ, TA = 25°C.) Sym Parameter # Min Typ Max Units Conditions Shutdown Logic tSD SHUTDOWN delay # - 50 100 ns CL = 500pF, VSENSE = -VIN tSW SHUTDOWN pulse width # 50 - - ns --- tRW RESET pulse width # 50 - - ns --- tLW Latching pulse width # 25 - - ns SHUTDOWN and RESET low VIL Input low voltage - - - 2.0 V --- VIH Input high voltage - 7.0 - - V --- IIH Input current, input high voltage - - 1.0 5.0 μA VIN = VDD IIL Input current, input low voltage - - -25 -35 μA VIN = 0V - VDD - 0.25 - - - VDD - 0.3 - - - - - 0.2 - - - 0.3 Pull up - - 15 25 Pull down - - 8.0 20 Pull up - - 20 30 Pull down - - 10 30 Output VOH Output high voltage VOL Output low voltage ROUT Output resistance V IOUT = 10mA IOUT = 10mA, TA = -55°C to 125°C IOUT = -10mA V IOUT = -10mA, TA = -55°C to 125°C Ω IOUT = ±10mA Ω IOUT = ±10mA, TA = -55°C to 125°C tR Rise time # - 30 75 ns CL = 500pF tF Fall time # - 20 75 ns CL = 500pF Note: # Guaranteed by design. Not subject to production test. Truth Table SHUTDOWN RESET H H H H→L L H Off, not latched L L Off, latched L→H L Off, latched, no change Doc.# DSFP-HV9113 A031314 Output Normal operation Normal operation, no change 4 Supertex inc. www.supertex.com HV9113 Test Circuits Error Amp ZOUT +10V (VDD) PSRR 0.1V swept 10Hz - 1.0MHz 1.0V swept 100Hz - 2.2MHz 100K1% 60.4K (FB) + Reference GND (-VIN) 100K1% 10.0V – V1 Tektronix P6021 (1 turn secondary) 4.0V V2 40.2K – + Reference V2 V1 0.1µF 0.1µF NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE ± 1.0mV before connecting transformer Detailed Description Preregulator Bias Circuit The preregulator/startup circuit for the HV9113 consists of a high-voltage n-channel depletion-mode DMOS transistor driven by an error amplifier to form a variable current path between the VIN terminal and the VDD terminal. The maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source(generally the supply the chip is controlling). No current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. An external bias resistor, connected between the BIAS pin and VSS is required by the HV9113 to set currents in a series of current mirrors used by the analog sections of the chip. The nominal external bias current requirement is 15 to 20µA, which can be set by a 390kΩ to 510kΩ resistor if a 10V VDD is used, or a 510kΩ to 680kΩ resistor if VDD will be 12V. A precision resistor is not required; ± 5% is fine. Clock Oscillator The clock oscillator of the HV9113 consists of a ring of CMOS inverters, timing capacitors, and a capacitor discharge FET. A single external resistor between the OSC IN and OSC OUT is required to set the oscillator frequency (see graph). The Discharge pin can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. One major difference exists between the Supertex HV9113 and competitive 9113s. On the Supertex part, the oscillator is shut off when a shutoff command is received. This saves about 150µA of quiescent current, which aids in the construction of power supplies that meet CCITT specification I-430, and in other situations where an absolute minimum of quiescent power dissipation is required. An external capacitor between VDD and VSS is generally required to store energy used by the chip in the time between shutoff of the high voltage path and the VDD supply’s output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, i.e., CSTORAGE ≥ 100 x (gate charge of FET at 10V) as well as very good high frequency characteristics. Stacked polyester or ceramic caps work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor VDD for both the under voltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the under voltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the under voltage lockout always releases before the FET shuts off. Doc.# DSFP-HV9113 A031314 5 Supertex inc. www.supertex.com HV9113 Reference amplifier compensation. It is of mixed CMOS-bipolar construction: A PMOS input stage is used so the common mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity gain stable. The reference of the HV9113 consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier, when connected in a gain of –1 configuration, is as close to 4.0V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be. Current Sense Comparators The HV9113 uses a true dual comparator system with independent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction. A ≈ 50kΩ resistor is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and non-inverting input to the error amplifier). This allows overriding the internal reference with a low impedance voltage source ≤6.0V. Using an external reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage required. Because the reference of the HV9113 is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1µF. Remote Shutdown The SHUTDOWN and RESET pins of the 9113 can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open drain logic. When not used they should be left open, or connected to VDD. Output Buffer The output buffer of the HV9113 is of standard CMOS construction (P-channel pull-up, N-channel pull-down). Thus the body-drain diodes of the output stage can be used for spike clipping if necessary, and external Schottky diode clamping of the output is not required. Error Amplifier The error amplifier in the HV9113 is a true low-power differential input operational amplifier intended for around the Shutdown Timing Waveforms 1.5V tF ≤ 10ns VDD 50% SENSE 50% SHUTDOWN tR ≤ 10ns 0 0 tD VDD OUTPUT tSD VDD 90% OUTPUT 0 VDD SHUTDOWN 0 tSW 50% 90% 0 50% tR, tF ≤ 10ns tLW VDD RESET Doc.# DSFP-HV9113 A031314 50% 50% 0 50% tRW 6 Supertex inc. www.supertex.com HV9113 Typical Performance Curves Fig. 1 Output Switching Frequency vs. Oscillator Resistance Fig. 4 Error Amplifier Output Impedance (Z0) 1M 106 105 104 fOUT (Hz) Z0 (Ω) 10 HV9113 3 102 HV9110, 9111, 9112 100k 10 1.0 100 1k 10k 100k 1M 10k 10k 10M 100k Fig. 2 Fig. 5 PSRR - Error Amplifier and Reference 0 80 -10 70 -20 Gain (dB) PSSR (dB) -30 -40 -50 -60 -70 -80 10 100 1k 10k 100k Error Amplifier Open Loop Gain/Phase 60 180 50 120 40 60 30 0 20 -60 10 -120 0 -180 -10 100 1M 1k 10k Fig. 6 104 10 1M RDISCHARGE vs. tOFF (9113 only) ROSC = 100k VDD = 12V tOFF (nsec) Bias Current (µA) 100 100k Frequency (Hz) Frequency (Hz) Fig. 3 1M ROSC (Ω) Frequency (Hz) Phase (OC) 0.1 VDD = 10V 103 ROSC = 10k 0 5 10 ROSC = 1k 106 102 10-1 107 10 10 2 10 3 104 105 106 RDISCHARGE (Ω) Bias Resistance (Ω) Doc.# DSFP-HV9113 A031314 10 1 7 Supertex inc. www.supertex.com HV9113 14-Lead SOIC (Narrow Body) Package Outline (NG) 8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch D θ1 14 Note 1 (Index Area D/2 x E1/2) E1 E Gauge Plane L2 e 1 L1 b Top View L Seating Plane θ View B View B A h h A A2 Seating Plane A1 Side View View A-A A Note: 1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b 1.35* 0.10 1.25 0.31 - - - - 1.75 0.25 1.65* 0.51 D E E1 8.55* 5.80* 3.80* 8.65 6.00 3.90 8.75* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 L2 θ θ1 0 5O - - 8 15O O 1.04 REF 0.25 BSC O JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-14SOICNG, Version F041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV9113 A031314 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com