12-Bit, 41 MSPS Monolithic ADC AD9042 FEATURES FUNCTIONAL BLOCK DIAGRAM AVCC AIN A1 DVCC TH1 TH2 TH3 A2 ADC VOFFSET VREF ENCODE ENCODE APPLICATIONS 2.4V REFERENCE INTERNAL TIMING GND Cellular/PCS base stations GPS anti jamming receivers Communications receivers Spectrum analyzers Electro-optics Medical imaging ATE DAC ADC AD9042 7 6 DIGITAL ERROR CORRECTION LOGIC MSB LSB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00554-001 41 MSPS minimum sample rate 80 dB spurious-free dynamic range 595 mW power dissipation Single 5 V supply On-chip track-and-hold (T/H) and reference Twos complement output format CMOS-compatible output levels Figure 1. GENERAL DESCRIPTION The AD9042 is a high speed, high performance, low power, monolithic 12-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on chip to provide a complete conversion solution. The AD9042 operates from a single 5 V supply and provides CMOS-compatible digital outputs at 41 MSPS. Designed specifically to address the needs of wideband, multichannel receivers, the AD9042 maintains 80 dB spurious-free dynamic range (SFDR) over a bandwidth of 20 MHz. Noise performance is also exceptional; typical signal-to-noise ratio (SNR) is 68 dB. industrial grade is specified from −40°C to +85°C. However, the AD9042 was designed to perform over the full military temperature range (−55°C to +125°C); consult the factory for military grade product options. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Guaranteed sample rate is 41 MSPS. Dynamic performance specified over entire Nyquist band; spurious signals 80 dBc typical for −1 dBFS input signals. Low power dissipation: 595 mW off a single 5 V supply. Reference and track-and-hold included on chip. Packaged in 44-lead LQFP. The AD9042 is built on a high speed complementary bipolar process (XFCB) used by Analog Devices, Inc., and uses an innovative multipass architecture. Units are packaged in a 44-lead LQFP low profile quad flat package. The AD9042 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1995–2009 Analog Devices, Inc. All rights reserved. AD9042 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ....................................................................................... 1 Encoding the AD9042 ............................................................... 13 Functional Block Diagram .............................................................. 1 Driving the Analog Input .......................................................... 14 General Description ......................................................................... 1 Power Supplies ............................................................................ 15 Product Highlights ........................................................................... 1 Output Loading .......................................................................... 15 Revision History ............................................................................... 2 Layout Information .................................................................... 15 Specifications..................................................................................... 3 Digital Wideband Receivers .......................................................... 16 DC Specifications ......................................................................... 3 Introduction ................................................................................ 16 Switching Specifications .............................................................. 4 Noise Floor and SNR ................................................................. 18 AC Specifications.......................................................................... 4 Processing Gain .......................................................................... 18 Absolute Maximum Ratings............................................................ 6 Overcoming Static Nonlinearities with Dither ...................... 18 Thermal Resistance ...................................................................... 6 Receiver Example ....................................................................... 19 Explanation of Test Levels ........................................................... 6 IF Sampling, Using the AD9042 as a Mix-Down Stage ........ 20 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Receive Chain for Digital and Analog Beam Forming Medical Ultrasound Using the AD9042........................................................ 21 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 22 Terminology .................................................................................... 11 Ordering Guide .......................................................................... 22 Equivalent Circuits ......................................................................... 12 REVISION HISTORY 9/09—Rev. A to Rev. B Updated Format .................................................................. Universal Reorganized Layout ............................................................ Universal Deleted DH-28 Package ................................................ Throughout Changes to General Description Section and Product Highlights Section ............................................................................ 1 Deleted Wafer Test Limits Section ................................................. 4 Deleted Die Layout and Mechanical Information Table and Die Layout with Pad Labels Figure ........................................................ 6 Changes to Figure 4 .......................................................................... 7 Deleted Figure 7; Renumbered Sequentially................................. 7 Deleted Figure 15 and Figure 16 ..................................................... 9 Deleted Evaluation Boards Section .............................................. 13 Changes to Layout Information Section...................................... 16 Removed Evaluation Boards Section ........................................... 18 Changes to Figure 49 and Figure 50 ............................................. 19 Changes to Figure 52 ...................................................................... 20 Changes to Figure 54 ...................................................................... 22 Updated Outline Dimension......................................................... 24 Changes to Ordering Guide .......................................................... 24 5/96—Rev. 0 to Rev. A Changes to Specifications Section ...................................................2 Changes to Switching Specifications Section.................................2 Changes to AC Specifications Section ............................................3 Changes to Ordering Guide .............................................................4 Changes to Pin Descriptions Section..............................................5 Added Die Layout and Mechanical Information Section ............6 Changes to Figure 2, Figure 3, Figure 5, and Figure 6 ..................7 Changes to Figure 37...................................................................... 14 Added Figure 38 ............................................................................. 15 Added Table 2 ................................................................................. 15 Added Figure 43, Figure 44, Figure 45, and Figure 46 .............. 17 Added Figure 47 and Figure 48 .................................................... 18 Changes to Figure 53...................................................................... 21 Changes to Figure 54...................................................................... 22 Added Receiver Example Section................................................. 22 Added Multitone Performance Section ....................................... 22 Added Receive Chain for Digital Beam-Forming Medical Ultrasound Using the AD9042 Section ....................................... 23 Added Figure 58 ............................................................................. 23 10/95—Rev. 0: Initial Version Rev. B | Page 2 of 24 AD9042 SPECIFICATIONS DC SPECIFICATIONS AVCC = DVCC = 5 V; VREF tied to VOFFSET through 50 Ω; TMIN = −40°C, TMAX = +85°C. Table 1. Parameter 1 RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Tempco Gain Error Gain Tempco REFERENCE OUT (VREF) 2 ANALOG INPUT (AIN) Input Voltage Range Input Resistance Input Capacitance ENCODE INPUT 3 Logic Compatibility 4 Logic 1 Voltage Logic 0 Voltage Logic 1 Current (VINH = 5 V) Logic 0 Current (VINL = 0 V) Input Capacitance DIGITAL OUTPUTS Logic Compatibility Logic 1 Voltage (IOH = 10 μA) Logic 0 Voltage (IOL = 10 μA) Output Coding POWER SUPPLY AVCC Supply Voltage AVCC Current (I) DVCC Supply Voltage DVCC Current (I) ICC (Total) Supply Current Power Dissipation Power Supply Rejection Ratio (PSRR) Temperature Test Level Min Full Full Full Full Full 25°C VI VI V VI V V Full 25°C IV V 200 Full Full Full Full 25°C VI VI VI VI V 2.0 0 450 −400 25°C Full 25°C Full I IV I IV 3.5 3.5 −10 −6.5 Typ 12 Guaranteed ±3 25 0 −50 2.4 VREF ± 0.500 250 5.5 Max Unit Bits +10 +6.5 mV ppm/°C % FS ppm/°C V 300 V Ω pF TTL/CMOS 625 −300 2 5.0 0.8 800 −200 CMOS 4.2 0.75 0.80 0.85 V V μA μA pF V V V V Twos complement Full Full Full Full Full Full 25°C Full VI V VI V VI VI I V 1 −20 5.0 109 5.0 10 119 595 ±1 ±5 C1 (Pin 10) tied to GND through a 0.01 μF capacitor. VREF is normally tied to VOFFSET through 50 Ω. If VREF is used to provide dc offset to other circuits, it should first be buffered. 3 ENCODE driven by single-ended source; ENCODE bypassed to ground through a 0.01 μF capacitor. 4 ENCODE may also be driven differentially in conjunction with ENCODE; see the Encoding the AD9042 section for details. 2 Rev. B | Page 3 of 24 147 735 +20 V mA V mA mA mW mV/V mV/V AD9042 SWITCHING SPECIFICATIONS AVCC = DVCC = 5 V; ENCODE and ENCODE = 41 MSPS; VREF tied to VOFFSET through 50 Ω; TMIN = −40°C, TMAX = +85°C. Table 2. Parameter 1 Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) ENCODE Pulse Width High ENCODE Pulse Width Low Output Delay (tOD) 1 Temperature Full Full 25°C 25°C 25°C 25°C Full Test Level VI IV V V IV IV IV Min 41 Typ Max 5 −250 0.7 10 10 5 9 14 Unit MSPS MSPS ps ps rms ns ns ns C1 (Pin 10) tied to GND through a 0.01 μF capacitor. AC SPECIFICATIONS AVCC = DVCC = 5 V; ENCODE and ENCODE = 41 MSPS; VREF tied to VOFFSET through 50 Ω; TMIN = −40°C, TMAX = +85°C. Table 3. Parameter 1, 2 SNR 3 Analog Input at −1 dBFS 1.2 MHz 9.6 MHz 19.5 MHz SINAD 4 Analog Input at −1 dBFS 1.2 MHz 9.6 MHz 19.5 MHz WORST SPUR 5 Analog Input at −1 dBFS 1.2 MHz 9.6 MHz 19.5 MHz SMALL SIGNAL SFDR (WITH DITHER) 6 Analog Input 1.2 MHz 9.6 MHz 19.5 MHz TWO-TONE IMD REJECTION 7 F1, F2 @ –7 dBFS TWO-TONE SFDR (WITH DITHER) 8 THERMAL NOISE Temp Test Level 25°C Full 25°C Full 25°C Full V V V V I V 25°C Full 25°C Full 25°C Full V V V V I V 25°C Full 25°C Full 25°C Full V V V V I V Full Full Full Full Full 25°C Min Typ Max Units 68 67.5 67.5 67 67 66.5 dB dB dB dB dB dB 67.5 67 67.5 67 67 66.5 dB dB dB dB dB dB 80 78 80 78 80 78 dBc dBc dBc dBc dBc dBc V V V 90 90 90 dBFS dBFS dBFS V V V 80 90 0.33 dBc dBFS LSB rms Rev. B | Page 4 of 24 64 64 73 AD9042 Parameter 1, 2 DIFFERENTIAL NONLINEARITY (ENCODE = 20 MSPS) INTEGRAL NONLINEARITY (ENCODE = 20 MSPS) ANALOG INPUT BANDWIDTH TRANSIENT RESPONSE OVERVOLTAGE RECOVERY TIME Temp 25°C Full Test Level I V Full 25°C 25°C 25°C V V V V Min −1.0 Typ ±0.3 ±0.4 ±0.75 100 10 25 Max +1.0 Units LSB LSB LSB MHz ns ns All ac specifications tested by driving ENCODE and ENCODE differentially; see the Encoding the AD9042 section for details. C1 (Pin 10 on AD9042ASTZ only) tied to GND through a 0.01 μF capacitor. 3 Analog input signal power at −1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). 4 Analog input signal power at −1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. 5 Analog input signal power at −1 dBFS; worst spur is the ratio of the signal level to worst spur, usually limited by harmonics. 6 Analog input signal power swept from −20 dBFS to –95 dBFS; dither power = −32.5 dBm; dither circuit used on input signal (see the Overcoming Static Nonlinearities with Dither section); SFDR is the ratio of converter full scale to worst spur. 7 Tones at −7 dBFS (f1 = 15.3 MHz, f2 = 19.5 MHz); two-tone intermodulation distortion (IMD) rejection is ratio of either tone to worst-third order intermodulation product. 8 Both input tones swept from −20 dBFS to −95 dBFS; dither power = −32.5 dBm; dither circuit used on input signal (see the Overcoming Static Nonlinearities with Dither section); two-tone spurious-free dynamic range (SFDR) is the ratio of converter full scale to worst spur. 1 2 Rev. B | Page 5 of 24 AD9042 ABSOLUTE MAXIMUM RATINGS Table 4. 1 Parameter AVCC Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating 0 V to 7 V 0 V to 7 V 0.5 V to 4.5 V 20 mA 0 V to AVCC 4V −40 to +40 mA −40 °C to +85°C +150°C +300°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 44-Lead LQFP θJA 55 Unit °C/W 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. EXPLANATION OF TEST LEVELS I. II. 100% production tested. 100% production tested at +25°C, and sample tested at specified temperatures. AC testing done on sample basis. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. VI. Parameter is a typical value only. 100% production tested at +25°C; sample tested at temperature extremes. ESD CAUTION Rev. B | Page 6 of 24 AD9042 GND GND DVCC DVCC GND GND DVCC DVCC D9 D10 D11 (MSB) PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 DVCC 1 33 D8 PIN 1 DVCC 2 ENCODE 3 31 D6 ENCODE 4 30 D5 GND 5 GND 6 32 D7 AD9042 29 D4 TOP VIEW (Not to Scale) 28 D3 AIN 7 VOFFSET 8 26 D1 VREF 9 25 D0 (LSB) 27 D2 C1 10 24 GND AVCC 11 00554-003 GND GND AVCC AVCC GND GND AVCC AVCC GND GND 12 13 14 15 16 17 18 19 20 21 22 AVCC NC = NO CONNECT 23 NC Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 2 3 4 5, 6 7 8 9 Mnemonic DVCC ENCODE ENCODE GND AIN VOFFSET VREF 10 11, 12 13, 14 15, 16 17, 18 19, 20 21, 22 23 24 25 26 to 33 34, 35 36, 37 38, 39 40, 41 42, 43 44 C1 AVCC GND AVCC GND AVCC GND NC GND D0 (LSB) D1 to D8 GND DVCC GND DVCC D9 to D10 D11 (MSB) Description 5 V Power Supply (Digital). Powers output stage only. Encode Input. Data conversion initiated on rising edge. Complement of ENCODE. Drive differentially with ENCODE or bypass to ground for single-ended clock mode. Ground. Analog Input. Voltage Offset Input. Sets mid point of analog input range. Normally tied to VREF through a 50 Ω resistor. Internal Voltage Reference. Nominally 2.4 V; normally tied to VOFFSET through a 50 Ω resistor. Bypass to ground and with 0.1 μF + 0.01 μF microwave chip capacitor. Internal Bias Point. Bypass to ground with a 0.01 μF capacitor. 5 V Power Supply (Analog). Ground. 5 V Power Supply (Analog). Ground. 5 V Power Supply (Analog). Ground. No Connect Ground. Digital Output Bit (Least Significant Bit). Digital Output Bits. Ground. 5 V Power Supply (Digital). Powers output stage only. Ground. 5 V Power Supply (Digital). Powers output stage only. Digital Output Bits. Digital Output Bit (Most Significant Bit). Output coded as twos complement. Rev. B | Page 7 of 24 AD9042 0 ENCODE = 41MSPS AIN = 1.2MHz WORST-CASE HARMONIC (dBc) –20 –40 –60 2 3 4 5 6 7 8 ENCODE = 41MSPS TEMP = –40°C, +25°C, AND +85°C 81 9 –80 –100 T = +25°C 80 T = –40°C T = +85°C 79 78 4.1 8.2 12.3 FREQUENCY (MHz) 16.4 20.5 0 2 20 20 0 ENCODE = 41MSPS AIN = 9.6MHz ENCODE = 41MSPS TEMP = –40°C, +25°C, AND +85°C 70 –20 69 SNR (dB) –40 –60 4 8 8 5 3 7 6 2 –80 T = –40°C 68 T = +25°C 67 T = +85°C –100 4.1 8.2 12.3 FREQUENCY (MHz) 16.4 20.5 00554-014 66 –120 dc 0 2 4 6 8 10 12 14 16 ANALOG INPUT FREQUENCY (MHz) Figure 4. Single Tone at 9.6 MHz 18 Figure 7. SNR vs. AIN 0 90 ENCODE = 41MSPS –40 –60 2 4 6 8 9 7 5 3 –80 –100 –120 dc 4.1 8.2 12.3 FREQUENCY (MHz) 16.4 20.5 80 70 60 50 40 30 1 2 4 10 20 40 ANALOG INPUT FREQUENCY (MHz) Figure 8. Worst-Case Harmonics vs. AIN Figure 5. Single Tone at 19.5 MHz Rev. B | Page 8 of 24 100 00554-018 WORST-CASE HARMONIC (dBc) –20 ENCODE = 41MSPS AIN = 19.5MHz 00554-015 POWER RELATIVE TO ADC FULL SCALE (dB) 18 Figure 6. Worst-Case Harmonics vs. AIN Figure 3. Single Tone at 1.2 MHz POWER RELATIVE TO ADC FULL SCALE (dB) 4 6 8 10 12 14 16 ANALOG INPUT FREQUENCY (MHz) 00554-016 –120 dc 00554-017 77 00554-013 POWER RELATIVE TO ADC FULL SCALE (dB) TYPICAL PERFORMANCE CHARACTERISTICS –40 –60 –80 –100 4.1 8.2 12.3 FREQUENCY (MHz) 16.4 20.5 –20 –40 –60 4 –80 –100 –120 dc 4.1 POWER RELATIVE TO ADC FULL SCALE (dB) AIN = 4.3MHz WORST SPUR 80 75 70 SNR 65 10 15 20 25 30 35 SAMPLE RATE (MSPS) 40 45 50 –20 ENCODE = 41MSPS AIN = 19.5MHz @ –29dBFS NO DITHER –40 –60 –80 2 6 8 8 7 5 3 4.1 8.2 12.3 FREQUENCY (MHz) 16.4 20.5 Figure 13. 4K FFT Without Dither 90 100 ENCODE = 41MSPS AIN = 19.5MHz 80 90 WORST-CASE SPURIOUS (dBc) 85 WORST SPUR 75 70 SNR 65 60 55 50 45 40 80 ENCODE = 41MSPS AIN = 19.5MHz NO DITHER 70 60 50 40 30 20 SFDR = 80dB REFERENCE LINE 10 35 30 35 40 45 50 55 60 ENCODE DUTY CYCLE (%) 65 70 75 00554-023 SNR (dB), WORST-CASE SPURIOUS (dBc) 4 –100 Figure 10. SNR, Worst Harmonic vs. Encode 30 25 20.5 0 –120 dc 00554-022 SNR (dB), WORST-CASE SPURIOUS (dBc) 85 5 16.4 Figure 12. NPR Output Spectrum Figure 9. Two Tones at 15.3 MHz and 19.5 MHz 60 dc 8.2 12.3 FREQUENCY (MHz) 00554-025 –120 dc ENCODE = 41MSPS AIN = BROADBAND_NOISE 00554-024 ENCODE = 41MSPS AIN = 15.3MHz, 19.5MHz 0 0 –80 Figure 11. SNR, Worst Spurious vs. Duty Cycle –70 –60 –50 –40 –30 –20 –10 ANALOG INPUT POWER LEVEL (dBFS) Figure 14. SFDR Without Dither Rev. B | Page 9 of 24 0 00554-026 –20 POWER RELATIVE TO ADC FULL SCALE (dB) 0 00554-019 POWER RELATIVE TO ADC FULL SCALE (dB) AD9042 100 0 ENCODE = 41MSPS AIN = 2.5MHz @ –26dBFS NO DITHER 90 –40 –60 –80 –100 80 ENCODE = 41MSPS AIN = 19.5MHz DITHER = –32.5dBm 70 60 50 40 30 20 SFDR = 80dB REFERENCE LINE 10 4.1 8.2 12.3 FREQUENCY (MHz) 16.4 20.5 0 –80 –70 –60 –50 –40 –30 –20 –10 ANALOG INPUT POWER LEVEL (dBFS) Figure 17. SFDR with Dither POWER RELATIVE TO ADC FULL SCALE (dB) 0 ENCODE = 41MSPS AIN = 19.5MHz @ –29dBFS DITHER = –32.5dBm –20 –40 –60 –80 2 4 6 8 8 7 5 3 –100 –120 dc 4.1 8.2 12.3 FREQUENCY (MHz) 16.4 20.5 0 Figure 16. 4K FFT with Dither ENCODE = 41MSPS AIN = 2.5MHz @ –26dBFS DITHER = –32.5dBm –20 –40 –60 –80 –100 –120 dc 00554-028 POWER RELATIVE TO ADC FULL SCALE (dB) Figure 15. 128K FFT Without Dither 0 4.1 8.2 12.3 FREQUENCY (MHz) Figure 18. 128K FFT with Dither Rev. B | Page 10 of 24 16.4 20.5 00554-030 –120 dc 00554-029 WORST-CASE SPURIOUS (dBc) –20 00554-027 POWER RELATIVE TO ADC FULL SCALE (dB) AD9042 AD9042 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Signal-to-Noise Ratio SNR (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in decibels (degrades as signal levels is lowered) or in decibels relative to full scale (always related back to converter full scale). Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity (DNL) The deviation of any code from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in a Logic 1 state to achieve the rated performance; pulse width low is the minimum time that the ENCODE pulse should be left in low state. At a given clock rate, these specifications define an acceptable encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component, reported in dBc. Integral Nonlinearity (INL) The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Transient Response The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Maximum Conversion Rate The encode rate at which parametric testing is performed. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Output Propagation Delay The delay between the 50% point of the rising edge of the ENCODE command and the time when all output data bits are within valid logic levels. Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal 150% of full scale is reduced to midscale. Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) Ratio The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Rev. B | Page 11 of 24 AD9042 EQUIVALENT CIRCUITS N tA = –250 ps TYP ANALOG INPUT (AIN) N+1 ENCODE INPUTS (ENCODE) DIGITAL OUTPUTS (D11 TO D0) N–1 N 00554-006 N–2 tOD = 9ns TYP Figure 19. Timing Diagram AVCC DVCC 3.5V CURRENT MIRROR AVCC 250µA 250Ω 250Ω AIN AVCC 250µA VOFFSET DVCC VREF 200Ω D0 TO D11 1.5V 00554-007 6pF Figure 20. Analog Input Stage AVCC AVCC R1 17kΩ R1 17kΩ 00554-010 CURRENT MIRROR AVCC Figure 23. Digital Output Stage ENCODE ENCODE TIMING CIRCUITS AVCC R2 8kΩ AVCC 00554-008 R2 8kΩ 2.4V VREF 0.5mA AVCC Figure 24. 2.4 V Reference VREF AVCC AVCC C1 (PIN 10) 00554-009 CURRENT MIRROR Figure 22. Compensation Pin, C1 Rev. B | Page 12 of 24 00554-011 Figure 21. Encode Inputs AD9042 THEORY OF OPERATION VL 0.01µF ENCODING THE AD9042 The AD9042 is designed to interface with TTL and CMOS logic families. The source used to drive the ENCODE pin(s) must be clean and free from jitter. Sources with excessive jitter limit SNR (see Equation 1 in the Noise Floor and SNR section). AD9042 TTL OR CMOS SOURCE ENCODE 0.01µF 00554-031 ENCODE Figure 25. Single-Ended TTL/CMOS Encode The AD9042 encode inputs are connected to a differential input stage (see Figure 21 in the Equivalent Circuits section). With no input connected to either the ENCODE or input, the voltage dividers bias the inputs to 1.6 V. For TTL or CMOS usage, the encode source should be connected to ENCODE. ENCODE should be decoupled using a low inductance or microwave chip capacitor to ground. Devices such as the AVX 05085C103MA15, a 0.01 μF capacitor, work well. R1 ENCODE R2 AD9042 To raise the logic threshold, use the following equation: V1 = 5R 2 R1 R X R2 + R1 + R X AVCC RX ENCODE VL ENCODE 0.01µF AD9042 5V R1 R2 00554-033 ENCODE SOURCE Figure 27. Raise Logic Threshold for Encode Although the single-ended encode works well for many applications, driving the encode differentially provides increased performance. Depending on circuit layout and system noise, a 1 dB to 3 dB improvement in SNR can be realized. It is not recommended that differential TTL logic be used, however, because most TTL families that support complementary outputs are not delay or slew rate matched. Instead, it is recommended that the encode signal be ac-coupled into the ENCODE and ENCODE pins. The simplest option is shown in Figure 28. The low jitter TTL signal is coupled with a limiting resistor, typically 100 Ω, to the primary side of an RF transformer (these transformers are inexpensive and readily available; part number in Figure 28 is from Mini-Circuits). The secondary side is connected to the ENCODE and ENCODE pins of the converter. Because both encode inputs are self-biased, no additional components are required. If a logic threshold other than the nominal 1.6 V is required, the following equations show how to use an external resistor, Rx, to raise or lower the trip point (see Figure 21; R1 = 17 kΩ, R2 = 8 kΩ). To lower the logic threshold, use the following equation: V1 = RX 5V Figure 26. Lower Logic Threshold for Encode The residue signal is passed to TH3 on a subsequent clock cycle where the signal is amplified by the residue amplifier, A2, and converted to a digital word by the 7-bit residue ADC. One bit of overlap is used to accommodate any linearity errors in the coarse ADC. The 6-bit coarse ADC word and 7-bit residue word are added together and corrected in the digital error correction logic to generate the output word. The result is a 12-bit parallel digital word, which is CMOS-compatible, coded as twos complement. ENCODE 5R 2 R X R1 R 2 + R1 R X + R 2 R X Rev. B | Page 13 of 24 100Ω TTL T1-1T ENCODE AD9042 ENCODE Figure 28. TTL Source Differential Encode 00554-034 As shown in Figure 1, the 1 V p-p single-ended analog input, centered at 2.4 V, drives a single-input to differential-output amplifier, A1. The output of A1 drives the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of the 6-bit coarse ADC. The digital output of the coarse ADC drives a 6-bit DAC; the DAC is 12 bits accurate. The output of the 6-bit DAC is subtracted from the delayed analog signal at the input to TH3 to generate a residue signal. TH2 is used as an analog pipeline to null out the digital delay of the coarse ADC. ENCODE SOURCE 00554-032 The AD9042 analog-to-digital converter (ADC) employs a twostage subrange architecture. This design approach ensures 12-bit accuracy, without the need for laser trim, at low power. AD9042 If no TTL source is available, a clean sine wave can be substituted. In the case of the sine source, the matching network is shown in Figure 29. Because the matching transformer specified is a 1:1 impedance ratio, R, the load resistor should be selected to match the source impedance. The input impedance of the AD9042 is negligible in most cases. + 50Ω 2.4V REFERENCE 00554-035 Figure 29. Sine Source Differential Encode If a low jitter ECL clock is available, another option is to accouple a differential ECL signal to the encode input pins as shown in Figure 30. The capacitors shown here should be chip capacitors but do not need to be of the low inductance variety. 0.1µF ENCODE 0.1µF ENCODE AD9042 Although the AD9042 can be used in many applications, it was specifically designed for communications systems that must digitize wide signal bandwidths. As such, the analog input was designed to be ac-coupled. Because most communications products do not downconvert to dc, this should not pose a problem. One example of a typical analog input circuit is shown in Figure 33. In this application, the analog input is coupled with a high quality chip capacitor, the value of which can be chosen to provide a low frequency cutoff that is consistent with the signal being sampled; in most cases, a 0.1 μF chip capacitor works well. 510Ω AIN RT Figure 30. Differential ECL for Encode 0.1µF ENCODE 0.1µF 50Ω – ENCODE AD9042 510Ω –VS 00554-037 510Ω VOFFSET 50Ω Figure 31. ECL Comparator for Encode Care should be taken not to overdrive the encode input pins when ac-coupled. Although the input circuitry is electrically protected from overvoltage or undervoltage conditions, improper circuit operations may result from overdriving the encode input pins. 00554-039 VREF As a final alternative, the ECL gate can be replaced by an ECL comparator. The input to the comparator could then be a logic signal or a sine signal. + AD9042 0.1µF ANALOG SIGNAL SOURCE 00554-036 –VS AD96687 (1/2) AD9042 0.1µF Figure 32. Analog Input Offset by 2.4 V Reference AD9042 ENCODE 510Ω VOFFSET TIED TO VREF THROUGH 50Ω – ENCODE R ECL GATE AIN 00554-038 T1-1T SINE SOURCE 250Ω 250Ω 0.1µF Figure 33. AC-Coupled Analog Input Signal Another option for ac coupling is a transformer. The impedance ratio and frequency characteristics of the transformer are determined by examining the characteristics of the input signal source (transformer primary connection), and the AD9042 input characteristics (transformer secondary connection). Given the transformer turns ratio, RT should be chosen to satisfy the termination requirements of the source. A blocking capacitor is required to prevent AD9042 dc bias currents from flowing through the transformer. ANALOG SIGNAL SOURCE 0.1µF XFMR BPF AD9042 AIN RT VOFFSET 50Ω VREF LO Because the AD9042 operates from a single 5 V supply, the analog input range is offset from ground by 2.4 V. The analog input, AIN, is an operational amplifier configured in an inverting mode (see Figure 32). VOFFSET is the noninverting input, which is normally tied through a 50 Ω resistor to VREF (see Figure 32). Because the operational amplifier forces its inputs to the same voltage, the inverting input is also at 2.4 V. Therefore, the analog input has a Thevenin equivalent of 250 Ω in series with a 2.4 V source. It is strongly recommended that the internal voltage reference of the AD9042 be used for the amplifier offset; this reference is designed to track internal circuit shifts over temperature. Rev. B | Page 14 of 24 0.1µF Figure 34. Transformer-Coupled Analog Input Signal 00554-040 DRIVING THE ANALOG INPUT AD9042 When calculating the proper termination resistor, note that the external load resistor is in parallel with the AD9042 analog input resistance, 250 Ω. The external resistor value can be calculated from the following equation: RT = OUTPUT LOADING 1 1 1 − Z 250 where Z is desired impedance. A dc-coupled input configuration (shown in Figure 35) is limited by the drive amplifier performance. The on-chip reference of the AD9042 is buffered using the OP279 dual, railto-rail operational amplifier. The resulting voltage is combined with the analog source using an AD9631. Pending improvements in drive amplifiers, this dc-coupled approach is limited to ~75 dB to 80 dB of dynamic performance depending on which drive amplifier is used. The AD9631 and OP279 run off ±5 V. SIGNAL SOURCE AD9631 21Ω 79Ω AD9042 50Ω 200Ω 0.1µF 0pF TO 50pF 114Ω Care must be taken when designing the data receivers for the AD9042. It is recommended that the digital outputs drive a series resistor of 499 Ω followed by a CMOS gate such as the 74AC574. To minimize capacitive loading, there should be only one gate on each output pin. The digital outputs of the AD9042 have a unique constant slew rate output stage. The output slew rate is about 1 V/ns independent of output loading. A typical CMOS gate combined with PCB trace and through hole has a load of approximately 10 pF. Therefore, as each bit switches, 10 mA of dynamic current per bit flows in or out of the device. A fullscale transition can cause up to 120 mA (12 bits × 10 mA/bit) of current to flow through the digital output stage. The series resistor minimizes the output currents that can flow in the output stage. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided because they can appreciably add to the dynamic switching currents of the AD9042. ⎛ 1V ⎞ ⎜10 pF × ⎟ ⎜ 1 ns ⎟⎠ ⎝ AIN VOFFSET 1kΩ 49.9Ω LAYOUT INFORMATION VREF 571Ω OP279 OP279 (1/2) (1/2) 00554-041 0.1µF Figure 35. DC-Coupled Analog Input Circuit POWER SUPPLIES Care should be taken when selecting a power source. Linear supplies are strongly recommended because switching supplies tend to have radiated components that may be received by the AD9042. Each of the power supply pins should be decoupled as close to the package as possible using 0.1 μF chip capacitors. The AD9042 has separate digital and analog 5 V pins. The AVCC pins are the analog supply pins, and the DVCC pins are the digital supply pins. Although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching noise back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The pinout of the AD9042 facilitates ease of use and the implementation of high frequency/high resolution design practices. All of the digital outputs are on one side of the package, and all of the inputs are on the other sides of the package. It is highly recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. Depending on the configuration used for the encode and analog inputs, one or more capacitors are required on those input pins. The capacitors used on the ENCODE and VREF pins must be low inductance chip capacitors as noted previously. Although a multilayer board is recommended, it is not required to achieve good results. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connected directly to the receiving gate (broken only by the insertion of the series resistor). Logic fanout for each bit should be one CMOS gate. Rev. B | Page 15 of 24 AD9042 DIGITAL WIDEBAND RECEIVERS INTRODUCTION Several key technologies are now being introduced that may forever alter the vision of radio. Figure 36 shows the typical dual conversion superheterodyne receiver. The signal picked up by the antenna is mixed down to an intermediate frequency (IF) using a mixer with a variable local oscillator (LO); the variable LO is used to tune in the desired signal. This first IF is mixed down to a second IF using another mixer stage and a fixed LO. Demodulation takes place at the second or third IF using either analog or digital techniques. NARROW-BAND FILTER LNA IF1 RF ADCs NARROW-BAND FILTER I IF2 Q 900MHz SHARED System Description FIXED 00554-054 VARIABLE ONE RECEIVER PER CHANNEL Figure 36. Narrow-Band Digital Receiver Architecture If demodulation takes place in the analog domain, then traditional discriminators, envelope detectors, phase-locked loops, or other synchronous detectors are generally used to strip the modulation from the selected carrier. However, as general-purpose DSP chips such as the ADSP-2181 become more popular, they can be used in many baseband sampled application such as the one shown in Figure 36. As shown in the figure, prior to ADC conversion, the signal must be mixed down and filtered, and the I and Q components must be separated. These functions are realized through DSP techniques; however, several key technology breakthroughs are required: high dynamic range ADCs, such as the AD9042, new DSPs (highly programmable with fast onboard memory), digital tuner and filter (with programmable frequency and BW), and wideband mixers (high dynamic range with >12.5 MHz BW). LNA WIDEBAND MIXER WIDEBAND FILTER WIDEBAND ADC "n" CHANNELS TO DSP RF 12.5MHz (416 CHANNELS) FIXED SHARED CHANNEL SELECTION 00554-055 900MHz First, many passive discrete components that formed the tuning and filtering functions have been eliminated. These passive components often require adjusting and special handling during assembly and final system alignment. Digital components require no such adjustments; tuner and filter characteristics are always exactly the same. Moreover, the tuning and filtering characteristics can be changed through software. Because software is used for demodulation, different routines may be used to demodulate different standards such as AM, FM, GMSK, or any other desired standard. In addition, as new standards arise or new software revisions are generated, they may be field installed with standard software update channels. A radio that performs demodulation in software as opposed to hardware is often referred to as a soft radio because it can be changed or modified simply through code revision. In the wideband digital radio (see Figure 37), the first downconversion functions in much the same way as a block converter does. An entire band is shifted in frequency to the desired intermediate frequency. In the case of cellular base station receivers, 5 MHz to 20 MHz of bandwidth are downconverted simultaneously to an IF frequency suitable for digitizing with a wideband ADC. Once digitized, the broadband digital data stream contains all of the in-band signals. The remainder of the radio is constructed digitally using special-purpose and generalpurpose programmable DSP to perform filtering, demodulation, and signal conditioning, not unlike the analog counterparts. In the narrow-band receiver (see Figure 36), the signal to be received must be tuned. This is accomplished by using a variable local oscillator at the first mix-down stage. The first IF then uses a narrow-band filter to reject out-of-band signals and condition the selected carrier for signal demodulation. In the digital wideband receiver (see Figure 37), the variable local oscillator has been replaced with a fixed oscillator, so tuning must be accomplished in another manner. Tuning is performed digitally using a digital downconversion and a filter chip frequently called a channelizer. The term, channelizer, is used because the purpose of these chips is to select one channel out of the many within the broadband of spectrum actually present in the digital data stream of the ADC. Figure 37. Wideband Digital Receiver Architecture DECIMATION FILTER LOW-PASS FILTER I DECIMATION FILTER LOW-PASS FILTER Q COS Rev. B | Page 16 of 24 DATA DIGITAL TUNER SIN Figure 38. Digital Channelizer 00554-056 Figure 37 shows such a wideband system. This design shows that the front-end variable local oscillator has been replaced with a fixed oscillator (for single-band radios), and the back end has been replaced with a wide dynamic range ADC, digital tuner, and DSP. This technique offers many benefits. AD9042 Figure 38 shows the block diagram of a typical channelizer. Channelizers consist of a complex NCO (numerically controlled oscillator), dual multiplier (mixer), and matched digital filters. These are the same functions that would be required in an analog receiver but implemented in digital form. The digital output from the channelizer is the desired carrier, frequently in I and Q format; all other signals are filtered and removed based on the filtering characteristics desired. Because the channelizer output consists of one selected RF channel, one tuner chip is required for each frequency received, although only one wideband RF receiver is needed for the entire band. Data from the channelizer can then be processed using a digital signal processor such as the ADSP-2181 or the SHARC ADSP-21062 processor. This data may then be processed through software to demodulate the information from the carrier. bipolar device, power dissipation is not a function of sample rate. Thus, there is no penalty paid in power by operating at faster sample rates. By carefully selecting input frequency range and sample rate, the drive amplifier and ADC harmonics can actually be placed out-of-band. Thus, other components such as filters and IF amplifiers may actually end up being the limiting factor on dynamic range. Figure 39 shows a typical wideband receiver subsystem based around the AD9042. This strip consists of a wideband IF filter, amplifier, ADC, latches, channelizer, and interface to a digital signal processor. This design shows a typical clocking scheme used in many receiver designs. All timing within the system is referenced back to a single clock. Although this is not necessary, it facilitates PLL design, ease of manufacturing, system test, and calibration. Keeping in mind that the overall performance goal is to maintain the best possible dynamic range, many choices must be considered. Table 7. Example Frequency Plan For example, if the system has second and third harmonics that are unacceptably high, the careful selection of the encode rate and signal bandwidth can place these second and third harmonics out-of-band. For the case of an encode rate equal to 40.96 MSPS and a signal bandwidth of 5.12 MHz, placing the fundamental at 5.12 MHz places the second and third harmonics out-ofband as shown in Table 7. Parameter Encode Rate Fundamental Second Harmonic Third Harmonic Another option is found through band-pass sampling. If the analog input signal range is from dc to FS/2, then the amplifier and filter combination must perform to the specification required. However, if the signal is placed in the third Nyquist zone (FS to 3 FS/2), the amplifier is no longer required to meet the harmonic performance required by the system specifications because all harmonics fall outside the pass-band filter. For example, the pass-band filter ranges from fS to 3 FS/2. The second harmonic would span from 2 FS to 3 FS, well outside the range of the pass-band filter. The burden then is placed on the filter design, provided that the ADC meets the basic specifications at the frequency of interest. In many applications, this is a worthwhile trade-off because many complex filters can easily be realized using SAW and LCR techniques alike at these relatively high IF frequencies. Although the harmonic performance of the drive amplifier is relaxed by this technique, intermodulation performance cannot be sacrificed because intermods must be assumed to fall in-band for both amplifiers and converters. One of the biggest challenges is selecting the amplifier used to drive the AD9042. Because this is a communications application, the key specification for this amplifier is spurious-free dynamic range (SFDR). An amplifier should be selected that can provide SFDR performance better than 80 dB into 250 Ω. One such amplifier is the AD9631. These low spurious levels are necessary because harmonics due to the drive amplifier and ADC can distort the desired signals of interest. Two other key considerations for the digital wideband receiver are converter sample rate and IF frequency range. Because performance of the AD9042 converter is nearly independent of both sample rate and analog input frequency (see Figure 6, Figure 7, and Figure 10), the designer has greater flexibility in the selection of these parameters. Also, because the AD9042 is a 5V (A) 5V (D) 5MHz TO 15MHz PASS BAND LNA M/N PLL SYNTHESIZER ADSP-2181 D11 I AND Q DATA 12 AD9042 864MHz CHANNELIZER 499Ω AIN LO DRIVE CMOS BUFFER NETWORK CONTROLLER INTERFACE ENCODE REF IN ENCODE D0 CLK 40.96MHz 00554-057 PRESELECT FILTER Value 40.96 MSPS 5.12 MHz to 10.24 MHz 10.24 MHz to 20.48 MHz 15.36 MHz to 10.24 MHz REFERENCE CLOCK Figure 39. Simplified 5 MHz Wideband “A” Carrier Receiver Rev. B | Page 17 of 24 AD9042 NOISE FLOOR AND SNR Oversampling is the act of sampling at a rate that is greater than twice the bandwidth of the signal desired. Oversampling has nothing to do with the actual frequency of the sampled signal. It is the bandwidth of the signal that is key. Band-pass or IF sampling refers to sampling a frequency that is higher than Nyquist and often provides additional benefits such as downconversion using the ADC and track-and-hold as a mixer. Oversampling leads to processing gains because the faster the signal is digitized, the wider the distribution of noise. Because the integrated noise must remain constant, the actual noise floor is lowered by 3 dB each time the sample rate is doubled. The effective noise density for an ADC may be calculated by the following equation: V NOISE rms / Hz = 10 − SNR / 20 4 FS For a typical SNR of 68 dB and a sample rate of 40.96 MSPS, this is equivalent to 31 nV/√Hz . This equation shows the relationship between the SNR of the converter and the sample rate FS. This equation can be used todetermine overall receiver noise. The SNR for an ADC can be predicted. When normalized to ADC codes, the following equation accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. 2 1/ 2 ⎤ 2 ⎡ ⎛ 1 + ε ⎞ ⎛ VNOISErms ⎞⎟ ⎥ SNR= − 20 log⎢ 2 πFANALOG× tJ rms 2 + ⎜ 12 ⎟ + ⎜ 12 ⎟ ⎥ ⎢ ⎝ 2 ⎠ ⎜⎝ 2 ⎠ ⎦ ⎣ ( ) where FANALOG is analog input frequency. t J rms is rms jitter of the encode (rms sum of encode source and internal encode circuitry). ε is average DNL of the ADC. VNOISE rms is V rms thermal noise referred to the analog input of the ADC. PROCESSING GAIN Processing gain is the improvement in SNR gained through DSP processes. Most of this processing gain is accomplished using the channelizer chips. These special-purpose DSP chips not only provide channel selection and filtering but also provide a data rate reduction. Few, if any, general-purpose DSPs can accept and process data at 40.96 MSPS. The required rate reduction is accomplished through a process called decimation. The term decimation rate is used to indicate the ratio of input data rate to output data rate. For example, if the input data rate is 40.96 MSPS and the output data rate is 30 kSPS, then the decimation rate is 1365. Large processing gains may be achieved in the decimation and filtering process. The purpose of the channelizer, beyond tuning, is to provide the narrow-band filtering and selectivity that traditionally has been provided by the ceramic or crystal filters of a narrow-band receiver. This narrow-band filtering is the source of the processing gain associated with a wideband receiver and is simply the ratio of the pass-band to whole band expressed in dBc. For example, if a 30 kHz AMPS signal is digitized with an AD9042 sampling at 40.96 MSPS, the ratio is 0.030 MHz/20.48 MHz. Expressed in log form, the processing gain is −10 × log (0.030 MHz/20.48 MHz) or 28.3 dB. Additional filtering and noise reduction techniques can be achieved through DSP techniques; many applications obtain additional process gains through proprietary noise reduction algorithms. OVERCOMING STATIC NONLINEARITIES WITH DITHER Typically, high resolution data converters use multistage techniques to achieve high bit resolution without large comparator arrays that would be required if traditional flash ADC techniques were used. The multistage converter typically provides better wafer yields, meaning lower cost and much lower power. However, because it is a multistage device, certain portions of the circuit are used repetitively as the analog input sweeps from one end of the converter range to the other. Although the worst DNL error may be less than 1 LSB, the repetitive nature of the transfer function can create havoc with low level dynamic signals. Spurious signals for a full-scale input may be −88 dBc; however, at 29 dB below full scale, these repetitive DNL errors can cause SFDR to fall to 80 dBc as shown in Figure 13. A common technique for randomizing and reducing the effects of repetitive static linearity is through the use of dither. The purpose of dither is to force the repetitive nature of static linearity to appear as if it were random. Then, the average linearity over the range of dither dominates the SFDR performance. In the AD9042, the repetitive cycle is every 15.625 mV p-p. To ensure adequate randomization, 5.3 mV rms is required; this equates to a total dither power of −32.5 dBm. This randomizes the DNL errors over the complete range of the residue converter. Although lower levels of dither such as that from previous analog stages reduces some of the linearity errors, the full effect is gained only with this larger dither. Increasing dither even more can be used to reduce some of the global INL errors. However, signals much larger than the microvolts proposed in this data sheet begin to reduce the usable dynamic range of the converter. Even with the 5.3 mV rms of noise suggested, SNR is limited to 36 dB if injected as broadband noise. To avoid this problem, noise can be injected as an out-of-band signal. Typically, this may be around dc but may just as well be at FS/2 or at some other frequency not used by the receiver. The bandwidth of the noise is several hundred kilohertz. By band-limiting and controlling its location in frequency, large levels of dither can be introduced into the receiver without seriously disrupting receiver performance. The result can be a marked improvement in the SFDR of the data converter. Rev. B | Page 18 of 24 AD9042 performance. The result can be a marked improvement in the SFDR of the data converter. RECEIVER EXAMPLE Figure 16 shows the same converter shown in Figure 13 but with this injection of dither (see Figure 13). SFDR is now 94 dBFS. Figure 14 and Figure 17 show an SFDR sweep before and after adding dither. To fully appreciate the improvement that dither can have on performance, Figure 15 and Figure 18 show similar dither plots, one using and one not using dither. Increasing to 128k sample points lowers the noise floor of the FFT; this simply makes it easier to see the dramatic reduction in spurious levels resulting from dither. +15V 16kΩ 16 1 1µF LOW CONTROL (0V TO 1V) 15 2 A NC202 NOISE DIODE (Noisecom) 2.2kΩ 14 3 4 13 +5V 12 –5V REF 5 To determine how the ADC performance relates to overall receiver sensitivity, the simple receiver in Figure 42 can be examined. This example assumes that the overall downconversion process can be grouped into one set of specifications, instead of individually examining all components within the system and summing them together. Although a more detailed analysis should be employed in a real design, this model provides a good approximation. In examining a wideband digital receiver, several considerations must be applied. Although other specifications are important, receiver sensitivity determines the absolute limits of a radio, excluding the effects of other outside influences. Assuming that receiver sensitivity is limited by noise and not by adjacent signal strength, several sources of noise can be identified and their overall contribution to receiver sensitivity calculated. GAIN = 30dB NF = 20dB BW = 12.5MHz 2kΩ SINGLE CHANNEL BW = 30kHz 1kΩ 6 11 39Ω AD600 OP27 9 OPTIONAL HIGH POWER DRIVE CIRCUIT 390Ω Figure 40. Noise Source (Dither Generator) The simplest method for generating dither is through the use of a noise diode (see Figure 40). In this circuit, the noise diode, NC202, generates the reference noise that is gained up and driven by the AD600 and OP27 amplifier chain. The level of noise can be controlled by either presetting the control voltage when the system is set up or by using a digital-to-analog converter (DAC) to adjust the noise level based on input signal conditions. Once generated, the signal must be introduced to the receiver strip. The easiest method is to inject the signal into the drive chain after the last downconversion, as shown in Figure 41. FROM RF/IF AIN AD9042 VOFFSET VREF LPF Figure 41. Using the AD9042 with Dither 00554-059 NOISE SOURCE RF/IF AD9042 REF IN ENCODE CHANNELIZER 40.96MHz 00554-058 8 0.1µF 10 DSP 00554-060 A 7 Figure 42. Receiver Analysis The first noise calculation to make is based on the signal bandwidth at the antenna. In a typical broadband cellular receiver, the IF bandwidth is 12.5 MHz. Given that the power of noise in a given bandwidth is defined by Pn = kTB, where B is bandwidth, k = 1.38 × 10−23 is Boltzmann’s constant, and T = 300k is absolute temperature, this gives an input noise power of 5.18 × 10−14 watts or −102.86 dBm. If the receiver front end has a gain of 30 dB and a noise figure of 20 dB, then the total noise presented to the ADC input becomes −52.86 dBm (−102.86 + 30 + 20) or 0.51 mV rms. Comparing receiver noise to the dither required for good SFDR, note that in this example, the receiver supplies about 10% of the dither required for good SFDR. Based on a typical ADC SNR specification of 68 dB, the equivalent internal converter noise is 0.140 mV rms. Therefore, total broadband noise is 0.529 mV rms. Before processing gain, this is an equivalent SNR (with respect to full scale) of 56.5 dB. Assuming a 30 kHz AMPS signal and a sample rate of 40.96 MSPS, the SNR, through processing gain, is increased by 28.3 dB to 84.8 dB. However, if eight strong and equal signals are present in the ADC bandwidth, each must be placed 18 dB below full scale to prevent ADC overdrive. In addition, 3 dB to 15 dB should be used for ADC headroom should another signal come in-band unexpectedly. For this example, 12 dB of headroom can be allocated. Therefore, 30 dB of range is given away and the carrier-to-noise ratio (C/N) is reduced to 54.8 dB (C/N is the ratio of signal to in-band noise). Rev. B | Page 19 of 24 AD9042 This noise-limited example does not adequately demonstrate the true limitations in a wideband receiver. Other limitations such as SFDR are more restrictive than SNR and noise. Assume that the ADC has an SFDR specification of −80 dBFS or −76 dBm (full scale = 4 dBm). Also assume that a tolerable carrierto-interferer (C/I) (different from C/N) ratio is 18 dB (C/I is the ratio of signal to in-band interfere). This means that the minimum signal level is −62 dBFS (−80 plus 18) or −58 dBm. At the antenna, this is −88 dBm. Therefore, as can be seen, SFDR (single or multitone) would limit receiver performance in this example. However, SFDR can be greatly improved through the use of dither (see Figure 15 and Figure 18). In many cases, the addition of the out-of-band dither can improve receiver sensitivity nearly to that limited by thermal noise. Because the performance of the AD9042 extends beyond the baseband region into the second and third Nyquist zone, the converter may find many uses as a mix-down converter in both narrow-band and wideband applications. Many common IF frequencies exist in this range of frequencies. If the ADC is used to sample these signals, they are aliased down to baseband during the sampling process in much the same manner that a mixer downconverts a signal. For signals in various Nyquist zones, the following equations may be used to determine the final frequency after aliasing. f1NYQUISTS = fSAMPLE − fSIGNAL f2NYQUISTS = abs (fSAMPLE − fSIGNAL) f3NYQUISTS = 2 × (fSAMPLE − fSIGNAL) f4NYQUISTS = abs (2 × fSAMPLE − fSIGNAL) Using the converter to alias down these narrow-band or wideband signals has many potential benefits. First and foremost is the elimination of a complete mixer stage, along with amplifiers, filters, and other devices, reducing cost and power dissipation. One common example is the digitization of a 21.4 MHz IF using a 10 MSPS sample clock. Using the equation for the fifth Nyquist zone, the resultant frequency after sampling is 1.4 MHz. Figure 44 shows performance under these conditions. Even under these conditions, the AD9042 typically maintains better than 80 dB SFDR. Multitone Performance 0 –20 ENCODE = 41MSPS –40 –60 8 7 8 6 2 5 3 3 6 9 7 4 2 5 8 –80 –100 4.1 8.2 12.3 FREQUENCY (MHz) 16.4 20.5 Figure 43. Multitone Performance Rev. B | Page 20 of 24 4 –80 –100 dc 1 2 3 FREQUENCY (MHz) 4 Figure 44. IF Sampling at 21.4 MHz Input –60 –120 dc ENCODE = 10.0MSPS AIN = 21.4MHz –20 –120 –40 00554-061 POWER RELATIVE TO ADC FULL SCALE (dB) Figure 43 shows the AD9042 in a worst-case scenario of four strong tones spaced fairly close together. In this plot, no dither was used, and the converter still maintains 85 dBFS of spuriousfree range. As noted in the Overcoming Static Nonlinearities with Dither section, a modest amount of dither introduced outof-band can be used to lower the nonlinear components. 0 5 00554-062 To improve sensitivity, several things can be done. First, the noise figure of the receiver can be reduced. Because front-end noise dominates the 0.529 mV rms, each dB reduction in noise figure translates to an additional dBc of sensitivity. Second, providing broadband AGC can improve sensitivity by the range of the AGC. However, the AGC only provides useful improvements if all in-band signals are kept to an absolute minimal power level so that AGC can be kept near the maximum gain. IF SAMPLING, USING THE AD9042 AS A MIXDOWN STAGE POWER RELATIVE TO ADC FULL SCALE (dB) Assuming that the C/N ratio must be 6 dB or better for accurate demodulation, one of the eight signals can be reduced by 48.8 dB before demodulation becomes unreliable. At this point, the input signal power would be 40.6 μV rms on the ADC input or −74.8 dBm. Referenced to the antenna, this is −104.8 dBm. AD9042 RECEIVE CHAIN FOR DIGITAL AND ANALOG BEAM FORMING MEDICAL ULTRASOUND USING THE AD9042 Figure 45 shows the AD9042 used in one channel of the receive chain of a medical ultrasound system. The AD604 receives its input directly from the transducer or from an external preamp connected to the transducer. The AD604 contains two separate stages. The first stage is a preamp with a fixed gain (14 dB to 20 dB) selected by a fixed resistor. The second stage is a variable gain amplifier with the gain set by the AD7226 DAC. The gain is increased over time to compensate for the attenuation of signal level in the body. PRE-AMP +14dB TO +20dB VGA –14dB TO +34dB TRANSDUCER/ PRE-AMP INPUT AD9042 AD604 LPF AD8041 AD7226 00554-063 The AD9042 is an excellent digitizer for digital and analog beamforming medical ultrasound systems. The price/performance ratio of the AD9042 allows ultrasound designers the luxury of using state-of-the-art ADCs without jeopardizing their cost budgets. ADC performance is critical for image quality. The high dynamic range and excellent noise performance of the AD9042 enable higher image quality medical ultrasound systems. Figure 45. Using the AD9042 in Ultrasound Applications Following the AD604, a low-pass filter is used to minimize the amount of noise presented to the ADC. The AD8041 is used to buffer the filter from the AD9042 input. This function may not be required depending on the filter configuration and PCB partitioning. The digital outputs of the AD9042 are then presented to the digital system for processing. Rev. B | Page 21 of 24 AD9042 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 44 34 1 33 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE VIEW A 0.20 0.09 7° 3.5° 0° 0.10 COPLANARITY 11 23 12 VIEW A 0.80 BSC LEAD PITCH 22 0.45 0.37 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCB 051706-A 1.45 1.40 1.35 Figure 46. 44-Lead Low Profile Quad Flat Package [LQFP] (ST-44-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9042ASTZ1 Temperature Range −40°C to +85°C Package Description 44-Lead Low Profile Quad Flat Package [LQFP] 1 Z = RoHS Compliant Part. Rev. B | Page 22 of 24 Package Option ST-44-1 AD9042 NOTES Rev. B | Page 23 of 24 AD9042 NOTES ©1995–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00554-0-9/09(B) Rev. B | Page 24 of 24