6 5 4 3 2 1 REVISION RECORD LTR D ECO NO: APPROVED: DATE: D Connector for programming I2C EEPROM FMC-LPC Connector 3P3VAUX CON_PAR_DATA[10] CON_PAR_DATA[6] SDA J3-1 +3.3V J3-2 CON_PAR_DATA[0] CON_PAR_INT GND J3-3 SCL J3-4 CON_PAR_FS[2] CON_PAR_CLK CON_SPI_MISO CON_I2C0_SDA 3P3VAUX C U1 CON_GPIO[3] CON_GPIO[7] 8 VCC GA1 GA0 1 E0 2 E1 3 E2 6 7 SDA 5 FPGA I2C Lines GA0 SCL TP1 WP VCC12_P VSS 4 M24C02-WDW6TP J1-A ASP-134606-01 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 AK20 AK21 AJ24 AK25 AD21 AE21 AD27 AD28 AJ28 AJ29 GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND CARRIER_POWER_GOOD CON_PAR_DATA[15] CON_PAR_DATA[12] CON_PAR_DATA[8] CON_PAR_DATA[4] CON_PAR_DATA[2] CON_PAR_WR CON_PAR_ADDR[2] CON_PAR_ADDR[0] CON_SPI_SEL_A CON_SPI_MOSI CON_SPI_CLK CON_I2C0_SCL CON_GPIO[1] CON_GPIO[5] 3P3VAUX GA1 J1-B ASP-134606-01 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 AE23 AF23 AG22 AH22 AK23 AK24 AB24 AC25 AB27 AC27 AH26 AH27 AK29 AK30 PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V J1-C ASP-134606-01 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 CON_PAR_DATA[11] CON_PAR_DATA[7] CON_PAR_DATA[3] CON_PAR_RD CON_PAR_ADDR[3] CON_PAR_FS[3] CON_SPORT_DR1 CON_SPORT_RSCLK CON_SPORT_RFS CON_SPORT_DT0 CON_SER_INT CON_SPI_SEL_C CON_I2C1_SCL CON_GPIO[2] CON_GPIO[6] LPC_RESET CON_TMR_B CON_CLKOUT AD23 AE24 AG20 AH20 AJ22 AJ23 AA20 AB20 AC22 AD22 AF26 AF27 AJ27 AK28 AC26 AD26 AE28 AF28 AD29 AE29 AC29 AC30 GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND J1-D ASP-134606-01 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 CON_PAR_DATA[14] CON_PAR_DATA[13] CON_PAR_DATA[9] CON_PAR_DATA[5] CON_PAR_DATA[1] CON_PAR_CS CON_PAR_ADDR[1] CON_PAR_FS[1] CON_SPORT_DT1 CON_SPORT_DR0 CON_SPORT_TFS CON_SPORT_TSCLK CON_SPI_SEL_B CON_I2C1_SDA CON_GPIO[0] CON_GPIO[4] CON_TMR_A CON_UART_RX CON_TMR_D CON_UART_TX AF22 AG23 AF20 AF21 AH21 AJ21 AG25 AH25 AE25 AF25 AC24 AD24 AJ26 AK26 AG27 AG28 AG30 AH30 AE30 AF30 AB29 AB30 Y30 AA30 VREF_A_M2C PRSNT_M2C_L GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ Board present pin C ADP2301 Enabled at +9.07V VIN 5 VCC12_P C1 10uF 25V BST R1 1% 64K9 SW 4 EN FB R7 5% 1K C2 0.1uF X7R 25V L1 6 +5V 500mA (Capable of 1.2A Max) VCC_SWITCHED 4.7uH R5 5% 2K2 R4 1% 52K3 3 GND DNP R8 LPC_RESET 1 VIN D1 2A 30V B U4 VCC S1 2 3 CON_I2C0_SDA MR CON_I2C0_SCL R3 1% 10K CARRIER_POWER_GOOD 4 C7 100nF 16V R6 5% 2K2 1 C3 10uF 6.3V 2 R2 1% 10K +3.3V_SWITCHED B U2 ADP2301AUJZ +3.3V_SWITCHED EEPROM required in VITA standard I2C line pull-up resistors on FPGA board RESET 2 CON_RESETOUT GND 1 ADM6384YKS29D1Z 2K2 Pull-ups for 1st I2C bus (None needed for 2nd I2C bus) Power-on reset and reset by FPGA of SDP daughter board U3 1 VCC_SWITCHED 3 A C4 100nF 16V 2 IN OUT EN NC GND +3.3V 20mA Max +3.3V_SWITCHED 5 4 C5 100nF 16V C6 10uF 6.3V COMPANY: R10 5% 680R ANALOG DEVICES A TITLE: ADP121-AUJZ33 LED1 Power LED DRAWN: SDP-FMC INTERPOSER BOARD DATED: 07/Feb/'12 GREEN CHECKED: DATED: <Checked Date> QUALITY CONTROL: <QC By> RELEASED: <Released By> DATED: <QC Date> CODE: <Code> SIZE: C DRAWING NO: REV: SDP-I-FMC 1 DATED: <Release Date>SCALE: <Scale> SHEET: 1OF 2 6 5 4 3 2 1 REVISION RECORD LTR ECO NO: APPROVED: DATE: D D SDP Connector J2-56 TWI_A0 +3.3V_SWITCHED R9 100K DGND CON_RESETOUT J2-92 SPORT_RSCLK CON_SPORT_RFS J2-90 SPORT_RFS CON_SPORT_DR1 J2-91 J2-31 J2-110 CON_PAR_DATA[14] J2-12 CON_PAR_DATA[13] J2-13 CON_PAR_DATA[12] J2-108 CON_PAR_DATA[11] J2-14 CON_PAR_DATA[10] J2-107 CON_PAR_DATA[9] J2-15 CON_PAR_DATA[8] J2-106 CON_PAR_DATA[7] J2-16 CON_PAR_DATA[6] J2-105 RESET_OUT CON_SPORT_RSCLK CON_SPORT_DR0 C J2-57 CON_PAR_DATA[15] J2-116 VCC_SWITCHED SPORT1_D0 J2-5 SPORT1_D1 CON_SPORT_TSCLK J2-87 SPORT_TSCLK CON_PAR_DATA[5] J2-18 CON_SPORT_TFS J2-89 SPORT_TFS CON_PAR_DATA[4] J2-103 CON_SPORT_DT0 J2-88 SPORT_DT0 CON_PAR_DATA[3] J2-19 CON_SPORT_DT1 J2-32 SPORT_DT1 CON_PAR_DATA[2] J2-102 CON_SER_INT J2-35 SERIAL_INT CON_PAR_DATA[1] J2-20 CON_PAR_DATA[0] J2-101 C J2-3 J2-4 J2-6 J2-11 CON_SPI_SEL_A J2-85 SPI_SEL_A CON_SPI_SEL_B J2-37 SPI_SEL_B CON_SPI_SEL_C J2-38 SPI_SEL_C CON_SPI_MOSI J2-84 SPI_MOSI CON_SPI_MISO J2-83 SPI_MISO CON_SPI_CLK J2-82 J2-17 J2-23 J2-28 CON_CLKOUT J2-80 SDA_0 CON_I2C0_SCL J2-79 SCL_0 CON_I2C1_SDA J2-41 J2-42 J2-21 PAR_RD CON_PAR_WR J2-100 PAR_WR CON_PAR_CS J2-22 PAR_CS CON_PAR_INT J2-99 PAR_INT J2-59 UART_RX CON_UART_TX J2-62 UART_TX J2-43 GPIO_0 CON_GPIO[1] J2-78 GPIO_1 CON_GPIO[2] J2-44 GPIO_2 CON_GPIO[3] J2-77 GPIO_3 CON_GPIO[4] J2-45 GPIO_4 CON_GPIO[5] J2-76 GPIO_5 CON_GPIO[6] J2-47 GPIO_6 CON_GPIO[7] J2-74 GPIO_7 CON_TMR_A J2-48 TMR_A CON_TMR_B J2-73 TMR_B CON_TMR_D J2-72 TMR_D J2-40 J2-46 J2-52 J2-58 J2-63 CON_PAR_ADDR[3] J2-24 PAR_A3 CON_PAR_ADDR[2] J2-97 PAR_A2 CON_PAR_ADDR[1] J2-25 PAR_A1 CON_PAR_ADDR[0] J2-96 PAR_A0 SCL_1 CON_UART_RX CON_GPIO[0] CON_PAR_RD SDA_1 B CLOCKOUT J2-36 SPI_CLK CON_I2C0_SDA CON_I2C1_SCL J2-71 J2-69 J2-75 J2-81 B J2-86 J2-93 CON_PAR_FS[3] J2-26 PAR_FS3 CON_PAR_FS[2] J2-95 PAR_FS2 CON_PAR_FS[1] J2-27 PAR_FS1 J2-98 J2-104 J2-109 J2-115 CON_PAR_CLK J2-94 J2-117 PAR_CLK J2-118 DGND COMPANY: A ANALOG DEVICES A TITLE: DRAWN: SDP-FMC INTERPOSER BOARD DATED: 07/Feb/'12 CHECKED: DATED: <Checked Date> QUALITY CONTROL: <QC By> RELEASED: <Released By> DATED: <QC Date> CODE: <Code> SIZE: C DRAWING NO: REV: SDP-I-FMC 1 DATED: <Release Date>SCALE: <Scale> SHEET: 2OF 2