AN-H24

Supertex inc.
AN-H24
Application Note
Expected Voltages and Waveforms
from an HV9120-Controlled Flyback Converter
1
+VIN
1
2
T1
F
3
+
2
F
4
6
9
12
U1
VDD
OSC
OUT
13 11 16
10
6
5
D2
C
G
B
OUT
VSS
DIS
RES
6
SD
↑
7
HV9120
14 COMP
BIAS
FDBK
VREF
VIN
15
7
8
OSC
IN
1
3
E
5
CS
D
+
4
A
4
5
Input
return
Introduction
The following drawings provide details of the waveforms that
one should expect to see at selected points around the converter circuit. For reference purposes, each voltage and time
is defined only once across all drawings in the series. Thus
a T7 or a V3 means the same thing regardless of on which
drawing it occurs.
In most circumstances the waveforms will be as shown. However, it is possible that, because of certain circuit features
of an individual converter, different waveforms may be observed. Generally though, if a waveform differs significantly
from the ones shown here, it may be a symptom of a circuit
which is not operating as expected, and a valuable clue as to
what to do about correcting the improper operation.
It should also be noted that, though the sketches were based
on a converter using an HV9120, results will be very similar
with any of the PWM ICs or SMPS ICs in the HV91 family of
products
Doc.# DSAN-AN-H24
A040313
Expected Voltages
1. VIN
2. If the converter is running, this will usually be 10V ±1%.
For some converters, a different voltage may be used.
If the converter is shut off or disabled (by removing the
FET, for example), this will be 9 ±.5V.
3. With the converter running and regulating, this will be
very close to 4.0V. Be careful measuring 3. Pin 15 is a
high impedance node and is very sensitive.
4. 4.00V ± <2%.
5. (VDD -0.9) to (VDD -4) depending on the value of bias
resistor chosen.
6. If VDD is below its regulated value, this will be 6–8V. If
VDD equals its regulated value, this will be between 1.8
and 3.2V. If VDD is greater than 10V, this will be very
close to zero. This last condition can only be observed
as a transient, when a large load is removed from the
output or when a large rise in VIN occurs.
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AN-H24
Expected Waveforms
A
V1
T3
V2
Note W
Note X
0
0
Note V
Medium
Minimum Load,
Load and Line Maximum Line
High Load,
Low Line
T1
T2
B
V3
T3
Note U
V4
V4
0
High Load,
Low Line
Medium Load
and Line
Low Load,
High Line
T1
Note U
T2
Note S
C
Note Z
V6
V6
Note Y
V6
VIN
VIN
VIN
V5
0
T2
D
T5
V5
0
T4
T2
0
T4
T3
T3
High Load,
Low Line
Medium Load
and Line
T2 T4
T3
Light Load,
High Line
E
T5
V5
T5
VDD
7-9V
4-5V
Doc.# DSAN-AN-H24
A040313
≈0
≈ 1V
0
T6
2
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AN-H24
Expected Waveforms (cont.)
F
G
T3
T3
T3
T3
V7
T4
Maximum Load,
Minimum Line
V1
V2
V3
V4
Medium Load
and Line
T2
Low Load,
High Line
Can be any height. For best results, should be less
than approximately 2.5V. Height is dependent on QG
of MOSFET, transformer intrawinding (not interwinding) capacitance, tRR of output diodes, and board layout. QG of FET is usually main component, as can be
shown by operating PWM with FET drain open.
Between 0 - 1.0V when unit is regulating. Actual
value depends on the energy the regulator needs to
provide to the load. May be as high as 1.4V during
startup or overload.
Usually between 0.5 - 0.7 of V1. If it is much less than
half of V1, check tRR of output diodes.
VDD (pin 7).
V5
(RDS(ON) • IPEAK) + (RCURRENT SENSE • IPEAK). This is
shown only to note that there is a small ramp at the
bottom of the switch’s on-time waveform.
V6
VIN + ( VOUT •
VIN + ( VOUT •
NOUTPUT WINDING
NINPUT WINDING
LOUTPUT
√
LINPUT
) or
)
V7
Output ripple voltage depends on size and particularly on ESR of output capacitors. Beware of cheap
aluminum electrolytics!
V8
This wouldn’t exist if capacitors were perfect. The
largest one is the main switch turning off. The next
largest is the main switch turning on. The small one
(which may not exist) is the diodes turning off. To reduce these, parallel the main capacitors with ceramics, mylars, or both, with good high frequency characteristics. The noise is coupled into the outputs by the
interwinding capacitance of the coupled inductor and
the layout. Sometimes using a Faraday shield on the
coupled inductor helps, but generally mylar capacitors are an easier way to deal with it.
Doc.# DSAN-AN-H24
A040313
V8
3
These waveforms must be viewed with the
oscilloscope input AC coupled. All others can be
viewed with the oscilloscope input DC coupled.
T1
Should be kept to ­80nsec, or current sense will end
cycle prematurely. Width is dependent on QG of FET,
ESR, and size of the capacitor between pins 6 and 7
of the IC.
T2
Anywhere from approximately 80nsec (minimum) to
1/2T3 for HV9120 (for HV9123 can be >1/2T3), depending on line and load. Length is directly proportional to load, and inversely proportional to line.
T3
Determined by oscillator resistor value (= 1/FOPERATION).
T4
This is the section of tOFF during which the coupled
inductor is discharging into the load. Its actual width
is dependent only on load. At maximum load it is
close to 50% of T3. At smaller loads it is less. During
the time that the inductor is discharged into the output, the output waveform ramps up. The rest of the
time it ramps down.
T5
1/2 of T3 for HV9110, HV9120 and equal to T3 for
HV9113, HV9123.
T6
100nsec +100% –50%. Actual time depends on VDD,
the size of clock resistor, additional clock loading (if
any), whether the part is an HV9110/20 (faster) or an
HV9113/23 (slower), and process variation.
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Notes
S
The rise time of T1 is equal to the entire width of the
leading edge spike on waveform A.
U
Due to the heavy capacitive load from the FET gate,
and clamping by body diodes of the FETs in the IC
driving the external FET, there is usually very little
ringing on this waveform.
V
At extreme low load and/or extreme high input, the
ramp section of the waveform can virtually shorten
until it disappears. Current starts ramping up in the
inductor, however, almost as soon as the leading
edge spike starts rising.
W
The leading edge spike is caused when the PWM
charges the gate capacitance of the FET. The trailing
edge negative spike is caused by gate discharge.
X
A little ringing during the transition from leading
edge spike to ramp sections is normal. If there is a
lot of ringing here, check board layout.
Y
This ring looks horrific, huge, and ugly. It is unavoidable and innocuous - it contains almost no energy
(not enough to forward bias a diode, anyway). What
is ringing is the FET’s drain capacitance and the
coupled inductor’s input side inductance. Eventually the ringing will die out, and the voltage level will
return to VIN.
Because this waveform appears on the MOSFET
drain/coupled inductor interface, it will also be visible on all other windings of the coupled inductor (as
shown or inverted).
Z
Ringing when the main switch turns off is unavoidable. The energy to do this comes from the leakage
inductance in the coupled inductor. Leakage inductance should be minimized because too much of a
spike here can overheat or damage the main switch.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSAN-AN-H24
A040313
4
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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