INFINEON TLE6266G

System Basis Chip
TLE 6266 G
Target Datasheet
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Features
Standard Fault Tolerant differential CAN-Transceiver
Bus Failure Management
Low current consumption mode <70µA
CAN Data Transmission Rate up to 125 kBaud
Low-Dropout Voltage Regulator 5V ± 2%
Two Low Side Switches
Three High Side Switches with internal Charge Pump
Power On and Under-Voltage Reset Generator
Vcc Supervisor
Window Watchdog
Flash Program Mode
Programable Cyclic Wake Timing via SPI
Integrated Fail-Safe Mechanism
Standard 16 bit SPI-Interface
Wide Input Voltage and Temperature Range
Thermal Protection
Enhanced Power P-DSO-Package
Wakeup Input Pin
P-DSO-28-6
Enhanced Power
Type
Ordering Code
Package
TLE 6266 G
on request
P-DSO-28-6
2
Description
The TLE 6266 G is a monolithic integrated circuit in an enhanced power P-DSO-28-6
package, which incorporates a failure tolerant low speed CAN-transceiver for differential
mode data transmission, a low dropout voltage regulator for internal and external 5V
supply as well as a 16 bit SPI interface to control and monitor the IC. Further there are
integrated additional features like three high side switches, two low side switches, a
window watchdog circuit and a reset circuit. The IC offers a low current consumption
mode, that reduces the current to typ. 70µA.
The IC is designed to withstand the severe conditions of automotive applications and is
optimized for low-speed data transmission (up to 125 kBaud).
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Pin Configuration
(top view)
CANH 1
28 WK
RTH 2
27 PWM
RO 3
26 TxD
CANL 4
25 RxD
RTL 5
24 Vcc
GND 6
23 GND
GND 7
22 GND
GND 8
21 GND
GND 9
20 GND
OUTH1 10
19 CLK
OUTL1 11
18 DI
OUTL2 12
17 DO
OUTH2 13
16 CSN
OUTH3 14
15 Vs
P-DSO-28-6
(enhanced power package)
Figure 1
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TLE 6266 Block Diagram
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Target Datasheet TLE 6266
4
Pin Definitions and Functions
Pin No.
Symbol
Function
1
CANH
CAN-H bus line; HIGH in dominant state
2
RTH
CANH-Termination input; connected to CANH via external
termination resistor
3
RO
Reset output; open drain output; integrated pull up; active LOW
4
CANL
CAN-L bus line; LOW in dominant state
5
RTL
CANL-Termination input; connected to CANL via external
termination resistor
6, 7, 8, 9, GND
20, 21,
22, 23
Ground; to reduce thermal resistance place cooling areas on
PCB close to this pins.
10
OUTH1
High side output 1; controlled via PWM input and/or SPI input,
short circuit protected
11
OUTL1
Low side output 1; SPI controlled, with active zener
12
OUTL2
Low side output 2; SPI controlled, with active zener
13
OUTH2
High side output 2; SPI controlled
14
OUTH3
High side output 3; SPI controlled, in cyclic wake mode
controlled by an internal autotiming function
15
VS
Power supply; block to GND directly at the IC with ceramic
capacitor
16
CSN
SPI interface Chip Select Not; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal LOW.
CSN input should only be transitioned when CLK is LOW. CSN
has an internal active pull up and requires CMOS logic level
inputs. See Figure 11 for more details.
17
DO
SPI interface Data Out; DO is a tristate output that transfers
diagnosis data to the control device. Serial data transfered from
DO is a 16 bit diagnosis word with the Least Significant Bit (LSB)
transmitted first. The output will remain 3-stated unless the device
is selected by a LOW on Chip-Select-Not (CSN). DO will accept
data on the rising edge of CLK-signal; see Table 6 for output data
protocol and Figure 11 for more timing details.
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4
Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Function
18
DI
SPI interface Data In; DI receives serial data from the control
device. Serial data transmitted to DI is a 16 bit control word with
the Least Significant Bit (LSB) transferred first. The input has an
active pull down and requires CMOS logic level inputs. DI will
accept data on the falling edge of CLK-signal; see Table 6 for
input data protocol and Figure 11 for more details.
19
CLK
SPI interface clock input; clocks the shiftregister; CLK has an
internal active pull down and requires CMOS logic level inputs
24
VCC
Output voltage regulator; 5V logic supply, block to GND with an
100nF external ceramic capacitor directly at the IC + external
capacitor CQ ³ 22 µF
25
RxD
CAN Receive data output; push-pull output;
LOW: bus becomes dominant, HIGH: bus becomes recessive
26
TxD
CAN Transmit data input; integrated pull up;
LOW: bus becomes dominant, HIGH: bus becomes recessive
27
PWM
Pulse Width Modulation control; integrated pull down, active
HIGH. To PWM-control highside-switch HS1
28
WK
Wake-Up input; for detection of external wake-up events within
cyclic wake mode, integrated pull down, active HIGH, switches on
rising edge
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Functional Block Diagram
OUTL1
Drive
Charge
Pu mp
OUTL2
Drive
Vs
OUTH1
Sw itch
Fail Detect
Protection + Drive
PW M
OUTH2
Drive
OUTH3
Vcc
CS N
Drive
UVLO
CLK
SPI
DI
DO
Vcc
Timer
+
Band
Gap
Oscillator
Reset
Generator
+
Window
Watchdog
LDO
RO
Vs
Vcc
Mode Control
WK
RTL
H Output Stage
CA NL
L Output Stage
RTH
Filter
Receiver
Vcc
Fail Management
CA NH
TxD
Driver
Temp.
Protect
Vcc
Input
Stage
RxD
CA N Fail Detect
G ND
Figure 2
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TLE 6266 G Functional Block Diagram
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6
Circuit Description
The TLE 6266 G is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for
internal and external 5V supply as well as a SPI interface to control and monitor the IC.
Further there are three high side switches, two low side switches, a window watchdog
circuit and a reset circuit integrated. Figure 2 shows the block diagram of the TLE 6266.
6.1
Operation Modes
The TLE 6266 offers four different operation modes (see Figure 3), that are controlled
via the SPI input bits 9,10 (mode bits M0,M1) as shown in Table 1: the normal operation
mode, the receive-only mode, the Vbat stand-by mode and the cyclic wake operation
mode.
The cyclic wake mode itself is subdivided into two modes: the cyclic HS OFF and the
cyclic HS ON mode. Cyclic wake and Vbat stand-by mode are both designed for periods
that do not require communication on the CAN-Bus but offer a low power mode. The
lowest current consumption is achieved in the cyclic wake mode(<70µA).
Table 1
Operation modes bit settings
Mode Bit M1
(SPI Bit 10)
Mode Bit M0
(SPI Bit 9)
Normal operation
1
1
Cyclic Wake
1
0
RxD only
0
1
Vbat stand-by
0
0
Normal Operation Mode
The normal operation mode is designed to receive and transmit data messages as well
as to supply the ECU and control loads via HS- and LS- switches. RTL is switched to
VCC, RTH to GND. Table 3 gives an overview about the available functions in this mode.
RxD-only Mode
In the receive-only mode the receiver stage is activated and the transmitter stage is
deactivated. This means that data at the TxD input is not transmitted to the CAN bus but
receiving of data is still possible. The CANL line is pulled-up to VCC via the RTL output
and CANH is pulled to GND via RTH. This mode is useful in combination to a dedicated
network-management software that allows separate diagnosis for all nodes (see
Chapter 6.2). Table 3 gives an overview about the available functions in this mode.
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Vbat stand-by Mode
In the Vbat stand-by mode the CAN transmitter and receiver stage are deactivated, to
achieve a low power consumption. All other functions are active as in the normal mode
(see Table 3). The CANL line is pulled-up to battery supply voltage via the RTL output
and CANH pulled to GND via RTH. A wake-up request via a CAN message on the bus
is immediately reported to the microcontroller by setting RxD=LOW. The wake pin WK
is not active in this mode. A power-on condition (Vbat pin is supplied) or a watchdog reset,
automatically switches the TLE 6266 to Vbat stand-by mode. Also if the supply voltage
drops below the specified limits (undervoltage reset), the transceiver is automatically
switched to Vbat stand-by mode or power down mode, respectively.
Cyclic Wake Modes
In the cyclic wake operation mode the lowest power consumption is achieved. This mode
consists of two states, the Cyclic HS ON and the Cyclic HS OFF mode.
In the HS ON state the transmitter, receiver and all switches, except the HS3 switch, are
deactivated. The CANL line is pulled-up to battery supply voltage via the RTL output and
CANH pulled to GND via RTH. A wake-up via CAN bus message sets the RxD output to
LOW. In the HS ON state, a long open window is started. If there is no valid watchdog
trigger or a PWM transition into the HS OFF state during this time, a watchdog reset is
activated. Only a correct trigger signal on the PWM Pin causes a transition into the cyclic
HS OFF state. This is called the “failsafe PWM” feature.
In the HS OFF state, almost all functions of the IC are deactivated(also HS3-switch).
Only the wake-up input, the oscillator and the power-on reset circuit are activated. The
oscillator is used to realize the HS3-cyclic wake function.This automatically switches to
HS ON state after a programed time, to enabled HS3 (see Table 2).The CANL line is
pulled-up to battery supply voltage via the RTL output and CANH pulled to GND via RTH.
Only the wake up via CAN message sets the RxD to low (visible in HS ON state).
There are three possibilities to enter the cyclic HS ON mode from the HS OFF mode:
• the cyclic wake function
• a falling edge at the wake-up pin
• a CAN bus wake
Table 2
SPI Bit settings for the cyclic wake function
Input Bit 13
Input Bit12
Period
# of Cycles
(1 cycle = 512µs typ.)
0
0
48ms
94
0
1
96ms
188
1
0
192ms
376
1
1
no cyclic wake-up
-
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Start Up
Power Up
Power Down
Normal Mode
M1 = 1
M0 = 1
SPI
all functions active
SPI
SPI
SPI
RxD-Only
M1 = 0
M0 = 1
SPI
Power
ON
Reset
Vbat Stand-By
M1 = 0
M0 = 0
SPI
all functions active
SPI
Vcc = ON
RTL = 12V
WD = ON
POR = ON
PWM HS12)
3VSU = ON
RxD = H/L
SPI
t>TWDR
Cyclic Wake
Cyclic HS OFF
M1 = 1
M0 = 0
SPI
Watch
dog
Reset
Vcc = OFF/ON POR = ON
RTL = 12V
RxD = H
WD = OFF
3V SV1) = ON
HS3 = OFF
automatic transition after:
- cyclic wake time
- WK pin = H
PWM3)
- CAN bus wake
Cyclic HS ON
M1 = 1
M0 = 0
Vcc = ON
RTL = 12V
WD = ON
HS3 = ON
Mode Bits:
M0 = SPI Input Bit 9
M1 = SPI Input Bit 10
POR = ON
RxD = H/L
3V SV1) = ON
SPI
SPI
1) 3V supervisor feature only active if selected via SPI
2) HS1 is controlled by the SPI input bit 1(activate HS1) and also the PWM
input pin27 if the SPI input bit 11 (PWM enable) is set. In case both
controls are active, the HS1 switch is masked by the SPI input bit 1 (see
figure 12)
3) this function makes sure that the cyclic HS OFF mode can only be
entered via a correct signal at the PWM pin
Figure 3
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State Diagram
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Table 3
Operation mode table
Feature
Normal
mode
RxD only
mode
Vbat
stand-by
mode
Cyclic
Wake
HS ON
Cyclic
Wake
HS OFF
LDO
ON
ON
ON
ON
OFF/ON
Reset
ON
ON
ON
ON
ON
Watchdog
ON
ON
ON
ON
OFF
SPI
ON
ON
ON
ON
OFF
Oscillator
ON
ON
ON
ON
ON
CAN transmit
ON
OFF
OFF
OFF
OFF
CAN receive
ON
ON
OFF
OFF
OFF
OUTHS 11) 2) 3)
ON
ON
ON
OFF
OFF
PWM HS12)
ON
ON
ON
OFF
OFF
OUTHS 21) 3)
ON
ON
ON
OFF
OFF
OUTHS 31) 3)
ON
ON
ON
OFF
OFF
OUTHS 3 cycl. HS
ON1) 3)
OFF
OFF
OFF
ON
OFF
OUTLS 11) 3)
ON
ON
ON
OFF
OFF
1) 3)
OUTLS 2
ON
ON
ON
OFF
OFF
OUT HS 3
Timebase-Test
ON
ON
ON
OFF
OFF
Wake Pin
OFF
OFF
OFF
OFF
ON
Failsafe PWM 4)
OFF
OFF
OFF
ON
OFF
3V Supervisor 1)
ON
ON
ON
ON
ON
RTL output
switched to
Vcc
switched to
Vcc
switched to
Vs
switched to
Vs
switched to
Vs
RxD output
L = bus
dominant;
H = bus
recessive
L = bus
dominant;
H = bus
recessive
active low on
active low on
CAN message CAN message
wake-up
wake-up
active low on
CAN message
wake-up
1)
only active when selected via SPI
2)
HS1 is controlled by the SPI input bit 1(activate HS1) and also the PWM input pin27 if the SPI input bit 11 (PWM
enable) is set. In case both controls are active, the HS1 switch is masked by the SPI input bit 1 (see figure 12)
3)
automatically disabled when a reset resp. watchdog reset occurs
4)
this function makes sure that the cyclic HS OFF mode can only be entered via a correct signal at the PWM pin
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6.2
LS CAN Transceiver
The CAN transceiver TLE 6266 works as the interface between the CAN protocol
controller and the physical CAN bus-lines. Figure 4 shows the principle configuration of
a CAN network.
Controller 1
RxD1
Controller 2
TxD1
RxD2
TxD2
Transceiver2
Transceiver1
BUS Line
Figure 4
CAN Network Example
In normal operation mode a differential signal is transmitted/received. When bus wiring
failures are detected, the device automatically switches in a dedicated single-wire mode
to maintain communication. While no data is transferred, the power consumption can be
minimized by multiple low power operation modes. Further a receive-only mode is
implemented that allows a separate CAN node diagnosis. During normal and RxD-only
mode, RTL is switched to VCC and RTH to GND. During Vbat stand-by and the cyclic
wake mode, RTL is switched to VS and RTH to GND.
Receive-only Mode
The receive only mode is designed for a special test procedure to check the bus
connections. Figure 5 shows a network consisting of 5 nodes. If the connection between
node 1 and node 3 shall be tested, the nodes 2,4 and 5 are switched into receive only
mode. Node 1 and node 3 are in normal mode. If node 1 sends a message, node 3 is the
only node which can acknowledge the message, the other nodes can only listen but
cannot send an acknowledge bit. If node 1 receives the acknowledge bit from node 3,
the connection is OK.
Electromagnetic Emmision (EME)
To reduce radiated electromagnetic emission (EME), the dynamic slopes of the CANL
and CANH signals are both limited and symmetric. This allows the use of an unshielded
twisted or parallel pair of wires for the bus. During single-wire transmission (one of the
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bus lines is affected by a bus line failure) the EME performance of the system is
degraded from the differential mode.
5
4
1
3
2
Figure 5
6.3
Testing the Bus Connection in Receive-only Mode
Bus Failure Management
There are 9 different CAN bus wiring failures defined by the ISO 11519-2 standard.
These failures are devided into 7 failure groups (see Table 4). When a bus wiring failure
is detected the device automatically switches to a dedicated CANH or CANL single-wire
mode to maintain the communication if necessary. Therefore it is equipped with one
differential receiver and four single ended comparators (two for each bus line).
To avoid false triggering by external RF influences, the single wire modes are activated
after a certain delay time. As soon as the bus failure disappears the transceiver switches
back to differential mode after another time delay.
The bus failures are monitored via the diagnosis protocoll of the SPI. Therefore it is
possible to distinguish 6 CAN bus failures or failure groups on the SPI output bits 8 to 13
(see Table 4 and 5). The failures are reported until transmission of the next CAN word
begins.The SPI output bit 0 for CAN bus wiring failure can be read out without SPI
transmission directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal
from LOW to HIGH resets the SPI diagnosis bit 0.
The differential receiver threshold is set to typ. -2.5V. This ensures correct reception in
the normal operation mode as well as in the failure cases 1, 2, 3a and 4 with a noise
margin as high as possible. When one of the bus failures 3, 5, 6, 6a, and 7 is detected,
the defective bus wire is disabled by switching off the affected bus termination and output
stage. Simultaneously the multiplexing output of the receiver circuit is switched to the
unaffected single ended comparator.
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Table 4
CAN bus line failure cases (according to ISO 11519-2)
Failure
#
Failure Description
1
CANL line interrupted
2
CANH line interrupted
3
CANL shorted to Vbat, CANL > 7.2 V
3a (no ISO failure) CANL shorted to Vcc; 3.2 V < CANL < 7.2 V
4
CANH shorted to GND
5
CANL shorted to GND
6
CANH shorted to Vbat; CANH > 7.2 V
6a (no ISO failure) CANH shorted to Vcc; 1.8 V < CANH < 7.2 V
7
CANL shorted to CANH
In case the transmission data input TxD is permanently dominant, both, the CANH and
CANL transmitting stage are disabled after a certain delay time tTxD. This is necessary
to prevent the bus from being blocked by a defective protocol unit or short to GND at the
TxD input.
In order to protect the transceiver output stages from being damaged by shorts on the
bus lines, current limiting circuits are integrated. The CANL and CANH output stage
respectively are protected by an additional temperature sensor, that disables them as
soon as the junction temperature exceeds the maximum value. In the temperature shutdown condition of the CAN output stages receiving messages from the bus lines is still
possible. A thermal shutdown of the CAN-transceiver circuit is monitored via the SPI
output bit 15. The CANH and CANL pins are also protected against electrical transients
which may occur in the severe conditions of automotive environments.
Table 5
SPI output bits for bus failure diagnosis
OBIT
Bus Failure
13
CAN Failure 2 and 4
12
CAN Failure 1 and 3a
11
CAN Failure 6
10
CAN Failure 6a
9
CAN Failure 5 and 7
8
CAN Failure 3
0
CAN Bus Failure
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6.4
Low Dropout Voltage Regulator
The TLE6266 is able to drive external 5V loads up to 45 mA. Its output voltage tolerance
is less than ± 2%. In addition the regulator circuit drives the internal loads like the CANtransceiver circuit. In the cyclic wake HS OFF operation mode the voltage regulator is
switched on and off by a control mechanism (see Chapter 6.5).
The current limitation of the LDO is set to typ. 180mA, to grant that the external capacitor
can be charged quickly. In normal operating mode the external current should be less
then 45mA. This has to guaranteed by the system architecture.
An external reverse current protection is recommended to prevent the output capacitor
from being discharged by negative transients or low input voltage.
Stability of the output voltage is guaranteed for output capacitors CVCC ³ 100 nF.
Nevertheless a lot of applications require a much larger output capacitance to buffer the
output voltage in case of low input voltage or negative transients. Furthermore the due
function of e.g. the reset and 3V-supervisor circuit are supported by a larger output
capacitance because of their reaction times. Therefore a output capacitance
CVCC ³ 22 µF is recommended.
6.5
LDO activation during Cyclic Wake HS OFF
During the cyclic wake HS OFF mode, the LDO is switched on and off, depending on the
output voltage level, which is monitored internaly. Figure 6 shows a detailed flowchart
of the Vcc control loop and also a graph of the Vcc voltage and the thresholds in this
mode. The voltage regulator is switched on as soon as the voltage at VCC falls below the
load-threshold to charge an external capacitor for 1ms. When the nominal voltage level
is reached again, the voltage regulator is automatically deactivated to minimize the
current consumption. The period of charging/decharging is dependant on the external
stabilization capacitor at VCC.
6.6
3V-Supervisor
If the output voltage falls below the 3V-supervisor threshold VST, an internal flip-flop is
set LOW. The SPI output bit 7 monitors this. In normal operation this flip-flop has to be
activated via the SPI input bit 7. This feature is useful e.g. to monitor that the RAM data
of the microcontroller might be damaged or the application is connected to VS the first
time.
The 3V supervisor uses a comparator to monitor the voltage. Additional, there is a
possibility to disable this comparator in order to reduce the current consumption. To do
this, set SPI input bit 15 first and in the next step set SPI input bit 7.
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Monitor Vcc in Cyclic wake
HS OFF Mode
Vcc
Vcc
Yes
5
VCC TH
4
VRESET TH
Vcc > load threshold
VCC TH ?
t
tCHARGE
Charge Diagram
No
Vcc
No
Vcc< reset threshold
VRESET TH
for t > 3µs ?
Charge of Vcc for 1ms
(Switch on LDO)
Yes
RESET after filteringtime
Figure 6
6.7
LDO activation flowchart for the cyclic wake HS OFF mode
SPI (serial peripheral interface)
The 16-bit wide programming word or input word (see Table 6) is read in via the data
input DI, and this is synchronized with the clock input CLK supplied by the µC. The
diagnosis word appears synchroniously at the data output DO (see Table 7).
The transmission cycle begins when the chip is selected by the chip select not input CSN
(H to L). After the CSN input returns from L to H, the word that has been read in becomes
the new control word. The DO output switches to tristate status at this point, thereby
releasing the DO bus for other usage.
The state of DI is shifted into the input register with every falling edge on CLK. The sate
of DO is shifted out of the output register after every rising edge on CLK. For more details
of the SPI timing please refer to Figure 11 to 15.
CAN Bus Wiring Failure direct Read-out
The SPI output bit 0 for CAN bus wiring failure can be read out without SPI transmission
directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal from LOW to
HIGH resets the SPI diagnosis bit 0.
SPI CLK Monitoring during Cyclic Wake Mode
The TLE 6266 offers a feature to monitor the SPI clock signal (CLK pin) during the cyclic
wake mode. If there are edges on the CLK signal, the IC performs a reset and the RO
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pin is set to LOW for t= tWDR (after tWDR a long open window is started and RO is HIGH
again). This feature is activated if the CSN pin is set to HIGH.
Table 6
SPI Input Data Protocol
Table 7
SPI Output Data Protocol
IBIT
Input Data
OBIT
Output Data
15
Disable 3V Reset Comparator
15
Thermal Shutdown Transceiver
14
not used
14
Thermal Shutdown Switches
13
Cyclic Wake Time Bit2
13
CAN Failure 2 and 4
12
Cyclic Wake Time Bit1
12
CAN Failure 1 and 3a
11
PWM Enable HS1
11
CAN Failure 6
10
Mode 1
10
CAN Failure 6a
9
Mode 0
9
CAN Failure 5 and 7
8
not used
8
CAN Failure 3
7
Supervisor Enable
7
3V Supervisor (Vcc < 3V)
6
LS-Switch 2
6
Status LS2
5
LS-Switch 1
5
Status LS1
4
Timebase Test
4
Temperature Prewarning for all
Switches
3
HS-Switch 3
3
Vs Undervoltage Lockout
2
HS-Switch 2
2
Window Watchdog Reset
1
HS-Switch 1
1
Overcurrent HS1
0
Watchdog Trigger
0
CAN Bus Failure
H=ON
L=OFF
6.8
H=ON
L=OFF
Oscillator
The TLE 6266 has an internal oscillator with +/-15% accuracy. The typ. frequency of the
oscillator is 125kHz. After an internal 64-times frequency divider, this gives an typ. cycle
time tcyc= 0.512ms. The frequency of the oscillator can be measured within the normal,
the Vbat stand-by and the RxD-only mode. This is a timebase test (see Chapter 6.15),
activated via SPI input bit 3 and 4. During this test, the HS3-switch will be activated
cyclically.
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6.9
Window Watchdog and Reset
When the output voltage VCC exceeds the reset threshold voltage VRT the reset output
RO is switched HIGH after a delay time tRD. This is necessary for a defined start of the
microcontroller when the application is switched on. As soon as an under-voltage
condition of the output voltage (VCC < VRT) appears, the reset output RO is switched
LOW again. The LOW signal is guaranteed down to an output voltage VCC ³ 1V. Please
refer to Figure 17, reset timing diagram.
In the cyclic wake HS OFF mode, the watchdog circuit is automatically disabled.Both,
the undervoltage reset and the watchdog reset set all SPI input bits LOW.
Long Open Window
After the delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is
started by opening a long open window. The long open window allows the
microcontroller to run his set-up and to trigger the watchdog via the SPI afterwards.
Within the long open window period a watchdog trigger is alternating detected as a
“rising” or “falling edge” by sampling a HIGH on the SPI input bit 0. The trigger is
accepted when the CSN input becomes HIGH after the transmission of the SPI word.
After every reset condition (watchdog reset, undervoltage reset) as well as a transition
in the cyclic wake mode from HS OFF to HS ON, the watchdog starts the long open
window and the default value of the SPI input bit 0 is LOW.
Closed/Open Window
A correct watchdog trigger immediately results in starting the window watchdog by
opening the closed window followed by the open window (see Figure 18). From now on
the microcontroller has to service the watchdog trigger by inverting the SPI input bit 0
alternating. The “negative” or “positive” edge has to meet the open window time. A
correct watchdog service immediately results in starting the next closed window. Please
refer to Figure 19, watchdog timing diagram.
Watchdog Trigger Failure
If the trigger signal does not meet the open window a watchdog reset is created by
setting the reset output RO low for tWDR. Then the watchdog starts again by opening the
long open window. In addition, the SPI output bit 2 is set HIGH until the next successful
watchdog trigger, to monitor a watchdog reset. SPI output bit 2 is also HIGH until the
watchdog is correctly triggered after power-up/start-up. For fail safe reasons the
TLE6266 is automatically switched in Vbat stand-by mode if a watchdog trigger failure
occurs.
6.10
High Side Switch 1
The high side output OUTH1 is able to switch loads up to 250 mA. Its on-resistance is
1.0 W typ. @ 25°C. This switch can be controlled either via the PWM input or the SPI
input bit 1. When the input PWM is used, it has to be enabled by setting the SPI input bit
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11 HIGH. In case of both control inputs being active the PWM signal is masked by the
SPI signal (see Figure 16, High Side Switch 1 Timing Diagram).
The SPI output bit 14 monitors a thermal shutdown of the switches, whereas output bit
4 flags a thermal prewarning. So the microcontroller is able to reduce the power
dissipation of the TLE 6266 by switching off functions of minor priority before the
temperature threshold of the thermal shutdown is reached. Further OUTH1 is protected
against short circuit and overload. The SPI output bit 1 indicates an overload of OUTH1.
As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the
switches are automatically disabled by the under-voltage lockout circuit. This is flagged
by the SPI output bit 3. Moreover the switch is disabled when a reset occurs. After the
second correct triggered watchdog, the switch is released for usage.
6.11
High Side Switch 2
The high side output OUTH2 is able to switch loads up to 250 mA. Its on-resistance is
1.0 W typ. @ 25°C. This switch is controlled via the SPI input bit 2.
The SPI output bit 14 monitors a thermal shutdown of the switches, whereas output bit
4 flags a thermal prewarning. So the microcontroller is able to reduce the power
dissipation of the TLE 6266 by switching off functions of minor priority before the
temperature threshold of the thermal shutdown is reached. As soon as the under-voltage
condition of the supply voltage is met (VS < VUVOFF), the switches are automatically
disabled by the under-voltage lockout circuit. This is flagged by the SPI output bit 3.
Moreover the switch is disabled when a reset occurs. After the second correct triggered
watchdog, the switch is released for usage.
6.12
High Side Switch 3
The high side output OUTH3 is able to switch loads up to 250 mA. Its ON-resistance is
1.0 W typ. @ 25°C. This switch is controlled via the SPI input bits 3 and 4. To supply
external wake-up circuits in low power mode (cyclic wake mode), the output OUTH3 is
periodically activated by entering the cyclic wake HS ON mode. The autotiming period
is programable via SPI (see Table 2).This has to be done, to minimize the current
consumption depending on the cyclic wake time (see Figure 21).
In the cyclic wake mode, the PWM signal is used to switches HS3 from the cyclic HS ON
to the cyclic HS OFF state, if correctly triggered within the long open window (see Figure
17). This is called the “fail-safe PWM” feature
The SPI output bit 14 monitors a thermal shutdown of the switches, whereas output bit
4 flags a thermal prewarning. So the microcontroller is able to reduce the power
dissipation of the TLE 6266 by switching off functions of minor priority before the
temperature threshold of the thermal shutdown is reached. As soon as the under-voltage
condition of the supply voltage is met (VS < VUVOFF), the switches are automatically
disabled by the under-voltage lockout circuit. This is flagged by the SPI output bit 3.
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Target Datasheet TLE 6266
Moreover the switch is disabled when a reset occurs. After the second correct triggered
watchdog, the switch is released for usage.
6.13
Low Side Switches 1 & 2
The two low side outputs OUTL1 and OUTL2 are able to switch loads up to 100 mA.
Their on-resistance is 1.5 W typ. @ 25°C. This switches are controlled via the SPI input
bits 5 and 6. In case of high inrush currents a built in zener circuit (typ. 37 V) activates
the switches to protect them.
The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 4
flags a thermal prewarning. So the microcontroller is able to reduce the power dissipation
of the TLE 6266 by switching off functions of minor priority before the temperature
threshold of the thermal shutdown is reached. The SPI output bits 5/6 are giving a
feedback about current status (ON/OFF) of OUTL1/OUTL2. As soon as the undervoltage condition of the supply voltage is met (VS < VUVOFF), the switches are
automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI
diagnosis bit 3. In addition the outputs OUTL1 and OUTL2 are disabled when a reset
occurs. After the second correct triggered watchdog, the switches are released for
usage.
6.14
Wake Up Pin
This pin is used to wake up the TLE 6266 with an external signal from the µC. The
feature is active during cyclic HS OFF mode to switch the transceiver into the cyclic HS
ON mode before starting up the µC. A correct wake up signal is a rising edge at the WK
pin during cyclic HS OFF mode. The WK pin has an implemented pull down resistance.
6.15
Timebase Test
This test is useful to measure the internal cycle time of the TLE 6266. The µC may use
this information to activate special functions or routines in the cyclic wake mode, which
are depending on timing.(e.g. to switch on/off a LED after a certain number of cyclic HS
ON conditions). During the long open window the timebase test is not available.
To measure the internal cyclic timing, the SPI input bit 3 and 4 have to be set HIGH. Then
the HS3 switch is automatically enabled for 3 times during the closed window of the
watchdog (see Figure 7). A correct SPI input word (with IBit 3 and 4 set HIGH) has to
be read in first, to activate the timebase test. Due to he fact, that the input command gets
activated after the CSN LOW to HIGH transition, it takes t=tSYNC to activate the timebase
test. If this SPI input command is given within the open window, tSYNC=max 500ns. If the
command is given during closed window (this is not a watchdog trigger command) the
synchronisation tSYNC can last up to 500µs.
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HS3
closed window (12 cycles)
2cycl.
ON
OFF
CSN
2cycl.
2cycl.
2cycl.
2cycl.
2cycl.
t
t SYNC
SPI Input word with
timebase test
command
t
Figure 7
6.16
Timebase Test Diagram
Flash program mode
To disable the watchdog feature a flash program mode is available. This mode is
selected by applying a voltage of 6.8V < VPWM < 7.2V at pin PWM. This is useful e.g. if
the flash-memory of the micro has to be programmed and therefore a regular watchdog
triggering is not possible. If the SPI is required in the flash program mode to change e.g.
the mode of the TLE6266, the first input telegram has to be “00000000”.
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7
Explanation of the Mode Transitions
To better understand the description, the reader has to be familiar with the Chapter 6.
All descriptions are starting from the normal mode, as the main operation mode. This
means, the component was powered up before and after the power up procedure
automaticaly in the Vbat stand-by mode.
Now, the watchdog circuit has to be operated correctly to switch the component in the
other modes ( details see Chapter 6). So the starting point is the TLE 6266 in normal
mode with a correct triggered watchdog like shown in Figure 8,9,10.
Normal Mode and Cyclic HS ON
In normal mode, the watchdog has to be triggered within the open window with a
dedicated SPI input command (Watchdog Trigger IBit 0, alternatively HIGH, LOW,...).
The CAN bus communication is active and a message can be transfered/received. After
the correct SPI input command to change into the Cyclic HS mode, the HS3 switch gets
activated. In parallel a long open window is started, wich has to be triggered. This mode
can be operated as long as the watchdog is triggered correctly. In this mode, no
communication is possible but an external circuit can be supplied by HS3. CANL is
pulled up to Vs by the RTL termination, CANH is pulled to GND via RTH.
Cyclic HS OFF mode
To switch from HS ON to HS OFF, the PWM input has to be triggered with a falling egde.
This is called the PWM failsafe trigger to avoid unwanted transitions into the HS OFF
mode. In the HS OFF mode the HS3 switch is deactivated and the lowest power
consumption is achieved. The LDO monitors Vcc and switches on/off due to a special
control mechanism explained in Chapter 6.5. Three possibilities can switch the TLE
6266 back to the cyclic wake HS ON mode:
7.1
CAN Bus Wake-Up
CANL is pulled to Vs. A signal transition at CANL below a certain wake-up threshold
causes a wake up and automatic transition into the cyclic HS ON mode (see Figure 8).
HS3 is activated again and also the long open window of the watchdog mechanism. The
watchdog has to be triggered correctly from that time on. If the signal at the PWM pin
makes a HIGH to LOW transition, the device switches to HS OFF again.
This wake up via the CAN bus message is flagged to the µC by setting the RxD output
pin from HIGH to LOW. The reason for this behavior is to indicate the µC a wake up
request. Now, the µC is able to activate the whole module to serve the requested action
by the bus system.
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Mode State
Normal Mode
Normal Mode
Cyclic HS ON
Cyclic HS OFF
Cyclic HS ON
Cyclic HS ON
Normal Mode
Vbat Stdby
CSN,
SPI word*
SPI
normal
mode
SPI
cyclic HS
ON
SPI
cyclic HS
ON
SPI
normal
mode
t
Watchdog trigger bit
=SPI bit0**
t
missing trigger =
timeout =
Watchdog Reset
Window watchdog***
closed
window
open
window
closed
window
open
window
long open window
long open window
closed
window
open
window
closed
window
open
window
Watchdog reset pulse time tWDR
long open window
t
HS3
t
PWM
PWM trigger
PWM
trigger
Vs
Vcc
Bus
Wake
trigger
CANL
t
CAN Bus message
CANH
t
Input filtering time tIFT
* for the exact timing relations between CSN
and SPI-DI and -DO word please look at
datasheet fig. 11,12,13,14,15
Figure 8
7.2
** bit0 is transfered with the SPI input word
BUT
the watchdog trigger is set, after readout of
the SPI input bit = CSN LOW to HIGH
(see arrows at CSN signal)
*** for a correct watchdog triggering:
closed window must always exceed 12 cycles
open window is max. 20 cycles
long open window is max. 128 cycles
otherwise
a watchdog reset will be generated
Cyclic Wake with CAN Message Wake-up
Wake-Up via Wake Pin
CANL is pulled to Vs. A signal transition at the wake pin WK from LOW to HIGH (rising
edge) causes a wake up and automatic transition into the cyclic HS ON mode (see
Figure 9). HS3 is activated again and also the long open window of the watchdog
mechanism. The watchdog has to be triggered correctly from that time on. If the signal
at the PWM pin makes a HIGH to LOW transition, the device switches to HS OFF again.
This wake up via the wake pin is comming from an external circuitry (switch, etc.) and
is not flagged by the RxD.
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Mode State
Normal Mode
Normal Mode
Cyclic HS ON
Cyclic HS OFF
Cyclic HS ON
Cyclic HS ON
Normal Mode
Vbat Stdby
CSN,
SPI word*
SPI
normal
mode
SPI
cyclic HS
ON
SPI
cyclic HS
ON
SPI
normal
mode
t
Watchdog trigger bit
=SPI bit0**
closed
window
open
window
closed
window
t
missing trigger =
timeout =
Watchdog Reset
Window watchdog***
open
window
long open window
long open window
closed
window
open
window
closed
window
open
window
long open window
Watchdog reset pulse time tWDR
t
HS3
t
PWM
PWM trigger
PWM
trigger
t
wake trigger
Wake
Wake event
t
Input filtering time tIFT
* for the exact timing relations between CSN
and SPI-DI and -DO word please look at
datasheet fig. 11,12,13,14,15
Figure 9
7.3
** bit0 is transfered with the SPI input word
BUT
the watchdog trigger is set, after readout of
the SPI input bit = CSN LOW to HIGH
(see arrows at CSN signal)
*** for a correct watchdog triggering:
closed window must always exceed 12 cycles
open window is max. 20 cycles
long open window is max. 128 cycles
otherwise
a watchdog reset will be generated
Cyclic Wake with Wake Pin
Wake-Up Cyclic Wake Autotiming Function
CANL is pulled to Vs. After the transition from HS ON to HS OFF, an autotiming function
is started. This is a timer controled by the internal oscillator, which can be programed by
SPI IBit 12,13. If the timer exceeds the programed time this causes a wake up and
automatic transition into the cyclic HS ON mode (see Figure 10). HS3 is activated again
and also the long open window of the watchdog mechanism. The watchdog has to be
triggered correctly from that time on. If the signal at the PWM pin makes a HIGH to LOW
transition, the device switches to HS OFF again.
This wake up via the autotiming function is not flagged to the µC by setting the RxD pin.
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Mode State
Normal Mode
Normal Mode
Cyclic HS ON
Cyclic HS ON
Cyclic HS OFF
Cyclic HS ON
Normal Mode
Vbat Stdby
CSN,
SPI word*
SPI
normal
mode
SPI
cyclic HS
ON
SPI
cyclic HS
ON
SPI
normal
mode
t
Watchdog trigger bit
=SPI bit0**
closed
window
open
window
closed
window
t
missing trigger =
timeout =
Watchdog Reset
Window watchdog***
open
window
long open window
long open window
closed
window
open
window
Cyclic wake time
48ms selected
HS3
closed
window
open
window
long open window
Watchdog reset pulse time tWDR
t
48ms
t
PWM
PWM trigger
PWM
trigger
t
* for the exact timing relations between CSN
and SPI-DI and -DO word please look at
datasheet fig. 11,12,13,14,15
Figure 10
Version 1.06
*** for a correct watchdog triggering:
closed window must always exceed 12 cycles
open window is max. 20 cycles
long open window is max. 128 cycles
otherwise
a watchdog reset will be generated
** bit0 is transfered with the SPI input word
BUT
the watchdog trigger is set, after readout of
the SPI input bit = CSN LOW to HIGH
(see arrows at CSN signal)
Cyclic Wake with Cyclic Wake Autotiming Function
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8
Electrical Characteristics
8.1
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
VS
VS
VCC
VCANH/L
VCANH/L
-0.3
28
V
-0.3
40
V
-0.3
5.5
V
-10
28
V
-40
40
V
VS >0 V
tp< 0.5s; tp/T < 0.1
VBUS
– 150
100
V
see ISO 7637
-0.3
VCC
V
Voltages
Supply voltage
Supply voltage
Regulator output voltage
CAN input voltage (CANH, CANL)
CAN input voltage
(CANH, CANL)
Transient voltage at CANH
and CANL
Logic input voltages ( DI, CLK, VI
CSN, WK, PWM, TxD)
tp< 0.5s; tp/T < 0.1
+0.3
Logic output voltage
(DO, RO, RxD)
VDO/RO/RD -0.3
VCC
Termination input voltage
(RTH, RTL)
VTL /TH
Electrostatic discharge
voltage at pin CANH, CANL
VESD
-4000
4000
V
human body model;
C = 100pF, R = 1.5kW
Electrostatic discharge
voltage to any other pin
VESD
-2000
2000
V
human body model;
C = 100pF, R = 1.5kW
ICC
IOUTH1
IOUTH2
IOUTH3
IOUTL1
IOUTL2
*
0,2
A
* internally limited
*
0.3
A
* internally limited
-0.7
0.3
A
tp< 0.5s; tp/T < 0.1
-0.7
0.3
A
tp< 0.5s; tp/T < 0.1
-0.2
0.4
A
tp< 0.5s; tp/T < 0.1
-0.2
0.4
A
tp< 0.5s; tp/T < 0.1
V
+0.3
-0.3
VS
V
+0.3
Currents
Output current; Vcc
Output current; OUTH1
Output current; OUTH2
Output current; OUTH3
Output current; OUTL1
Output current; OUTL2
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8.1
Absolute Maximum Ratings (cont’d)
Parameter
Symbol
Limit Values
Unit
min.
max.
-40
150
°C
-50
150
°C
Remarks
Temperatures
Junction temperature
Storage temperature
Tj
Tstg
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause
irreversible damage to the integrated circuit.
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8.2
Operating Range
Parameter
Symbol
Limit Values
min.
Unit
Remarks
After VS rising above
VUV ON
max.
Supply voltage
VS
VUV OFF 27
V
Supply voltage slew rate
dVS /dt
-0.5
5
V/ms
Supply voltage increasing
VS
VS
VI
-0.3
VUV ON V
VUV OFF V
VCC
V
Supply voltage decreasing
Logic input voltage (DI, CLK,
CSN, PWM, TxD )
-0.3
-0.3
22
SPI clock frequency
ICC
CCC
fCLK
–
1
MHz
Junction temperature
Tj
-40
150
°C
Rthj-pin
Rthj-a
–
25
K/W
–
65
K/W
Output current
Output capacitor
45
Outputs in tristate
Outputs in tristate
mA
mF
Thermal Resistances
Junction pin
Junction ambient
measured to pin 7
Thermal Prewarning and Shutdown (junction temperatures)
Thermal prewarning
ON temperature
TjPW
120
170
°C
bit 0 of SPI diagnosis
word;
hysteresis 30°K (typ.)
Thermal shutdown temp.
TjSD
150
200
°C
hysteresis 30°K (typ.)
Ratio of SD to PW temp.
TjSD / TjPW 1.05
–
–
160
°C
Thermal shutdown temp. CAN TjSD
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Target Datasheet TLE 6266
8.3
Electrical Characteristics
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
IS
ISSB1
–
8
10
mA
normal mode
–
75
100
mA
cycl. wake 48ms;
VS=12V; Tj=25°C
ISTAT
–
–
70
mA
4.9
5.0
5.1
V
0.1mA < ICC< 30mA
4.8
5.0
5.5
V
0A < ICC < 100µA
Line regulation
VCC
VCC
,VCC
-20
20
mV
9 V < VS < 15 V;
ICC = 10mA
Load regulation
,VCC
-25
25
mV
0.1mA < ICC< 30mA;
VS = 9V
dB
VS < 1 Vss;
CQ ³ 22µF;
100Hz< f <100kHz
Quiescent current Pin VS
Current consumption
Quiescent current
ISSB1 = IS - ICC
Static quiescent current
Voltage Regulator; Pin VCC
Output voltage
Output voltage
Power supply ripple rejection PSRR
Output current limit
Dropvoltage
VDR = VS - VCC
40
ICCmax
VDR
155
IIL
VIH
VIL
0.2 ´ –
–
V
VIHY
tIFT
50
200
500
mV
–
–
3
µs
-
-
mA
1)
0.15
0.45
V
ICC = 30 mA;
see note 1)
–3
–2
–1
mA
–
–
0.7 ´ V
Wake-up Input WK
Input current
H-input voltage threshold
L-input voltage threshold
Hysteresis of input voltage
Input filtering time
VCC
VCC
1) measured when output voltage VCC dropped 100 mV from the nom. value obtained at 13.5 V inp. voltage VS
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8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
Oscillator
Oscillator frequency fosc
Cycle time
(guaranteed by design)
fOSC
tCYC
125
kHz
+/-15% accuracy
512
µs
64 times frequency
divider
Reset Generator; Pin RO
4.0
Reset low output voltage
VRT
VRO
Reset high output voltage
VRO
4.0
Reset threshold voltage
4.3
4.65
V
0.2
0.4
V
IRO = 1mA
(VCC ³ VRT) or
VCC ³ 1V
(IRO = 200 µA)
VCC+ V
0.1
20
150
500
mA
VRO = 0V
Reset reaction time
IRO
tRR
1
3
10
µs
VCC < VRT to
RO = L; normal, RxD,
stand-by mode
Reset reaction time
tRR
–
–
50
µs
VCC < VRT to
RO = L; cyclic wake
mode
Reset delay time (16 cyl.)
tRD
6.1
8.1
10.2
ms
2.3
2.7
3.1
V
2
8
20
µs
7.6
10
12.3
ms
4.6
6.1
7.6
ms
Reset pull up current
3 V Supervisor; (bit 7 of SPI output word)
Supervisor threshold voltage VST
Supervisor reaction time
tSR
VCC < VST to
diagnosis bit 7 = L
Watchdog Generator
tWD
Closed window time (12 cyl.) tCW
Watchdog trigger time
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8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Open window time (20 cyl.)
Watchdog reset-pulse time
(4 cyl.)
Symbol
tOW
tWDR
Limit Values
Unit Test Condition
min.
typ.
max.
7.7
10.2
12.7
ms
1.5
2.0
2.6
ms
Long open window (128 cyl.) tLOW
65
ms
Under-Voltage Lockout (bit 3 of SPI output word)
UV-Switch-ON voltage
UV-Switch-OFF voltage
UV-ON/OFF-Hysteresis
VUV ON
VUV OFF
VUV HY
–
5.35
6.00
V
VS increasing
4.50
4.85
5.20
V
VS decreasing
–
0.5
–
V
VUV ON – VUV OFF
PWM Input to control OUTH1; Pin PWM (high active)
VIH
–
L-input voltage threshold
VIL
0.2 ´ –
Vcc
–
V
Hysteresis of input voltage
VIHY
II
CI
50
200
500
mV
5
25
180
mA
VI = 0.2 * VCC
–
10
15
pF
0 V < VCC < 5.25 V
H-input voltage threshold
Pull down current
Input capacitance
Version 1.06
–
0.7 ´ V
VCC
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Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
Switches
High Side Output OUTH1; (controlled by PWM or bit 1 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTH1 = -0.25 A
RDSON H1 –
VOUTH1
Clamp diode forward voltage VOUTH1
Leakage current
IOLH1
Switch ON delay time
tdONH1
Active zener voltage
-5.0
-100
1.0
2.0
W
1.5
4.0
W
5.2 V £ VS £ 9 V
-3.0
-0.5
V
IOUTH1 = – 0.25 A
0.8
1
V
IOUTH1 = 0.25 A
-5
–
µA
VOUTH1 = 0 V
10
100
ms
PWM to OUTH1;
RL = 100 W
20
100
ms
PWM to OUTH1;
RL = 100 W
Switch OFF delay time
tdOFFH1
Overcurrent shutdown
threshold
ISDH1
-1.0
-0.6
-0.3
A
Shutdown delay time
tdSDH1
IOCLH1
10
25
50
ms
-2.0
-1.0
-0.5
A
Current limit
High Side Output OUTH2; (controlled by bit 2 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTH2 = -0.25 A
RDSON H2 –
VOUTH2
Clamp diode forward voltage VOUTH2
Leakage current
IOLH1
Switch ON delay time
tdONH1
Active zener voltage
Switch OFF delay time
Version 1.06
-5.0
-100
tdOFFH1
31
1.0
2.0
W
1.5
4.0
W
5.2 V £ VS £ 9 V
-3.0
-0.5
V
IOUTH2 = – 0.25 A
0.8
1
V
IOUTH2 = 0.25 A
-5
–
µA
VOUTH2 = 0 V
10
100
µs
CSN high to OUTH2;
RL = 100 W
20
100
µs
CSN high to OUTH2;
RL = 100 W
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
High Side Output OUTH3; (controlled by bit 3 and bit 4 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTH3 = -0.25 A
RDSON H3 –
VOUTH3
Clamp diode forward voltage VOUTH3
Leakage current
IOLH3
Switch ON delay time
tdONH3
Active zener voltage
Switch OFF delay time
-5.0
-100
tdOFFH3
1.0
2.0
W
1.5
4.0
W
5.2 V £ VS £ 9 V
-3.0
-0.5
V
IOUTH3 = – 0.25 A
0.8
1
V
IOUTH3 = 0.25 A
-5
–
µA
VOUTH3 = 0 V
10
100
µs
CSN high to OUTH3;
RL = 100 W
20
100
µs
CSN high to OUTH3;
RL = 100 W
1.5
3.0
W
2.0
5.0
W
5.2 V £ VS £ 9 V
37
42
V
IOUTL1 = + 0.1 A
5
µA
VOUTL1 =15 V;
Tj < 85°C
Low Side Output OUTL1 ( bit 5 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTL1 = 0.1 A
RDSON L1
Active zener clamp voltage
Leakage current
VOUTL1
IOLL1
Switch ON delay time
tdONL1
5
50
µs
CSN high to OUTL1;
RL = 100 W
Switch OFF delay time
tdOFFL1
5
50
µs
CSN high to OUTL1;
RL = 100 W
1.5
3.0
W
2.0
5.0
W
–
32
Low Side Output OUTL2 ( bit 6 of SPI input word)
Static Drain-Source
ON-Resistance;
IOUTL2 = 0.1 A
Version 1.06
RDSON L2
–
32
5.2 V £ VS £ 9 V
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
32
37
42
V
IOUTL2 = + 0.1 A
5
µA
VOUTL2 =15 V;
Tj < 85°C
Leakage current
VOUTL2
IOLL2
Switch ON delay time
tdONL2
5
50
µs
CSN high to OUTL2;
RL = 100 W
Switch OFF delay time
tdOFFL2
5
50
µs
CSN high to OUTL2;
RL = 100 W
2
cycl.
2
cycl.
Active zener clamp voltage
Timebase Test TBT(bit 4 of SPI input word)
HS3 OFF timing
tTBON
tTBOFF
# of HS activations for TBT
nTBT
HS3 ON timing
Version 1.06
2
33
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
VCC
–
VCC
V
I0 = – 250µA
VOL
0
–
0.9
V
I0 = 1.25mA
HIGH level input voltage
threshold
VIH
0.7 ´ –
VCC
V
LOW level input voltage
threshold
VIL
-0.3
0.3 ´ V
HIGH level input current
IIH
IIL
-200
-50
-10
µA
Vi = 4 V
-800
-200
-40
µA
Vi = 1 V
CAN-Transceiver
Receiver Output R´D
HIGH level output voltage
VOH
– 0.9
LOW level output voltage
Transmission Input T´D
LOW level input current
VCC
–
+ 0.3
VCC
Bus Lines CANL, CANH
Differential receiver
recessive-to-dominant
threshold voltage
VdRxD(rd) – 2.8 – 2.5 – 2.2 V
VCC = 5.0 V
Differential receiver
dominant-to-recessive
threshold voltage
VdRxD(dr) – 3.2 – 2.9 – 2.6 V
VCC = 5.0 V
CANH recessive output
voltage
VCANH,r
0.10
CANL recessive output
voltage
VCANL,r
VCC –
– 0.2
CANH dominant output
voltage
VCANH,d VCC VCC VCC
– 1.4 – 1.0
Version 1.06
34
0.15
0.30
V
TxD = VCC;
RRTH < 4 kW
–
V
TxD = VCC;
RRTL < 4 kW
V
TxD = 0 V;
ICANH = – 40 mA
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
1.0
1.4
V
TxD = 0 V;
ICANL = 40 mA
CANL dominant output
voltage
VCANL,d
–
CANH output current
ICANH
– 110 – 80
– 50
mA
VCANH = 0 V;
TxD = 0 V
–5
0
5
mA
cycl. wake mode;
VCANH = 12 V
50
80
110
mA
VCANL = 5 V;
TxD = 0 V
–5
0
5
mA
cycl. wake mode;
VCANL = 0 V;
VS = 12 V
Voltage detection threshold Vdet(th)
for short-circuit to battery
voltage on CANH and CANL
6.5
7.3
8.0
V
Voltage detection threshold
for short-circuit to battery
voltage on CANH
Vdet(th)
VBAT VBAT
– 2.5 – 2
VBAT
–1
V
CANH wake-up voltage
threshold
VCANH,w 1.2
1.9
2.7
V
CANL wake-up voltage
threshold
VCANL,w 2.2
3.1
3.9
V
Wake-up voltage threshold
hysteresis
DVwu
0.2
–
–
V
DVwu = VCANL,wu –
VCANH,wu
CANH single-ended receiver VCANH
threshold
1.6
2.1
2.6
V
failure cases 3, 5 and
7
CANL single-ended receiver
threshold
VCANL
2.4
2.9
3.4
V
failure case 6 and 6a
CANL leakage current
ICANL,lk
–5
0
5
mA
VCC = 0 V; VS = 0 V;
VCANL = 12 V;
Tj < 85 °C
CANH leakage current
ICANH,lk
–5
0
5
mA
VCC = 0 V; VS = 0 V;
VCANH = 5 V;
Tj < 85 °C
CANL output current
Version 1.06
ICANL
stand-by/
cycl. wake mode
u
u
35
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
typ.
max.
40
95
Unit Test Condition
Termination Outputs RTL, RTH
W
Io = – 10 mA
VCC VCC –
– 1.0 – 0.7
V
|Io| < 1 mA;
RoRTL
5
15
30
kW
VBAT stand-by or cycl.
wake mode
RTH to ground switch-on
resistance
RRTH
–
40
95
W
Io = 10 mA
RTH output voltage
VoRTH
–
0.7
1.0
V
Io = 1 mA;
low power mode
RTH pull-down current
IRTH,pd
40
75
120
mA
failure cases 6 and 6a
RTL pull-up current
IRTL,pu
– 120 – 75
– 40
mA
failure cases 3, 3a, 5
and 7
RTH leakage current
IRTH,lk
–5
0
5
mA
VCC = 0 V;
VS = 0 V;
VRTH = 5 V;
Tj < 85 °C
RTL leakage current
IRTL,lk
–5
0
5
mA
VCC = 0 V;
VS = 0 V;
VRTL = 12 V;
Tj < 85 °C
CANH and CANL bus output trd
transition time recessive-todominant
0.6
1.2
2.1
µs
10% to 90%;
C1 = 10 nF;
C2 = 0; R1 = 100 W
CANH and CANL bus output tdr
transition time dominant-torecessive
0.3
0.6
1.3
µs
10% to 90%;
C1 = 1 nF; C2 = 0; R1 =
100 W
RTL to VCC switch-on
resistance
RRTL
–
RTL output voltage
VoRTL
RTL to BAT switch series
resistance
CAN-Transceiver
Dynamic Characteristics
Version 1.06
36
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition
Minimum dominant time for
wake-up on CANL or CANH
twu(min)
8
22
38
µs
stand-by mode;
VS = 12 V
Minimum wake-up time on
pin WK (wake-up)
tWK(min)
15
25
50
µs
Low power mode; VS =
12 V
Failure cases 3 and 6
detection time
tfail
10
45
80
µs
normal operating
mode
Failure case 6a detection
time
2
4
8
ms
normal operating
mode
Failure cases 5, 6, 6a and 7
recovery time
10
45
80
µs
normal operating
mode
Failure cases 3
recovery time
250
500
750
µs
normal operating
mode
Failure cases 5 and 7
detection time
1.0
2.0
4.0
ms
normal operating
mode
Failure cases 5 detection
time
0.4
1.0
2.4
ms
stand-by mode;
VS = 12 V
Failure cases 6, 6a and 7
detection time
0.8
4.0
8.0
ms
stand-by mode;
VS = 12 V
Failure cases 5, 6, 6a and 7
recovery time
–
2
–
µs
stand-by mode;
VS = 12 V
Propagation delay
tPD(L)
TxD-to-RxD LOW (recessive
to dominant)
–
1.5
2.1
µs
C1 = 100 pF;
C2 = 0; R1 = 100 W; no
failures and bus failure
cases 1, 2, 3a and 4
–
1.7
2.4
µs
C1 = C2 = 3.3 nF;
R1 = 100 W; no bus
failure and failure
cases 1, 2, 3a and 4
–
1.8
2.5
µs
C1 100 pF; C2 = 0;
R1 = 100 W; bus failure
cases 3, 5, 6, 6a and 7
–
2.0
2.6
µs
C1 = C2 = 3.3 nF;
R1 =100 W; bus failure
cases 3, 5, 6, 6a and 7
Version 1.06
37
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
–
1.2
2.0
µs
C1 = 100 pF;
C2 = 0; R1 =100 W; no
failures and bus failure
cases 1, 2, 3a and 4
–
2.5
3.5
µs
C1 = C2 = 3.3 nF;
R1 = 100 W; no bus
failure and failure
cases 1, 2, 3a and 4
–
1.0
2.1
µs
C1 100 pF; C2 = 0;
R1 = 100 W; bus failure
cases 3, 5, 6, 6a and 7
–
1.5
2.6
µs
C1 = C2 = 3.3 nF;
R1 = 100 W; bus failure
cases 3, 5, 6, 6a and 7
15
25
50
µs
Edge-count difference
ne
(falling edge) between CANH
and CANL for failure cases 1,
2, 3a and 4 detection
–
4
–
–
Edge-count difference (rising
edge) between CANH and
CANL for failure cases 1, 2,
3a and 4 recovery
–
2
–
–
1.0
2.0
3.5
ms
Propagation delay
TxD-to-RxD HIGH
(dominanat to recessive)
Minimum hold time to go
sleep command
TxD permanent dominant
disable time
Version 1.06
tPD(H)
th(min)
tTxD
38
normal operating
mode
normal mode
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
VIH
–
–
0.7 ´ V
VIL
0.2 ´ –
–
V
VIHY
IICSN
IICLK/DI
CI
50
200
500
mV
-100
-25
-5
mA
VCSN = 0.7 ´ VCC
5
25
100
mA
VDI = 0.2 ´ VCC
–
10
15
pF
0 V < VCC < 5.25 V
VDOH
VCC
VCC
–
V
IDOH = 1 mA
SPI-Interface
Logic Inputs DI and CSN
H-input voltage threshold
L-input voltage threshold
Hysteresis of input voltage
Pull up current at pin CSN
Pull down current at pin DI
Input capacitance
at pin CSN, DI
VCC
VCC
Logic Output DO
H-output voltage level
– 1.0 – 0.7
L-output voltage level
Tri-state leakage current
VDOL
IDOLK
–
0.2
0.4
V
IDOL = – 1.6 mA
-10
–
10
mA
VCSN = VCC
0 V < VDO < VCC
Tri-state input capacitance
CDO
–
10
15
pF
VCSN = VCC
0 V < VCC < 5.25 V
Data Input Timing
Clock period
Clock high time
Clock low time
Clock low before CSN low
CSN setup time
Version 1.06
tpCLK
tCLKH
tCLKL
tbef
tlead
1000
–
–
ns
500
–
–
ns
500
–
–
ns
500
–
–
ns
500
–
–
ns
39
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont’d)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C; CANtransceiver circuitry: – 40 °C < Tj < 125 °C; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
CLK setup time
Clock low after CSN high
DI setup time
DI hold time
Input signal rise time
at pin DI, CLK and CSN
Input signal fall time
at pin DI, CLK and CSN
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
tlag
tbeh
tDISU
tDIHO
trIN
500
–
–
ns
500
–
–
ns
250
–
–
ns
250
–
–
ns
–
–
200
ns
tfIN
–
–
200
ns
trDO
tfDO
tENDO
tDISDO
tVADO
–
50
100
ns
CL = 100 pF
–
50
100
ns
CL = 100 pF
–
–
250
ns
low impedance
–
–
250
ns
high impedance
–
100
250
ns
VDO < 0.2 VCC;
VDO > 0.7VCC;
CL = 100 pF
Data Output Timing
DO rise time
DO fall time
DO enable time
DO disable time
DO valid time
Version 1.06
40
2002-11-26
Target Datasheet TLE 6266
9
Timing Diagrams
CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register
CSN
time
CSN Low to High: Data from Shift-Register is transfered to Output Power Switches
CLK
1
0
2
3
5
4
6
7
8
10 11 12
9
13 14 15
0
1
2
3
4
5
_
6
7
8
1
new Data
actual Data
DI
0
9
10 11 12
0
+
13 14 15
1
+
DI: Data will be accepted on the falling edge of CLK-Signal
actual Status
previous Status
DO
_0
_1
_2
_3
4_
5_
_6
_7
_8
_9
_ 11
_ 12
_
10
_ 14
_ 15
_
13
0
1
DO: State will change on the rising edge of CLK-Signal
eg.
HS1
Figure 11
Version 1.06
old Data
actual Data
Data Transfer Timing
41
2002-11-26
Target Datasheet TLE 6266
Figure 12
SPI-Input Timing
Figure 13
Turn OFF/ON Time
Version 1.06
42
2002-11-26
Target Datasheet TLE 6266
Figure 14
DO Valid Data Delay Time and Valid Time
Figure 15
DO Enable and Disable Time
Version 1.06
43
2002-11-26
Target Datasheet TLE 6266
SPI input
bit 1
H
L
PWM
(SPI input
bit 11 = H)
t
H
L
HSSwitch1
t
ON
OFF
t
Figure 16
Cyclic
Wake
High Side Switch1 Timing Diagram
Vbat
stand-by
mode
ON
Vbat
stand-by
mode
Cyclic Wake Mode
Cyclic HS ON
Cyclic HS OFF
Cyclic HS ON
OFF
PWM
Correct
Trigger
No Trigger
t
H
L
HSSwitch3
t
ON
OFF
Cyclic Wake
Time
RO
Long Open Window tLOW
t
H
tWDR
L
Figure 17
Version 1.06
Cyclic Wake Timing Diagram
44
2002-11-26
Target Datasheet TLE 6266
tWD
tCW
tOW
closed window
open window
t / ms
Figure 18
Watchdog Timeout Definitions
tCW
WD
Trigger
tCW
tCW
tOW
tOW
tCW+tOW
tCW
tCW+tOW
tOW
tOW
tCW
tCW
tCW
tOW
tWDR
Reset
Out
t
Watchdog
timer reset
t
normal
operation
Figure 19
Version 1.06
timeout
(to long)
normal
operation
timeout
(to short)
normal
operation
Watchdog Timing Diagram
45
2002-11-26
Target Datasheet TLE 6266
Vcc
VRT
t < tRR
VST
tRD
WD
Trigger
tCW+tOW
tCW
tOW
tCW
tOW
tCW+tOW
Watchdog
timer reset
SPI output
bit 2
t
t
tRR
tWDR
Reset
Out
tRD
t
start up
normal operation
tSR
undervoltage
start up
HIGH
LOW
t
activation by
microcontroller
Figure 20
Reset Timing Diagram
Current Consumption (typ.)
76
75
Current (µA)
74
73
Current (µA) typ.
72
71
"Static" Current
70
69
10
48
100
1000
10000
Cyclic Wake Time (ms)
Figure 21
Version 1.06
Current Consumption during Cyclic Wake Mode
46
2002-11-26
Target Datasheet TLE 6266
RxD
5V
R1
C1
C2
RTH
TxD
CANH
CSN
20 pF
DO
CANL
C1
R1
CLK
RTL
DI
OUTL1
PWM
OUTL2
RO
OUTH1
WK
OUTH2
VCC
OUTH3
13.5 V
+VS
22 µF
GND
100 nF
Figure 22
Version 1.06
Timing Test Circuit
47
2002-11-26
Target Datasheet TLE 6266
10
Application
Vbat
CAN bus
CSN
+VS
CLK
33 V
DI
22 µF 68 nF
CANH
DO
CANL
TxD
µC
e.g.
Infineon
C164
RxD
RTH
PWM
RTL
RO
OUTL2
Vcc
OUTL1
OUTH3
22 µF
OUTH2
WK
OUTH1
GND
GND
TLE 6266 G
Figure 23
Version 1.06
Application Circuit
48
2002-11-26
Target Datasheet TLE 6266
11
Package Outlines
GPS05123
P-DSO-28-6
(Plastic Dual Small Outline Package)
Figure 24
The P-DSO-28-6 package
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Version 1.06
49
2002-11-26
Target Datasheet TLE 6266
Edition 1999-10-12
Published by Infineon Technologies AG
St.-Martin-Strasse 53
D-81541 München
© Infineon Technologies AG1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Version 1.06
50
2002-11-26
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defined processes, which are both constantly under review and
ultimately lead to good operating results.
Better operating results and business excellence mean less
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thereby, less frustration and more satisfaction.”
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Published by Infineon Technologies AG