Supertex inc. P-Channel Enhancement-Mode Vertical DMOS FET Features ►► ►► ►► ►► ►► ►► ►► TP2640 General Description Low threshold (-2.0V max.) High input impedance Low input capacitance Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Applications ►► ►► ►► ►► ►► ►► ►► Logic level interfaces - ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Ordering Information Product Summary TP2640LG-G Package Option 8-Lead SOIC 2500/Reel TP2640N3-G 3-Lead TO-92 1000/Bag Part Number Packing BVDSS/BVDGS (max) (min) 15Ω -2.0A VGS(th) (max) -0.7V Pin Configuration TP2640N3-G P003 3-Lead TO-92 2000/Reel DRAIN DRAIN DRAIN DRAIN TP2640N3-G P013 TP2640N3-G P014 GATE SOURCE N/C N/C -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature -55 C to +150 C O O Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Typical Thermal Resistance Package θja 8-Lead SOIC 101OC/W TO-92 132OC/W Doc.# DSFP-TP2640 B081613 ID(ON) -400V TP2640N3-G P002 TP2640N3-G P005 RDS(ON) DRAIN SOURCE GATE TO-92 8-Lead SOIC Product Marking YYWW P2640 LLLL YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging Package may or may not include the following marks: Si or 8-Lead SOIC SiTP 2 6 4 0 YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging Package may or may not include the following marks: Si or TO-92 Supertex inc. www.supertex.com TP2640 Thermal Characteristics (continuous)† ID ID Power Dissipation (pulsed) @TA = 25OC 8-Lead SOIC -86mA -600mA TO-92 -180mA -0.8mA Package † ‡ IDR† IDRM 0.74W‡ -86mA -600mA 1.0W -180mA -0.8mA ID (continuous) is limited by max rated Tj . Mounted on FR5 board, 25mm x 25mm x 1.57mm. Electrical Characteristics (T = 25°C unless otherwise specified) A Symbol Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage -400 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -0.8 - -2.0 V VGS = VDS, ID = -1.0mA Change in VGS(th) with temperature - - 5.0 mV/OC VGS = VDS, ID = -1.0mA Gate body leakage - -100 nA VGS = ±20V, VDS = 0V ΔVGS(th) IGSS -1.0 IDSS ID(ON) RDS(ON) ΔRDS(ON) Zero gate voltage drain current - On-state drain current VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC - - A VGS = -10V, VDS = -25V 12 15 11 15 11 15 - - 0.75 %/ C VGS = -10V, ID = -300mA 200 - - mmho VDS = -25V, ID = -300mA GFS Forward transconductance CISS Input capacitance - - 300 COSS Common source output capacitance - - 50 CRSS Reverse transfer capacitance - - 12 td(ON) Turn-on delay time - - 10 Rise time - - 15 Turn-off delay time - - 60 Fall time - - 40 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr VGS = 0V, VDS = Max rating mA - Change in RDS(ON) with temperature -10.0 VGS = 0V, VDS = -100V µA -1.0 -0.7 Static drain-to-source on-state resistance - Conditions VGS = -2.5V, ID = -20mA VGS = -4.5V, ID = -150mA Ω VGS = -10V, ID = -300mA O pF VGS = 0V, VDS = -25V, f = 1.0MHz ns VDD = -25V, ID = -300mA, RGEN = 25Ω -1.8 V VGS = 0V, ISD = -200mA - ns VGS = 0V, ISD = -200mA Notes: 1. All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V INPUT -10V Pulse Generator 10% td(ON) 0V OUTPUT VDD Doc.# DSFP-TP2640 B081613 tr td(OFF) 90% 10% RGEN 90% t(OFF) t(ON) D.U.T. tf INPUT OUTPUT RL 90% 10% 2 VDD Supertex inc. www.supertex.com TP2640 Typical Performance Curves BVDSS Variation with Temperature On-Resistance vs. Drain Current 30 1.1 RDS(ON) (ohms) BVDSS (normalized) 1.0 VGS = -4.5V VGS = -2.5V 24 VGS = -10V 18 12 6.0 0 50 100 0 150 0 -0.4 -0.8 -2.0 -1.2 -1.6 -2.0 Tj ( C) ID (amperes) Transfer Characteristics V(th) and RDS Variation with Temperature O VDS = -25OC 2.5 25OC 1.2 RDS(ON) @ -10V, -0.3A 2.0 VGS(th) (normalized) ID (amperes) -1.6 TA = -55OC -1.2 125OC -0.8 1.1 1.5 1.0 1.0 0.9 0.5 -0.4 0.8 0 RDS(ON) (normalized) 0.9 -50 0 -2.0 -4.0 -6.0 -8.0 -10 V(th)@ -1mA -50 0 50 0 150 100 Tj (OC) VGS (volts) Capacitance vs. Drain-to-Source Voltage Gate Drive Dynamic Characteristics -10 400 f = 1MHz -8.0 CISS VGS (volts) C (picofarads) 300 200 678 pF -6.0 100 0 CRSS 0 -10 -20 -30 0 0 -40 1.0 2.0 3.0 4.0 5.0 QG (nanocoulombs) VDS (volts) Doc.# DSFP-TP2640 B081613 VDS = -40V -2.0 COSS 263pF VDS = -10V -4.0 3 Supertex inc. www.supertex.com TP2640 Typical Performance Curves (cont.) Output Characteristics Saturation Characteristics -2.0 -1.0 VGS = -10V -0.8 -6V ID (amperes) ID (amperes) -1.6 -1.2 -0.8 VGS = -10V -6V -4V -0.6 -0.4 -3V -4V -0.4 0 -0.2 -3V 0 -10 -20 -30 -40 0 -50 0 -2.0 -4.0 -8.0 -10 Power Dissipation vs. Temperature Transconductance vs. Drain Current 1.0 -6.0 VDS (volts) VDS (volts) 2.0 VDS = -25V 0.6 PD (watts) GFS (siemens) 0.8 TA = -55OC 0.4 0 25OC 125OC 0.2 0 -0.4 -0.8 TO-92 1.0 -1.2 -1.6 0 -2.0 0 25 50 Thermal Resistance (normalized) ID (amperes) TO-92 (pulsed) TO-92 (DC) -0.01 -1.0 -10 -100 150 0.8 0.6 0.4 0.2 0 0.001 -1000 VDS (volts) Doc.# DSFP-TP2640 B081613 125 1.0 TA = 25OC -0.1 100 Thermal Response Characteristics Maximum Rated Safe Operating Area -10 -1.0 75 TA (OC) ID (amperes) TO-92 TC = 25OC PD = 1.0W 0.01 0.1 1.0 10 tp(seconds) 4 Supertex inc. www.supertex.com TP2640 8-Lead SOIC (Narrow Body) Package Outline (LG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch θ1 D 8 Note 1 (Index Area D/2 x E1/2) E1 E L2 L 1 θ L1 Top View View B Note 1 Gauge Plane Seating Plane View B h A h A A2 Seating Plane A1 e b Side View View A-A A Note: 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 A2 b MIN 1.35* 0.10 1.25 0.31 NOM - - - - MAX 1.75 0.25 1.65* 0.51 D E E1 4.80* 5.80* 3.80* 4.90 6.00 3.90 5.00* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 L2 θ θ1 0 5O - - 8 15O O 1.04 REF 0.25 BSC O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version I041309. Doc.# DSFP-TP2640 B081613 5 Supertex inc. www.supertex.com TP2640 3-Lead TO-92 Package Outline (N3) D A Seating Plane 1 2 3 L c b e1 e Side View Front View E1 E 1 3 2 Bottom View Symbol Dimensions (inches) A b c MIN .170 .014 NOM - - MAX .210 .022 † .014 † D E E1 e e1 L .175 .125 .080 .095 .045 .500 - - - - - - .205 .165 .105 .105 .055 .610* † .022 † JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TP2640 B081613 6 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com