AD9523/AD9523-1 Schematics PDF

8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
OUT0
OUT0_N
R12
D
D
100
1
2
3
P4
SAMTECTSW10608GS3PIN
J2
JOHNSON142-0701-201
3.3V OUT 4-7
1
SI04
R13
R16
10K
10K
GND
EEPROM_SEL
2 3 4 5
C11
0.1UF
GND
C13
0.1UF
C12
0.1UF
1
2
3
P5
SAMTECTSW10608GS3PIN
1
R66
3.3V OUT 0-3
10K
10K
C
STATUS1/SP1
3.3V OUT 4-7
R19
R20
10K
10K
P6
DNI
0
C129
0.33UF
C8
0.47UF
GND
0.1UF
C3
R5
49.9
R2
0.33UF
0.1UF
C10
TBD0402
DNI
C5
TBD0402
DNI
R4
0
3.3V_PLL2
C7
R6
0.47UF
0.47UF
0 DNI
OUT5
OUT5_N
VDD_1_8_OUT6_7
OUT6
OUT6_N
VDD3_OUT6_7
OUT7
OUT7_N
VDD_1_8_OUT8_9
OUT8
OUT8_N
VDD3_OUT8_9
OUT9
OUT9_N
CONFIGURATION FOR CMOS VCXO AND LVPECL VCXO
1
2
3
10K
REF_SEL
P3
10K
A
R8
SAMTECTSW10608GS3PIN
AD9523 - C6 CONNECT TO LDO_VCO PIN 14: R4 = 0 OHM AND R6 = DNI.
AD9523-1 - C6 CONNECT TO LDO_VCO PIN 12: R4 = DNI AND R6 = 0 OHM.
R7
3.3V REF
RESETB
CSB_DUT
SCLK/SCL_DUT
SDIO/SDA_DUT
SDO_DUT
CONFIGURATION FOR AD9523 AND AD9523-1
1.8V OUT 4-9
OUT4
OUT4_N
OUT5
OUT5_N
OUT6
OUT6_N
B
3.3V OUT 4-7
OUT7
OUT7_N
OUT8
OUT8_N
3.3V OUT 8-9
OUT9
OUT9_N
AD9523
SYNCB
3.3V REF
PDB
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CMOS VCXO - DNI R1, R2, R3, C2, AND C3. REPLACE C4 WITH 0 OHM RESISTOR.
LVPECL VCXO - R1, R2, R3, C2, C3, C4 AS SHOWN.
SDIO_SDA
RESET_N
CS_N
SCLK_SCL
GND
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
SI03
1
J3
A
1.8V OUT 10-13
R3
0.1UF
3
VCXO_CTRL
VDD_1_8_OUT4_5
OUT10_N
OUT10
C2
4
5
X1
OUT4
OUT4_N
VDD3_OUT4_5
OUT11_N
OUT11
3.3V_PLL2
VC
OUT+
OUTGND
LDO_PLL1
VDD3_PLL1
REFA
REFA_N
REFB
REFB_N
LF1_EXT_CAP
OSC_CTRL
OSC_IN
OSC_IN_N
LF2_EXT_CAP
LDO_PLL2
VDD3_PLL2
LDO_VCO
PD_N
REF_SEL
SYNC_N
VDD3_REF
OUT12_N
OUT12
B
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
3.3V OUT 10-13
60-800MHZ
6
VCC
C9
C4
1000PF
DNI
DNI
C6
0.1UF
Y1
49.9
R75
0
GND
3.3V_PLL1
REFA
REFA_N
REFB
REFB_N
49.9
GND
C134
R1
J1
JOHNSON142-0701-201
1
3.3V VCXO
2 3 4 5
GND
R74
0
OUT13_N
OUT13
3.3V_PLL1
SAMTECTSW10608GS3PIN
STATUS0_SP0
STATUS1_SP1
1K
GND
SDO
REF_TEST
OUT13_N
OUT13
VDD3_OUT12_13
OUT12_N
OUT12
VDD_1_8_OUT12_13
OUT11_N
OUT11
VDD3_OUT10_11
OUT10_N
OUT10
VDD_1_8_OUT10_11
R10
VCXO_CTRL
ZD_IN_N
ZD_IN
VDD_1_8_OUT0_1
OUT0
OUT0_N
VDD3_OUT0_1
OUT1
OUT1_N
VDD_1_8_OUT2_3
OUT2
OUT2_N
VDD3_OUT2_3
OUT3
OUT3_N
EEPROM_SEL
PAD
PLL1_OUT
PAD
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNI
GND
STATUS0/SP0
OUT3
OUT3_N
OUT2
OUT2_N
R21
1
2
3
TP1
WHT
R18
GND
THIS SMA WILLL SERVE AS DUAL USE FOR AN ALTERNATE CLK INPUT
OUT1
OUT1_N
1.8V PLL2
C
1.8V OUT 0-3
3.3V OUT 4-7
AN A LO G
DE V CES
2 3 4 5 JOHNSON142-0701-201
GND
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
GND
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD9523
EVALUATION BOARD
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
E
9523EE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
D
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
R.Huntley
2
SCALE
NONE
SHEET
1
1
OF 5
8
6
7
2
3
4
5
1
REVISIONS
REV
PLACE TERMINATIONS CLOSE TO DUT
T4
MABA-007159-000000
C16
5
1
OUT1
3
49.9
2 3 4 5
2
R22
5
6
1
ADTT1-1
GND
R24
100
REFB
J19
PRI
SEC
C17
4
2
3
OUT1_N
4 3 2
R31
100
142-0761-861
GND
0.1UF
C31
OUT2_N
GND
-(NC)
0.1UF
0.1UF
REFB_N
GND
GND
142-0761-861
142-0761-861
2 3 4
C32
O3
OUT4
O4
1
OUT3
2 3 4
C18
1
C
5
2
6
1
ADTT1-1
REFA
R32
100
J13
1
O3N
OUT3_N
0.1UF
0.1UF
C33
J27
1
O4N
OUT4_N
0.1UF
4 3 2
4 3 2
142-0761-861
142-0761-861
REFA_N
GND
GND
142-0761-861
142-0761-861
C34
2 3 4
O6
OUT6
O5
1
1
R33
100
J14
0.1UF
C21
J15
0.1UF
142-0761-861
C36
0
2 3 4
O7
1
R34
100
J16
J17
0.1UF
0.1UF
C37
OUT8_N
1
O7N
3.3V OUT 8-9
16
15
1
2
PAD
OUT8
0.1UF
C23
GND
U12
VCC
VT
VREF
D
Q
D_N
Q_N
PAD
VEE
0.1UF
4 3 2
C86
O8
12
11
R86
150
GND
142-0761-861
C38
O9
4
2
3
J18
SEC
O10
OUT10
1
OUT9_N
PRI
B
GND
R35
100
GND
J32
R28 0.1UF
100 C25
R87
150
1
OUT9
4 3 2
GND
2 3 4
1
1
GND
142-0761-861
5
O8N
2 3 4
C24
J31
0.1UF
142-0761-861
GND
B
0.1UF
C87
GND
142-0761-861
T3
MABA-007159-000000
ADCLK905BCPZ-WP
GND
0.1UF
R85
GND
OUT7_N
4 3 2
GND
GND
R27
100
142-0761-861
C85
142-0761-861
OUT7
1
0.1UF
4 3 2
C22
J29
O6N
OUT6_N
1
O5N
OUT5_N
0.1UF
C35
14
7
R26
100
J28
OUT5
2 3 4
C20
C
GND
GND
13
8
GND
3
0.1UF
C19
49.9
2 3 4 5
T2 4
R23
SI01
J12
1
R25
100
J26
JOHNSON142-0701-201
J9
J30
T1 4
C30
OUT2
1
SI02
ROUTE AS 50OHM SINGLE ENDED TRACES
1
0.1UF
D
142-0761-861
1
APPROVED
OUTPUT TERMINATIONS
REFERENCE INPUTS
JOHNSON142-0701-201
J8
DATE
2 3 4
D
DESCRIPTION
0.1UF
C39
J33
1
O10N
OUT10_N
-(NC)
0.1UF
0.1UF
4 3 2
142-0761-861
GND
C26
C40
OUT11
OUT12
R29
100
R36
100
0.1UF
C27
OUT11_N
0.1UF
C41
OUT12_N
0.1UF
0.1UF
GND
A
A
142-0761-861
2 3 4
C28
O13
OUT13
1
J20
R30
100
0.1UF
C29
SCHEMATIC
J21
O13N
OUT13_N
0.1UF
1
AN A LO G
DE V CES
4 3 2
142-0761-861
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
GND
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
<DRAWING_TITLE_HEADER>
AD9523
EVALUATION BOARD
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
E
9523EE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
D
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
R.Huntley
2
SCALE
NONE
SHEET
1
2
OF 5
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
BYPASS CAPACITORS
(FOR ONLY THE 9523)
D
3.3V OUT 0-3
C44
0.1UF
3.3V OUT 4-7
C44B
0.1UF
C50
0.1UF
C53
0.1UF
DNI
DNI
3.3V_PLL1
C45
0.1UF
C50B
0.1UF
C45B
0.1UF
3.3V OUT 10-13
C53B
0.1UF
C55
0.1UF
C51B
0.1UF
C54
0.1UF
C54B
0.1UF
3.3V OUT 8-9
C57B
0.1UF
C61
0.1UF
DNI
C56
0.1UF
C56B
0.1UF
DNI
3.3V OUT 10-13
C61B
0.1UF
C65
0.1UF
DNI
1.8V OUT 0-3
1.8V PLL2
DNI
DNI
C57
0.1UF
DNI
3.3V REF
C51
0.1UF
C55B
0.1UF
DNI
3.3V_PLL2
D
C59
0.1UF
DNI
1.8V OUT 4-9
C59B
0.1UF
C62
0.1UF
DNI
DNI
C65B
0.1UF
1.8V OUT 10-13
C62B
0.1UF
C66
0.1UF
C66B
0.1UF
C74
0.1UF
DNI
DNI
C74B
0.1UF
C72
0.1UF
DNI
C72B
0.1UF
C67
0.1UF
DNI
C67B
0.1UF
DNI
GND
C
C
DC TO DC STEP DOWN
L2
P7
6VDC
1
2
3
6V_FILT
1UH
CR1
1
1
BAT54
4VDC
C58
R39
33UH
C47
4.7UF
R55
0
R82 DNI
4.99K
0
2
3
5
25
26
27
GND
GND
C49
1UF
SYNC
FREQ
UV2
EN1
EN2
LDOSD
12
16
7
10
11
6V_FILT
C77
C70
C
A
8.5V OVER PROTECTION CIRCUIT
CR7
MMSZ4693T1G
R17
R49
3 Q5
10
1
33UH
28K
3
Q3
2
SI2316BDS-T1-E3
C73
0.1UF
C78
1UF
ADP1829ACPZ-R7
C69
AN A LO G
DE V CES
100NF
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
2 MMBT3904
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OF ANALOG DEVICES.
<DRAWING_TITLE_HEADER>
AD9523
EVALUATION BOARD
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
E
9523EE01
SIZE
PTD ENGINEER
D
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
7
SCHEMATIC
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
GND
8
C79
4.7UF
A
2.0K
R11
10K
C81
1.0UF
1
GND
R69
10K
2.2VDC
10
C71
1UF
L3
R50
1000PF
29 VREG
VREG
SI2316BDS-T1-E3
R53
100NF
GND
GND
A
DH2
DL2
COMP2
POK2
BST2
4
19
15
PAD
2
17
28
14
CSL2
13
SW2
9
SS2
6
FB2
28K
3
2.21K
10000PF
1
SI2316BDS-T1-E3
C63
R41
4VDC
Q2
R45
GND
1000PF
R43
R37
22UF
C42
100
C43
1.0UF
R44
L1
0
22UF
13.3K
2
1
C80
GND
R51
22
18
32
24
23
Q4
1K
R42
0
2
SI2316BDS-T1-E3
R38
DH1
DL1
COMP1
POK1
BST1
3
R54
DNI
1800PF
TRK1
TRK2
CSL1
SW1
SS1
FB1
B
GND
DNI
1
U1
R52
R84
0
10
GND
PGND1
PGND2
PAD
R83
0
1UF
33PF
100
GND
10
R48
31
VREG 8
R46 20
2.21K 21
C64
10000PF
30
1
1
2.2VDC
3
C68
C76
C60
4.99K
Q1
C1
2
R40
BAT54
R47
100NF
B
3
PV
IN
6V_FILT
CR2
1800PF
3
15K
N
C52
470UF
C75
P
4.7UF
N
C46
470UF
C48
P
GND
PJ-102A
6
5
4
3
R.Huntley
2
SCALE
NONE
SHEET
1
3
OF 5
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
APPROVED
DATE
3.3V REGULATORS
D
L11
MAX I 300MA
1UH
U5
1
IN
3
EN
4
R15
0
5
OUT
BYP
DNI
GND
L12
1
TP13
WHT
3.3V OUT 0-3
10000PF
C104
R68
0
DNI
2
C102
10UF
1
TP6
WHT
3.3V OUT 4-7
ADP1713AUJZ-3.3-R7
4VDC
D
C108
10UF
1UH
C110
10UF
C114
10UF
1
GND
DNI
L13
MAX I 300MA
OUT
BYP
1UH
C
5
GND
2
1
L14
TP12
WHT
3.3V OUT 10-13
10000PF
C105
TP7
WHT
U7
1
IN
3
EN
4
C100
10UF
1
3.3V OUT 8-9
ADP1713AUJZ-3.3-R7
C
TP17
WHT
C109
10UF
1UH
C111
10UF
C115
10UF
GND
MAX I 150MA
U4
ADP150AUJZ-3.3-R7
1
1.8V REGULATOR
VIN
3
EN
NC
4
VOUT
3.3V REF
1UH
R70
0
L9
5
DNI
3.3V_PLL2
R72
0
R73
0
DNI
DNI
1
TP15
WHT
1UH
GND
2
C107
10UF
C99
10UF
B
1
L8
TP8
WHT
R71
0
L10
3.3V_PLL1
DNI
R67
0
DNI
R14
0
DNI
1
TP14
WHT
B
1UH
C113
10UF
C116
10UF
C117
10UF
1
MAX I 150MA
DNI
U2
ADP150AUJZ-1.8-R7
1
P19
1
2
GND
2.2VDC
VIN
3
Z5.530.3225.0
EN
NC
4
VOUT
TP9
WHT
GND
1
L4
5
TP4
WHT
1.8V OUT 4-9
MAX I 300MA
1UH
GND
R79
0
2
R80
0
DNI
DNI
L5
R81
0
ADP1713AUJZ-3.3-R7
DNI
1
TP11
WHT
U3
1.8V OUT 0-3
C14
10UF
1
IN
3
EN
4
1UH
R76
0
C84
10UF
DNI
L6
R77
0
DNI
R78
0
DNI
1
BYP
TP10
WHT
OUT
1
L7
5
TP5
WHT
3.3V USB
1UH
GND
2
C93
10UF
C97
10UF
C95
10UF
C98
10UF
C101
1UH
10000PF
1.8V OUT 10-13
C112
10UF
C106
10UF
GND
A
1
3
C15
10UF
VIN
EN
NC
4
VOUT
1
R88
0
U11
ADP150AUJZ-1.8-R7
GND
DNI
1
L15
5
TP18
WHT
1.8V PLL2
A
TP3
WHT
DNI
1UH
SCHEMATIC
GND
2
C82
C83
10UF
10UF
1
AN A LO G
DE V CES
TP16
WHT
<DRAWING_TITLE_HEADER>
AD9523
EVALUATION BOARD
GND
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
E
9523EE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
D
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
R.Huntley
2
SCALE
NONE
SHEET
1
4
OF 5
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
USB INTERFACE
D
D
BYPASS CAPS FOR CY7C68013A
2.2UF
C121
C122
0.1UF
C123
0.1UF
C124
0.1UF
C125
0.1UF
C126
0.1UF
C127
0.1UF
C128
0.1UF
GND
(P10)
1
2
3
P11
SAMTECTSW10608GS3PIN
3.3V USB
(P10)
(P14)
(P18)
(P6)
(P24)
(P34)
(P39)
SDIO_U
SDIO/SDA
C118
EEPROM_SEL
USB SCL
SDO
CY7C68013A-56PVXC
STATUS1/SP1
P13
CSB
SAMTECTSW10608GS3PIN
RESETB
C130
GND
3.3V USB
PDB
0.1UF
SCLK/SCL
SDIO/SDA
CSB
3.3V USB
P14
1
2
3
SAMTECTSW10608GS3PIN
PDB
REF_SELA
19
1
2
B
SCLK/SCL
SCLK/SCL_DUT
TSW-113-23-L-D
CSB
CSB_DUT
GND
3
R60
140
5
EEPROM_SEL
R61
140
GND
C
GND
LNJ312G8TRA (GREEN)
CY7C68013A-56PVXC
R62
140
CR4
A
C
LNJ312G8TRA (GREEN)
CR5
A
A
C
LNJ312G8TRA (GREEN)
SN74LVC125APW
U10
11
12
AN A LO G
DE V CES
GND
SN74LVC125APW
3.3V USB
14
GND
SN74LVC125APW
U10
8
13
A
SN74LVC125APW
U10
6
9
CR3
1
2
STATUS1/SP1
STATUS0/SP0
P15
U10
P20
2
1A
1B
GND
USB STATUS
A
SYNCB
1
2
1
SDIO_U
SDO
74LVC541APW
7914J-1-000E
USB STATUS
CSB_U
RESETB_U
SYNCB_U
PDB_U
REFSEL_U
1
40
41
42
43
44
45
46
47
25
26
27
28
29
30
31
32
52
53
54
55
56
1
2
3
4
PA0/INT0*
PA1/INT1*
PA2/SLOE
PA3/WU2
PA4/FIFOADR0
PA5/FIFOADR1
PA6/PKTEND
PA7/FLAGD/SLCS*
PB0/FD0
PB1/FD1
PB2/FD2
PB3/TXD1/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
PD0/FD8
PD1/FD9
PD2/FD10
PD3/FD11
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
VCC
GND
I0
O0
I1
O1
I2
O2
I3
O3
I4
O4
I5
O5
I6
O6
I7
O7
EN1_N EN2_N
10
B
2
3
4
5
6
7
8
9
U9
18
17
16
15
14
13
12
11
10K
U6
10
R65
20
S2
2A
2B
GND
SDO_DUT
SDO
1
2
GND2
SDIO/SDA_DUT
1
2
CTL2/FLAGC
STATUS0/SP0
SDIO/SDA
P18
SCLK/SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P16
4-1734376-8
ROUTE TO A TEST POINT
1M
GND
P2
P17
1
4
5
R64
JUNK2
10UF
C120
1UF
24.000MHZ
Y2
2
12PF
GND
C119
2
3
6
REF_SELA
A
C
LNJ312G8TRA (GREEN)
1
2
3
13
17
1A
1B
6
18
24
34
39
50
GND
4
7
19
33
35
48
AGND
100K
R57
100K
P12
3.3V USB
D+
D-
140
4700PF
1
2
TSW-102-08-G-S
SCL
SDA
RESET*
WAKEUP
RDY0/SLRD
RDY1/SLWR
RESERVED
GND
C133
USB SDA
22
23
49
51
8
9
21
P1
12PF
C132
1
USB SCL
24LC00SN
R56
10
14
AVCC
U6
VCC
XTALIN 12
11
XTALOUT
15
DPLUS
16
DMINUS
5
CLKOUT/T1OUT
20
IFCLK/T0OUT
36
CTL0/FLAGA
37
CTL1/FLAGB
38
REF_SEL
GND
P8
8
7
6
5
VCC
NC4
SCL
SDA
CR6
R63
DNI
NC1
NC2
NC3
VSS
C
C131
1
2
GND
1
2
3
4
2.2K
U8
2.2K
R59
R58
0.1UF
C
7914J-1-000E
S1
2A
2B
3.3V USB
U10
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD9523
EVALUATION BOARD
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
E
9523EE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
7
8
7
6
5
OF ANALOG DEVICES.
SN74LVC125APW GND
SIZE
PTD ENGINEER
D
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
4
3
R.Huntley
2
SCALE
NONE
SHEET
1
5
OF 5
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