FUJITSU SEMICONDUCTOR DATA SHEET DS06-20206-5E Semicustom CMOS Standard cell CS81 Series ■ DESCRIPTION The CS81 series 0.18 µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 40 million gates which have a gate delay time of 11 ps, resulting in both integration and speed about three times higher than conventional products. In addition, CS81 can operate at a power-supply voltage of down to 1.1 V, substantially reducing power consumption. ■ FEATURES : 0.18 µm silicon-gate CMOS, 3- to 6-layer wiring capable of integrating a mixture of highspeed processes and cells on a single chip (under development) Supply voltage : +1.8 V ± 0.15 V (normal) to +1.1 V ± 0.1 V Junction temperature range : −40 to +125 °C Gate delay time : tpd = 11 ps (1.8 V, inverter, F/O = 1) Gate power consumption : Pd = 5 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1) Support for high speed (62.2 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps) interface macros for transmission Output buffer cells with noise reduction circuits Inputs with on-chip input pull-up/pull-down resistors (33 kΩ typical) and bidirectional buffer cells Buffer cells dedicated to crystal oscillators Special interfaces (P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, and others. including those under development) IP macros (CPU (FR, ARM7, ARM9), DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others. including those under development) Capable of incorporating compiled cells (RAM/ROM/multiplier, and others.) Configurable internal bus circuits Advanced hardware/software co-design environment Short-term development using a timing driven layout tool Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time (Continued) • Technology • • • • • • • • • • • • • • • Copyright©1999-2007 FUJITSU LIMITED All rights reserved CS81 Series (Continued) • Hierarchical design environment for supporting large-scale circuits • Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture • Support for memory (RAM/ROM) SCAN • Support for memory (RAM) BIST • Support for boundary SCAN • Support for path delay test • A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, FCBGA, LQFP) ■ MACRO LIBRARY (Including macros being prepared) 1. Logic cells (about 400 types) • • • • • • • • • • Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR SCAN Flip Flop ENOR AND-OR • • • • • • • • • • • Decoder Non-SCAN Flip Flop Inverter Buffer OR-AND OR-AND Inverter OR Selector BUS Driver EOR Others 2. IP macros CPU/DSP FR, SPARClite, ARM7, ARM9, Communications DSP, DSP for AV and others High speed interface macros 622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps Interface macro PCI, IEEE1394, USB, IrDA, and others Multimedia processing macros JPEG, MPEG, and others Mixed signal macros ADC, DAC, OPAMP, and others Compiled macros RAM, ROM, multiplier, adder, multiplier-accumulator, and others PLL Analog PLL, digital PLL 3. Special I/O interface macros • T-LVTTL • LVDS • IEEE1394 2 • SSTL • PCI • SDRAM-I/F • HSTL • AGP • P-CML • USB CS81 Series ■ COMPILED CELLS Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS81 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.) 1. Clock synchronous single-port RAM (1 address : 1 RW) • High density type/Partial write type Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Memory capacity Word range Bit range Unit 256 to 144 K 64 to 2 K 4 to 72 bit Word range Bit range Unit 4 K to 16 K 6 to 72 bit Word range Bit range Unit • High speed type Column type 8 • Large scale partial write type Column type Memory capacity 16 24.5 K to 1179 K 2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R) • High density type/Partial write type Column type Memory capacity 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit 3. Clock synchronous register file (3 addresses : 1 W, 2 R) Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 bit 4. Clock synchronous register file (4 addresses : 2 W, 2 R) Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 bit 5. Clock synchronous ROM (1 addresses, 1 R) Column type Memory capacity Word range Bit range Unit 16 256 to 512 K 128 to 4 K 2 to 128 bit 6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R) Column type Memory capacity Word range Bit range Unit 8 256 to 32 K 32 to 1 K 8 to 32 bit 16 384 to 32 K 64 to 2 K 6 to 16 bit 32 512 to 32 K 128 to 4 K 4 to 8 bit 3 CS81 Series ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Min Unit Max +2.5*2 VDD −0.5 Input voltage*1 VI −0.5 Output voltage*1 VO −0.5 Storage temperature Tst −55 +125 °C Junction temperature Tj −40 +125 °C Output current*4 IO ⎯ ±4 Supply voltage*1 V +4.0*3 VDD+0.5 ( ≤ 2.5 V) *2 V VDD+0.5 ( ≤ 4.0 V) *3 VDD+0.5 ( ≤ 2.5 V) *2 V VDD+0.5 ( ≤ 4.0 V) *3 mA 5 Input signal transmitting rate RI ⎯ Clock input* : 200 Normal input : 100 Mbps*6 Output signal transmitting rate RO ⎯ 100 Mbps*6 Output load capacitance CO ⎯ 3000/RO pF Supply pin current ID ⎯ *7 mA *1 : VSS = 0 V *2 : Internal gate part in case of single power supply or dual power supply *3 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. *4 : DC current which continues more than 10 ms, or average DC current *5 : in case of I/O cell for clock input *6 : bps = bit per second *7 : Supply pin current for one VDD/GND pin Frame YS, YI B Source type Maximum current [mA] Standard source Additional source VDDE, VDDI, VDD, VSS 68 68 VDDE 39 39 VDDI, VDD, VSS 68 68 VDDE, VDDI, VDD, VSS 43 30 Number of layer 4, 5 3 ⎯ WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 4 CS81 Series ■ RECOMMENDED OPERATING CONDITIONS • Single power supply (VDD = +1.8 V ± 0.15 V) Parameter (VSS = 0 V) Symbol Value Min Typ Max Unit Supply voltage (1.8 V supply voltage) VDD 1.65 1.8 1.95 V “H” level input voltage (1.8 V CMOS) VIH VDD × 0.65 ⎯ VDD + 0.3 V “L” level input voltage (1.8 V CMOS) VIL −0.3 ⎯ VDD × 0.35 V Junction temperature Tj −40 ⎯ +125 °C • Dual power supply (VDDE = +3.3 V ± 0.3 V, VDDI = +1.8 V ± 0.15 V) Parameter Supply voltage “H” level input voltage “L” level input voltage Symbol (VSS = 0 V) Value Min Typ Max 1.8 V supply voltage VDDI 1.65 1.8 1.95 3.3 V supply voltage VDDE 3.0 3.3 3.6 VDDI × 0.65 ⎯ VDDI + 0.3 2.0 ⎯ VDDE + 0.3 −0.3 ⎯ VDDI × 0.35 −0.3 ⎯ +0.8 −40 ⎯ +125 1.8 V CMOS 3.3 V CMOS 1.8 V CMOS 3.3 V CMOS Junction temperature VIH VIL Tj • Dual power supply (VDDE = +3.3 V ± 0.3 V, VDDI = +1.5 V ± 0.1 V / +1.1 V ± 0.1 V) Parameter Symbol VDDE Supply voltage VDDI Unit V V V °C (VSS = 0 V) Value Unit Min Typ Max 3.0 3.3 3.6 V 1.0 1.1 1.2 V 1.4 1.5 1.6 V “H” level input voltage 3.3 V CMOS VIH 2.0 ⎯ VDDE + 0.3 V “L” level input voltage 3.3 V CMOS VIL −0.3 ⎯ +0.8 V Tj −40 ⎯ +125 °C Junction temperature 5 CS81 Series • Dual power supply (VDDE = +2.5 V ± 0.2 V, VDDI = +1.8 V ± 0.15 V) Parameter Supply voltage “H” level input voltage “L” level input voltage 1.8 V CMOS 2.5 V CMOS 1.8 V CMOS 2.5 V CMOS Junction temperature Symbol (VSS = 0 V) Value Typ Max VDDE 2.3 2.5 2.7 V VDDI 1.65 1.8 1.95 V VDDI × 0.65 ⎯ VDDI + 0.3 V 1.7 ⎯ VDDE + 0.3 V −0.3 ⎯ VDDI × 0.35 V −0.3 ⎯ +0.7 V −40 ⎯ +125 °C VIH VIL Tj • Dual power supply (VDDE = +2.5 V ± 0.2 V, VDDI = +1.5 V ± 0.1 V / +1.1 V ± 0.1 V) Parameter Symbol VDDE Supply voltage Unit Min VDDI (VSS = 0 V) Value Unit Min Typ Max 2.3 2.5 2.7 V 1.0 1.1 1.2 V 1.4 1.5 1.6 V “H” level input voltage 2.5 V CMOS VIH 1.7 ⎯ VDDE + 0.3 V “L” level input voltage 2.5 V CMOS VIL −0.3 ⎯ +0.7 V Tj −40 ⎯ +125 °C Junction temperature WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 CS81 Series ■ ELECTRICAL CHARACTERISTICS 1. DC characteristics • Signal power supply : VDD = 1.8 V Parameter (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Symbol Conditions Supply Current IDDS ⎯ “H” level output voltage VOH “L” level output voltage VOL Input leakage current IL Pull up/Pull down resistance RP Value Unit Min Typ Max ⎯ ⎯ * mA IOH = −100 µA VDD − 0.2 ⎯ VDD V IOL = +100 µA 0 ⎯ 0.2 V ⎯ ⎯ ±5 µA ⎯ 18 ⎯ kΩ ⎯ Pull up VIL = 0 Pull down VIH = VDD * : For details of YS, YI, B frame of CS81 series, contact Fujitsu. • Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V / 1.5 V ± 0.1 V / 1.1 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Conditions IDDS ⎯ Supply Current “H” level output voltage “L” level output voltage “H” level output V-I characteristics Unit Min Typ Max ⎯ ⎯ *1 mA VOH4 3.3 V Output IOH = −100 µA VDDE − 0.2 ⎯ VDDE V VOH2 1.8 V Output IOH = −100 µA VDDI − 0.2 ⎯ VDDI V VOL4 3.3 V Output IOL = 100 µA 0 ⎯ 0.2 V VOL2 1.8 V Output IOL = 100 µA 0 ⎯ 0.2 V ⎯ “L” level output V-I characteristics ⎯ Input leakage current IL Pull up/Pull down resistance Value RP 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯ ⎯ 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯ ⎯ ⎯ ⎯ ⎯ ±5 1.8 V Pull up VIL=0 Pull down VIH=VDDI ⎯ 18 ⎯ 3.3 V Pull up VIL=0 Pull down VIH=VDDE 10 µA kΩ 33 80 *1 : For details of YS, YI, B frame of CS81 series, contact Fujitsu. *2 : Refer to the Fig.1 to 2. 7 CS81 Series • Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V / 1.5 V / 1.1 V (VDDE = 2.5 V ± 0.2 V, VDDI = 1.8 V ± 0.15 V / 1.5 V ± 0.1 V / 1.1 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Supply Current “H” level output voltage “L” level output voltage Input leakage current Pull up/Pull down resistance Symbol Conditions IDDS ⎯ Unit Min Typ Max ⎯ ⎯ * mA VOH3 2.5 V Output IOH = −100 µA VDDE − 0.2 ⎯ VDDE V VOH2 1.8 V Output IOH = −100 µA VDDI − 0.2 ⎯ VDDI V VOL3 2.5 V Output IOL = 100 µA 0 ⎯ 0.2 V VOL2 1.8 V Output IOL = 100 µA 0 ⎯ 0.2 V ⎯ ⎯ ±5 µA 2.5 V Pull up VIL=0 Pull down VIH=VDDE ⎯ 25 ⎯ 1.8 V Pull up VIL=0 Pull down VIH=VDDI ⎯ IL RP ⎯ * : For details of YS, YI, B frame of CS81 series, contact Fujitsu. 8 Value kΩ 18 ⎯ CS81 Series • V-I Characteristics Conditions (Fig 1, 2) Min : Process = Slow, Tj = +125 °C, VDD = 3.6 V Typ : Process = TYPICAL, Tj = +25 °C, VDD = 3.3 V Max : Process = FAST, Tj = −40 °C, VDD = 3.0 V VOH−VDD (V) −3.0 −4.0 −2.0 −1.0 0.0 0 120 −20 100 −40 80 −60 Max IOL (mA) Typ IOH (mA) Max Min 60 −80 40 −100 20 −120 0 Typ Min 0.0 1.0 2.0 3.0 4.0 VOL (V) Fig.1 V-I characteristics (3.3 V normal I/O L, M type) VOH−VDD (V) Min Typ −2.0 −1.0 0.0 0 160 −20 140 −40 120 −60 100 −80 IOL (mA) −3.0 IOH (mA) −4.0 60 −120 40 −140 20 −160 Typ 80 −100 Max Max Min 0 0.0 2.0 1.0 3.0 4.0 VOL (V) Fig.2 V-I characteristics (3.3 V normal I/O H, V type) 9 CS81 Series 2. AC characteristics Parameter Delay time (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Rating Symbol tpd*1 Unit Min Typ Max* typ*2 × tmin*3 typ*2 × ttyp*3 typ*2 × tmax*3 ns *1 : Delay time = propagation delay time, enable time, disable time *2 : “typ” is calculated based on the cell specifications. *3 : Measurement conditions. Measurement condition tmin ttyp tmax VDD = 1.8 V±0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C 0.64 1.00 1.58 VDD = 1.5 V±0.10 V, VSS = 0 V, Tj = −40 °C to +125 °C 0.83 1.31 2.05 VDD = 1.1 V±0.10 V, VSS = 0 V, Tj = −40 °C to +125 °C 1.37 2.45 4.88 Note : tpd max is calculated according to the maximum junction temperature (Tj) . ■ INPUT/OUTPUT PIN CAPACITANCE (Tj = +25 °C, VDD = VI = 0 V, f = 1 MHz) Parameter Symbol Requirements Unit CIN Max 16 pF Output pin COUT Max 16 pF I/O pin CI/O Max 16 pF Input pin Note : Capacitance varies according to the package and the location of the pin. ■ DESIGN METHOD SCCAD2 is the standard cell integrated design environment providing three major functions, enabling highquality, large-scale system LSIs to be developed in a shorter period of time. They include: the timing driven layout function for automatic placement/routing based on timing constraints to prevent timing problems after layout, the function for shortening the development cycle time by dividing a large-scale circuit and performing simultaneous logical/physical design of multiple circuits, and the function for automatically generating power/ signal wiring patterns while evaluating the supply voltage drop, signal noise, delay penalty, and crosstalk (Contact your nearest Fujitsu office for more information and availability). 10 CS81 Series ■ PACKAGES The table below lists the package types available. Consult Fujitsu for the combination of each package and the time of availability. Package Pin count Material TAB-BGA 304 352 480 560 660 720 Plastic Plastic Plastic Plastic Plastic Plastic EBGA 576 660 672 Plastic Plastic Plastic HQFP 208 240 256 304 Plastic Plastic Plastic Plastic TQFP 100 120 Plastic Plastic LQFP 144 176 208 Plastic Plastic Plastic FBGA 288 Plastic FCBGA 1089 1225 1369 1681 1849 2116 Plastic Plastic Plastic Plastic Plastic Plastic 11 CS81 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0703