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TS4621E
High-performance class-G stereo headphone amplifier
with I2C volume control
Features
TS4621EIJT - flip-chip
■
Power supply range: 2.3 V to 4.8 V
■
0.6 mA/channel quiescent current
■
2.1 mA current consumption with
100 µW/channel (10 dB crest factor)
■
0.006% typical THD+N at 1 kHz
■
100 dB typical PSRR at 217 Hz
■
100 dB of SNR A-weighted at G = 0 dB
■
Zero pop and click
■
I2C interface for volume control
■
Digital volume control range from -60 dB to
+4 dB
■
Independent right and left channel shutdown
control
Pinout (top view)
■
Integrated high-efficiency buck converter
■
Low software standby current: 5 µA max
■
Output-coupling capacitors removed
■
Thermal shutdown and short-circuit protection
■
Flip-chip package: 1.65 mm x 1.65 mm,
400 µm pitch, 16 bumps
Applications
■
Cellular phones, smart phones
■
Mobile internet devices
■
PMP/MP3 players
VOUTR
SCL
SDA
D
INR+
CMS
PVSS
C2
C
INL+
HPVDD
C1
AGND
B
INL-
VOUTL
AVDD
SW
A
4
3
2
1
Balls are underneath
When powered by a battery, the buck converter
generates the appropriate voltage to the amplifier
depending on the amplitude of the audio signal to
supply the headsets. It achieves a total 2.1 mA
current consumption at 100 µW output power
(10 dB crest factor).
THD+N is 0.02% maximum at 1 kHz and PSRR is
100 dB at 217 Hz, which ensures a high audio
quality of the device in a wide range of
environments.
The traditionally bulky output coupling capacitors
can be removed.
Description
The TS4621E is a class-G stereo headphone
driver dedicated to high audio performance, high
power efficiency and space-constrained
applications.
It is based on the core technology of a low power
dissipation amplifier combined with a highefficiency buck converter for supplying this
amplifier.
September 2011
INR-
A dedicated common-mode sense pin removes
parasitic ground noise.
The TS4621E is designed to be used with an
output serial resistor. It ensures unconditional
stability over a wide range of capacitive loads.
The TS4621E is packaged in a tiny 16-bump
flip-chip package with a pitch of 400 µm.
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32
Contents
TS4621E
Contents
1
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
2
Typical application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.1
I²C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.2
Control register CR2 - address 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.3
Control register CR1 - address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2
Wake-up and standby time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3
Common mode sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Doc ID 022201 Rev 1
TS4621E
1
Absolute maximum ratings and operating conditions
Absolute maximum ratings and operating conditions
Table 1.
Absolute maximum ratings
Symbol
VCC
Vin+,VinTstg
Tj
Rthja
Pd
Parameter
Supply voltage (1) during 1ms.
Input voltage referred to ground
Storage temperature
Maximum junction temperature(2)
Thermal resistance junction to ambient
(3)
Power dissipation
Value
Unit
5.5
V
+/- 1.2
V
-65 to +150
°C
150
°C
200
°C/W
Internally
limited(4)
(HBM)(5)
Human body model
All pins
VOUTR, VOUTL vs. AGND
ESD
2
4
kV
Machine model (MM), min. value(6)
100
V
Charge device model (CDM)
All pins
VOUTR, VOUTL
500
750
V
IEC61000-4-2 level 4, contact(7)
IEC61000-4-2 level 4, air discharge(7)
Latch-up
+/- 8
+/- 15
kV
Latch-up immunity
200
mA
Lead temperature (soldering, 10 sec)
260
°C
1. All voltage values are measured with respect to the ground pin.
2. Thermal shutdown is activated when maximum junction temperature is reached.
3. The device is protected from over-temperature by a thermal shutdown mechanism, active at 150° C.
4. Exceeding the power derating curves for long periods may provoke abnormal operation.
5. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
6. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of
connected pin combinations while the other pins are floating.
7. The measurement is performed on an evaluation board, with ESD protection EMIF02-AV01F3.
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Absolute maximum ratings and operating conditions
Table 2.
Operating conditions
Symbol
VCC
HPVDD
SDA, SCL
4/32
TS4621E
Parameter
Supply voltage
Buck DC output voltages
High rail voltage
Low rail voltage
Input voltage range
Value
Unit
2.3 to 4.8
V
1.9
1.2
V
GND to Vcc
V
≥ 16
Ω
RL
Load resistor
CL
Load capacitor
Serial resistor of 12 Ω minimum, RL ≥ 16 Ω
0.8 to 100
Toper
Operating free air temperature range
-40 to +85
°C
Rthja
Flip-chip thermal resistance junction to ambient
90
°C/W
Doc ID 022201 Rev 1
nF
TS4621E
Typical application schematics
Figure 1.
Typical application schematics for the TS4621E
Vbat
L1
3.3 uH
Cs
2.2 uF
AVdd
Sw
Positive
supply
Cin
2.2 uF
Negative left input
Ct
10 uF
-
Level
detector
InL+
Positive left input
+
Cin
2.2 uF
Cin
2.2 uF
Negative right input
3
2
J1
1
Level
detector
Rout
VoutR
12 ohms min.
SDA
SCL
Cout
0.8 nF min.
Negative
supply
I2C
PVss
I²C bus
12 ohms min.
InR+
-
Cin
2.2 uF
Cout
0.8 nF min.
Rout
VoutL
CMS
InR-
Positive right input
HpVdd
InL-
+
2
Typical application schematics
C1
Css
2.2 uF
C2
AGnd
C12
2.2 uF
AM06119
Table 3.
TS4621E pin description
Pin number
Pin name
Pin definition
A1
SW
A2
AVDD
Analog supply voltage, connect to battery
A3
VOUTL
Output signal for left audio channel
A4
INL-
B1
AGND
B2
C1
B3
HPVDD
B4
INL+
C1
C2
C2
PVSS
Negative supply generator output
C3
CMS
Common mode sense, to be connected as close as possible to the
ground of headphone/line out plug
C4
INR+
Positive input signal for right audio channel
D1
SDA
I²C data signal, up to VCC tolerant input
D2
SCL
I²C clock signal, up to VCC tolerant input
D3
VOUTR
D4
INR-
Switching node of the buck converter
Negative input signal for left audio channel
Device ground
Flying capacitor terminal for internal negative supply generator
Buck converter output, power supply for amplifier
Positive input signal for left audio channel
Flying capacitor terminal for internal negative supply generator
Output signal for right audio channel
Negative input signal for right audio channel
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Typical application schematics
Table 4.
TS4621E component description
Component
Value
Description
2.2 µF
Decoupling capacitors for VCC. A 2.2 µF capacitor is sufficient for proper
decoupling of the TS4621E. An X5R dielectric and 10 V rating voltage is
recommended to minimize ΔC/ΔV when VCC = 4.8 V.
Must be placed as close as possible to the TS4621E to minimize parasitic
inductance and resistance.
C12
2.2 µF
Capacitor for internal negative power supply operation. An X5R dielectric and
6.3 V rating voltage is recommended to minimize ΔC/ΔV when
HPVDD = 1.9 V.
Must be placed as close as possible to the TS4621E to minimize parasitic
inductance and resistance.
CSS
2.2 µF
Filtering capacitor for internal negative power supply. An X5R dielectric and
6.3 V rating voltage is recommended to minimize ΔC/ΔV when
HPVDD = 1.9 V.
Cin
1
Cin = ----------------------2πZinFc
Input coupling capacitor that forms with Zin/2 a first-order high-pass filter with
a -3 dB cutoff frequency FC. For example, at maximum gain G = 4 dB,
Zin = 12.5 kΩ, Cin = 2.2 µF, therefore FC = 6 Hz.
Cout
0.8 to 100 nF
Output capacitor of 0.8 nF minimum to 100 nF maximum. This capacitor is
mandatory for operation of the TS4621E.
Rout
12 Ω min.
Output resistor in-series with the TS4621E output. This 12 Ω minimum resistor
is mandatory for operation of the TS4621E.
3.3 µH
Inductor for the buck convertor.
References of inductors:
FDK: MIPSZ2012D3R3 (DC resistance = 0.19 Ω, rated current = 0.8 A)
Murata: LQM2MPN3R3G0 (DC resistance = 0.12 Ω, rated current = 1.2 A)
10 µF
Tank capacitor for internal buck convertor. An X5R dielectric and 6.3 V rating
voltage is recommended to minimize ΔC/ΔV when HPVDD = 1.9 V.
ESR of the Ct capacitor must be as low as possible to obtain the best buck
efficiency.
Cs
L1
Ct
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TS4621E
Doc ID 022201 Rev 1
TS4621E
Electrical characteristics
3
Electrical characteristics
Table 5.
Electrical characteristics of the I²C interface
for VCC = +3.6 V, AGND = 0 V, Tamb = 25°C (unless otherwise specified)
Symbol
Parameter
VIL
Low level input voltage on SDA, SCL pins
VIH
High level input voltage on SDA, SCL pins
VOL
Low level output voltage, SDA pin, Isink = 3mA
Iin
Table 6.
Is
ISTBY
Typ.
Max.
Unit
0.6
V
1.2
Input current on SDA, SCL
V
0.4
V
V
SDA, SCL
--------------------------------600kΩ
10
µA
Typ.
Max.
Unit
1.2
1.5
mA
2.3
3.7
4.7
2.1
3.1
3.9
3.5
5
6.5
0.6
5
µA
1
Vrms
+500
µV
Electrical characteristics of the amplifier
for VCC = +3.6 V, AGND = 0 V, RL= 32 Ω + 15 Ω, Tamb = 25° C
(unless otherwise specified)
Symbol
ICC
Min.
Parameter
Min.
Quiescent supply current, no input signal, both channels
enabled
Supply current, with input modulation, both channels enabled,
HPVDD = 1.2 V, output power per channel, F=1kHz
Pout = 100 µW at 3 dB crest factor
Pout = 500 µW at 3 dB crest factor
Pout = 1 mW at 3 dB crest factor
Pout = 100 µW at 10 dB crest factor
Pout = 500 µW at 10 dB crest factor
Pout = 1 mW at 10 dB crest factor
Standby current, no input signal, I²C CR1 = 01h
VSDA = 0 V, VSCL = 0 V
Vin
Input differential voltage range(1)
Voo
Output offset voltage
No input signal
Vout
Maximum output voltage, in-phase signals
RL = 16 Ω, THD+N = 1% max, f = 1 kHz
RL = 47 Ω, THD+N = 1% max, f = 1 kHz
RL = 10 kΩ, Rs = 15 Ω, CL = 1 nF, THD+N = 1% max,
f = 1 kHz
-500
THD+N
Total harmonic distortion + noise, G = 0 dB
Vout = 700 mVrms, F = 1 kHz
Vout = 700 mVrms, 20 Hz < F < 20 kHz
PSRR
Power supply rejection ratio(1), Vripple = 200 mVpp, grounded
inputs
F = 217 Hz, G = 0 dB, RL ≥16 Ω
F = 10 kHz, G = 0 dB, RL ≥16 Ω
Doc ID 022201 Rev 1
0.6
1.0
1.0
0.8
1.1
1.3
0.006
0.05
90
100
70
mA
Vrms
0.02
%
dB
7/32
Electrical characteristics
Table 6.
Electrical characteristics of the amplifier
for VCC = +3.6 V, AGND = 0 V, RL= 32 Ω + 15 Ω, Tamb = 25° C
(unless otherwise specified) (continued)
Symbol
CMRR
Crosstalk
SNR
ONoise
G
Mute
TS4621E
Parameter
Min.
Common mode rejection ratio
F = 1 kHz, G = 0 dB, Vic = 200 mVpp
F = 20 Hz to 20 kHz, G = 0 dB, Vic = 200 mVpp
Channel separation
RL = 32 Ω + 15 Ω , G = 0 dB, F = 1 kHz, Po = 10 mW
RL = 10 kΩ, G = 0 dB, F = 1 kHz, Vout = 1 Vrms
60
80
Signal-to-noise ratio, A-weighted, Vout = 1 Vrms, THD+N < 1%,
F = 1 kHz(1)
G = +4 dB
G = +0 dB
99
100
Output noise voltage, A-weighted (1)
G = +4 dB
G = +0 dB
Gain range with gain (dB) = 20 x log[(VoutL/R)/(InL/R+ - InL/R-)]
Typ.
Max.
Unit
65
45
dB
100
110
dB
dB
9
-60
InL/R+ - InL/R- = 1 Vrms
11
9
µVrms
+4
dB
-80
dB
-
Gain step size error
-0.5
+0.5
stepsize
-
Gain error (G = +4 dB)
-0.45
+0.42
dB
Zin
Differential input impedance
25
Input impedance during wake-up phase (referred to ground)
34
kΩ
2
kΩ
Zout
Output impedance when CR1 = 00h (negative supply is ON and
amplifier output stages are OFF)(1)
F < 40 kHz
F = 6 MHz
F = 36 MHz
twu
Wake-up time(2)
12
tstby
Standby time
100
µs
tatk
Attack time. Setup time between low rail buck voltage and high
rail buck voltage
100
µs
tdcy
Decay time
50
ms
1. Guaranteed by design and parameter correlation.
2. Refer to the application information in Section 4.3 on page 27.
8/32
Doc ID 022201 Rev 1
10
500
75
kΩ
Ω
Ω
16
ms
TS4621E
Electrical characteristics
Table 7.
Timing characteristics of the I²C interface for I²C interface signals over
recommended operating conditions (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
400
kHz
fSCL
Frequency, SCL
td(H)
Pulse duration, SCL high
0.6
µs
td(L)
Pulse duration, SCL low
1.3
µs
tst1
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
0
ns
Bus free time between stop and start condition
1.3
µs
tst2
Setup time, SCL to start condition
0.6
µs
th2
Hold time, start condition to SCL
0.6
µs
tst3
Setup time, SCL to stop condition
0.6
µs
tf
Figure 2.
SCL and SDA timing diagram
t d(H)
t d(L)
SCL
t st1
t h1
SDA
AM06113
Figure 3.
Start and stop condition timing diagram
SCL
t st2
tf
t h2
t st3
SDA
Start condition
Stop condition
AM06114
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Electrical characteristics
Figure 4.
TS4621E
Current consumption vs. power
supply voltage
Figure 5.
Standby current consumption vs.
power supply voltage
Quiscent Supply Current ICC (mA)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
No load; No input Signal
Both channels enabled
Ta = 25°C
0.2
0.0
No load; No input Signal
SDA=SCL = 0V
Ta = 25°C
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8
Power Supply Voltage Vcc (V)
Figure 6.
Maximum output power vs. load
Figure 7.
80
80
Inputs = 0°, F = 1kHz
THD+N = 1%
Tamb = 25°C
70
VCC=4.8V
60
50
VCC=3.6V
40
30
20
VCC=2.3V
10
0
10
Figure 8.
120
VCC=4.8V
70
Output power (mW)
60
Output power (mW)
Maximum output power vs. load
VCC=3.6V
50
40
VCC=2.3V
30
20
10
100
RL Load resistance ( )
Maximum output power vs. power
supply voltage
RL = 16Ω, F = 1kHz
BW < 30kHz, Tamb = 25°C
0
10
1k
Figure 9.
THD+N=10% (180°)
80
100
RL Load resistance ( )
RL = 32Ω, F = 1kHz
BW < 30kHz, Tamb = 25°C
Output power (mW)
Output power (mW)
THD+N=10% (0°)
THD+N=1% (180°)
40
THD+N=1% (0°)
20
10/32
THD+N=10% (0°)
THD+N=10% (180°)
60
0
2.3
1k
Maximum output power vs. power
supply voltage
100
80
Inputs = 180°, F = 1kHz
THD+N = 1%
Tamb = 25°C
2.7
3.1
3.5
3.9
4.3
Power Supply Voltage Vcc (V)
4.7
60
40
20
0
2.3
Doc ID 022201 Rev 1
THD+N=1% (180°)
2.7
THD+N=1% (0°)
3.1
3.5
3.9
4.3
Power Supply Voltage Vcc (V)
4.7
TS4621E
Electrical characteristics
Figure 10. Maximum output power vs. power
supply voltage
1600
THD+N=10% (180°)
40
20
THD+N=1% (0°)
THD+N=1% (180°)
F = 1kHz
BW < 30kHz, Tamb = 25°C
Inputs = 0°, THD+N = 1%
1500
THD+N=10% (0°)
Output Voltage (mVrms)
Output power (mW)
60
RL = 47Ω, F = 1kHz
BW < 30kHz, Tamb = 25°C
Figure 11. Maximum output voltage vs. power
supply voltage
1400
2.7
3.1
3.5
3.9
4.3
Power Supply Voltage Vcc (V)
10 KΩ
1300
60 Ω
1200
1100
1000
16 Ω
700
2.3
4.7
47 Ω
32 Ω
900
800
0
2.3
600 Ω
2.7
3.1
3.5
3.9
4.3
Power Supply Voltage Vcc (V)
4.7
Figure 12. Maximum output voltage vs. power Figure 13. Current consumption vs. total
supply voltage
output power
100
1600
Output Voltage (mVrms)
1500
1400
600 Ω
10 KΩ
Supply Current IS (mA)
F = 1kHz
BW < 30kHz, Tamb = 25°C
Inputs = 180°, THD+N=1%
1300
1200
1100
47 Ω
32 Ω
60 Ω
1000
16 Ω
900
Both channels enabled
RL = 16Ω, F = 1KHz
Ta = 25°C
Crest Factor = 3dB
Vcc=2.3V
Vcc=3.6V
10
Vcc=4.8V
800
700
2.3
2.7
3.1
3.5
3.9
4.3
Power Supply Voltage Vcc (V)
1
0.1
4.7
Figure 14. Current consumption vs. total
output power
Supply Current IS (mA)
Supply Current IS (mA)
100
Both channels enabled
RL = 32Ω, F = 1KHz
Ta = 25°C
Crest Factor = 3dB
Vcc=2.3V
Vcc=3.6V
Both channels enabled
RL = 47Ω, F = 1 KHz
Ta = 25°C
Crest Factor = 3dB
Vcc=2.3V
Vcc=3.6V
10
Vcc=4.8V
1
0.1
10
Figure 15. Current consumption vs. total
output power
100
10
1
Total Output Power (mW)
1
Vcc=4.8V
10
1
0.1
Total Output Power (mW)
1
10
Total Output Power (mW)
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Electrical characteristics
TS4621E
Figure 16. Current consumption vs. total
output power
Figure 17. Power dissipation vs. total output
power
100
Both channels enabled
RL = 47Ω, F = 1KHz
Ta = 25°C, Vcc = 3.6V
R = 16 Ω
Power Dissipation (mW)
Supply Current IS (mA)
100
10
Crest Factor=3dB
R = 32 Ω
10
R = 47 Ω
Both channels enabled
F = 1KHz,
Ta = 25°C
Crest Factor = 3dB
Crest Factor=10dB
1
0.1
1
0.1
1
Total Output Power (mW)
1
10
Total Output Power (mW)
Figure 18. Output impedance vs. frequency
Figure 19. Differential input impedance vs.
gain
80
Differential Input Impedance (K )
Input Floating
Input grounded
Vcc=2.3V to 4.8V
HIz; Right & Left
Osc level=0.5VRMS
Ta = 25°C
70
60
50
40
Vcc=2.3V to 4.8V
Ta = 25°C
30
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Gain (dB)
Figure 20. THD+N vs. output power
Figure 21. THD+N vs. output power
Vcc = 2.5V, RL = 16Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
Vcc = 2.5V, RL = 16Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
12/32
Doc ID 022201 Rev 1
F=80Hz
0
TS4621E
Electrical characteristics
Figure 22. THD+N vs. output power
Figure 23. THD+N vs. output power
Vcc = 3.6V, RL = 16Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
Vcc = 3.6V, RL = 16Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
F=80Hz
Figure 24. THD+N vs. output power
Figure 25. THD+N vs. output power
Vcc = 4.8V, RL = 16Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
Vcc = 4.8V, RL = 16Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=80Hz, 1kHz
Figure 26. THD+N vs. output power
F=80Hz, 1kHz
Figure 27. THD+N vs. output power
Vcc = 2.5V, RL = 32Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
Vcc = 2.5V, RL = 32Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
Doc ID 022201 Rev 1
F=80Hz
13/32
Electrical characteristics
TS4621E
Figure 28. THD+N vs. output power
Figure 29. THD+N vs. output power
Vcc = 3.6V, RL = 32Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
Vcc = 3.6V, RL = 32Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
F=80Hz
Figure 30. THD+N vs. output power
Figure 31. THD+N vs. output power
Vcc = 4.8V, RL = 32Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
Vcc = 4.8V, RL = 32Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
Figure 32. THD+N vs. output power
F=80Hz
Figure 33. THD+N vs. output power
Vcc = 2.5V, RL = 47Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
Vcc = 2.5V, RL = 47Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
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Doc ID 022201 Rev 1
F=80Hz
TS4621E
Electrical characteristics
Figure 34. THD+N vs. output power
Figure 35. THD+N vs. output power
Vcc = 3.6V, RL = 47Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
Vcc = 3.6V, RL = 47Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
F=80Hz
Figure 36. THD+N vs. output power
Figure 37. THD+N vs. output power
Vcc = 4.8V, RL = 47Ω
G = 4dB, Inputs = 0°
BW < 30kHz, Tamb = 25°C
Vcc = 4.8V, RL = 47Ω
G = 4dB, Inputs = 180°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
F=80Hz
Figure 38. THD+N vs. frequency
Figure 39. THD+N vs. frequency
RL = 16Ω
Vcc = 2.5V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
RL = 16Ω
Vcc = 2.5V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=15mW
20
Po=15mW
20k
20
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20k
15/32
Electrical characteristics
TS4621E
Figure 40. THD+N vs. frequency
Figure 41. THD+N vs. frequency
RL = 16Ω
Vcc = 3.6V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
RL = 16Ω
Vcc = 3.6V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=15mW
20
Po=15mW
20k
Figure 42. THD+N vs. frequency
RL = 16Ω
Vcc = 4.8V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
20
20k
Figure 43. THD+N vs. frequency
RL = 16Ω
Vcc = 4.8V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=15mW
Po=15mW
20
20k
Figure 44. THD+N vs. frequency
20
Figure 45. THD+N vs. frequency
RL = 32Ω
Vcc = 2.5V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
RL = 32Ω
Vcc = 2.5V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=10mW
20
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20k
Po=10mW
20k
20
Doc ID 022201 Rev 1
20k
TS4621E
Electrical characteristics
Figure 46. THD+N vs. frequency
Figure 47. THD+N vs. frequency
RL = 32Ω
Vcc = 3.6V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
RL = 32Ω
Vcc = 3.6V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=10mW
Po=10mW
20
20k
Figure 48. THD+N vs. frequency
20
20k
Figure 49. THD+N vs. frequency
RL = 32Ω
Vcc = 4.8V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
RL = 32Ω
Vcc = 4.8V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=10mW
Po=10mW
20
20k
Figure 50. THD+N vs. frequency
20
Figure 51. THD+N vs. frequency
RL = 47Ω
Vcc = 2.5V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
RL = 47Ω
Vcc = 2.5V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=10mW
20
20k
Po=10mW
20k
20
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20k
17/32
Electrical characteristics
TS4621E
Figure 52. THD+N vs. frequency
Figure 53. THD+N vs. frequency
RL = 47Ω
Vcc = 3.6V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
RL = 47Ω
Vcc = 3.6V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=10mW
20
Po=10mW
20k
Figure 54. THD+N vs. frequency
20
20k
Figure 55. THD+N vs. frequency
RL = 47Ω
Vcc = 4.8V
G = 0dB
Inputs = 0°
Bw < 20kHz
Tamb = 25°C
RL = 47Ω
Vcc = 4.8V
G = 0dB
Inputs = 180°
Bw < 20kHz
Tamb = 25°C
Po=1mW
Po=1mW
Po=10mW
20
Po=10mW
20k
20
20k
Figure 56. THD+N vs. frequency
Figure 57. THD+N vs. frequency
RL = RC network + 10kΩ
Vcc = 2.3V to 4.8V
G = 0dB, Inputs = 0° & 180°
Bw < 20kHz, Tamb = 25°C
RL = RC network + 600Ω
Vcc = 2.3V to 4.8V
G = 0dB, Inputs = 0° & 180°
Bw < 20kHz, Tamb = 25°C
Vo=100mVrms
Vo=100mVrms
Vo=1Vrms
20
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Vo=1Vrms
20k
20
Doc ID 022201 Rev 1
20k
TS4621E
Electrical characteristics
Figure 58. THD+N vs. output voltage
Figure 59. THD+N vs. output voltage
RL = RC network + 600Ω
Vcc = 2.3V to 4.8V, G = 4dB
Inputs = 0° & 180°
BW < 30kHz, Tamb = 25°C
RL = RC network + 10kΩ
Vcc = 2.3V to 4.8V, G = 4dB
Inputs = 0° & 180°
BW < 30kHz, Tamb = 25°C
F=8kHz
F=8kHz
F=1kHz
F=1kHz
F=80Hz
F=80Hz
Figure 60. THD+N vs. input voltage, HiZ left
and right
Figure 61. CMRR vs. frequency
0
HiZ Left & Right
Vcc = 2.3V to 4.8V
Zout generator = 1kΩ
BW < 30kHz, Tamb = 25°C
-10
Δ
-20
≥
Ω
°
-30
Line In F=8kHz
Line In F=1kHz
-40
Line In F=80Hz
-50
-60
-70
Reference F=80Hz, 1kHz, 8kHz
-80
20
Figure 62. PSRR vs. frequency
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
20
≥
°
G=4dB
G=0dB
G=-6dB
1000
1000
10000 20k
Figure 63. PSRR vs. frequency
Ω
100
100
10000 20k
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
20
Doc ID 022201 Rev 1
≥
Ω
°
G=4dB
G=0dB
G=-6dB
100
1000
10000 20k
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Electrical characteristics
TS4621E
Figure 64. PSRR vs. frequency
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
20
Figure 65. Output signal spectrum
Ω
≥
°
Ω
°
G=4dB
G=0dB
G=-6dB
100
1000
10000 20k
Figure 66. Crosstalk vs. frequency
Figure 67. Crosstalk vs. frequency
0
0
-10
-10
-20
-30
-40
-20
-30
Ω
-40
°
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
-120
20
100
1000
10000 20k
Figure 68. Crosstalk vs. frequency
0
-20
-40
Ω
°
-50
-60
-70
-80
-90
-100
-110
-120
20
20/32
100
1000
°
100
1000
10000 20k
Figure 69. Crosstalk vs. frequency
-10
-30
-120
20
Ω
10000 20k
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
20
Doc ID 022201 Rev 1
Ω
°
100
1000
10000 20k
TS4621E
Electrical characteristics
Figure 70. Wake-up time
Figure 71. Shutdown time
I²C ACK after
Shutdown command
SDA
2 ms/div
1V/div
VOUT
2ms/div
20mv/div
VOUT
10µs/div
100mv/div
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Application information
TS4621E
4
Application information
4.1
I2C bus interface
In compliance with the I²C protocol, the TS4621E uses a serial bus to control the chip’s
functions with the clock (SCL) and data (SDA) wires. These two lines are bi-directional
(open collector) and require an external pull-up resistor (typically 10 kΩ). The maximum
clock frequency in fast mode specified by the I²C standard is 400 kHz, which the TS4621E
supports. In this application, the TS4621E is always the slave device and the controlling
microcontroller MCU is the master device.
The slave address of the TS4621E is 1100 000x (C0h).
Table 8 summarizes the pin descriptions for the I²C bus interface.
Table 8.
I²C bus interface pin descriptions
Pin
4.1.1
Functional description
SDA
Serial data pin
SCL
Clock input pin
I²C bus operation
The host MCU can write to the TS4621E control register to control the TS4621E, and read
from the control register to obtain a configuration from the TS4621E. The TS4621E is
addressed by the byte consisting of the 7-bit slave address and the R/W bit.
Table 9.
First byte after the START message for addressing the device
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
0
0
0
0
X
There are four control registers (Table 10) named CR1 to CR4. In read mode, all the control
registers can be accessed. In write mode, only CR1, CR2 and CR3 can be addressed.
Table 10.
Summary of control registers
Description
22/32
Register
address
CR1
1
CR2
volume control
2
CR3
3
CR4
identification
4
D7
D6
HP_EN_L HP_EN_R
D5
D4
0
0
D3
D2
SC_L SC_R T_SH
Mute_L
Mute_R
0
0
0
0
0
0
0
1
0
0
0
0
Doc ID 022201 Rev 1
D1
Volume control
D0
SWS
0
HiZ_L HiZ_R
0
0
TS4621E
Application information
Writing to the control registers
To write data to the TS4621E, after the "start" message the MCU must:
●
send the I²C 7-bit slave address and a low level for the R/W bit.
●
send the register address to write to.
●
send the data bytes (control register settings).
All bytes are sent MSB first. The transfer of written data ends with a "stop" message. When
transmitting several data bytes, the data can be written without having to repeat the "start"
message or send the byte with the slave address. If several bytes are transmitted, they will
be written repeatedly to CR1, CR2 and CR3.
Figure 72. I²C write operations
DATA BYTES
SLAVE DEVICE ADDRESS
REGISTER ADDRESS
CR X
CRX+1
SDA
S
1
1
0
0
0
0
0
0 ACK A7 A6
A1 A0 ACK D7 D6
D1 D0 ACK D7 D6
D1 D0 ACK P
Stop
condition
Start
condition
R/W
Acknowledge
from slave
Acknowledge
from slave
AM06115
Reading from the control registers
To read data from the TS4621E, after the "start" message the MCU must:
●
send the I²C 7-bit slave address and a low level for the R/W bit.
●
send the register address to write to.
●
send the I²C 7-bit slave address and a high level for the R/W bit.
●
receive the data (control register value).
All bytes are read MSB first. The transfer of read data ends with a "stop" message. When
transmitting several data bytes, the data can be read without having to repeat the "start"
message or send the byte with the slave address. If several bytes are transmitted, they will
be read repeatedly from CR1, CR2, CR3 and CR4.
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Application information
TS4621E
Figure 73. I²C read operations
DATA BYTES
DEVICE ADDRESS
DEVICE ADDRESS
REGISTER ADDRESS
CRX
SDA
S
1
1
0
0
0
0
0
0 ACK A7
A0 ACK
Start condition
S
1
1
0
0
0
0
D0 ACK D7
D0 A
P
Stop
condition
Repeat
start condition
R/W
1 ACK D7
0
CRX+1
R/W
Not
Acknowledge
Acknowledge
fom slave
AM06116
4.1.2
Control register CR2 - address 2
Table 11.
Volume control register CR2 - address 2
Volume control range: -60 dB to +4 dB
D5
D4
D3
D2
D1
Gain
(in dB)
D5
D4
D3
D2
D1
Gain
(in dB)
0
0
0
0
0
-60 dB
1
0
0
0
0
-11 dB
0
0
0
0
1
-54 dB
1
0
0
0
1
-10 dB
0
0
0
1
0
-50.5 dB
1
0
0
1
0
-9 dB
0
0
0
1
1
-47 dB
1
0
0
1
1
-8 dB
0
0
1
0
0
-43 dB
1
0
1
0
0
-7 dB
0
0
1
0
1
-39 dB
1
0
1
0
1
-6 dB
0
0
1
1
0
-35 dB
1
0
1
1
0
-5 dB
0
0
1
1
1
-31 dB
1
0
1
1
1
-4 dB
0
1
0
0
0
-27 dB
1
1
0
0
0
-3 dB
0
1
0
0
1
-25 dB
1
1
0
0
1
-2 dB
0
1
0
1
0
-23 dB
1
1
0
1
0
-1 dB
0
1
0
1
1
-21 dB
1
1
0
1
1
0 dB
0
1
1
0
0
-19 dB
1
1
1
0
0
+1 dB
0
1
1
0
1
-17 dB
1
1
1
0
1
+2 dB
0
1
1
1
0
-15 dB
1
1
1
1
0
+3 dB
0
1
1
1
1
-13 dB
1
1
1
1
1
+4 dB
Mute function: bits MUTE_L and MUTE_R
In the volume register, MUTE_L and MUTE_R are dedicated to enabling the mute function,
independently of the channel. When MUTE_L and MUTE_R are set to VIH, the mute
function is enabled on the corresponding channel and the gain is set to -80 dB. When
MUTE_L and MUTE_R are set to VIL, the I²C gain level is applied to the channel.
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Doc ID 022201 Rev 1
TS4621E
4.1.3
Application information
Control register CR1 - address 1
Amplifier output short-circuit detection: bits SC_L and SC_R
The amplifier’s outputs are protected from short-circuits that might accidentally occur during
manipulation of the device. In a typical application, if a short-circuit arises on the jack plug,
there will be no detection because of the serial resistor present on the amplifier output, thus
the output current threshold will not be reached.
To be active, the detection has to occur directly on the amplifier’s output with a signal
modulation on the inputs of the TS4621E. This detection is depicted in Figure 74.
Figure 74. Flowchart for short-circuit detection
Counter = 0
Shortcut detection
TS4621E power ON
Shortcut detection
Counter = counter + 1
Reset
TS4621E power OFF
Counter < 3
Counter = 3
Wait 40 ms
Set flag SC_L or SC_R to 1
Set flag HiZ_L or HiZ_R to 1
TS4621E power ON
Timeout = 40 ms
Shortcut detection
Shortcut detection & timeout = 0
AM06117
If a short-circuit is detected three consecutive times on one channel, a flag is raised in the
I²C read register CR1.
●
SC_L: equals 0 during normal operation, equals 1 when a short-circuit is detected on
the left channel.
●
SC_R: equals 0 during normal operation, equals 1 when a short-circuit is detected on
the right channel.
The corresponding channel’s output stage is then set to high impedance mode. An I²C read
command allows the reading of the SC_L and SC_R flags but does not reset them. An I²C
write command has to be sent to CR1 to reset the flags to 0 and restore normal operation.
Doc ID 022201 Rev 1
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Application information
TS4621E
Thermal shutdown protection: bit T_SH
A thermal shutdown protection is implemented to protect the device from overheating. If the
temperature rises above the thermal junction of 150°C, the device is put into standby mode
and a flag is raised in the read register CR1.
●
T_SH: equals 0 during normal operation, equals 1 when a thermal shutdown is
detected.
When the temperature decreases to safe levels, the circuit switches back to normal
operation and the corresponding flag is cleared.
Software shutdown: bit SWS
When SWS equals 1, the device is set to I²C software shutdown. When SWS equals 0, the
negative supply and buck converters are activated.
Channel activation: bits HP_EN_L and HP_EN_R
When HP_EN_L or HP_EN_R equals 1, the corresponding amplifier channel is enabled.
4.2
Wake-up and standby time definition
The wake-up time of the TS4621E is guaranteed at 12 ms typical (refer to Chapter 3:
Electrical characteristics on page 7). However, since the TS4621E is activated with an I2C
bus, the wake-up start procedure is as follows.
1.
The master sends a start bit.
2.
The master sends the device address.
3.
The slave (TS4621E) answers by an acknowledge bit.
4.
The master sends the register address.
5.
The slave (TS4621E) answers by an acknowledge bit.
6.
The master sends the output mode configuration (CR1).
7.
If the TS4621E was previously in standby mode, the wake-up starts on the falling edge
of the eighth clock signal (SCL) corresponding to the CR1 byte.
8.
After 12 ms (de-pop sequence time), the TS4621E outputs are operational.
The standby time is guaranteed as 100 µs typical (refer to Chapter 3: Electrical
characteristics on page 7). However, since the TS4621E is de-activated with an I2C bus, the
standby time operates as follows.
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1.
The master sends a start bit.
2.
The master sends the device address.
3.
The slave (TS4621E) answers by an acknowledge bit.
4.
The master sends the register address.
5.
The slave (TS4621E) answers by an acknowledge bit.
6.
The master sends the output mode configuration (CR1), which corresponds, in this
case, to standby mode.
7.
The standby time starts on the falling edge of the eighth clock signal (SCL)
corresponding to the CR1 byte.
8.
After 100 µs, the TS4621E is in standby mode.
Doc ID 022201 Rev 1
TS4621E
4.3
Application information
Common mode sense
The TS4621E implements a common-mode sense pin to correct any voltage differences
that might occur between the return of the headphone jack and the GND of the device and
create parasitic noise in the headphone and/or line out.
The solution to strongly reduce and practically eliminate this noise consists in connecting
the headphone jack ground to the CMS pin. This pin senses the difference of potential
(voltage noise) between the TS4621E ground and the headphone ground. By way of the
frequency response of the common-mode sense pin, this noise is removed from the
TS4621E outputs.
Doc ID 022201 Rev 1
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Package information
5
TS4621E
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 75. TS4621E footprint recommendation
75 µm min.
100 μm max.
400 μm
400 μm
Track
150 μm min.
Not soldered
mask opening
400 μm
400 μm
PCB pad size: Φ = 260 µm maximum
Φ = 220 µm recommended
Solder mask opening: Φ = 300 μm min
(for 260 µm diameter pad)
Pad in Cu 18 μm with Flash NiAu (2-6 μm, 0.2 μm max.)
Figure 76. Pinout
TOP VIEW (balls are underneath)
INR -
VOUTR
SCL
SDA
D
D
SDA
SCL
VOUTR
INR -
INR+
CMS
PVSS
C2
C
C
C2
PVSS
CMS
INR+
INL+
HPVDD
C1
AGND
B
B
AGND
C1
HPVDD
INL+
INL -
VOUTL
AVDD
SW
A
A
SW
AVDD
VOUTL
INL -
3
2
1
1
2
3
4
4
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BOTTOM VIEW
Doc ID 022201 Rev 1
TS4621E
Package information
Figure 77. Marking (top view)
■
Logo: ST
E
■
Symbol for lead-free: E
■
Part number: 21
■
X digit: Assembly code
■
Date code: YWW
■
The dot marks pin A1
21X
YWW
Figure 78. Flip-chip - 16 bumps
1650 μm
■
■
400 μm
1650 μm
Die height (including bumps): 600 µm
±55 µm
■
Bump diameter: 250 µm ±40 µm
■
Bump height: 205 µm ±35 µm
■
Die height: 395 µm ±20 µm
■
Pitch: 400 µm ±40 µm
■
Coplanarity: 50 µm max
600 μm
400 μm
Die size: 1.65 mm x 1.65 mm ± 30 µm
Figure 79. Device orientation in tape pocket
1.5
4
1
1
A
Die size Y + 70 µm
A
8
Die size X + 70 µm
4
All dimensions are in mm
User direction of feed
Doc ID 022201 Rev 1
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Ordering information
6
Ordering information
Table 12.
30/32
TS4621E
Order codes
Order code
Temperature range
Package
Packing
Marking
TS4621EIJT
-40°C to +85°C
Flip-chip
Tape & reel
21
Doc ID 022201 Rev 1
TS4621E
7
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
06-Sep-2011
1
Changes
Initial release.
Doc ID 022201 Rev 1
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TS4621E
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