March 2011 TLE5011 GMR Angle Sensor Final Data Sheet V2.0 Sensors Edition 2011-03 Published by Infineon Technologies AG 81726 Munich, Germany © 2011 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TLE5011 Revision History: 2011-03, V2.0 Previous Revision: V1.0 Page Subjects (major changes since last revision) 6 Ordering code updated 7 Section 1.2 updated 14 Table 3, supply voltage and magnetic induction expanded; figure 7 added 15 Table 4; notes of supply current expanded 16 Table 5; table 6 added 17 Table 7, ESD expanded 21 Table 10, Notes updated 27 Table 14, register 0x0D updated 42 Package outline in figure 23 modified 43 Figure 24 added general Spelling and typing errors We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Final Data Sheet 3 V2.0, 2011-03 TLE5011 Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 1.1 1.2 1.3 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 GMR Voltage Regulator VRG (VDDG-Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Analog Voltage Regulator VRA (VDDA-Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Digital Voltage Regulator VRD (VDDD-Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset and Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplitude Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature-dependent behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Orthogonality Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Components of the Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Error Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature-dependent Offset Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplitude Normalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Orthogonality Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resulting Angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters after Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Communication Interface (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 3.6 3.6.1 3.6.2 3.6.3 3.7 3.8 3.9 3.9.1 Final Data Sheet 4 6 6 7 7 13 13 13 14 15 15 17 17 17 18 18 18 18 19 19 19 19 19 19 19 19 20 20 20 20 21 21 22 22 23 23 V2.0, 2011-03 TLE5011 Table of Contents 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 3.9.7 3.9.8 3.10 3.10.1 3.10.2 3.10.3 3.11 3.11.1 3.11.2 3.11.3 3.11.4 4 4.1 SSC Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter for DATA and CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Command Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers (08H to 0BH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Communication via SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave-active Byte Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example1: CRC calculation (Update X and Y and set ADC-Test Mode) . . . . . . . . . . . . . . . . . . . Example2: Use of two TLE5011 units in a bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Angle Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Angle Test and Temperature Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 25 26 26 26 27 27 30 33 34 34 35 36 37 37 38 38 39 40 40 40 40 41 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 42 43 43 44 44 Final Data Sheet 5 V2.0, 2011-03 GMR Angle Sensor 1 1.1 TLE5011 Product Description Overview The TLE5011 is a 360° angle sensor that detects the orientation of a magnetic field by measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR) elements. Data communications are accomplished with a bi-directional Synchronous Serial Communication (SSC) interface that is SPI compatible. The sine and cosine values can be read out digitally. These signals can be digitally processed to calculate the angle orientation of the magnetic field (magnet). This calculation can be done by using a COordinate Rotation DIgital Computer (CORDIC) algorithm. It is possible to connect more than one TLE5011 to one SSC interface of a microcontroller for redundancy or any other reason. If multiple TLE5011 devices are used, the synchronization of the connected TLE5011 is performed by a broadcast command. Each connected TLE5011 can be addressed by a dedicated Chip Select CS pin. Type Marking Ordering Code Package TLE5011 5011 SP000857850 PG-DSO-8 Final Data Sheet 6 V2.0, 2011-03 TLE5011 Product Description 1.2 • • • • • • • • • • • • • • • • • Features Giant Magneto Resistance (GMR)-based principle Integrated magnetic field sensing for angle measurement Designed for 3.3 V and 5 V systems Full 0 - 360° angle measurement Highly accurate single-bit SD-ADC 16-bit representation of sine / cosine values on the interface Wide magnetic operating range: 30mT to 50mT Bi-directional SSC interface up to 2 Mbit/s 3-pin SSC interface, SPI compatible with open drain ADCs and filters synchronized with external commands via SSC Test resistors for simulating angle values Core supply voltage 2.5 V 0.25-µm CMOS technology Automotive qualified: -40°C to +150°C (junction temperature) Latch-up immunity according JEDEC standard ESD > 4 kV (HBM) Green package with lead-free (Pb-free) plating 1.3 Application Example The TLE5011 GMR angle sensor is designed for angular position sensing in automotive applications, such as: • • • • Steering angle Brushless DC motor commutation (e.g. Electric Power Steering (EPS)) Rotary switch General angular sensing Final Data Sheet 7 V2.0, 2011-03 TLE5011 Functional Description 2 Functional Description 2.1 General The GMR angle sensor is implemented in vertical integration. This means that the GMR active areas are integrated above the logic portion of the TLE5011 device. GMR elements change their resistance depending on the direction of the magnetic field. Four individual GMR elements are connected to one Wheatstone sensor bridge. These GMR elements sense either of two components of the applied magnetic field: • • X component, VX (cosine) Y component, VY (sine) The advantage of a full-bridge structure is that the amplitude of the GMR signal is doubled. GMR Resistors S 0° VX VY N ADCX+ ADCX - GND ADCY + ADCY- VDDG 90° Figure 1 Sensitive Bridges of the GMR Angle Sensor Note: In Figure 1, the arrows in the resistor symbols denote the direction of the reference layer, which is used for the further explanation (Figure 2). The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are orientated orthogonally to each other to measure the 360° angle range. Using the ARCTAN function, the true 360° angle value can be calculated that is represented by the relation of the cosine (here X) and sine (here Y) signals. Because only the relative values influence the result, the absolute size of the two signals is of minor importance. Therefore, most influences on the amplitudes are compensated. Final Data Sheet 8 V2.0, 2011-03 TLE5011 Functional Description Y Component (SIN) VY X Component (COS) VX V VX (COS) 90° 0° 180° 270° 360° Angle α VY (SIN) Figure 2 Ideal Output of the GMR Angle Sensor 2.2 Pin Configuration Figure 3 2.3 Table 1 8 7 6 5 1 2 3 4 Center of Sensitive Area Pin Configuration (Top View) Pin Description Pin Describtion Pin No. Symbol In/Out Function 1 CLK I Chip Clock 2 SCK I SSC Clock 3 CS I SSC Chip Select 4 DATA I/O SSC Data, open drain 5 TST1 I/O Test Pin 1, must be connected to GND 6 VDD - Supply Voltage 7 GND - Ground 8 TST2 I/O Test Pin 2, must be connected to GND Final Data Sheet 9 V2.0, 2011-03 TLE5011 Functional Description 2.4 Block Diagram The block diagram shows all switches in the reset position. GND VDD GND-off Comp TST 1 VDD_max VDD_OV Comp VDD-off Comp CLK SCK SCK VRG VRG_OV VRG_Rst VRA VRA_OV VRA_Rst VRD VRD_OV SSC VRD_Rst DATA CS Angle Voltage GMR X Temperature Sensor VDDG A D 2 1 GND Comb Filter 16 FSYNC FIR Filter 16 XH XL Control FSM FCNT VDDG A D 2 GND 1 Comb 16 Filter FIR 16 Filter YH YL Angle Voltage GMR Y Analog Clock Digital Clock 2 VRG_Rst VRA_Rst VRD_Rst differential TLE5011 Reset PLL CLK Lock Digital Reset TST1 Figure 4 TST 2 Block Diagram Final Data Sheet 10 V2.0, 2011-03 TLE5011 Functional Description 2.5 Functional Block Description 2.5.1 Internal Power Supply The internal stages of the TLE5011 are supplied with different voltage regulators: • • • GMR Voltage Regulator VRG Analog Voltage Regulator VRA Digital Voltage Regulator VRD Each voltage regulator has its own overvoltage and undervoltage detection circuits. 2.5.2 GMR Voltage Regulator VRG (VDDG-Voltage) The GMR voltage regulator supplies all GMR parts: • • • GMR bridges Test voltages for angle test ADC reference voltage The voltages are monitored in the VRG overvoltage and undervoltage detectors. 2.5.3 Analog Voltage Regulator VRA (VDDA-Voltage) The analog voltage regulator supplies the analog parts: • • • • • ADCs PLL (analog) VDD-off comparator GND-off comparator VDD Overvoltage detection The voltages are monitored in the VRA overvoltage and undervoltage detectors. 2.5.4 Digital Voltage Regulator VRD (VDDD-Voltage) The digital voltage regulator supplies all digital parts: • • • • • Comb filters, FIR filters PLL (digital) Control FSM with bitmap SSC interface Counters (Reset, FSYNC, FCNT) The voltages are monitored in the VRD overvoltage and undervoltage detectors. 2.5.5 Phase-Locked Loop (PLL) The clock for the sensors is provided externally. This ensures synchronous operation in case of multiple system participants. The sensor has its own PLL to generate the necessary clock frequency for the chip operation. Final Data Sheet 11 V2.0, 2011-03 TLE5011 Functional Description 2.5.6 Safety Features The TLE5011 has a multiplicity on safety features to support Safety Integrity Level (SIL). Sensors meeting this performance standard are identified by Infineon with the following logo: Figure 5 PRO SIL Logo Safety features are: • • • • • • • • • Angle test (generated via test voltages feeding the ADC). Crossed signal paths (switchable for comparison) Invertable ADC bitstreams Overvoltage and undervoltage detection of internal and external voltages VDD-off and GND-off to detect supply malfunctions Frame counter and synchronisation counter Separate bandgap-reference voltages for regulators and comparators CRC-protected SSC protocol Locked configuration registers Disclaimer PRO-SIL™ is a Registered Trademark of Infineon Technologies AG The PRO-SIL™ Trademark designates Infineon products which contain SIL Supporting Features. SIL Supporting Features are intended to support the overall System Design to reach the desired SIL (according to IEC61508) or A-SIL (according to ISO26262) level for the Safety System with high efficiency. SIL respectively A-SIL certification for such a System has to be reached on system level by the System Responsible at an accredited Certification Authority. SIL stands for Safety Integrity Level (according to IEC 61508) A-SIL stands for Automotive-Safety Integrity Level (according to ISO 26262) Final Data Sheet 12 V2.0, 2011-03 TLE5011 Specification 3 Specification 3.1 Application Circuit The application circuit shows the microcontroller version with open-drain capabilities. 12V Voltage Regulator VDD SSC CLK each 100 R 1k VDD 100 R DATA_o CAN RX CAN TX CAN Tranceiver CAN µController Master GMR-Sensor TLE5011 DATA_i SCK 100 nF GND CSQ GND Figure 6 Application Circuit A complete system may consist of one TLE5011 and a microcontroller. The second TLE5011 may be used for redundancy to increase system reliability. The microcontroller should contain a CORDIC coprocessor for fast angle calculations, and flash memory for the calibration data storage. 3.2 Absolute Maximum Ratings Table 2 Absolute Maximum Rating Parameters Parameter Symbol Limit Values min. Unit Notes max. Voltage on VDD pin with respect VDD to ground (VSS) -0.5 6.5 V max 40 h / lifetime Voltage on any pin with respect to ground (VSS) VIN -0.5 6.5 V VDD + 0.5 V may not be exceeded Junction temperature TJ -40 150 °C 150 °C for 1000 h not additive - |125| mT max 5 min. @ TA = 25°C - |100| max 5 h @ TA = 25°C - |70| max 1000 h @ TA = 85°C not additive - |60| max 1000 h @ TA = 100°C not additive -40 150 Magnetic field induction Storage temperature B TST °C without magnetic field Note: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Final Data Sheet 13 V2.0, 2011-03 TLE5011 Specification 3.3 Operating Range To ensure correct operation of the TLE5011, the operating conditions identified in Table 3 must not be exceeded. All parameters specified in the following sections refer to these operating conditions, unless otherwise indicated. Table 3 is valid for -40°C < TJ < 150°C Table 3 Operating Range Parameter Symbol Limit Values min. typ. max. Unit Notes Supply Voltage VDD 3.0 - 5.5 V For 3.3 & 5.0V systems1) Output Current IQ - -5 -10 mA 2) 3) Input Voltage VIN -0.3 - 5.5 V VDD + 0.35 V may not be exceeded Magnetic Induction at TA= 25°C 4) 5) BXY 30 - 50 mT -40°C < TJ<150°C BXY 30 - 60 mT -40°C < TJ<100°C BXY 30 - 70 mT -40°C < TJ<85°C BXY 25 - 30 mT Additional angle error of 0.1° 6) Ang 0 - 360 ° Sine / cosine Expanded Magnetic Induction at TA = 25°C 4) 5) Angle Range 1) 2) 3) 4) 5) 6) Directly blocked with 100-nF ceramic capacitor Maximum current to GND over Open Drain Output The corresponding voltage levels are listed in Table 5 and Table 6 Values refer to an homogenous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT) See Figure 7 0h The field strength of a magnet can be selected within the colored area in Figure 7. By limitation of the junction temperature, a higher magnetic field can be applied. In case of a maximum temperature TJ = 100°C a magnet with up to 60mT at TA = 25°C is allowed. Figure 7 Magnet performance (ambient temperature) Final Data Sheet 14 V2.0, 2011-03 TLE5011 Specification Note: The thermal resistances listed in Table 21 “Package Parameters” on Page 42 must be used to calculate the corresponding ambient temperature. Calculation of the Junction Temperature The total power dissipation PTOT of the chip increases its temperature above the ambient temperature. The power multiplied by the total thermal resistance RthJA (Junction to Ambient) leads to the final junction temperature. RthJA is the sum of the addition of the values of the two components Junction to Case and Case to Ambient. RthJA = RthJC + RthCA TJ = TA + ΔT ΔT = RthJA x PTOT = RthJA x ( VDD x IDD + VOUT x IOUT ) IDD , IOUT > 0, if direction is into IC Example (assuming no load on Vout): – VDD = 5 V – IDD = 15 mA – ΔT =150 [K/W] x (5 [V] x 0.015 [A] + 0 [VA] ) =11.25 K For moulded sensors, the calculation with RthJC is more adequate. 3.4 Characteristics 3.4.1 Electrical Parameters The indicated electrical parameters apply to the full operating range, unless otherwise specified. The typical values correspond to a supply voltage VDD = 5.0 V and 25°C, unless individually specified. All other values correspond to - 40°C < TJ < 150°C. Table 4 Electrical Parameters Parameter Supply Current Symbol 1) IDD Limit Values min. typ. max. - 15 20 - - 21 Unit Notes mA VDD = 3.0 to 5.5V VDD = 6.5 V POR Level VPOR 2.0 2.3 2.9 V POR Hysteresis VPORhy - 30 - mV Power-On Time tPon 50 100 200 µs VDD > VDDmin & after first edge on fCLK PLL Jitter tPLLjit_S - 1.3 2.0 2) ns short term 3) 3.0 3.9 1 2.2 tPLLjit_L ADC Noise 5) NADC - Final Data Sheet 2) 2 4.4 15 Power-On Reset long term 4) digits 1 σ @ FIR_BYP = 0 1 σ @ FIR_BYP = 1 V2.0, 2011-03 TLE5011 Specification Table 4 Electrical Parameters Parameter Symbol Limit Values min. typ. max. Unit Notes Input Signal Low Level VL -0.35 - 0.3 VDD V Input Signal High Level VH 0.7 VDD - VDD +0.35 V Tested only at DATA pin as structures of all pins are identical Capacitance of SSC Data Pin CLDATA - 4 6 2) pF Internal 1) 2) 3) 4) 5) Without external pull-up resistor for SSC interface Not subject to production test - verified by design/characterization From pulse to pulse Accumulated over 1 ms ADC noise with respect to the peak ADC value specified in “Signal Processing” on Page 21. Noise tested using 1 σ of 100 sample values from Angle Test “000” Table 5 Electrical Parameters for 3.0V < VDD < 3.6V Parameter Symbol Limit Values Unit min. typ. max. Notes Input Hysteresis VHY3 0.02 VDD - - V Pull-Up Current IPU3 -5 - -50 µA CS, DATA Pull-Down Current IPD3 10 - 150 µA SCK, CLK 8 - 100 TST1 5 - 50 TST2 - - 1.3 0.9 0.4 Output Signal Low Level VOL3 V IQ = - 10 mA IQ = - 7 mA1) IQ = - 2.5 mA 1) Unit Notes 1) Not subject to production test - verified by design/characterization Table 6 Electrical Parameters for 4.5V < VDD < 5.5V Parameter Symbol Limit Values min. typ. max. Input Hysteresis VHY5 0.07 VDD - - V Pull-Up Current IPU5 -10 - -150 µA CS, DATA Pull-Down Current IPD5 15 - 225 µA SCK, CLK 15 - 225 TST1 10 - 150 TST2 - - 0.7 0.4 Output Signal Low Level VOL5 V IQ = - 10 mA IQ = - 5 mA 1) 1) Not subject to production test - verified by design/characterization Final Data Sheet 16 V2.0, 2011-03 TLE5011 Specification 3.4.2 ESD Protection Table 7 ESD Protection Parameter Symbol Limit Values min. ESD Voltage Unit Notes max. VHBM - ±4 kV HBM 1) VSDM - ± 500 V SDM 2) 1) Human Body Model (HBM) according to: AEC-Q100-002 2) Socketed Device Model (SDM) according to: ESDA/ANSI/ESD SP5.3.2-2008 3.4.3 GMR Parameters All parameters apply over the full operating range, unless otherwise specified. Table 8 Basic GMR Parameters Parameter Symbol Limit Values Unit Notes min. typ. max. RGADC - - ±23230 digits AX, AY 6000 9500 15781 digits 3922 - 20620 k 80 100 120 % at calibration conditions OX, OY -3000 0 3000 digits at calibration conditions X, Y Orthogonality Error ϕ -10.0 0 10.0 ° at calibration conditions X, Y without field X0, Y 0 -5000 - 5000 digits without magnet4) X, Y Output range X, Y Amplitude 1) X, Y Synchronism X, Y Offset 1) 2) 3) 4) 2) 3) at calibration conditions Operating Range See Figure 2 k = 100 x ( AX / AY ). OSIN = ( YMAX + YMIN ) / 2 ; OCOS = ( XMAX + XMIN ) / 2 Not subject to production test - verified by design/characterization Offset and Amplitude VY +A 0° 90° 180° 0 Offset 270° 360° Angle -A Figure 8 Offset and Amplitude Definition Final Data Sheet 17 V2.0, 2011-03 TLE5011 Specification Offset Definition The offset of the X and Y signals is defined as the mean value between the signed maximum and minimum values of the idealized sine or cosine wave. X MAX + X MIN O X = --------------------------------- 2 Y MAX + Y MIN O Y = -------------------------------- 2 Amplitude Definition The amplitude is defined as half the difference between the signed maximum and minimum values of the idealized sine or cosine wave. X MAX – X MIN A X = -------------------------------- 2 Y MAX – Y MIN A Y = -------------------------------- 2 Temperature-dependent behavior The temperature offset gradients for both channels depend on the value at 25°C. The gradients can be calculated using the following linear equations: KT OX = tco_d_x + ( tco_k_x × O X25 ) KT OY = tco_d_y + ( tco_k_y × O Y25 ) OX25, OY25: Offset values at 25°C in digits. The application note “TLE5011 Calibration” describes in chapter 2.3, how to determine the coefficients (KTOX, KTOY). Orthogonality Definition The corresponding maximum and zero-crossing points of the SIN and COS signals do not occur at the precise distance of 90°. The difference between X and Y phase is called the orthogonality error. ϕ = ϕX – ϕY ϕideal = 0° ϕX: Phase error of X (= cos) signal ϕY: Phase error of Y (= sin) signal Final Data Sheet 18 V2.0, 2011-03 TLE5011 Specification 3.5 Calibration GMR Values The end-of-line calibration can be accomplished using following sequence: 1. 2. 3. 4. 5. 6. Turn magnetic field 360° left and measure X and Y values Calculate amplitude, offset, phase correction values of left turn Turn further 90° left and 90° back right without measurement Turn magnetic field 360° right and measure X and Y values Calculate amplitude, offset, phase correction values of right turn Calculate mean values of amplitude, offset, phase correction values The conditions are specified in Table 9. The values obtained from this sequence must be stored in a non-volatile memory. They are used for the correction of the read-out X and Y values before the angular calculation. The resulting angular deviation is calculated using the parameters determined above. Temperature Measurement The signal amplitude T25 of the temperature measurement path at the calibration conditions must be measured and stored. Calibration Conditions All errors are related to calibration performed by Infineon under the following conditions: Table 9 GMR test calibration conditions at IFX Parameter Symbol Limit Values min. typ. max. Unit Notes BZ = 0 mT Flux density BCAL - 30 - mT Temperature TCAL - 25 - °C 3.6 Angle Calculation 3.6.1 Components of the Output Signals The X and Y signals at the output can be described by the following equations: X = A X × cos ( α + ϕ X ) + O X Y = A Y × sin ( α + ϕ Y ) + O Y AX : Amplitude of X (= cos) signal AY : Amplitude of Y (= sin) signal OX : Offset of X (= cos) signal OY : Offset of Y (= sin) signal ϕX : Phase error of X (= cos) signal ϕY : Phase error of Y (= sin) signal 3.6.2 GMR Error Compensation Temperature-dependent Offset Value To increase the accuracy, the temperature-dependent offset drift can be compensated. The temperature of the chip must be read out. The offset values OX and OY can be described by the following equations. Final Data Sheet 19 V2.0, 2011-03 TLE5011 Specification KT OX O X = O X25 + -------------- × ( T – T 25 ) S T KT OY O Y = O Y25 + -------------- × ( T – T 25 ) S T OX25 , OY25 : Offset value at 25°C in digits T25 : Temperature value at 25°C in digits T : Temperature value in digits ST : Sensitivity of the temperature measurement path, (see “Temperature Measurement” on Page 38). Offset Correction After the X and Y values are read out, the temperature-corrected offset value must be subtracted. X1 = X – OX Y1 = Y – OY Amplitude Normalization Next, the X and Y values are normalized using the peak values determined in the calibration. X X 2 = ------1 AX Y1 Y 2 = -----AY Non-Orthogonality Correction The influence of the non-orthogonality can be compensated using thefollowing equation, in which only the Y channel must be corrected. Y 2 – X 2 × sin ( – ϕ ) Y 3 = ------------------------------------------ cos ( – ϕ ) Resulting Angle After correction of all errors, the resulting angle can be calculated using the arctan function1). Y3 α = arc tan ⎛⎝ ------⎞⎠ – ϕ X X2 1) Microcontroller function “arctan2(Y3,X2)” to resolve 360° Final Data Sheet 20 V2.0, 2011-03 TLE5011 Specification 3.6.3 GMR Parameters after Calibration After calibration under the conditions specified in Table 9 “GMR test calibration conditions at IFX” on Page 19, the sensor has a remaining error as shown in Table 10. The error value refers to BZ = 0 mT and operating conditions given in Table 3 “Operating Range” on Page 14. Table 10 GMR Parameter with Temperature-Dependent Offset Compensation Parameter Symbol Overall Angle Error Limit Values αerr min. typ. - 0.7 1) Unit Notes ° Including temperature drift max. 1.6 2) 3) 1) 2) 3) 4) - 2.2 ° Including lifetime and temperature drift 2) 4) At 25°C, B=30mT Including hysteresis error At 0h Not subject to production test - verified by design/characterization 3.7 Signal Processing Table 11 Signal Processing Parameter Symbol Internal Cutoff Frequency (-3dB) of sin or cos Value fCut-Off Update Time of sin or cos Value2) tupd Settle Time 3) Limit Values min. typ. - 4.9 1) Unit Notes kHz FIR_BYP=0 max. - 19.6 tsettle Peak ADC Output value ADCPk FIR_BYP=1 - 81.9 - µs - 20.5 - FIR_BYP=1 - 163.8 - FIR_BYP=0 - 41.0 - FIR_BYP=1 - - 23230 digits FIR_BYP=0 Signed 16-bit integer (2s complement) 4) 5) 6) 1) For 4-MhHz input frequency 2) tupd = 8192 / (25 x fCLK) for FIR_BYP = 0 tupd = 8192 / (100 x fCLK) for FIR_BYP = 1 3) tsettle = 2 x tupd , after change of ADC input source 4) Output values are valid up to this limit. Above it, corrupted results may occur due to non-linearity of the ADC. 5) One digit typically represents 5.166 µV 6) Corresponds to max. GMR output value Final Data Sheet 21 V2.0, 2011-03 TLE5011 Specification 3.8 Clock Supply (CLK Timing Definition) The clock signal input “CLK” must fulfill certain requirements described in this section: • • • The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width and must be spike filtered. The duty-cycle factor should be 0.5 but can deviate from the values limited by tCLKh(f_min) and tCLKl(f_min). The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is generated automatically. tCLK tCLKh t CLKl VH VL t Figure 9 CLK Timing Definition Table 12 CLK Timing Specification Parameter Symbol Limit Values Unit Notes min. typ. max. fCLK 3.8 4.00 4.2 MHz CLKDUTY 30 50 70 % CLK rise time tCLKr - - 20 ns from VL to VH CLK fall time tCLKf - - 20 ns from VH to VL PLL Frequency fPLL - 100 - MHz fCLK * 25 Digital Clock fDIG - 25 - MHz ( 25 / 4 ) * fCLK Digital Clock Periode tDIG - 40 - ns 4 / (25 * fCLK) Input Frequency CLK Duty Cycle 1) 1) Minimum duty-cycle factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min) = 1 / fCLK(f_min) Maximum duty-cycle factor: tCLKh(f_max) / tCLK(f_min)with tCLKh(f_max) = tCLK(f_min) - tCLKl(min) 3.9 Synchronous Serial Communication Interface (SSC) The 3-pin SSC interface has a bidirectional data line (open drain), a serial clock signal, and Chip Select. The SSC interface is designed to communicate with a microcontroller with bi-directional SSC interface supporting open drain. Other microcontrollers may require an external NPN transistor. This allows communication with SPI-compatible devices. Final Data Sheet 22 V2.0, 2011-03 TLE5011 Specification µC (SSC Master) TLE 501x (SSC Slave) typ. 1k Ω DATA Shift Register *) *) DATA Shift Register *) SCK SCK *) CS Clock Generator Figure 10 CS *) optional , e.g. 100 Ω SSC Half-Duplex Configuration - Microcontroller with Open Drain µC (SSC Master) Shift Register TLE 501x (SSC Slave) typ. 1kΩ MRST *) *) MTSR DATA Shift Register optional *) SCK SCK *) Clock Generator CS CS *) optional , e.g. 100 Ω Figure 11 SSC Half-Duplex Configuration - Microcontroller without Open Drain 3.9.1 SSC Timing Definition SSC Timing Diagram tSCKp tCSs tSCKh tCSh tSCKl CS VH VL SCK VH VL DATA VH VL tDATr Figure 12 tCSoff tDATw SSC Timing Definition SSC Inactive Time ( CSoff ) The SSC Inactive Time defines the delay before the TLE5011 can be selected again after a transfer. The TLE5011 reacts only to one command after an SSC Inactive Time. Then the SSC interface of the TLE5011 is disabled until the next SSC Inactive Time occurs. Final Data Sheet 23 V2.0, 2011-03 TLE5011 Specification DATA Write Time ( tDATW ) During this time, the TLE5011 changes the data line, so the data are invalid. The DATA Write Time values are defined without a pull-up resistor. Pull-up Time Value ( tPU ) The value in Table 13 “SSC Timing Specification” on Page 24 is estimated at 60 ns. Table 13 SSC Timing Specification Note: Timing must be calculated according to Table 12 “CLK Timing Specification” on Page 22 Parameter Symbol Limit Values Unit min. typ. max. SSC Baud Rate fSSC - 2.0 2.11) Mbit / s CS Setup Time tCSs 3*tDIG+10 - - ns CS Hold Time tCSh 5*tDIG+10 - - ns CSoff tCSoff 10*tDIG - - ns SCK High tSCKh 5*tDIG - - ns SCK Low tSCKl 5*tDIG - - ns DATA Read Time (Data Valid Time) tDATr 6*tDIG-10 - 7*tDIG+10 ns 5*tDIG-10 - 7*tDIG+10 DATA Write Time (Data Valid Time) 2) tDATw 6*tDIG+25 - 7*tDIG+50 + tPU ns DATA slope tDATs - 20 30 3) 1) 2) 3) 4) Notes SSC inactive time SSC_FILT = 0 SSC_FILT = 1 ns Falling edge 4) fCLK/2, synchronized to fCLK if fCLK = fCLK(max) tPU is the time generated by the pull-up resistor Not subject to production test - verified by design/characterization Internal slope control of falling edge for data bit transition from VH to VL. tSCKl MIN tSCKh SCK tDATw MIN SSC_FILT=0 Wr tDATw MAX tPU Earliest sample timepoint tDATr MIN tDATr MAX Rd SCK tDATw MIN SSC_FILT=1 Wr tDATw MAX tPU t DATr MIN tDATr MAX Figure 13 Earliest sample timepoint of second sample from 2 of 3 filter Rd SSC Interface Timing Details - Worst-Case Specified Timing Note: The read window includes the sampling of the data bit. For SSC_FILT = 1, the 2-of-3 selection is already considered. Only the two last data values need to be equal. For SSC_FILT = 0, only one sample point is selected. Final Data Sheet 24 V2.0, 2011-03 TLE5011 Specification The margin time shown in Table 14 is the time between write access to the SSC data line and the earliest possible sample read of the TLE5011 itself for read-back. It is useful to have a maximum distance between the WRITE and subsequent READ. This ensures a reliable readback of the written data for the Slave-Active Byte generation. Table 14 Maximum Pull-up Time Margin with Worst-Case Specified Timing SSC_FILT SSC_TIMING 0 don’t care Min. tPU Margin 1) Unit 90 ns 1 Comment 50 1) Calculation: Margin=tSCKl(min)+tDATwMAX-(tPU)-tDATrMIN.For Margin<50 ns no problems can occur. 3.9.2 SSC Baud rate The SSC baud rate depends on the internal clock frequency. Twelve internal digital clock cycles are necessary to ensure reliable operation. Therefore, the maximum SSC baud rate depends on the external CLK. f CLK f SSC = ---------- 2 3.9.3 SSC Spike Filter A spike filter for all SSC lines can be selected via the SSC_FILT bit. SSC Spike Filter Off When the spike filter is disabled, each slope with rising voltage is used to define a bit. This is independent of the length of the sampled pulse. For example, a positive spike generates a rising and a falling edge. SSC Spike Filter On A sliding window with four consecutive sample bits is analyzed. The sample frequency is: 1 f S = --------------f DIGIT Rising Edge Detect for SCK • • After a rising edge (LH combination), at least one of the two following samples must be high. Valid bit combinations: 0111 , 0110 , 0101. A falling condition must be detected previously. Falling Edge Detect for SCK • • After a falling edge (HL combination), at least one of the two following samples must be low. Valid bit combinations: 1000 , 1001 , 1010. A rising condition must be detected previously. Final Data Sheet 25 V2.0, 2011-03 TLE5011 Specification ) SCK (PAD) SCK Fall SCK fall detected Suppressed Spike ) SCK rise detected ) ) SCK Rise Masked, because no fall detected Figure 14 SSC Spike Filter Filter for DATA and CS The following conditions apply: • • The DATA pin has a ’2-of-3’ filter The CS input has a ’2-of-3’ filter that suppresses only positive spikes 3.9.4 SSC Data Transfer The following transfer Byte are possible: • • • • Command Byte (to access and change operating modes of the TLE5011) Data Bytes (any data transferred in any direction) CRC Byte (cyclic redundancy check) Slave-active Byte (response of all selected slaves) SSC-Master is driving DATA (µC) SSC-Slave is driving DATA (Sensor) Command Byte Data Byte(s) SCK DATA MSB 6 5 4 3 2 1 LSB MSB 6 5 CRC SlaveActive 4 3 2 1 LSB CS DATA Command Byte SSC-Master is driving DATA (µC) Data SSC-Slave is driving DATA (Sensor) Figure 15 SSC Data Transfer (Data Read Example) 3.9.5 SSC Command Byte The TLE5011 is controlled by a command Byte. It is sent first at every data transmission. Table 15 Structure of the Command Byte Name Bits Description RW [7] Read - Write 0 = write, 1 = read ADDR [6..3] Address to be read / written 0..15 - register start address (address auto increment) ND [2..0] Number of data Bytes 0..7 - number of data Bytes to be transferred Final Data Sheet 26 V2.0, 2011-03 TLE5011 Specification Register Table This section describes the complete address range as well as all registers of the TLE5011. It also defines the read/write access rights of the specific registers. Table 16 identifies the values with symbols. Access to the registers is accomplished via the SSC interface. Table 16 Addr. Address Map Name Bits 7 6 5 4 3 00H CTRL1 01H XL XLow 02H XH XHigh 03H YL YLow - - - - 04H YH 05H FCNT_ STAT - 06H FSYNC_IN V FILT_ INV 07H ANGT - 08H - reserved 09H - reserved 0AH - reserved 0BH - 0CH TST 0DH ID 0EH LOCK 0FH CRTL2 2 SSC_ FILT 1 - 0 AUTO UR YHigh STAT_ VR GMR_ OFF UPDATE FCNT FSYNC ANGT_E N ANGT_Y ANGT_X reserved TEMP_E N ADCPY FILT_ PAR FILT_ CRS FILT_ BYP DEV_ID TST_ ADC TST_ GMR TST_ CHAN reserved LOCK VDD_OV VDD_ OFF GND_OF F VRG_ OV VRA_ OV VRD_ OV S_NO Bit Types The types of bits used in the registers are listed here: Abbreviation Function Description L Locked Locked register. Locked registers can be written only when the unlock-value is written in the lock register (0EH). This ensures that these bits cannot be modified unintentionally during normal operation. U Update Update buffer for this bit is present. If an Update Command is issued and the Update-Mode bit (UR in CTRL1) is set, the immediate values are stored in this Update Buffer simultaneously. This enables a snapshot of all necessary system parameters at the same time. Final Data Sheet 27 V2.0, 2011-03 TLE5011 Specification Abbreviation Function Description S Status Reset only after readout R Read Read-only registers W Write Read and write registers CTRL1 Addr: 00H Reset Value: 01H 7 6 5 4 3 2 1 0 reserved reserved reserved reserved SSC_FILT reserved AUTO UR - - - WL WL - WL WL Field Bits Type Description reserved 7 - Reserved, must be set to 0 reserved 6 - Reserved, must be set to 0 reserved 5 - Reserved, must be set to 0 reserved 4 - Reserved, must be set to 0 SSC_FILT 3 WL SSC Digital Spike Filter enable for all SSC lines ( CS, CLK and DATA ) 0: Digital SSC Spike filters off 1: Digital SSC Spike filters on (modified timing) reserved 2 - Reserved, must be set to 0 AUTO 1 WL Automatic update at angle tests 0: no automatic update in Angle Test Mode 1: automatic update-command after tsettle, counters FSYNC and FCNT are reset to 0. Then the Angle-Test (ANGT_EN) is automatically disabled and switches back to normal operation. Also, the UPDATE bit is toggled UR 0 WL Update / Run Mode 0: Run Mode (Buffer1 values are immediate values) 1: Update Mode (Buffer2 values are stored values) The values in Register 01H to 04H represent one Byte of two’s complement signed 16 bit integer values. X_L Addr: 01H 7 Reset Value: 00H 6 5 4 3 2 1 0 2 1 0 X Low Byte RU X_H Addr: 02H 7 Reset Value: 00H 6 5 4 3 X High Byte RU Final Data Sheet 28 V2.0, 2011-03 TLE5011 Specification Y_L Addr: 03H Reset Value: 00H 7 6 5 4 3 2 1 0 2 1 0 2 1 0 Y Low Byte RU Y_H Addr: 04H Reset Value: 00H 7 6 5 4 3 Y High Byte RU FCNT_STAT Addr: 05H Reset Value: 80H 7 6 5 4 reserved STAT_VR GMR_OFF UPDATE FCNT - RS RU RS RU Field 3 Bits Type 7 - STAT_VR 6 RS Voltage Regulator Status This bit is a logical OR combination of Digital, Analog, GMR and VDD_OV Comparator and GND_OFF, and VDD_OFF Comparator outputs. 0: Voltage Supply OK 1: Voltage Supply is not OK GMR_OFF 5 RU ADC Values are no GMR values (e.g.: Temperature measurement is active) This bit indicates whether or not GMR values or any other values are connected to the ADCs. This value is read back from the multiplexer control signals. 0: X,Y Values are GMR values 1: X,Y Values normally represent temperature measurement or angle test values. In the case of non-functional MUX, this bit is set to 1 UPDATE 4 RU Update Toggle bit. This bit toggles after every update (update command or automatic update at angle test) The bit is independent of UR bit in CTRL1 FCNT 3-0 RU Frame Counter (4-bit unsigned integer value) This counter counts every new X,Y value pair coming out of the data path. (approx. 80µs) This counter is reset to 0H after any write to FSYNC and after every change of the ANGT_EN bit. As tsettle time has to elapse for valid X,Y data, this counter must be ≥ 2H to indicate valid X,Y values. If it overflows, it resets to 3H to show that values are still valid. reserved Description Note: If FIR_BYP is activated, this counter counts four times faster! Final Data Sheet 29 V2.0, 2011-03 TLE5011 Specification FSYNC_INV Addr: 06H Reset Value: 00H 7 6 5 4 3 FILT_INV FSYNC WU WU 2 1 0 Field Bits Type Description FILT_INV 7 WU Filter Input Inversion (to check the digital data path during operation) 0: Filter Inputs are not inverted 1: Filter Inputs are inverted FSYNC 6-0 WU Frame Synchronization (7-bit unsigned integer value) The Filter Update time of approx. 80 µs results from the filter decimation. The phase of this decimation can be set and checked by this counter. If FIR_BYP is activated, this counter overflows at the value 31D. ANGT Addr: 07H Reset Value: 00H 7 6 5 4 3 2 1 reserved ANGT_EN ANGT_Y ANGT_X - W W W 0 Field Bits Type Description reserved 7 - Reserved, must be set to 0 ANGT_EN 6 W Angle Test Enable 0: Angle Test disable command 1: Angle Test enable command in this case X and Y values represent resistive test values that can be used to simulate angle values ANGT_Y 5-3 W ANGT_X 2-0 W Angle Test X and Y value See : Table 18 “Functional Angle Test” on Page 37 Reserved Registers (08H to 0BH) The values in these registers are 8-bit unsigned integer values. The values in addr.8 and addr.9 have to be in reset status. Reserved Addr: 08H 7 Reset Value: FFH 6 5 4 3 2 1 0 Reserved Final Data Sheet 30 V2.0, 2011-03 TLE5011 Specification Reserved Addr: 09H - 0BH 7 Reset Value: 00H 6 5 4 3 2 1 0 Reserved TST Addr: 0CH Reset Value: 00H 7 6 5 4 3 2 1 0 TEMP_EN ADCPY FILT_PAR FILT_CRS FIR_BYP TST_ADC TST_GMR TST_ CHAN WL WL WL WL WL WL WL WL Field Bits Type Description TEMP_EN 7 WL Temperature Device Enable 0: Temperature Measurement disabled 1: Temperature Measurement enabled The X value represents the temperature. Automatic update mode enabled, if AUTO=1 ADCPY 6 WL Y Polarity 0: No inversion of Y bitstream 1: Inversion of Y bitstream (rotating direct. changed) FILT_PAR 5 WL Filter switched parallel 0: Filters in normal mode 1: Filters parallel, input selected by TST_CHAN FILT_CRS 4 WL Filter switched across 0: Filters in normal mode 1: Filters crossed, X and Y outputs are exchanged FIR_BYP 3 WL FIR Filter Bypass 0: No FIR Bypass 1: FIR Bypass TST_ADC 1) 2 WL ADC input switch to TST1and TST2 0: No ADC input switch, normal operation 1: ADC input switched to TST1,2, ADC selected by TST_CHAN 2) TST_GMR 1) 1 WL GMR switch to TST1and TST2 0: No GMR switch, normal operation 1: GMR switched to TST1,2 selected by TST_CHAN 2) TST_CHAN 0 WL Test Channel select 0: X channel linked to TST1and TST2 1: Y channel linked to TST1and TST2 1) Only for test purposes 2) if TST_ADC and TST_GMR are set to 1 at the same time, TST_GMR is forced to 0. TST_ADC has the higher priority. Final Data Sheet 31 V2.0, 2011-03 TLE5011 Specification ID Addr: 0DH Reset Value: 12H 7 6 5 4 3 2 1 0 2 1 0 1 0 DEV_ID Reserved R R Field Bits Type Description DEV_ID 7-4 R Device Identifier 001H: TLE5011 production chip reserved 3-0 - LOCK Addr: 0EH Reset Value: 00H 7 6 5 4 3 LOCK W Field Bits Type Description LOCK 7-0 W Lock Byte ≠ 5AH: Lock registers locked = 5AH: Lock registers unlocked CTRL2 Addr: 0FH Reset Value: 00H 7 6 5 4 3 2 VDD_OV VDD_OFF GND_OFF VRG_OV VRA_OV VRD_OV S_NO RS RS RS RS RS RS WL Field Bits Type Description VDD_OV 7 RS VDD Overvoltage Comparator 0: No VDD Overvoltage occurred 1: VDD Overvoltage occurred VDD_OFF 6 RS VDD - off Comparator 0: No VDD - off occurred 1: VDD - off occurred GND_OFF 5 RS GND - off Comparator 0: No GND - off occurred 1: GND - off occurred VRG_OV 4 RS GMR Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRG Overvoltage occurred Final Data Sheet 32 V2.0, 2011-03 TLE5011 Specification Field Bits Type Description VRA_OV 3 RS Analog Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRA Overvoltage occurred VRD_OV 2 RS Digital Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRD Overvoltage occurred S_NO 1-0 WL Slave Number Used in the SSC protocol 3.9.6 Data Communication via SSC Data communication via the SSC interface has the following characteristics: • • • • • • • • • • • • • The data transmission order is “Most Significant Bit (MSB) first”. Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK. The SSC interface is Byte-aligned. All functions are activated after each transmitted Byte. A “high” condition on the negated Chip Select pin (CS) of the selected TLE5011 interrupts the transfer immediately. The CRC calculator is automatically reset. Every access to the TLE5011 with the number of data (ND) ≥ 1 is performed with address auto-increment. After an auto-increment overflow, the addresses begin from 00H. For every data transfer with ND ≥ 1, an 8-bit CRC Byte will be appended by the selected TLE5011. No CRC Byte is sent in a data transfer with ND = 0 (e.g. Update Command). After the CRC Byte is sent, the bit represented by S_NO is pulled low by the selected slave in the Slave-ActiveByte (bits [3..0], low nibble). In this way, broadcast messages also produce individual feedback of every selected slave. This is necessary to differentiate among the individual TLE5011 slave responses, because the CRC Byte is written by both TLE5011 units in parallel. If the CRC Byte on the bus is the same as the internally generated CRC of each TLE5011, each slave pulls the dedicated bit in the Slave-Active Byte (bits [7..4], high nibble) low. If not, the bit in the high nibble remains 1. A write command to address 00H with ND = 0 will update all values inside the TLE5011, and only in this case can the transfer proceed. Furthermore, this command is added to the CRC calculation of the following SSC transfer. A command of 0000_0000 is called Update Command. This command transfers the present immediate values of each register to the update register. After an Update Command, the CS line does not need to be set and reset again. The transfer ends after the CRC and Slave-active Byte have been sent. The TLE5011 always sends logical 1 and all following sent bits from the SSC Master are ignored (TLE5011 is in Idle mode). To enable data transfers again, the Chip Select pin (CS) of the TLE5011 must be deselected for CSoff (see Table 13) once. If the Update Mode is selected (CTRL register, UR = 1), all accesses are performed to update registers where update registers are present. Other registers are accessed directly. Final Data Sheet 33 V2.0, 2011-03 TLE5011 Specification 3.9.7 CRC Generation These are the requirements for CRC generation: • • • • • • This CRC is defined according to the J1850 Bus-Specification of 15.Feb.1994 for Class B Data Communication. Every new transfer resets the CRC generation. Every Byte of a transfer will be taken into account to generate the CRC [also the sent command(s)]. Generator Polynomial: X8+X4+X3+X2+1, the fast CRC generation circuit, is used for CRC generation. (See Figure 16) The remainder of the fast CRC circuit is initially set to 11111111B. The remainder is bit-inverted before transmission. Figure 16 shows the fast CRC Polynomial. The zero extension for initial CRC calculation is included! Input xor TX_CRC & 1 1 X0 xor xor 1 X1 X2 xor 1 1 X3 1 X4 1 X5 Serial CRC output 1 X6 X7 parallel Remainder Figure 16 Fast CRC Polynomial Division Circuit 3.9.8 Slave-active Byte Generation The position of the 0 in a nibble corresponds to the given slave number. The slave-active Byte (cccc_nnnn) consists of: • • low nibble (nnnn). One 0 is generated always according to the slave number. high nibble (cccc). The 0 is only generated, if the readback CRC is correct. Slave1: S_NO = 0 Ö bit 0 is pulled low Slave-active Byte: 1110_1110 Slave2: S_NO = 1 Ö bit 1 is pulled low Slave-active Byte: 1101_1101 Slave3: S_NO = 2 Ö bit 2 is pulled low Slave-active Byte: 1011_1011 Slace4: S_NO = 3 Ö bit 3 is pulled low Slave-active Byte: 0111_0111 Example of a communication disturbed by other bus participants: Slave1: S_NO = 0 Ö bit 0 is pulled low, but the high nibble remains as ’1111’. > Slave-active Byte: 1111_1110 Final Data Sheet 34 V2.0, 2011-03 TLE5011 Specification Example1: CRC calculation (Update X and Y and set ADC-Test Mode) Command Data CRC (init all ‘0’) 00000001 00000101 00000000 ----------------------------------xor 11111111 -------=11111110.0 . .A xor 10001110.1 . . --------.. . = 01110000.10 . .B xor 1000111.01 . . -------.-. . = 0110111.110 . .C xor 100011.101 . . ------.--. . = 10100.0110 . .D xor 10001.1101 . . -----.---. . = 00101.101101 . .E xor 100.011101 . . ---.------ . . = 001.11000001. .F xor 1.00011101. . ---.------ . . =.11011100.0 .G xor.10001110.1 . .--------.. = 1010010.10 .H xor 1000111.01 . -------.. = 10101.1100 .I xor 10001.1101 . ----.----. = 100.000100 .J xor 100.011101 . ---.------ . =01100100. Remainder 10011011 inverted Remainder Transmitted Sequence: Command Data CRC 00000001 00000101 10011011 Final Data Sheet 35 V2.0, 2011-03 TLE5011 Specification Example2: Use of two TLE5011 units in a bus mode. Table 17 Update X,Y of two TLE5011 units, and read first TLE5011 SSC Byte no. Description Master transmitting TLE5011 transmitting 1 Command1) 0_0000_000 (update all TLE5011) - 2 Command2) 1_0001_110 (read first TLE5011) - 3 Data Byte 1 to 01H - XL 4 Data Byte 2 to 02H - XH 5 Data Byte 3 to 03H - YL 6 Data Byte 4 to 04H - YH 7 Data Byte 5 to 05H - FCNT_STAT 8 Data Byte 6 to 06H - FSYNC_INV 9 CRC - calc. CRC value 10 Slave-active - cccc_nnnn 3) 11 Command 1_0001_110 (read second TLE5011) - 12 Data Byte 1 to 01H - XL 13 Data Byte 2 to 02H - XH 14 Data Byte 3 to 03H - YL 15 Data Byte 4 to 04H - YH 16 Data Byte 5 to 05H - FCNT_STAT 17 Data Byte 6 to 06H - FSYNC_INV 18 CRC - calc. CRC value 19 Slave-active - cccc_nnnn 1) Both TLE5011 are selected (CS1=CS2=active) during this command Byte. 2) CS2 of the second TLE5011 slave is deactivated after the second command Byte. 3) CS1 of the first TLE5011 slave is deactivated after the third command Byte. Final Data Sheet 36 V2.0, 2011-03 TLE5011 Specification 3.10 Test Structures Two different test signal structures are implemented in the TLE5011: • • Functional Angle Test. In this case, well-known signals feed the ADCs. Temperature Measurement. This is useful to read out the chip temperature for compensation purposes. 3.10.1 Functional Angle Tests It is possible to feed the ADCs with appropriate values to simulate a certain magnet position and other GMR effects. The values are generated with resistors on the chip. The following X / Y ADC values can be programmed: • • • • 4 points, circle amplitude = 70.7% (0°, 90°, 180°, 270°) 8 points, circle amplitude = 100.0% (0°, 45°, 90°, 135°,180°, 225°, 270°, 315°) 8 points, circle amplitude = 122.1% (35.3°, 54.7°, 125.3°, 144.7°, 215.3°, 234.7°, 305.3°, 324.7°) 4 points, circle amplitude = 141.4% (45°, 135°, 225°, 315°) Note: The 100% values typically correspond to 21700 digits and a voltage of ~ 110 mV. Table 18 Functional Angle Test Register bits X / Y Values (decimal) min. typ. max. 000 -400 0 400 001 14800 15500 16200 010 20700 21700 22700 011 100 32767 1) -400 0 400 101 -16200 -15500 -14800 110 -22700 -21700 -20700 111 -32768 1) Not allowed to use. Final Data Sheet 37 V2.0, 2011-03 TLE5011 Specification ADC Test Vectors Y 122.1% 141.4% 100.0% 0% X 70.7% Figure 17 ADC Test Vectors 3.10.2 Temperature Measurement An internal bandgap voltage can be used to measure the temperature on the chip. This may be used to compensate for temperature-dependent errors. The temperature values is sent out instead of the X value. Table 19 Temperature Measurement Parameter Symbol Limit Values Unit min. typ. max. Value at -40°C T-40 - - +22000 digits Value at 25°C T25 +2550 +5775 +9000 digits Value at 150°C T150 -22000 - - digits Temperature Sensitivity ST - -188.75 - dig / K Notes 1) 1) Should be used for temperature compensation of offset errors Final Data Sheet 38 V2.0, 2011-03 TLE5011 Specification 3.10.3 Functional Angle Test and Temperature Measurement Timing The functional angle test and the temperature readout are based on the same mechanism. In the Normal Mode, the output path is linked to the functional angle test or to the temperature measurement unit until the mode is terminated. < tupd < tupd tupd tupd tupd tupd tupd tupd FSYNC (reset) 4 5 0 1 2 0 1 2 ADC&Filter Val_G4 Val_G5 Val_A0 Val_A1 Val_A2 Val_G0 Val_G1 Val_G2 X[16],Y[16] Buffer1 Val_G3 Val_G0 Val_G1 FCNT[4] Val_G4 Val_A0 Val_A1 ANGT_EN or TEMP_EN Update useful GMR_OFF Figure 18 No GMR signal available Measurement in Normal Mode In Automatic Mode, the signal is automatically switched back to GMR measurement after the read-out of one value. < tupd tupd tupd tupd FSYNC (reset) FCNT[4] tupd tupd tupd Updated FCNT=2 4 5 0 1 0 1 2 ADC&Filter Val_G4 Val_G5 Val_A0 Val_A1 Val_G0 Val_G1 Val_G2 X[16],Y[16] Buffer1 Val_G3 Val_A0 Val_A1 Val_G0 Val_G4 Val_G1 ANGT_EN or TEMP_EN automatic! Update GMR_OFF Figure 19 No GMR signal available Measurement in Automatic Mode Final Data Sheet 39 V2.0, 2011-03 TLE5011 Specification 3.11 Overvoltage Comparators Various comparators monitor the voltage in order to ensure error-free operation. The overvoltages must be active for at least tDEL to set the test comparator bits in the SSC interface registers. This works as digital spike suppression. Table 20 Test Comparators Parameter Symbol Limit Values Unit Notes min. typ. max. VOVG - 2.80 - V VOVA - 2.80 - V VOVD - 2.80 - V VDD Overvoltage VDDOV - 6.5 - V GND - off Voltage VGNDoff - 0.54 - V VGNDoff = VGND - VTST1 VDD - off Voltage VVDDoff - 0.48 - V VVDDoff = VCLK - VDD or VSCK - VDD Spike filter Delay tDEL - 10 - µs The error condition has to last longer than this value (min. 256 clocks of fDIG) Overvoltage Detection 3.11.1 Internal Supply Voltage Comparators Every voltage regulator has an overvoltage comparator to detect a malfunction. If the nominal output voltage of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated. It sets the VRx_OV bit. . VDDA - REF VDD VRG VRA VRD 10µs Spike Filter + GND Figure 20 OV Comparator 3.11.2 VDD Overvoltage Detection xxx_OV GND The Overvoltage Detection Comparator monitors the external supply voltage at the VDD pin. It activates the STAT_VR (see Figure 20). 3.11.3 GND-off Comparator The GND-off Comparator is used to detect a voltage difference between the GND pin and TST1 (which must be soldered to GND in the application). It activates the STAT_VR bit. This circuit can detect a disconnection of the Supply GND Pin. Final Data Sheet 40 V2.0, 2011-03 TLE5011 Specification . VDD VDDA VGNDoff - +dV TST1 GND 10µs Spike Filter + GND_OFF GND Figure 21 GND-off Comparator 3.11.4 VDD - off Comparator The VDD-off Comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLE5011 is supplied by the SCK, CLK and CS input pins via the ESD structures. It activates the STAT_VR bit. The retriggerable analog monoflop is necessary because of the non-static signal of the CLK and SCK signals. This comparator is also activated if spikes on CLK or SCK achieve the condition: (VCLK - VDD) > VVDDoff or (VSCK - VDD) > VVDDoff . VDDA - VDD 1µs Mono Flop VVDDoff CLK SCK -dV GND Figure 22 + 10µs Spike Filter VDD _OFF GND VDD - off Comparator Final Data Sheet 41 V2.0, 2011-03 TLE5011 Package Information 4 Package Information 4.1 Package Parameters Table 21 Package Parameters Parameter Symbol Thermal Resistance Limit Values Unit Notes min. typ. max. RthJA - 150 200 K/W Junction to air 1) RthJC - - 75 K/W Junction to case RthJL - - 85 K/W Junction to lead Soldering Moisture Level Lead frame MSL 3 260°C Cu Plating Sn 100% > 7 µm 1) According to Jedec JESD51-7 Package Outline PG-DSO-8 Figure 23 PG-DSO-8 Package Dimension Final Data Sheet 42 V2.0, 2011-03 TLE5011 Package Information Figure 24 Position of Sensing Element 1.31 Footprint PG-DSO-8 5.69 0.65 1.27 Figure 25 Footprint PG-DSO-8 Packing 0.3 5.2 12 ±0.3 8 1.75 6.4 2.1 Figure 26 Tape and Reel Final Data Sheet 43 V2.0, 2011-03 TLE5011 Package Information Marking Position Marking Description 1st Line 5011xx See ordering table on page 6 2nd Line xxx Lot code 3rd Line Gxxxx G .. green, 4-digit .. date code Processing Note: For processing recommendations, please refer to Infineon’s Notes on Processing Final Data Sheet 44 V2.0, 2011-03 www.infineon.com Published by Infineon Technologies AG