Product Overview MC100EL14: Clock Fanout Buffer, 1:5 ECL, 5.0 V For complete documentation, see the data sheet Product Description The MC100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The BB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The EL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. Features • • • • • • • • • • 50 ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input ESD Protection: > 2 KV HBM, > 200 V MM The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input Pulldown Resistors on CLK, SCLK, SEL, and ENbar. Q Output will Default LOW with Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For more features, see the data sheet Part Electrical Specifications Product Compliance Status Type Chann els Input / Input Output Level Ratio Output VCC Level Typ (V) tJitterR MS Typ (ps) tskew(oo) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClo fmaxDat Packa ck Typ a Typ ge (MHz) (Mbps) Type MC100EL14DWG Pb-free Active Buffer 1 2:1:5 ECL 1 50 0.68 500 1000 ECL 5 Halide free For more information please contact your local sales support at www.onsemi.com Created on: 6/30/2016 SOIC20W