Product Overview MC100EP809: Clock Driver, 2:1:9 Differential HSTL / PECL to HSTL, 3.3 V For complete documentation, see the data sheet Product Description The MC100EP809 is a low skew 2:1:9 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state. The MC100EP809 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration. To ensure that tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. Designers can take advantage of the EP809's performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single-end by biasing the non-driven pin in an input pair. Features • • • • • • • • • 100 ps Typical Device-to-Device Skew 15 ps Typical Within Device Skew HSTL Compatible Outputs Drive 50Ω to Ground with no Offset Voltage Maximum Frequency > 750 MHz 850 ps Typical Propagation Delay Fully Compatible with Micrel SY89809L PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V Open Input Default State Pb-Free Packages are Available Applications • Clock distribution Part Electrical Specifications Product Compliance Status Type Chann els Input / Input Output Level Ratio Output VCC Level Typ (V) tJitterR MS Typ (ps) tskew(oo) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClo fmaxDat Packa ck Typ a Typ ge (MHz) (Mbps) Type MC100EP809FAG Pb-free Active Buffer 1 2:1:9 HSTL 1.4 50 0.85 600 750 LQFP32 600 750 LQFP32 600 750 QFN32 600 750 QFN32 Halide free ECL 3.3 CML 0.82 HST L LVD S MC100EP809FAR2G Pb-free Active Buffer 1 2:1:9 Halide free HST L HSTL 3.3 1.4 50 0.82 0.85 CML LVD S ECL MC100EP809MNG Pb-free Active Buffer 1 2:1:9 Halide free CML HSTL 3.3 1.4 50 LVD S 0.85 0.82 HST L ECL MC100EP809MNR4G Pb-free Halide free Active Buffer 1 2:1:9 ECL HSTL 3.3 1.4 HST L CML LVD S For more information please contact your local sales support at www.onsemi.com Created on: 6/30/2016 50 0.82 0.85