DK-DEV-4SE530N Dev Kit Schematic

8
7
6
5
4
NOTES:
E
1. Project Drawing Numbers:
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic Drawing
PCB Film
Bill of Materials
Schematic Design Files
Functional Specification
PCB Layout Guidelines
Assembly Rework
3
2
REV
DATE
PAGES
B
C-1
7/24/09
5/26/2011
All
1,26
100-0310904-C1
110-0310904-C1
120-0310904-C1
130-0310904-C1
140-0310904-C1
150-0310904-C1
160-0310904-C1
170-0310904-C1
180-0310904-C1
210-0310904-C1
220-0310904-C1
320-0310904-C1
1
DESCRIPTION
Released Rev B
Change bias voltages V1,V2,V3,V4,V5 to positive voltages and remove -12V
regulator circuit. LCD changed from F-51852 series to F-55472 series.
E
Stratix IV E FPGA Development Kit Board
Block Diagram
2. 1093 Parts, 80 Library Parts, 1068 Nets, 6228 Pins
PAGE
D
C
B
A
DESCRIPTION
1
Title, Notes, Block Diagram, Revision History
2
S4E FPGA Package Top
3
Power 1
4
Power 2
5
Power 3
6
Power 4
7
Power 5
8
Power & Temp Sense
9
Stratix IV E Power
10
Stratix IV E Clocks
11
Clock Circuitry
12
Stratix IV E Configuration
13
Embedded USB Blaster
14
Stratix IV E Banks 1 & 2
15
Stratix IV E Banks 3 & 4
16
Stratix IV E Banks 5 & 6
17
Stratix IV E Banks 7 & 8
18
DDR3 SDRAM DIMM
19
QDRII+ SRAM
20
RLDRAM II CIO
21
RLDRAM II CIO & QDRII TERMINATIONS
22
SSRAM & FLASH
23
MAX II
24
10/100/1000 Ethernet
25
User IO & Connector
26
Speaker, LCD connectors
27
HSM Connectors
28
Decoupling 1
29
Decoupling 2
D
C
B
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-C1
Thursday, May 26, 2011
2
Rev
(6XX-41504R)
Sheet
1
of
1
29
C-1
8
7
6
Notes:
1.
E
5
4
3
2
1
Stratix IV E FPGA Package Top
FPGA Schematic Symbol Breakdown:
(A) Bank 1 - DISPLAY, USB, ETHERNET
(B) Bank 2 - RLDRAM II CIO
(C) Bank 3 - DDR3 SDRAM DIMM
(D) Bank 4 - DDR3 SDRAM DIMM, LCD, USER 7-SEGMENT DISPLAY
(E) Bank 5 - HSMC PORT A
(F) Bank 6 - HSMC PORT B
(G) Bank 7 - QDR II+ SRAM, USER PB
(H) Bank 8 - FLASH, SSRAM
( I ) Some Clocks
( J) Configuration
( K) VCC, VCCD_PLL, VCCA_PLL, VCCPT, VCCAUX
( L) VCCIO, VREF
(M) Ground and NCs
(N) Ground
BANKS 7A, 7B, 7C
BANKS 8A, 8B, 8C
VCCIO = 1.5V/1.8V
VCCIO = 2.5V
QDR II+ SRAM
USER PB
FLASH
SSRAM
MAX II
USER DIPSWITCH, PUSH BUTTONS
E
D
D
BANKS 6A, 6C
BANKS 1A 1C
VCCIO = 2.5V
VCCIO = 2.5V
HSMC PORT B
GRAPHIC DISPLAY
ETHERNET
C
C
BANKS 5A, 5C
BANKS 2A, 2C
VCCIO = 2.5V
VCCIO = 1.5V/1.8V
HSMC PORT A
RLDRAM II CIO
B
B
BANK 4B
BANKS 4A, 4C
BANKS 3A, 3B, 3C
VCCIO = 2.5V
VCCIO = 1.5V
VCCIO = 1.5V
LCD DISPLAY
DDR3 SDRAM DIMM
USER 7-SEGMENT DISPLAY
DDR3 SDRAM DIMM
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
2
of
1
29
B
8
7
6
5
FM540
E
DC_INPUT
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
B4
B5
B6
C1
C2
C3
C4
C5
C6
C23
C35
C36
150uF
10uF
10uF
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
D2
20V Zener
LTM4601
5 6
SW3
EG2201A
100K
2 3
3.3V
10.0K
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
3.3V_SENSE
D
R119
2.94K
A10
A7
E12
C232
RUN
INTVCC
DRVCC
A8
A9
A11
47nF PHASE90
C316 0.01uF
R174
787K
MPGM
MARG0
MARG1
G12
F12
PGOOD
VFB
PLLIN
TRACK/SS
COMP
A12
C12
D12
MPGM
R183
K12
L12
DIFFVOUT
VOUT_LCL
VOSNS+
FSET
VOSNS-
R181
FSET
DNI
MPGM
B
R12
787K
A12
C12
D12
PLLIN
TRACK/SS
COMP
MPGM
MARG0
MARG1
12V
R299
100, 1%
D21
Blue_Led
2.5V
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
C320
1000pF
R17
1.00k
100pF
PGOOD
VFB
DIFFVOUT
VOUT_LCL
VOSNS+
FSET
VOSNS-
RUN_SW 6,7
3.3V_PG 23
E
U9B
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
POWER LED
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
D
G12
F12
LTM_FB_2.5V
R16
K12
L12
J12
B12
M12
2.5V_B4B
U6A
U6D
A8
A9
A11
10uF
13.3K
C30
47nF PHASE270
C19
0.01uF
10uF
LTM4601
J12
B12
M12
2.5V
RUN
INTVCC
DRVCC
C69
1000pF
2.5V
C24
C57
100uF
RUN_SW
3.3V_PG
C70
C349
3.3V
C
A10
A7
E12
C56
100uF
C45
470uF
10V
Tantalum
3.3V_PG
LTM_FB_3.3V
LTM4601
RUN_SW
+
PHASE270 5,23
PHASE90 5,23
.009
100pF
U9D
RUN_SW
R31
LTM4601
R190
1.00k
C342
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
2.5V
R13
FSET
C34
1000pF
DNI
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
19.1K
U6B
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
R30
1
R122
PHASE270
PHASE90
1
A1
A2
A3
A4
A5
A6
B1
B2
B3
1
LT4601 SWITCHER
3.3V
U9A
+
C48
100uF
C54
100uF
2
RAPC712X
U9C
2
D31
2
1
3
1
2
3.3V_SENSE
J22
4
3
Power 1, (3.3V and 2.5V)
DC_INPUT
14V-20V DC INPUT
R300
4
C37
470uF
10V
Tantalum
C53
C46
10uF
10uF
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
.009
2.5V_B1_B8
R29
.009
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
C
LTM4601
LTM4601
B
C27
1000pF
LTM4601
DC_INPUT
U6C
A1
A2
A3
A4
A5
A6
B1
B2
B3
A
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
B4
B5
B6
C1
C2
C3
C4
C5
C6
C9
C16
C12
150uF
10uF
10uF
D1
20V Zener
Title
LTM4601
Size
B
Date:
8
7
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
3
of
1
29
B
8
7
6
5
4
3
2
Power 2, (5.0V, RLDRAM II, QDRII+, 2.5V_FPGA)
1
2.5V_FPGA_PG
VDDQ_QDRII_PG
2.5V_HSMC_PG
2.5V_FPGA_PG 23
VDDQ_QDRII_PG 23
2.5V_HSMC_PG 23
1.5V_1.8V_RLD
5.0V
U42
E
10
TPS51100DGQ
VIN
VLDOIN
VDDQSNS
C478
2.5V
2
1
1.5V_1.8V_RLD
2
10uF
0.75V/0.9V VTT (3A Sink/Src)
1uF
VIN
1
SHDN
VTT_RLD
7
9
10.0K
10.0K
6
S3
S5
VTTREF
C480 C470
VOUT
ADJ
GND
TAB_GND
R108
R110
10uF
10uF
10uF
1
C468 C469
10uF
10.0K
J18
10uF
10uF
E
.009
VDDQ_RLD
LT1764A
C181
C474 C473
4
5
3
6
2
10uF
1
41.2K
R111
2
40.2K
R294
C198 R107
4.7uF
.009
HDR2x1
4
8
11
VREF_RLD
3
5
VTT
VTTSNS
PGND
GND
GND
R251
R254
1.5V_1.8V_B2
U27
C477
C475
41.2K // 40.2K = 20.3K needed for 1.8V operation
41.2K needed for 1.5V operation (Default)
0.1uF
1.5V_1.8V_QDR
5.0V
U37
D
10
TPS51100DGQ
VIN
2
1
VLDOIN
VDDQSNS
C308
D
C307
2.5V
5.0V
U16
10uF
1uF
1
2
VTT_QDRII
VTTREF
C313 C359
C390 C416
10uF
10uF
10uF
R49
10uF
10uF
C327
6
100K
10uF
SHDN
C84
10uF
C94
1uF
1.5V_1.8V_QDR
1.5V_1.8V_QDR
10
9
OUT2
OUT1
SW
GND
GND
6
4
C393 C343
4
8
11
VREF_QDRII
VTT
VTTSNS
S3
S5
5
BST
R54
8
7
ADJ
PG
R51
VDDQ_QDRII_PG
R50
1.5V_1.8V_B7
.009
3.57K
VDDQ_QDRII
4.7K
C110
R47
.009
J11
LTC3026
3
11
7
9
10.0K
10.0K
PGND
GND
GND
R180
R175
3
5
IN1
IN2
1
0.1uF
2
1
1.30K
R48
2
4.30K
R40
10uF
HDR2x1
1.5V_DIMM
5.0V
U50
10
1.30K // 4.3K = 1.00Kneeded for 1.8V operation
1.30K needed for 1.5V operation (Default)
TPS51100DGQ
VIN
VLDOIN
VDDQSNS
C561
2
1
C562
10uF
0.9V VTT (3A Sink/Src)
1uF
3.3V
5.0V
VTT_DIMM
6
S3
S5
3
5
1
2
C233 C215
VTTREF
C557 C229
C228 C556
4
10uF
10uF
10uF
10uF
10uF
10uF
R248
4
8
11
VREF_DIMM
VTT
VTTSNS
C558
6
100K
IN1
IN2
2.5V_FPGA
SHDN
0.1uF
10uF
C464
1uF
2.5V_FPGA
10
9
OUT2
OUT1
SW
C449
5
BST
GND
GND
7
9
10.0K
10.0K
PGND
GND
GND
R320
R321
C
U41
3
11
C
2.5V_VCCPGM
R62
8
7
ADJ
PG
R229
2.5V_FPGA_PG
R241
.009
5.23K
2.5V_VCC_CLKIN
4.7K
R58
.009
R230
1.00k
LTC3026
2.5V_VCCPD
R52
B
.009
B
C450
12V
5.0V
3.3V
5.0V
U45
1
10uF
VIN
SHDN
VOUT
ADJ
GND
TAB_GND
4
5
3
6
R274
1
2
10.0K
4
R270
3.16K
LT1764A
C495
4.7uF
R101
6
100K
IN1
IN2
BST
OUT2
OUT1
SW
SHDN
GND
GND
2
C494
10uF
U26
C169
3
11
10uF
ADJ
PG
5
C164
1uF
2.5V_HSMC
2.5V_HSMC
10
9
8
7
2.5V_B5_B6
R106
R103
2.5V_HSMC_PG
R102
5.23K
4.7K
R105
1.00k
LTC3026
.009
C174
10uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
4
of
1
29
B
5
4
3
2
1
Power 3, (VCC)
PHASE0
PHASE90
PHASE180
PHASE270
VCC
R126
0
PHASE0 23
PHASE90 3,23
PHASE180 23
PHASE270 3,23
12V
VCCL
VCC_OUT
U32C
150uF
C265
C275
10uF
10uF
0.1uF
D32
20V Zener
LTM4601
12V
C266
U31C
C
A1
A2
A3
A4
A5
A6
B1
B2
B3
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
B4
B5
B6
C1
C2
C3
C4
C5
C6
0.1uF
D
U32A
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
C257
+
C254
100uF
0.1uF
C255
100uF
C263
470uF
10V
Tantalum
U31A
+
C258
470uF
10V
Tantalum
VCC_OUT
1
C274
C246
+
C259
100uF
0.1uF
C250
100uF
2
C271
0.003
1
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
2
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
1
D
R123
B4
B5
B6
C1
C2
C3
C4
C5
C6
2
A1
A2
A3
A4
A5
A6
B1
B2
B3
C262
470uF
10V
Tantalum
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
LTM4601
LTM4601
U32B
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
10.0K
R312
DNI
DNI
0
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
LTM4601
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
C
LTM4601
U49
1
3
2
R314 PHASE_PH
R307 PHASE_DIV
R308
20.0K
R309
10
V
PH
DIV
0.1uF
C555
DNI
Default Settings:
PH:tied high for 4 phases
DIV: tied to GND for /1
OUT1
OUT2
OUT3
OUT4
SET
MOD
GND
C550
4
5
6
7
PHASE0
PHASE90
PHASE180
PHASE270
9
8
PHASE_MOD
DNI
0
R311
R313
3.3V
INT_VCC_C
U31D
10K
R335
RUN_SW2
INT_VCC_D
LTC6902
A10
A7
E12
RUN
INTVCC
DRVCC
C570
PHASE180
TRACK_C
COMP_C
1000pF
XJ1
A8
A9
A11
PLLIN
TRACK/SS
COMP
VCC_OUT
C572
C264
220PF
U32D
RUN_SW2
INT_VCC_C
C571
47nF
C574 0.01uF
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
LTM4601
INT_VCC_C
B
U31B
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
PHASE0
TRACK_C
COMP_C
A10
A7
E12
A8
A9
A11
A12
C12
D12
C573
DNI
RUN
INTVCC
DRVCC
PGOOD
VFB
PLLIN
TRACK/SS
COMP
DIFFVOUT
VOUT_LCL
VOSNS+
FSET
VOSNS-
MPGM
MARG0
MARG1
G12
F12
LTMC_VFB
K12
L12
881545-2
60.4K
VOUT_LCL
12V
R128
DNI
J21
C567
C559
DNI
1000pF
5.0V
(1-2) 0.9V operation
(2-3) 1.1V operation
VCC
10uF
SHDN
ADJ
PG
C551
1uF
1.1V for Stratix III low power
10
9
8
7
R310
5.11K
R303
R304
4.7K
+
C544
LTC3026
2.87K
R302
VCC
DNI
10uF
C547
470uF
10V
Tantalum
DNI
R326
INT_VCC_D
C566
B
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
B
Date:
4
J12
B12
M12
100pF
DNI
Size
5
C564
DC_INPUT
1
6
5
2
C554
100K
OUT2
OUT1
SW
GND
GND
R305
BST
3
11
4
A
IN1
IN2
VOUT_LCL
For Stratix IV option: (Default)
1) DNI R310 (Disables U48) and populate R126.
2) Place jumper on pins 1 and 2 of J21 (Selects 0.9V for VCCL and VCC)
For Stratix III 1.1V option:
1) DNI R310 (Disables U48) and populate R126 (Ties VCCL and VCC to same regulator).
2) Place jumper on pins 2 and 3 of J21 (Selects 1.1V for VCCL and VCC).
For Stratix III Low power option:
1) DNI R126 and populate R310 (Enables U48) and provides 1.1V to VCC
2) Place jumper on pins 1 and 2 of J21 (Selects 0.9V for VCCL)
U48
1
2
K12
L12
LTM4601
LTM4601
1.8V
VOSNS+
FSET
VOSNS-
LTMC_VFB
TSW-103-08-G-S
36.0K
R336
MPGM
MARG0
MARG1
DIFFVOUT
VOUT_LCL
G12
F12
1
2
3
VCCL
R129
J12
B12
M12
DNI
A12
C12
D12
PGOOD
VFB
3
2
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
Rev
(6XX-41504R)
Sheet
1
5
of
29
B
5
4
3
2
1
Power 4, (1.5V_DIMM, 1.1V, VCCD_PLL, VCCPT, VCCAUX and 2.5V_A)
1.5V_DIMM
DC_INPUT
1.5V_DDR3
U30C
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
B4
B5
B6
C1
C2
C3
C4
C5
C6
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
C270
C273
150uF
C272
10uF
10uF
D33
20V Zener
LTM4601
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
LTM4601
A10
A7
E12
C569
C
47nF
MPGMB
R337
787K
RUN
INTVCC
DRVCC
A8
A9
A11
MAX_PHASE_CLK0
C568 0.01uF
PGOOD
VFB
PLLIN
TRACK/SS
COMP
A12
C12
D12
R295
DIFFVOUT
VOUT_LCL
VOSNS+
FSET
VOSNS-
MPGM
MARG0
MARG1
G12
F12
LTMB_FB
K12
L12
1.5V_DDR3
+
C563
C251
100uF
100pF
C260
100uF
LTMB_FB
J12
B12
M12
R325
FSETB
Regulator Sense Signals
2.5V_A_SENSE_P
2.5V_A_SENSE_N
VCCD_SENSE_P
2.5V_VCCAUX
VCCPT
2.5V
6
SHDN
C76
3
11
10uF
2
DNI THIS
RESISTOR FOR
STRATIX IV
4
R32
6
100K
10uF
R61
2.5V_A_SENSE_N
R44
R38
21K (1%)
4.7K
C
SHDN
C89
R43
4.02K
10uF
1uF
1.5V_VCCPT
10
9
OUT2
OUT1
SW
C81
R53
8
7
ADJ
PG
VCCPT
R42
R37
11K
4.7K
+
C88
R41
4.02K
LTC3026
10uF
2.5V_A_SENSE_P
C106
470uF
10V
Tantalum
0.003
DNI THIS
RESISTOR FOR
STRATIX III
BLM15AG221SN1
+
LTC3026
0.003
5
BST
C75
L3
8
7
IN1
IN2
2.5V_VCCAUX
10
9
ADJ
PG
8
1.5V_VCCPT
3
11
1uF
1
100K
C82
C108
470uF
10V
Tantalum
1
2
DNI
GND
GND
1
BLM15AG221SN1
2
R33
GND
GND
B
VCCD_SENSE_P
5.0V
U12
2.5V_A
OUT2
OUT1
SW
2.5V_A_SENSE_P 8
2.5V_A_SENSE_N 8
1000pF
U13
4
RUN_SW 3,7
C565
5.0V
5
MAX_PHASE_CLK0 23
100K
+
BST
LT4601 SWITCHER
DO NOT INSTALL BOTH R59 AND R53 AT THE SAME TIME!
R59
IN1
IN2
D
RUN_SW
L2
1
2
C261
470uF
10V
Tantalum
MAX_PHASE_CLK0
R323
40.2K
LTM4601
3.3V
.009
LTM4601
U30D
RUN_SW
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
1
D
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
2
A1
A2
A3
A4
A5
A6
B1
B2
B3
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
1
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
U30A
2
U30B
B
C107
470uF
10V
Tantalum
3.3V
5.0V
1.1V
U39
U14
6
100K
OUT2
OUT1
SW
SHDN
GND
GND
R34
BST
C77
A
3
11
10uF
ADJ
PG
LTC3026
C83
1uF
R216
VCCD_PLL
10
9
C429
VCCD_SENSE_P
R55
0.003
10uF
8
7
R46
R39
5.11K
4.7K
+
C87
R45
4.02K
100K
6
SW
SHDN
ADJ
PG
10
9
8
7
1.1V
R221
R215
10uF
LTC3026
R219
C109
470uF
10V
Tantalum
+
2.87K
10uF
C423
470uF
10V
Tantalum
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
For Stratix III use 2.87K
4
5.11K
4.7K
C437
R45 Value:
2.87K needed for 1.1V operation
4.02K needed for 0.9V operation
5
1uF
1
4
IN1
IN2
5
2
1
2
OUT2
OUT1
C417
1
4
VCCD_PLL
5
2
5.0V
BST
GND
GND
3.3V
IN1
IN2
3
11
1
2
Date:
3
2
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
Rev
(6XX-41504R)
Sheet
1
6
of
29
B
8
7
6
5
4
3
2
1
Power 5, (12V and 1.8V)
MAX_PHASE_CLK180
RUN_SW
1.8V_PG
MAX_PHASE_CLK180 23
RUN_SW 3,6
1.8V_PG 23
E
E
1.8V
DC_INPUT
2.5V
12V
U20
U33A
D
A8
RUN_SW
MAX_PHASE_CLK180
R322
1.5K
R324 0.1uF
1.00k
C560
A10
B9
F5
B8
F6
A6
A7
B7
C
L4
1
3.3uH
2
M4
M3
M2
M1
L4
L3
L2
L1
K4
K3
K2
K1
J4
J3
J2
J1
M9
M8
M7
L9
L8
L7
K9
K8
K7
J9
J8
B
U33B
PGOOD
RUN
VFB
STBYMD
PLLIN
FCB
INTVCC
SENSEPLLFLTR
EXTVCC
SS
SENSE+
SGND
COMP RSENSE
RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
SW1 RSENSE
RSENSE
SW2 RSENSE
SW2 RSENSE
SW2 RSENSE
SW2 RSENSE
SW2 RSENSE
SW2 RSENSE
SW2 RSENSE
SW2 RSENSE
SW2 RSENSE
SW2
SW2
B5
B6
R319
R136
7.15K
A9
100uF
A5
R137
D1
G1
4.7K
C267
A4
12V_SENSE
.009
M6
M5
L6
L5
K6
K5
J7
J6
J5
H12
H11
H10
H9
H8
H7
H6
H5
G12
G11
G10
G9
G8
G7
G6
G5
F12
F11
F10
C269
C268
10uF
10uF
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
A1
A2
A3
A11
A12
B1
B2
B3
B4
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
E1
E2
F1
F2
F3
F4
G1
G2
G3
G4
H1
H2
H3
H4
C496
C253
C252
10uF
10uF
E1
C249
0.01uF
100uF
C160
10uF
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
B1
C1
C3
C4
C5
C6
C7
D7
E6
E7
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B6
B7
B8
B9
B10
B11
C8
C9
C10
PGOOD
RUN/SS
COMP
FB
TRACK
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SW
SW
F1
1.8V_PG
G2
4.02K
R271
4.7K
R272
D
B3
B4
1.8V
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
D8
D9
D10
D11
E8
E9
E10
E11
F6
F7
F8
F9
F10
F11
G6
G7
G8
G9
G10
G11
C149
C119 C118 C117
100uF
22uF 22uF 22uF
C150
100uF
C
C11
E4
E5
F3
F4
F5
G3
G4
G5
LTM4604A
B
LTM4605
LTM4605
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
7
of
1
29
B
8
7
6
5
4
3
2
1
Power & Temp Monitor
5V_MONITOR1
5.0V
A/D #0
1.5V_1.8V_B7
U25
21
22
1.5V_1.8V_QDR
2.5V_B5_B6
23
24
2.5V_HSMC
1.5V_DDR3
25
26
1.5V_DIMM
2.5V_B4B
27
28
2.5V
1.5V_1.8V_B2
1
2
1.5V_1.8V_RLD
2.5V_VCCPD
3
4
2.5V_FPGA
D
C158
0.1uF
VCCL
5
6
VCC_OUT
VCCPT
7
8
2.5V_VCCAUX
10
CH0
CH1
VCC
REF+
CH2
CH3
REF-
CH4
CH5
F0
C166
10uF
R98
0
9
REF=5.0V
12
R90
DNI
19
SDO
SDI
SCK
CSn
CH8
CH9
U23
9
12
R78
DNI
SENSE5_ADC_F0 19
SENSE5_ADC_F0
17
20
18
16
17
20
18
SENSE5_CS1n 16
CH10
CH11
VCC
CH0
CH1
REF+
REF-
CH2
CH3
F0
CH4
CH5
CH6
CH7
SDO
SDI
SCK
CSn
CH8
CH9
CH10
CH11
R99
CH12
CH13
CH12
CH13
DNI
CH14
CH15
NC1
NC2
COM
GND
13
14
13
14
15
15
5.0V
2.5V
SENSE5_ADC_F0
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
12V
J12
2.5V
5.0V
TSENSE_FAN_CNTL
R259
10.0K
CH14
CH15
GND
COM
23
24
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
VCCD_SENSE_P
VCCD_SENSE_P
2.5V_A_SENSE_N
2.5V_A_SENSE_P
2.5V_VCCPGM
25
26
6
2.5V_A_SENSE_N 6
2.5V_A_SENSE_P 6
2.5V_FPGA
2.5V_VCC_CLKIN
27
28
2.5V_FPGA
2.5V_B1_B8
1
2
2.5V
3
4
D
5
6
2.5V
7
8
2.5V_DIV
3.3V_DIV
10.0K
10.0K
3.3V
R273
R269
10
R267
10.0K
23 SENSE_ADC_F0
23 SENSE_SDO
23 SENSE_SDI
23 SENSE_SCK
R275
10.0K
MAX3378
Q1
23
B1
OVERTEMP
FDV305N
3.3V
R261
22_23_2021
NC1
NC2
21
22
LTC2418
U44
14
13
12
11
10
9
8
High Side
VCCD_PLL
R74
0
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
SENSE5_CS0n
Low Side
E
C168
0.1uF
11
Fan Power Header
C
0
R84
0
CH6
CH7
C163
10uF
11
LTC2418
1
2
A/D #1
R82
R72
R80
R76
R70
Low Side
E
10K
10K
10K
10K
High Side
5V_MONITOR2
C
5.0V
2.5V
FAN
10K
R66
R65
R63
R64
U43
14
13
12
11
10
9
8
SENSE5_CS1n
SENSE5_CS0n
Temperature Sense
10K
10K
10K
10K
2.5V
3.3V
R260
10.0K
U18
6
10
TEMPDIODE_P 12
TEMPDIODE_N 12
B
3
4
OVERTn
ALERTn
SMBCLK
SMBDATA
3.3V
R60
15
1
200
C126
0.1uF
5
13
16
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
23 SENSE_CS1n
23 SENSE_CS0n
MAX3378
ADD1
ADD0
DXP
DXN
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
STBYn
VCC
GND1
GND2
GND3
9 23 OVERTEMPn
11 23 TSENSE_ALERTn
12V
5V_MONITOR1
14 23 TSENSE_SMB_CLK
12 23 TSENSE_SMB_DATA
2
7
8
U47
1
C509
4.7uF
ADDR = 01
3
VIN
VOUT
ADJ/BYPASS
SHDN
GND
5
4
2
LT1761
LT1761_CSENSE1 R284
= 5.37V
10.0K
R285
2.94K
B
C508
4.7uF
NC1
NC2
NC3
MAX1619
12V
R120
.009
5V_MONITOR2
U46
12V_SENSE
U21
1
2
8
C492
0.1uF
A
4
3
5
SENSE+
VIN
SHDN
ADR0
ADR1
ADIN
1
12V
SENSESCL
SDA
GND
EP_GND
10
C497
4.7uF
ADDR = 10
6
7
3
VIN
VOUT
ADJ/BYPASS
SHDN
GND
LT1761
5
4
2
LT1761_CSENSE2 R286
= 5.37V
10.0K
R278
2.94K
C510
4.7uF
9
11
Title
LTC4151
Size
B
Date:
8
7
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
8
of
1
29
B
8
7
6
5
4
3
2
1
Stratix IV E Power
U19K
Stratix IVE
Power
VCC
AB16
AB18
AB20
N15
N17
N19
R13
T22
U13
V22
W13
Y22
E
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCD_PLL
U26
V26
AF18
AF17
V9
U9
J17
J18
D
VCCD_PLL_L2
VCCD_PLL_L3
VCCD_PLL_B1
VCCD_PLL_B2
VCCD_PLL_R3
VCCD_PLL_R2
VCCD_PLL_T2
VCCD_PLL_T1
2.5V_A
U28
V28
AH18
AH17
V7
U7
G17
G18
2.5V_VCC_CLKIN
AG18
AE17
H17
K18
2.5V_VCCPGM
C
AD10
AD24
VCCA_PLL_L2
VCCA_PLL_L3
VCCA_PLL_B1
VCCA_PLL_B2
VCCA_PLL_R3
VCCA_PLL_R2
VCCA_PLL_T2
VCCA_PLL_T1
VCC_CLKIN3C
VCC_CLKIN4C
VCC_CLKIN7C
VCC_CLKIN8C
VCCPGM
VCCPGM
2.5V_VCCAUX
H8
J27
AG27
AG7
VCCPT
0
R258
2.5V_VCC_CLKIN
AJ17
F18
U29
V6
M25
AC10
DNI R258 for Stratix III
G6
B
D36
1N6263-W
VCCAUX_S3VCCPT
VCCAUX_S3VCCPT
VCCAUX_S3VCCPT
VCCAUX_S3VCCPT
VCCPT
VCCPT
VCCPT
VCCPT
VCCPT_S3NC
VCCPT_S3NC
VCCBAT
VCCL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPD1A
VCCPD1C
VCCPD2A
VCCPD2C
VCCPD3A
VCCPD3B
VCCPD3C
VCCPD4A
VCCPD4B
VCCPD4C
VCCPD5A
VCCPD5C
VCCPD6A
VCCPD6C
VCCPD7A
VCCPD7B
VCCPD7C
VCCPD8A
VCCPD8B
VCCPD8C
AA13
AA15
AA17
AA19
AA21
AB14
AB22
T14
T16
T18
T20
U15
U17
R21
R19
R17
R15
P22
P20
P18
P16
P14
N21
N13
U19
U21
V14
V16
V18
V20
W15
W17
W19
W21
Y14
Y16
Y18
Y20
U19L
B34
G32
H29
L26
N28
J26
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1A
VREF1A
M32
T31
U34
V30
P26
1.5V_1.8V_B2
VREF_RLD
AB28
AD25
AG28
AH32
AN34
AA26
AD32
W25
W29
W32
V27
1.5V_DDR3
VREF_DIMM
N23
R23
AA23
W23
AC23
AC21
AC19
AC13
AC15
AC17
AB12
Y12
P12
T12
M12
M14
M16
M22
M20
M18
AF25
AJ25
AL30
AM27
AG25
AF22
AM25
AG22
2.5V_VCCPD
AH21
AJ18
AM20
AH20
AF12
AH10
AL6
AM3
AG10
2.5V_B4B
AH13
AM10
AG13
AG16
AM13
AP17
AH16
2.5V_B5_B6
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VREF5A
VCCIO1C
VCCIO1C
VCCIO1C
VCCIO1C
VREF1C
VCCIO5C
VCCIO5C
VCCIO5C
VCCIO5C
VREF5C
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2A
VREF2A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VREF6A
VCCIO2C
VCCIO2C
VCCIO2C
VCCIO2C
VREF2C
VCCIO6C
VCCIO6C
VCCIO6C
VCCIO6C
VREF6C
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VREF3A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VREF7A
VCCIO3B
VCCIO3B
VREF3B
VCCIO7B
VCCIO7B
VREF7B
VCCIO3C
VCCIO3C
VCCIO3C
VREF3C
1.5V_DDR3
EP4SE530H1152
Version = 0.1 Preliminary
E
Stratix IVE
Power
2.5V_B1_B8
VCCIO7C
VCCIO7C
VCCIO7C
VREF7C
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VREF4A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VREF8A
VCCIO4B
VCCIO4B
VREF4B
VCCIO8B
VCCIO8B
VREF8B
VCCIO4C
VCCIO4C
VCCIO4C
VREF4C
VCCIO8C
VCCIO8C
VCCIO8C
VREF8C
AN1
AH3
AG6
AD9
AB7
AF7
U19M
AA11
AA14
AA16
AA18
AA2
AA20
AA22
AA5
AA8
AB13
AB15
AB17
AB19
AB21
AB23
AC14
AC16
AC18
AC20
AC24
AC27
AC30
AC33
AD11
AD14
AD17
AD2
AG2
AG17
AG14
AG11
AF9
AF33
AF30
AF27
AD20
V13
V15
V17
V19
V2
V21
V23
V5
V8
W14
W16
W18
W20
W22
Y13
M5
M8
W4
V1
U5
AC3
AA9
N7
L10
H7
G3
B1
P9
T6
T3
T10
L3
U8
1.5V_1.8V_B7
J10
F10
D5
C8
H10
VREF_QDRII
J13
C10
H13
G14
F17
C13
G15
2.5V_B1_B8
C32
D29
G25
J23
H25
C25
G22
H22
H19
C22
A18
G19
EP4SE530H1152
Version = 0.1 Preliminary
PLACE NEAR FPGA
VREF_DIMM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B24
B27
B3
B30
B33
B6
B9
C2
E12
E15
E18
E21
E24
E27
E30
E33
E6
E9
F2
F5
H12
H15
H18
H21
H24
H27
H30
H33
H9
J2
J5
J8
L12
L15
L18
L21
L24
L27
L30
L25
AH7
AK30
AL31
VREF_QDRII
C500
C511
C513
C512
C514
C373
C460
C459
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Stratix IVE
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
M21
N18
N20
N22
P13
P15
P17
P19
P21
P24
P27
P30
P33
R11
R14
R16
R18
R2
R20
R22
R5
R8
T13
T15
T17
T19
T21
U12
U14
U16
U20
U22
U23
U24
U27
U30
U33
V11
V12
D
C
D32
G7
K26
L11
EP4SE530H1152
Version = 0.1 Preliminary
B
TP7
TP6
TP5
TP4
TP8
TP2
TP1
TP3
0.1uF
1
POS
BT1
C461
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U19N
AD23
AD5
AD8
AG20
AG23
AG26
AG5
AG8
AJ30
AJ33
AK11
AK14
AK17
AK2
AK20
AK23
AK26
AK29
AK5
AK8
AM33
AN11
AN14
AN17
AN2
AN20
AN23
AN26
AN29
AN32
AN5
AN8
B12
B15
B18
B21
Y33
Y30
Y27
Y24
Y21
Y19
Y17
Y15
L33
M11
M15
M17
M19
M2
N16
N14
N12
EP4SE530H1152
Version = 0.1 Preliminary
VCCBAT
D35
1N6263-W
Stratix IVE
Power
VREF_RLD
A
A
Battery
2
NEG
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
C488
C493
0.1uF
0.1uF
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
9
of
1
29
B
8
7
6
5
4
Stratix IV E Clocks
CLKIN_100M_P
E
100, 1%
R235
CLKIN_100M_N
CLKIN_125M_P0
CLKIN_125M_P1
100, 1%
100, 1%
R262
R236
CLKIN_125M_N0
CLKIN_125M_N1
CLKIN_66M_P0
CLKIN_66M_P1
100, 1%
100, 1%
R265
R288
CLKIN_66M_N0
CLKIN_66M_N1
HSMA_CLK_IN_P1
HSMB_CLK_IN_P1
100, 1%
100, 1%
R266
R263
U19I
Stratix IVE Clocks
Bank 1A
PLL_L1_FB_CLKOUT0P/DIFFIO_TX_L1P
PLL_L1_CLKOUT0N/DIFFIO_TX_L1N
HSMA_CLK_IN_N1
HSMB_CLK_IN_N1
ENET_S_CLKP
ENET_S_CLKN
CLKIN_125M_P0
CLKIN_125M_N0
V31
V32
T33
T34
CLK0P/DIFFIO_RX_L28P
CLK0N/DIFFIO_RX_L28N
CLK1P
CLK1N
PLL_L2_FB_CLKOUT0P/DIFFIO_TX_L28P
PLL_L2_CLKOUT0N/DIFFIO_TX_L28N
PLL_L4_FB_CLKOUT0P/DIFFIO_TX_L56P
PLL_L4_CLKOUT0N/DIFFIO_TX_L56N
D
W33
W34
V33
V34
DDR3_DIMM_A4
DDR3_DIMM_A5
DDR3_DIMM_SDA
DDR3_DIMM_A8
AN18
AP18
AN19
AP19
CLKIN_66M_P1
CLKIN_66M_N1
CLKIN_SMA
DDR3_DIMM_A10
AN16
AP16
AN15
AP15
CLK2P/DIFFIO_RX_L29P
CLK2N/DIFFIO_RX_L29N
CLK3P
CLK3N
CLK6P/DIFFIO_RX_B33P
CLK6N/DIFFIO_RX_B33N
CLK7P/DIFFOUT_B66P
CLK7N/DIFFOUT_B66N
PLL_L3_FB_CLKOUT0P/DIFFIO_TX_L29P
PLL_L3_CLKOUT0N/DIFFIO_TX_L29N
PLL_B1_CLKOUT0P
PLL_B1_CLKOUT0N
PLL_B1_CLKOUT3
PLL_B1_CLKOUT4
PLL_B1_FBP/CLKOUT1/DIFFIO_RX_B31P
PLL_B1_FBN/CLKOUT2/DIFFIO_RX_B31N
Bank 4C
PLL_B2_CLKOUT0P
PLL_B2_CLKOUT0N
PLL_B2_CLKOUT3
PLL_B2_CLKOUT4
PLL_B2_FBP/CLKOUT1/DIFFIO_RX_B34P
PLL_B2_FBN/CLKOUT2/DIFFIO_RX_B34N
W2
W1
U4
U3
CLK8P
CLK8N
CLK9P/DIFFIO_RX_R28P
CLK9N/DIFFIO_RX_R28N
PLL_R3_FB_CLKOUT0P/DIFFIO_TX_R28P
PLL_R3_CLKOUT0N/DIFFIO_TX_R28N
PLL_R1_FB_CLKOUT0P/DIFFIO_TX_R56P
PLL_R1_CLKOUT0N/DIFFIO_TX_R56N
CLKIN_100M_P
CLKIN_100M_N
CLKIN_125M_P1
CLKIN_125M_N1
B
HSMB_CLK_IN0
USER_DIPSW1
HSMA_CLK_IN0
USER_DIPSW3
U2
U1
T2
T1
B17
A17
B16
A16
B19
A19
B20
A20
CLK10P
CLK10N
CLK11P/DIFFIO_RX_R29P
CLK11N/DIFFIO_RX_R29N
PLL_R2_FB_CLKOUT0P/DIFFIO_TX_R29P
PLL_R2_CLKOUT0N/DIFFIO_TX_R29N
HSMA_CLK_IN_N[2:1]
HSMA_CLK_OUT_P[2:1]
HSMA_CLK_OUT_N[2:1]
HSMA_TX_LED
HSMA_CLK_IN0
PLL_T2_CLKOUT0P
PLL_T2_CLKOUT0N
PLL_T2_CLKOUT3
PLL_T2_CLKOUT4
PLL_T2_FBP/CLKOUT1/DIFFIO_RX_T31P
PLL_T2_FBN/CLKOUT2/DIFFIO_RX_T31N
PLL_T1_CLKOUT0P
PLL_T1_CLKOUT0N
PLL_T1_CLKOUT3
PLL_T1_CLKOUT4
PLL_T1_FBP/CLKOUT1/DIFFIO_RX_T34P
PLL_T1_FBN/CLKOUT2/DIFFIO_RX_T34N
HSMA_TX_D_P[16:0] 16,27
HSMA_TX_D_N[16:0] 16,27
HSMA_CLK_IN_P[2:1]
27
HSMA_CLK_IN_N[2:1]
27
E
HSMA_CLK_OUT_P[2:1]
16,27
HSMA_CLK_OUT_N[2:1]
16,27
HSMA_TX_LED 25
HSMA_CLK_IN0 27
HSMC PORT B
HSMB_CLK_IN_P[2:1]
HSMB_CLK_IN_N[2:1]
HSMB_CLK_OUT_N[2:1]
W28
V29
HSMB_TX_D_P[16:0]
AD18
AE18
AD19
AE19
AJ19
AK19
DDR3_DIMM_CKE1
DDR3_DIMM_A14
DDR3_DIMM_A15
AE16
AF16
AD15
AD16
AL17
AM17
DDR3_DIMM_CSn1
DDR3_DIMM_A13
DDR3_DIMM_CSn2
DDR3_DIMM_CSn3
DDR3_DIMM_A0
DDR3_DIMM_A1
AH5
AH4
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMB_TX_D_N[16:0]
HSMB_SDA
HSMB_CLK_IN0
DDR3_DIMM_RESETn
DDR3_DIMM_A12
V10
W9
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
H6
H5
HSMB_CLK_OUT_P2
HSMB_CLK_OUT_N2
U11
U10
L17
K17
K16
L16
F16
E16
USER_DIPSW[7:0]
USER_PB[3:0]
27
HSMB_CLK_IN_N[2:1]
27
HSMB_CLK_OUT_P[2:1]
16,27
HSMB_CLK_OUT_N[2:1]
16,27
D
HSMB_TX_D_P[16:0] 16,27
HSMB_TX_D_N[16:0] 16,27
HSMB_SDA 27
HSMB_CLK_IN0 27
USER_DIPSW[7:0]
USER_PB[3:0]
17,25
25
ETHERNET INTERFACE
ENET_TX_D[7..0]
ENET_TX_P
ENET_TX_N
ENET_S_CLKP
ENET_S_CLKN
ENET_RX_D[7..0]
14,24
ENET_TX_D[7..0] 14,24
C
ENET_TX_P 24
ENET_TX_N 24
ENET_S_CLKP 24
ENET_S_CLKN 24
DDR3 DIMM INTERFACE
DDR3_DIMM_A[15:0]
CLKOUT_SMA
HSMB_SDA
DDR3_DIMM_CSn[3:0]
USER_PB0
USER_PB3
QDRII_RPSn
DDR3_DIMM_SDA
USER_PB1
USER_PB2
DDR3_DIMM_RESETn
QDRII_RPSn
K19
J19
L19
L20
D18
C18
HSMB_CLK_IN_P[2:1]
USER INTERFACE
DDR3_DIMM_CKE[1:0]
Bank 8C
CLK14P/DIFFIO_RX_T33P
CLK14N/DIFFIO_RX_T33N
CLK15P/DIFFOUT_T66P
CLK15N/DIFFOUT_T66N
RLDC_A19
RLDC_A11
HSMA_CLK_IN_P[2:1]
DDR3_DIMM_BA[2:0]
Bank 6C
Bank 7C
CLK12P/DIFFIO_RX_T32P
CLK12N/DIFFIO_RX_T32N
CLK13P/DIFFOUT_T63P
CLK13N/DIFFOUT_T63N
AG29
AG30
Bank 5C
Bank 6A
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
HSMB_CLK_IN_P2
HSMB_CLK_IN_N2
ENET_TX_P
ENET_TX_N
HSMA_TX_D_N[16:0]
ENET_RX_D[7..0]
PLL_R4_FB_CLKOUT0P/DIFFIO_TX_R1P
PLL_R4_CLKOUT0N/DIFFIO_TX_R1N
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
T29
T30
CLKIN_66M_P0 11
CLKIN_66M_N0 11
CLKIN_66M_P1 11
CLKIN_66M_N1 11
CLKIN_125M_P0 11
CLKIN_125M_N0 11
CLKIN_125M_P1 11
CLKIN_125M_N1 11
CLKIN_100M_P 11
CLKIN_100M_N 11
CLKIN_50 11,23
Bank 2C
Bank 5A
C
HSMA_TX_D_P[16:0]
CLKIN_66M_P0
CLKIN_66M_N0
CLKIN_66M_P1
CLKIN_66M_N1
CLKIN_125M_P0
CLKIN_125M_N0
CLKIN_125M_P1
CLKIN_125M_N1
CLKIN_100M_P
CLKIN_100M_N
CLKIN_50
1
HSMC PORT A
HSMB_CLK_OUT_P[2:1]
Bank 3C
CLK4P/DIFFIO_RX_B32P
CLK4N/DIFFIO_RX_B32N
CLK5P/DIFFOUT_B63P
CLK5N/DIFFOUT_B63N
HSMA_TX_LED
ENET_TX_D7
2
CLOCK INTERFACE
Bank 1C
Bank 2A
CLKIN_66M_P0
CLKIN_66M_N0
CLKIN_50
G30
G31
3
USER_DIPSW4
USER_DIPSW5
USER_DIPSW6
USER_DIPSW7
FSM_A25
USER_DIPSW2
DDR3_DIMM_A[15:0]
15,18
DDR3_DIMM_BA[2:0]
15,18
DDR3_DIMM_CSn[3:0]
15,18
DDR3_DIMM_CKE[1:0]
15,18
DDR3_DIMM_SDA
18
B
DDR3_DIMM_RESETn
QDRII_RPSn
18
19,21
QDRII SRAM INTERFACE
QDRII_A[21:0]
QDRII_A[21:0]
17,19,21
RLDRAM II INTERFACE
EP4SE530H1152
Version = 0.1 Preliminary
RLDC_A[22:0]
SMA Connector
RLDC_A[22:0]
14,20,21
(external clock source)
J17
1
A
FSM_A[26:0]
J16
1
CLKIN_SMA
FSM_A[26:0] 16,17,22,23
CLKOUT_SMA
A
R109
49.9
Title
5
4
3
2
5
4
3
2
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
10
of
1
29
B
8
7
6
5
4
3
2
1
General Clock Circuitry
CLOCK INTERFACE
CLK66_SEL
CLK50_EN
CLK66_EN
CLK100_EN
CLK125_EN
3.3V
Clock Enable
E
2.5V
C483
C479
2.2uF
0.1uF
3.3V
1.00k
1.00k
1.00k
1.00k
3.3V
From EPM2210 and DIP SW1
X3
4.7K
1
CLK66_EN
EN
VCC
R256
2
TDA04H0SB1
GND
3.3V
4
3
OUT
66.6MHz
R97
R75
4.7K
4.7K
U22
8
2
CLKIN_66
4
5
R83
1.00k
1.00k
From EPM2210 and DIP SW1
X5
4.7K
1
CLK50_EN
EN
VCC
2
GND
Q1p
Q1n
PCLKp
PCLKn
Q2p
Q2n
CLK_SEL
Q3p
Q3n
2.5V
C148
0.1uF
4
3
OUT
CLKIN_50
ECS-3525-500-B
C472
C476
2.2uF
0.1uF
To FPGA and
EPM2210
To Board Settings
DIP Switch
ICS8543
C155
0.1uF
100, 1%
100, 1%
3
CLK66_SEL
1 CLKIN_SMA_P
LTI-SASF546-P26-X1
J13
5
4
3
2
R253
CLKp
CLKn
6
7
CLKIN_SMA_CP
CLKIN_SMA_CN
2.5V
Q0p
Q0n
3.3V
R79
D
OE
CLK_EN
3.3V
R85
R91
84.5
84.5
C147
C145
C153
0.1uF
0.1uF
2.2uF
CLKIN_50
CLKIN_66M_P0
CLKIN_66M_N0
CLKIN_66M_P1
CLKIN_66M_N1
CLKIN_100M_P
CLKIN_100M_N
CLKIN_125M_P0
CLKIN_125M_N0
CLKIN_125M_P1
CLKIN_125M_N1
LVDS
VDD
VDD
R142
R143
R144
R145
CLK50_EN
CLK66_EN
CLK100_EN
CLK125_EN
GND
GND
GND
1
2
3
4
20
19
CLKIN_66M_P0
CLKIN_66M_N0
17
16
CLKIN_66M_P1
CLKIN_66M_N1
15
14
23,25
23
23
23
23
E
CLKIN_50 10,23
CLKIN_66M_P0 10
CLKIN_66M_N0 10
CLKIN_66M_P1 10
CLKIN_66M_N1 10
CLKIN_100M_P 10
CLKIN_100M_N 10
CLKIN_125M_P0 10
CLKIN_125M_N0 10
CLKIN_125M_P1 10
CLKIN_125M_N1 10
12
11
D
1
9
13
OPEN
8
7
6
5
10
18
SW1
CLK66_SEL
CLK50_EN
CLK66_EN
CLK100_EN
CLK125_EN
R93
R87
3.3V
1 CLKIN_SMA_N
LTI-SASF546-P26-X1
J14
CLKIN_SMA_CP
CLKIN_SMA_CN
124
124
5
4
3
2
LVPECL INPUT CLOCK
2.5V
From EPM2210 and DIP SW1
X2
1
4.7K CLK100_EN
EN
R35
C
2.5V
2
6
C72
C79
R86
R92
C159
C162
0.1uF
0.1uF
CLK66_SEL Settings:
OUT
NC
OUTn
VCC
GND
4
CLKIN_100M_P
Setting
SW2, DIP8
5
CLKIN_100M_N
High
PCLKp/n
Low
CLKp/n
3
C
100MHz
0.1uF 10uF
2.5V
U40
B
2.5V
From EPM2210 and DIP SW1
X4
R205
4.7K
CLK125_EN
1
2.5V
2
6
C369
C408
EN
OUT
NC
OUTn
VCC
GND
4
CK_125_P
5
CK_125_N
3
125.0MHz
0.1uF
10uF
5
13
14
15
16
11
12
9
10
VCC
VCC
VCC
VCC
VCC
D
VTD
VTD
D
Q0
Q0
Q1
Q1
NC
GND
GND
EP_GND
1
2
CLKIN_125M_P0
CLKIN_125M_N0
3
4
CLKIN_125M_P1
CLKIN_125M_N1
6
7
8
17
B
2.5V
C442
C441
C422
C439
C440
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
NB6L11SMNG
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
11
of
1
29
B
8
7
6
5
4
3
2
1
Stratix IV E Configuration
U19J
Stratix IVE Configuration
2.5V_VCCPGM
E
FPGA_DCLK
AL3
R276
R279
R318
10.0K
FPGA_STATUSn
10.0K
FPGA_CONFIGn
100, 1%FPGA_CONF_DONE
AH28
AE25
AH29
R264
10.0K
SYS_RESETn
FPGA_INIT_DONE
U31
T26
FPGA_DATA0
FPGA_DATA1
FPGA_DATA2
FPGA_DATA3
FPGA_DATA4
FPGA_DATA5
FPGA_DATA6
FPGA_DATA7
T28
T27
R34
R33
T25
T24
T32
R31
U25
U32
R30
D
DCLK
10.0K
AE26
FPGA_CEn
JTAG_TCK
TCK
TMS
TDO
TDI
TRST
nSTATUS
nCONFIG
CONF_DONE
DEV_CLRn/DQ17L/DIFFIO_RX_L27P
INIT_DONE/DQ17L/DIFFIO_TX_L27N
Bank 1C
ASDO
DATA0/DQ16L/DIFFIO_TX_L25N
DATA1/DQ16L/DIFFIO_TX_L25P
DATA2/DQSN16L/DIFFIO_RX_L25N
DATA3/DQ20R/DIFFIO_RX_R33N
DATA4/DQ16L/DIFFIO_TX_L26N
DATA5/DQ16L/DIFFIO_TX_L26P
DATA6/DQSN17L/DIFFIO_RX_L26N
DATA7/DQS17L/DIFFIO_RX_L26P
TEMPDIODEP
TEMPDIODEN
F30
H28
G29
G28
J28
MSEL0
MSEL1
MSEL2
CRC_ERR/DQ17L/DIFFIO_TX_L27P
DEV_OE/DQ17L/DIFFIO_RX_L27N
PORSEL
nCSO
nIO_PULLUP
K10
J9
K9
MSEL0
MSEL1
MSEL2
10.0K
10.0K
DNU
nCE
nCEO
2.5V
J4
1
C
2
USB_DISABLEn
R158
1.00k
2
R2
JTAG_EPM2210_TDO
HSMA_JTAG_TDO
HSMB_JTAG_TDO
R171
100, 1%
C314
JTAG Chain Control
XJ4
0.1uF
2.5V
2
881545-2
1EPM2210_JTAG_EN R36
JTAG_BLASTER_TDO
R160
10.0K
1.00k
2
U35
JTAG_EPM2210_TDO
2
JTAG_FPGA_TDO
3
HSMA_JTAG_TDI
7
HSMA_JTAG_TDO
13
TEMPDIODE_P 8
TEMPDIODE_N 8
1
5
D
2.5V
EPM2210_JTAG_EN
R157
1.00k
4
C
10
HSMA_JTAG_EN
8
9
2.5V
JTAG REFERENCE
USB_DISABLEn
TEMPDIODE_P
TEMPDIODE_N
70247-1051
HDR2x1
JTAG_EPM2210_TDO 23
HSMA_JTAG_TDO 27
HSMB_JTAG_TDO 27
USB_DISABLEn
J10
1
10.0K
HSMA_JTAG_TDI 27
HSMB_JTAG_TDI 27
JTAG_BLASTER_TDI 13
2.5V
AJ5
R159
E
JTAG_TCK 13,23,27
JTAG_TMS 13,23,27
JTAG_FPGA_TDO 23
JTAG_BLASTER_TDO 13
HSMA_JTAG_TDI
HSMB_JTAG_TDI
JTAG_BLASTER_TDI
XJ2
U18
JTAG_TCK
JTAG_BLASTER_TDI
JTAG_TMS
FPGA_DCLK 23
FPGA_CONF_DONE 23,25
FPGA_STATUSn 13,23
FPGA_CONFIGn 23
SYS_RESETn 23,25
FPGA_CEn 13
JTAG_TCK
JTAG_TMS
JTAG_FPGA_TDO
JTAG_BLASTER_TDO
10.0K
HDR2x1
1
3
5
7
9
23
JTAG
881545-2
J24
2
4
6
8
10
MSEL0
AF26
AE9
AF8
2.5V
1
1
2
R252
R255
CON2
USB Blaster Programming Header
(uses JTAG mode only)
881545-2
DNI
DNI
FPGA_DATA[7:0]
FPGA_DCLK
FPGA_CONF_DONE
FPGA_STATUSn
FPGA_CONFIGn
SYS_RESETn
FPGA_CEn
Fast Passive Parallel: MSEL[2:0]=000
Passive Serial:
MSEL[2:0]=010
FPP w/design security: MSEL[2:0]=001
MSEL pins have internal 5kOhm pull-downs.
CLKUSR/DQ18R/DIFFIO_RX_R30N
USB_DISABLEn
DNI
2.5V_VCCPGM
EP4SE530H1152
Version = 0.1 Preliminary
XJ3
R239
R240
C256
1.00K
2.5V_B4B
TEMPDIODE_P
TEMPDIODE_N
DNI
2.5V_VCCPD
AH6
E5
D4
R132
FPGA_DATA[7:0]
JTAG_TCK
JTAG_TMS
JTAG_FPGA_TDO
JTAG_BLASTER_TDO
JTAG_TRST
R257
J2
other DQ11 pins are in bank 1 section
R268
CONFIGURATION INTERFACE
Place at end of chain
XJ5
HSMB_JTAG_TDI
J15
1
2
881545-2
1
HSMA_JTAG_EN R104
1.00k
6
NLAS4717EPMTR2G
2
NLAS4717 Switch Functions
HDR2x1
When Pins 4 & 8 are:
LOW --> Pins 5 & 7 = ON and Pins 2 & 10 = OFF
2.5V
HIGH --> Pins 2 &10 = ON and Pins 5 & 7 = OFF
R172
100, 1%
C315
0.1uF
B
B
2.5V
XJ6
1
881545-2
FPGA Not Installed Jumper
J5
1
HSMB_JTAG_EN R11
1.00k
U36
1
J3
2
5
HDR2x1
2
2
HSMB_JTAG_EN
1
HSMB_JTAG_TDO
2
4
1
JTAG_FPGA_TDO
2
JTAG_BLASTER_TDO
DNI
3
Logic 0 = pin 5 --> pin 3 (EPM2210 Enabled)
Logic 1 = pin 2 --> pin 3 (EPM2210 Bypass)
JTAG_BLASTER_TDI
7
10
8
9
A
6
NLAS4717EPMTR2G
Title
Size
B
Date:
8
7
6
5
4
3
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
12
of
1
29
B
8
7
6
5
4
3
2
Embedded USB Blaster
1
3.3V_MAX
USB INTERFACE
5V_USB
U8A
L1
5V_USB
5V_USB
USB
J6
USB CON
3.3V_MAX
R182
470
C26
10uF
1
2
3
4
6
C352
0.1uF
R187
1.5K
5
SN65220DBV
USB_XTAL1
USB_XTAL2
5V_USB
R185
18pF
USB_RESETn
USB_EECS
USB_EESK
EEDATA
USB_XTAL1
2
C32
10.0K
32
1
2
RSTOUT#
XTIN
XTOUT
EECS
EESK
EEDATA
TEST
USB_XTAL2
D0
D1
D2
D3
D4
D5
D6
D7
RD#
WR
RESET#
TXE#
RXF#
SI/WU
PWREN#
25
24
23
22
21
20
19
18
USB_D0
USB_D1
USB_D2
USB_D3
USB_D4
USB_D5
USB_D6
USB_D7
16
15
USB_RDn
USB_WR
14
12
USB_TXEn
USB_RXFn
CLKIN_24MHZ
K8
L8
USB_RESETn
R188
1.00k
C39
10uF
10V
Tantalum
C15
0.1uF
C328
0.1uF
VCC
NC1
NC2
GND
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
IOB1/CLK0
IOB1/CLK1
IOB1/DEV_CLRn
IOB1/DEV_OE
11
10
USB_SI_WU
USB_PWR_ENn
R6
D6
Green_LED
USB_DISABLEn
FPGA_STATUSn
FPGA_CEn
12
FPGA_STATUSn 12,23
FPGA_CEn 12
USB_LED
JTAG_BLASTER_TDO
FPGA_CEn
FPGA_STATUSn
L7
L9
JTAG_TCK
K1
J2
K2
J1
USB_MAX_TCK
USB_MAX_TDI
USB_MAX_TDO
USB_MAX_TMS
D
3.3V_MAX
8
7
6
5
U8B
USB_TXEn
USB_D1
USB_D0
USB_WR
USB_RDn
USB_D7
USB_D6
USB_D5
A1
A10
A11
A2
A3
A4
A5
A6
USB_D4
USB_D3
USB_D2
A7
A8
A9
B10
B11
B2
B3
B4
8
7
6
5
MAX II
BANK2
F10
G11
10.0K
B
C379
IOB2_35
IOB2_36
IOB2_37
IOB2_38
IOB2_39
IOB2_40
IOB2_41
IOB2_42
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
IOB2_58
IOB2_43
IOB2_44
IOB2_45
IOB2_46
IOB2_47
IOB2_48
IOB2_49
IOB2_50
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_66
IOB2/CLK2
IOB2/CLK3
IOB2_67
IOB2_68
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
IOB2_74
( Optional )
USB_EEDATA
L1
L10
L11
L2
L3
L4
L5
L6
E
USB_DISABLEn
U38
AT93C46DN-SH-B
R168
2.2K
TCK
TDI
TDO
TMS
J7
K10
K3
K4
K5
K6
K7
K9
JTAG_TCK 12,23,27
JTAG_TMS 12,23,27
JTAG_BLASTER_TDI 12
JTAG_BLASTER_TDO 12
5V_USB
FT245BL
CS
SK
DIN
DOUT
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
R24
56.2
EPM240M100, Pre-programmed
U4
1
2
3
4
1
2
+
F2
E1
3.3V_MAX
5V_USB
DECOUPLING CAPS
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
IOB1_33
IOB1_34
C
5V_USB
F3
G1
G2
H1
H2
H3
J5
J6
USB_EECS
USB_EESK
EEDATA
USB_SI_WU
USB_DISABLEn
USB_PWR_ENn
13
3
26
VCC1
VCC2
USBDM
USBDP
9
17
1
18pF
4
31
Y1
6.000MHz
C31
27
28
3V3OUT
VCC-IO
8
7
27
27
AGND
D
NC1
A
NC2
B
GNDGND
R14
R15
29
6
U5
6
4
5
30
U7
AVCC
5
C329
0.1uF
C353
33nF
1
3
2
B1
C1
C2
D1
D2
D3
E2
F1
USB_RXFn
BLM21PG331SN1
GND1
GND2
E
MAX II
BANK1
B5
B6
B7
B8
B9
C10
C11
C5
1uF
1
2
3
4
9
IN
OUT
NC7 SENSE
NC6
NC3
SHDNn GND
EPAD
C388
R196
5.11K
1uF
C395
0.01uF
LT3010
R197
3.16K
C
C6
C7
D10
D11
D9
E10
E11
F11
U8C
D5
D7
E4
E8
G4
G8
H5
H7
F9
G10
H10
H11
H9
J10
J11 JTAG_TMS
K11 JTAG_BLASTER_TDI
3.3V_MAX
MAX II
Power
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCINT
VCCINT
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
E9
G3
E3
J4
J8
C4
C8
G9
B
EPM240M100, Pre-programmed
EPM240M100, Pre-programmed
3.3V_MAX
3.3V_MAX
3.3V_MAX
Install J27 only for prototype
3.3V_MAX
PLACE NEAR MAX II
J26
R28
1.00k
R22
3.3V_MAX
R21
1.00K USB_MAX_TCK
USB_MAX_TDO
1.00K USB_MAX_TMS
Y3
1
C59
0.01uF
A
2
EN
VCC
GND
OUT
24MHz
4
3
USB_MAX_TDI
CLKIN_24MHZ
C49
0.01uF
1
3
5
7
9
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
0
R23
0
C341
C354
C340
C345
C331
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
R20
2x5
C51
4.7uF
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
13
of
1
29
B
8
7
6
5
4
3
2
Stratix IV E Banks 1 & 2
RLDRAM II INTERFACE
RLDC_DQ[35:0]
D
Stratix IVE Bank 1
SEVEN_SEG_SEL3
LCD1_DATA2
MAX_OEn
MAX_WEn
ENET_RX_D0
LCD1_CSn
LCD1_E_RDn
LCD1_DATA1
J29
J30
K27
K28
M24
N25
H31
H32
ENET_TX_D5
ENET_RX_D4
LCD1_DATA0
ENET_INTn
C33
C34
F31
F32
SEVEN_SEG_SEL1
SEVEN_SEG_F
SEVEN_SEG_G
SEVEN_SEG_MINUS
ENET_TX_D3
SEVEN_SEG_DP
SEVEN_SEG_A
LCD1_DATA3
M26
M27
K29
K30
L28
L29
F33
E34
ENET_RX_P
ENET_RX_N
ENET_RX_COL
ENET_RX_D7
D33
D34
J31
J32
RUP1A
RDN1A
E31
E32
MAX_CSn
SEVEN_SEG_B
ENET_TX_D0
ENET_RX_D5
EEPROM_DIN
SEVEN_SEG_D
LCD1_WEn
ENET_RX_DV
N29
N30
P28
P29
R25
R26
N31
P32
ENET_RESETn
ENET_LED_LINK1000
ENET_GTX_CLK
ENET_TX_EN
M31
N32
M33
L34
DQ1L/DIFFIO_TX_L2P
DQ1L/DIFFIO_TX_L2N
DQ1L/DIFFIO_TX_L3P
DQ1L/DIFFIO_TX_L3N
DQ2L/DIFFIO_TX_L4P
DQ2L/DIFFIO_TX_L4N
DQ2L/DIFFIO_RX_L4P
DQ2L/DIFFIO_RX_L4N
Bank 1A
DQS2L/DIFFIO_RX_L3P
DQSN2L/DIFFIO_RX_L3N
DQS1L/DIFFIO_RX_L2P
DQSN1L/DIFFIO_RX_L2N
DQ5L/DIFFIO_TX_L8P
DQ5L/DIFFIO_TX_L8N
DQ5L/DIFFIO_TX_L9P
DQ5L/DIFFIO_TX_L9N
DQ6L/DIFFIO_TX_L10P
DQ6L/DIFFIO_TX_L10N
DQ6L/DIFFIO_RX_L10P
DQ6L/DIFFIO_RX_L10N
DQS5L/DIFFIO_RX_L8P
DQSN5L/DIFFIO_RX_L8N
DQS6L/DIFFIO_RX_L9P
DQSN6L/DIFFIO_RX_L9N
DQ3L/DIFFIO_TX_L5P
DQ3L/DIFFIO_TX_L5N
DQ3L/DIFFIO_TX_L6P
DQ3L/DIFFIO_TX_L6N
DQ4L/DIFFIO_TX_L7P
DQ4L/DIFFIO_TX_L7N
DQ4L/DIFFIO_RX_L7P
DQ4L/DIFFIO_RX_L7N
DQ7L/DIFFIO_TX_L11P
DQ7L/DIFFIO_TX_L11N
DQ7L/DIFFIO_TX_L12P
DQ7L/DIFFIO_TX_L12N
DQS7L/DIFFIO_RX_L11P
DQSN7L/DIFFIO_RX_L11N
DQS3L/DIFFIO_RX_L5P
DQSN3L/DIFFIO_RX_L5N
DQS4L/DIFFIO_RX_L6P
DQSN4L/DIFFIO_RX_L6N
DIFFIO_RX_L12P
DIFFIO_RX_L12N
N27
M28
P25
N26
L31
L32
H34
G34
ENET_MDIO
HSMB_SCL
LCD1_DATA6
LCD1_D_Cn
SEVEN_SEG_E
SEVEN_SEG_C
ENET_RX_D6
EEPROM_CS
RLDC_BA1
RLDC_CSn
RLDC_A20
RLDC_A7
RLDC_A16
RLDC_REFn
RLDC_A14
RLDC_A15
AC28
AC29
AA24
AA25
AD30
AD31
AH33
AG34
G33
F34
K31
K32
ENET_TX_D4
ENET_TX_D1
ENET_RX_ER
ENET_RX_CLK
RLDC_A17
RLDC_WEn
RLDC_CK_P
RLDC_CK_N
AE31
AE32
AF31
AF32
P23
N24
M29
M30
HSMB_RX_LED
LCD1_BS1
ENET_TX_ER
LCD1_DATA7
RLDC_A5
RLDC_A9
RLDC_A3
RLDC_A2
RLDC_DQ20
RLDC_DQ21
RLDC_DQ24
RLDC_DQ25
AB26
AB27
AB24
AB25
AE29
AE30
AG31
AG32
RLDC_A12
RLDC_DK_P1
RLDC_DK_N1
AJ34
AH34
AK33
AK34
J33
J34
K33
K34
LCD1_DATA4
ENET_RX_D2
ENET_RX_CRS
ENET_MDC
RUP1A/DIFFIO_RX_L1P
RDN1A/DIFFIO_RX_L1N
RUP2A
RDN2A
AK31
AK32
RLDC_A6
RLDC_A1
RLDC_A0
AA33
Y34
W26
W27
W30
W31
V24
V25
RLDC_BA2
RLDC_A8
Y31
Y32
AB33
AA34
DQ28L/DIFFIO_TX_L46P
DQ28L/DIFFIO_TX_L46N
DQ28L/DIFFIO_TX_L45P
DQ28L/DIFFIO_TX_L45N
DQ29L/DIFFIO_TX_L47P
DQ29L/DIFFIO_TX_L47N
DQ29L/DIFFIO_RX_L47P
DQ29L/DIFFIO_RX_L47N
DQS28L/DIFFIO_RX_L46P
DQSN28L/DIFFIO_RX_L46N
DQS29L/DIFFIO_RX_L48P
DQSN29L/DIFFIO_RX_L48N
DQ12L/DIFFIO_TX_L19P
DQ12L/DIFFIO_TX_L19N
DQ12L/DIFFIO_TX_L20P
DQ12L/DIFFIO_TX_L20N
DQ13L/DIFFIO_TX_L21P
DQ13L/DIFFIO_TX_L21N
DQ13L/DIFFIO_RX_L21P
DQ13L/DIFFIO_RX_L21N
Bank 1C
DQ34L/DIFFIO_TX_L55P
DQ34L/DIFFIO_TX_L55N
DQ34L/DIFFIO_TX_L54P
DQ34L/DIFFIO_TX_L54N
DQS34L/DIFFIO_RX_L55P
DQSN34L/DIFFIO_RX_L55N
AD28
AD29
AF28
AF29
AE27
AE28
AM34
AL34
RLDC_DQ18
RLDC_DQ19
RLDC_DQ22
RLDC_DQ23
RLDC_DQ30
RLDC_DQ31
RLDC_DQ34
RLDC_DQ33
DQ14L/DIFFIO_TX_L22P
DQ14L/DIFFIO_TX_L22N
DQ14L/DIFFIO_TX_L23P
DQ14L/DIFFIO_TX_L23N
DQ15L/DIFFIO_RX_L24P
DQ15L/DIFFIO_RX_L24N
DQ15L/DIFFIO_TX_L24P
EEPROM_DOUT
LCD1_DATA5
SEVEN_SEG_SEL4
SEVEN_SEG_SEL2
ENET_RX_D1
ENET_TX_D2
LCD1_SERn
DQS14L/DIFFIO_RX_L22P
DQSN14L/DIFFIO_RX_L22N
DQS15L/DIFFIO_RX_L23P
DQSN15L/DIFFIO_RX_L23N
N33
M34
P31
R32
ENET_TX_D6
ENET_RX_D3
EEPROM_CLK
ENET_TX_CLK
EP4SE530H1152
Version = 0.1 Preliminary
B
AJ31
AJ32
AH30
AH31
RLDC_QK_P1
RLDC_QK_N1
RLDC_A10
RLDC_DM
AC25
AC26
AD26
AD27
RLDC_DQ26
RLDC_DQ27
RLDC_DQ28
RLDC_DQ29
AL32
AL33
RLDC_DQ35
RLDC_DQ32
RLDC_CK_P
RLDC_CK_N
RLDC_WEn
RLDC_REFn
RLDC_CSn
RLDC_DM
RLDC_QVLD
DIFFIO_RX_L45P
DIFFIO_RX_L45N
HSMB_SCL
HSMB_RX_LED
RLDC_A4
RLDC_A22
RLDC_A21
RLDC_DQ10
RLDC_DQ11
RLDC_DQ14
RLDC_DQ15
AA31
AA32
Y28
Y29
RLDC_DK_P0
RLDC_DK_N0
AC34
AB34
Bank 2C
DQS18L/DIFFIO_RX_L31P
DQSN18L/DIFFIO_RX_L31N
DQS19L/DIFFIO_RX_L32P
DQSN19L/DIFFIO_RX_L32N
DQ21L/DIFFIO_TX_L35P
DQ21L/DIFFIO_TX_L35N
DQ21L/DIFFIO_TX_L34P
DQ21L/DIFFIO_TX_L34N
DQ22L/DIFFIO_RX_L36P
DQ22L/DIFFIO_RX_L36N
DQ22L/DIFFIO_TX_L36P
DQ22L/DIFFIO_TX_L36N
DQS21L/DIFFIO_RX_L35P
DQSN21L/DIFFIO_RX_L35N
DQS22L/DIFFIO_RX_L37P
DQSN22L/DIFFIO_RX_L37N
DQ20L/DIFFIO_RX_L33P
DQ20L/DIFFIO_RX_L33N
DQ20L/DIFFIO_TX_L33P
DQ20L/DIFFIO_TX_L33N
DQ23L/DIFFIO_TX_L37P
DQ23L/DIFFIO_TX_L37N
DQ23L/DIFFIO_TX_L38P
DQ23L/DIFFIO_TX_L38N
DQS20L/DIFFIO_RX_L34P
DQSN20L/DIFFIO_RX_L34N
DQS23L/DIFFIO_RX_L38P
DQSN23L/DIFFIO_RX_L38N
AG33
AF34
RLDC_A13
RLDC_A18
AA29
AA30
Y23
W24
AD33
AD34
Y25
Y26
RLDC_DQ0
RLDC_DQ1
RLDC_DQ13
RLDC_DQ12
RLDC_DQ4
RLDC_DQ5
RLDC_DQ7
RLDC_DQ8
AB31
AB32
AC31
AC32
RLDC_QK_P0
RLDC_QK_N0
RLDC_BA0
RLDC_QVLD
ENET_GTX_CLK
ENET_TX_CLK
ENET_TX_ER
ENET_TX_EN
ENET_MDIO
ENET_RESETn
ENET_INTn
ENET_RX_P
ENET_RX_N
ENET_RX_ER
ENET_RX_CLK
ENET_LED_LINK1000
ENET_RX_COL
ENET_RX_DV
ENET_RX_CRS
ENET_MDC
49.9
49.9
RUP1A
RDN1A
EEPROM_DOUT
EEPROM_CS
EEPROM_CLK
EEPROM_DIN
49.9
49.9
RUP2A
RDN2A
RLDC_DK_N[1:0]
20
RLDC_QK_P[1:0]
20
RLDC_QK_N[1:0]
20
RLDC_CK_P 20
RLDC_CK_N 20
RLDC_WEn 20,21
RLDC_REFn 20,21
RLDC_CSn 20,21
RLDC_DM 20
RLDC_QVLD 20
D
HSMB_SCL 27
HSMB_RX_LED 25
LCD1_DATA[7:0]
AA27
AA28
AB29
AB30
RLDC_DQ16
RLDC_DQ17
RLDC_DQ2
RLDC_DQ3
AE33
AE34
RLDC_DQ9
RLDC_DQ6
ENET_RX_D[7..0]
24
ENET_TX_D[7..0] 10,24
ENET_GTX_CLK 24
ENET_TX_CLK 24
ENET_TX_ER 24
ENET_TX_EN 24
ENET_MDIO 24
ENET_RESETn 24
ENET_INTn 24
ENET_RX_P 24
ENET_RX_N 24
ENET_RX_ER 24
ENET_RX_CLK 24
ENET_LED_LINK1000 24
ENET_RX_COL 24
ENET_RX_DV 24
ENET_RX_CRS 24
ENET_MDC 24
C
128x64 LCD DISPLAY INTERFACE
LCD1_CSn
LCD1_SERn
LCD1_D_Cn
LCD1_WEn
LCD1_E_RDn
LCD1_BS1
LCD1_DATA[7:0]
26
LCD1_CSn 26
LCD1_SERn 26
LCD1_D_Cn 26
LCD1_WEn 26
LCD1_E_RDn 26
LCD1_BS1 26
B
SEVEN-SEG INTERFACE
SEVEN_SEG_SEL[4:1]
MAX_CSn
MAX_OEn
MAX_WEn
20
ETHERNET INTERFACE
RUP2A/DIFFIO_RX_L56P
RDN2A/DIFFIO_RX_L56N
DQ18L/DIFFIO_RX_L30P
DQ18L/DIFFIO_RX_L30N
DQ18L/DIFFIO_TX_L30P
DQ18L/DIFFIO_TX_L30N
DQ19L/DIFFIO_TX_L32P
DQ19L/DIFFIO_TX_L32N
DQ19L/DIFFIO_TX_L31P
DQ19L/DIFFIO_TX_L31N
E
RLDC_DK_P[1:0]
HSMC PORT B
ENET_TX_D[7..0]
1.5V_1.8V_B2
SEVEN_SEG_A
SEVEN_SEG_B
SEVEN_SEG_C
SEVEN_SEG_D
SEVEN_SEG_E
SEVEN_SEG_F
SEVEN_SEG_G
SEVEN_SEG_DP
SEVEN_SEG_MINUS
MAX_CSn 23
MAX_OEn 23
MAX_WEn 23
EEPROM_DOUT 24
EEPROM_CS 24
EEPROM_CLK 24
EEPROM_DIN 24
SEVEN_SEG_SEL[4:1]
25
SEVEN_SEG_A 25
SEVEN_SEG_B 25
SEVEN_SEG_C 25
SEVEN_SEG_D 25
SEVEN_SEG_E 25
SEVEN_SEG_F 25
SEVEN_SEG_G 25
SEVEN_SEG_DP 25
SEVEN_SEG_MINUS 25
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
10,20,21
RLDC_QK_N[1:0]
MAX II INTERFACE
R280
R282
RLDC_A[22:0]
ENET_RX_D[7..0]
DQS30L/DIFFIO_RX_L49P
DQSN30L/DIFFIO_RX_L49N
DQS31L/DIFFIO_RX_L51P
DQSN31L/DIFFIO_RX_L51N
2.5V_B1_B8
A
20,21
RLDC_QK_P[1:0]
EP4SE530H1152
Version = 0.1 Preliminary
R232
R231
RLDC_BA[2:0]
RLDC_DK_N[1:0]
Bank 2B
T23
R24
R27
R28
P34
N34
R29
other DQ11 pin in config section
DQS12L/DIFFIO_RX_L19P
DQSN12L/DIFFIO_RX_L19N
DQS13L/DIFFIO_RX_L20P
DQSN13L/DIFFIO_RX_L20N
DQ32L/DIFFIO_TX_L51P
DQ32L/DIFFIO_TX_L51N
DQ32L/DIFFIO_TX_L52P
DQ32L/DIFFIO_TX_L52N
DQ33L/DIFFIO_TX_L53P
DQ33L/DIFFIO_TX_L53N
DQ33L/DIFFIO_RX_L53P
DQ33L/DIFFIO_RX_L53N
DQS32L/DIFFIO_RX_L52P
DQSN32L/DIFFIO_RX_L52N
DQS33L/DIFFIO_RX_L54P
DQSN33L/DIFFIO_RX_L54N
DQ30L/DIFFIO_TX_L49P
DQ30L/DIFFIO_TX_L49N
DQ30L/DIFFIO_TX_L48P
DQ30L/DIFFIO_TX_L48N
DQ31L/DIFFIO_TX_L50P
DQ31L/DIFFIO_TX_L50N
DQ31L/DIFFIO_RX_L50P
DQ31L/DIFFIO_RX_L50N
Bank 1B
C
Bank 2A
20
RLDC_A[22:0]
RLDC_DK_P[1:0]
Stratix IVE Bank 2
RLDC_DQ[35:0]
RLDC_BA[2:0]
U19B
U19A
E
1
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
14
of
1
29
B
8
7
6
5
4
3
2
1
Stratix IV E Banks 3 & 4
U19C
DDR3 DIMM INTERFACE
U19D
Stratix IVE Bank 3
E
AJ26
AH27
AJ27
AJ29
AM30
AN30
AM29
AL29
DDR3_DIMM_DQ7
DDR3_DIMM_DQ6
DDR3_DIMM_DQ5
DDR3_DIMM_DQ4
DDR3_DIMM_DQ3
DDR3_DIMM_DQ2
DDR3_DIMM_DQ1
DDR3_DIMM_DQ0
DDR3_DIMM_DM0
DDR3_DIMM_DQS_N9
DDR3_DIMM_DQS_P0
DDR3_DIMM_DQS_N0
AJ28
AK28
AM31
AM32
DQ1B/DIFFOUT_B3P
DQ1B/DIFFOUT_B1N
DQ1B/DIFFOUT_B1P
DQ1B/DIFFOUT_B3N
DQ2B/DIFFIO_RX_B3P
DQ2B/DIFFIO_RX_B3N
DQ2B/DIFFOUT_B5P
DQ2B/DIFFOUT_B5N
Bank 3A
RUP3A/DQS1B/DIFFIO_RX_B1P
RDN3A/DQSN1B/DIFFIO_RX_B1N
DQS2B/DIFFIO_RX_B2P
DQSN2B/DIFFIO_RX_B2N
DDR3_DIMM_DQ[71:0]
Stratix IVE Bank 4
DQ4B/DIFFOUT_B11P
DQ4B/DIFFOUT_B11N
DQ4B/DIFFIO_RX_B6P
DQ4B/DIFFIO_RX_B6N
DQ5B/DIFFOUT_B15N
DQ5B/DIFFOUT_B13N
DQ5B/DIFFOUT_B13P
DQ5B/DIFFOUT_B15P
DQS4B/DIFFIO_RX_B5P
DQSN4B/DIFFIO_RX_B5N
DQS5B/DIFFIO_RX_B7P
DQSN5B/DIFFIO_RX_B7N
AP30
AP32
AN31
AP31
AK25
AK27
AL28
AM26
AN33
AP33
AL26
AL27
DDR3_DIMM_DQ9
DDR3_DIMM_DQ8
DDR3_DIMM_DQ11
DDR3_DIMM_DQ10
DDR3_DIMM_DQ22
DDR3_DIMM_DQ20
DDR3_DIMM_DQ21
DDR3_DIMM_DQ23
DDR3_DIMM_DQS_P1
DDR3_DIMM_DQS_N1
DDR3_DIMM_DM2
DDR3_DIMM_DQS_N11
DDR3_DIMM_DQ50
DDR3_DIMM_DQ51
DDR3_DIMM_DQ48
DDR3_DIMM_DQ49
DDR3_DIMM_DQ52
DDR3_DIMM_DQ53
DDR3_DIMM_DQ54
DDR3_DIMM_DQ55
DDR3_DIMM_DQS_P6
DDR3_DIMM_DQS_N6
DDR3_DIMM_DM6
DDR3_DIMM_DQS_N15
AG12
AJ13
AH12
AJ12
AJ10
AL8
AL7
AJ9
AH11
AJ11
AK9
AL9
DQ33B/DIFFOUT_B112P
DQ33B/DIFFOUT_B112N
DQ33B/DIFFIO_RX_B56P
DQ33B/DIFFIO_RX_B56N
DQ34B/DIFFOUT_B114P
DQ34B/DIFFOUT_B114N
DQ34B/DIFFOUT_B116P
DQ34B/DIFFOUT_B116N
Bank 4A
DQS33B/DIFFIO_RX_B57P
DQSN33B/DIFFIO_RX_B57N
DQS34B/DIFFIO_RX_B58P
DQSN34B/DIFFIO_RX_B58N
DQ36B/DIFFOUT_B122P
DQ36B/DIFFOUT_B122N
DQ36B/DIFFOUT_B120P
DQ36B/DIFFOUT_B120N
DQ37B/DIFFOUT_B124P
DQ37B/DIFFOUT_B124N
DQ37B/DIFFIO_RX_B62P
DQ37B/DIFFIO_RX_B62N
DQS36B/DIFFIO_RX_B61P
DQSN36B/DIFFIO_RX_B61N
DQS37B/DIFFIO_RX_B63P
DQSN37B/DIFFIO_RX_B63N
AL4
AM4
AM6
AN6
AJ6
AK6
AJ7
AK7
DDR3_DIMM_DQ[71:0]
DDR3_DIMM_DQS_P[8:0]
DDR3_DIMM_DQ62
DDR3_DIMM_DQ63
DDR3_DIMM_DQ60
DDR3_DIMM_DQ61
DDR3_DIMM_DQS_P[8:0]
DDR3_DIMM_DQS_N[17:0]
DDR3_DIMM_DM[8:0]
DDR3_DIMM_A[15:0]
DDR3_DIMM_A[15:0]
DDR3_DIMM_CLK_P[1:0]
AL5
AM5
AH8
AJ8
DDR3_DIMM_DM7
DDR3_DIMM_DQS_N16
DDR3_DIMM_CLK_P0
DDR3_DIMM_CLK_N0
DDR3_DIMM_CLK_N[1:0]
DDR3_DIMM_CSn[3:0]
DDR3_DIMM_CKE[1:0]
D
C
DDR3_DIMM_DQ15
DDR3_DIMM_DQ13
DDR3_DIMM_DQ14
DDR3_DIMM_DQ12
AF23
AF24
AH25
AH26
DDR3_DIMM_DM1
DDR3_DIMM_DQS_N10
AG24
AH24
DDR3_DIMM_TEST2
AE24
AE23
DDR3_DIMM_DQ28
DDR3_DIMM_DQ30
DDR3_DIMM_DQ29
DDR3_DIMM_DQ31
DDR3_DIMM_DQ24
DDR3_DIMM_DQ25
DDR3_DIMM_DQ27
DDR3_DIMM_DQ26
AH23
AJ23
AJ24
AK22
AK24
AL25
AL23
AM23
AH22
DDR3_DIMM_DM3
DDR3_DIMM_DQS_N12 AJ22
AL24
DDR3_DIMM_DQS_P3
AM24
DDR3_DIMM_DQS_N3
DDR3_DIMM_DQ38
DDR3_DIMM_DQ36
DDR3_DIMM_DQ39
DDR3_DIMM_DQ37
DDR3_DIMM_DQ32
DDR3_DIMM_DQ33
DDR3_DIMM_DQ35
DDR3_DIMM_DQ34
AJ20
AL22
AJ21
AM22
AM21
AP20
AN21
AP21
DDR3_DIMM_DM4
DDR3_DIMM_DQS_N13
DDR3_DIMM_DQS_P4
DDR3_DIMM_DQS_N4
AK21
AL21
AN22
AP22
DQ3B/DIFFOUT_B9P
DQ3B/DIFFOUT_B7P
DQ3B/DIFFOUT_B9N
DQ3B/DIFFOUT_B7N
DQ6B/DIFFOUT_B17N
DQ6B/DIFFOUT_B17P
DQ6B/DIFFIO_RX_B9P
DQ6B/DIFFIO_RX_B9N
DQS3B/DIFFIO_RX_B4P
DQSN3B/DIFFIO_RX_B4N
DQS6B/DIFFIO_RX_B8P
DQSN6B/DIFFIO_RX_B8N
DQ7B/DIFFOUT_B19N
DQ7B/DIFFOUT_B19P
DQ9B/DIFFOUT_B25N
DQ9B/DIFFOUT_B27N
DQ9B/DIFFOUT_B25P
DQ9B/DIFFOUT_B27P
DQ10B/DIFFOUT_B29N
DQ10B/DIFFOUT_B29P
DQ10B/DIFFIO_RX_B15P
DQ10B/DIFFIO_RX_B15N
DQS7B/DIFFIO_RX_B10P
DQSN7B/DIFFIO_RX_B10N
Bank 3B
DQS9B/DIFFIO_RX_B13P
DQSN9B/DIFFIO_RX_B13N
DQS10B/DIFFIO_RX_B14P
DQSN10B/DIFFIO_RX_B14N
DQ17B/DIFFOUT_B51N
DQ17B/DIFFOUT_B49N
DQ17B/DIFFOUT_B51P
DQ17B/DIFFOUT_B49P
DQ18B/DIFFOUT_B53N
DQ18B/DIFFOUT_B53P
DQ18B/DIFFIO_RX_B27P
DQ18B/DIFFIO_RX_B27N
DQ11B/DIFFOUT_B33N
DQ11B/DIFFOUT_B33P
DQ11B/DIFFOUT_B31P
DQ11B/DIFFOUT_B31N
DQ12B/DIFFOUT_B35P
DQ12B/DIFFOUT_B35N
DQ12B/DIFFIO_RX_B18P
DQ12B/DIFFIO_RX_B18N
DQS11B/DIFFIO_RX_B16P
DQSN11B/DIFFIO_RX_B16N
DQS12B/DIFFIO_RX_B17P
DQSN12B/DIFFIO_RX_B17N
Bank 3C
DQ19B/DIFFOUT_B57N
DQ19B/DIFFOUT_B57P
DQ19B/DIFFOUT_B55N
DQ19B/DIFFOUT_B55P
DQS19B/DIFFIO_RX_B28P
DQSN19B/DIFFIO_RX_B28N
RUP3C/DQS17B/DIFFIO_RX_B25P
RDN3C/DQSN17B/DIFFIO_RX_B25N
DQS18B/DIFFIO_RX_B26P
DQSN18B/DIFFIO_RX_B26N
DIFFIO_RX_B29P
DIFFIO_RX_B29N
DIFFIO_RX_B30P
DIFFIO_RX_B30N
AM28
AP29
AN27
AP27
DDR3_DIMM_DQ16
DDR3_DIMM_DQ17
DDR3_DIMM_DQ19
DDR3_DIMM_DQ18
DDR3_DIMM_DQ58
DDR3_DIMM_DQ59
DDR3_DIMM_DQ56
DDR3_DIMM_DQ57
AP2
AP5
AN4
AP4
AN28
AP28
DDR3_DIMM_DQS_P2
DDR3_DIMM_DQS_N2
DDR3_DIMM_DQS_P7
DDR3_DIMM_DQS_N7
AN3
AP3
AC22
AD22
DDR3_DIMM_TEST1
RUP4A
RDN4A
AG9
AH9
AD21
AE20
AE21
AE22
AP23
AP26
AN24
AP24
DDR3_DIMM_DQ70
DDR3_DIMM_DQ71
DDR3_DIMM_DQ69
DDR3_DIMM_DQ68
DDR3_DIMM_DQ65
DDR3_DIMM_DQ64
DDR3_DIMM_DQ67
DDR3_DIMM_DQ66
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
AP9
AP11
AN10
AP10
AE13
AE14
AE15
AF15
AF21
AG21
AN25
AP25
DDR3_DIMM_DM8
DDR3_DIMM_DQS_N17
DDR3_DIMM_DQS_P8
DDR3_DIMM_DQS_N8
LCD_D_Cn
LCD_WEn
LCD_CSn
SPEAKER_OUT
AF13
AF14
AM9
AN9
AK18
AL18
AL20
AM18
DDR3_DIMM_A9
DDR3_DIMM_A2
DDR3_DIMM_A11
DDR3_DIMM_A3
AL19
AM19
DDR3_DIMM_A6
DDR3_DIMM_A7
DDR3_DIMM_CASn
DDR3_DIMM_ODT1
DDR3_DIMM_RASn
DDR3_DIMM_BA0
DDR3_DIMM_DQ42
DDR3_DIMM_DQ43
DDR3_DIMM_DQ40
DDR3_DIMM_DQ41
AK13
AL13
AL15
AM15
AG15
AK15
AH15
AJ15
AF19
AF20
AG19
AH19
DDR3_DIMM_TEST3
DDR3_DIMM_SCL
DDR3_DIMM_ERR_OUTn
DDR3_DIMM_PAR_IN
DDR3_DIMM_ODT0
DDR3_DIMM_WEn
DDR3_DIMM_DQS_P5
DDR3_DIMM_DQS_N5
AL14
AM14
AH14
AJ14
EP4SE530H1152
Version = 0.1 Preliminary
B
DQ35B/DIFFOUT_B118P
DQ35B/DIFFOUT_B118N
DQ35B/DIFFIO_RX_B59P
DQ35B/DIFFIO_RX_B59N
DQ38B/DIFFOUT_B128P
DQ38B/DIFFOUT_B128N
DQ38B/DIFFOUT_B126P
DQ38B/DIFFOUT_B126N
DQS35B/DIFFIO_RX_B60P
DQSN35B/DIFFIO_RX_B60N
DQ32B/DIFFOUT_B110P
DQ32B/DIFFOUT_B110N
RUP4A/DQS38B/DIFFIO_RX_B64P
RDN4A/DQSN38B/DIFFIO_RX_B64N
DQ27B/DIFFOUT_B94P
DQ27B/DIFFOUT_B94N
DQ27B/DIFFIO_RX_B47P
DQ27B/DIFFIO_RX_B47N
DQ28B/DIFFOUT_B98P
DQ28B/DIFFOUT_B98N
DQ28B/DIFFOUT_B96P
DQ28B/DIFFOUT_B96N
Bank 4B
DQS28B/DIFFIO_RX_B49P
DQSN28B/DIFFIO_RX_B49N
DQS27B/DIFFIO_RX_B48P
DQSN27B/DIFFIO_RX_B48N
DQ20B/DIFFOUT_B74P
DQ20B/DIFFOUT_B74N
DQ20B/DIFFOUT_B72P
DQ20B/DIFFOUT_B72N
DQ21B/DIFFOUT_B76P
DQ21B/DIFFOUT_B76N
DQ21B/DIFFIO_RX_B38P
DQ21B/DIFFIO_RX_B38N
DQS32B/DIFFIO_RX_B55P
DQSN32B/DIFFIO_RX_B55N
DQ29B/DIFFOUT_B100P
DQ29B/DIFFOUT_B100N
DQ29B/DIFFIO_RX_B50P
DQ29B/DIFFIO_RX_B50N
DQ30B/DIFFOUT_B102P
DQ30B/DIFFOUT_B102N
DQ30B/DIFFOUT_B104P
DQ30B/DIFFOUT_B104N
DQS29B/DIFFIO_RX_B51P
DQSN29B/DIFFIO_RX_B51N
DQS30B/DIFFIO_RX_B52P
DQSN30B/DIFFIO_RX_B52N
Bank 4C
DQS20B/DIFFIO_RX_B37P
DQSN20B/DIFFIO_RX_B37N
DQS21B/DIFFIO_RX_B39P
DQSN21B/DIFFIO_RX_B39N
DQ22B/DIFFOUT_B80P
DQ22B/DIFFOUT_B80N
DQ22B/DIFFOUT_B78P
DQ22B/DIFFOUT_B78N
DQS22B/DIFFIO_RX_B40P
DQSN22B/DIFFIO_RX_B40N
DIFFIO_RX_B35P
DIFFIO_RX_B35N
DIFFIO_RX_B36P
DIFFIO_RX_B36N
AE10
AF10
AE11
AF11
DDR3_DIMM_BA[2:0]
DDR3_DIMM_EVENTn
DDR3_DIMM_TEST4
DDR3_DIMM_ODT[1:0]
DDR3_DIMM_TEST5
DDR3_DIMM_SCL
DDR3_DIMM_PAR_IN
DDR3_DIMM_ERR_OUTn
DDR3_DIMM_EVENTn
DDR3_DIMM_RASn
DDR3_DIMM_CASn
DDR3_DIMM_WEn
AE12
AD13
AC12
AD12
AK10
AM11
AK12
AL12
AM8
AP8
AP6
AM7
HSMA_RX_LED
LCD1_RSTn
18
DDR3_DIMM_DQS_N[17:0]
DDR3_DIMM_DM[8:0]
DDR3_DIMM_CLK_P1
DDR3_DIMM_CLK_N1
18
18
18
10,18
DDR3_DIMM_CLK_P[1:0]
18
DDR3_DIMM_CLK_N[1:0]
18
DDR3_DIMM_CSn[3:0]
10,18
DDR3_DIMM_CKE[1:0]
10,18
DDR3_DIMM_BA[2:0]
18
DDR3_DIMM_ODT[1:0]
18
D
DDR3_DIMM_SCL 18
DDR3_DIMM_PAR_IN 18
DDR3_DIMM_ERR_OUTn 18
DDR3_DIMM_EVENTn 18
DDR3_DIMM_RASn 18
DDR3_DIMM_CASn 18
DDR3_DIMM_WEn 18
128x64 LCD DISPLAY INTERFACE
LCD1_RSTn
LCD1_RSTn 26
LCD DISPLAY INTERFACE
LCD_DATA[7:0]
LCD_CSn
LCD_D_Cn
LCD_WEn
AL10
AL11
AN7
AP7
HSMA_D0
HSMA_D1
HSMA_D2
HSMA_D3
AM12
AP13
AP14
AN13
DDR3_DIMM_DQ45
DDR3_DIMM_DQ44
DDR3_DIMM_DQ47
DDR3_DIMM_DQ46
AN12
AP12
DDR3_DIMM_DM5
DDR3_DIMM_DQS_N14
AL16
AM16
AJ16
AK16
DDR3_DIMM_CSn0
DDR3_DIMM_BA1
DDR3_DIMM_CKE0
DDR3_DIMM_BA2
LCD_DATA[7:0]
LCD_CSn 26
LCD_D_Cn 26
LCD_WEn 26
26
C
HSMA INTERFACE
HSMA_D[3:0]
HSMA_D[3:0] 27
HSMA_RX_LED
HSMA_RX_LED 25
SPEAKER_OUT
SPEAKER_OUT 26
EP4SE530H1152
Version = 0.1 Preliminary
J29
2
4
6
8
10
DDR3_DIMM_TEST1
DDR3_DIMM_TEST2
DDR3_DIMM_TEST3
DDR3_DIMM_TEST4
DDR3_DIMM_TEST5
2
4
6
8
10
1
3
5
7
9
E
B
1.5V_DDR3
1
3
5
7
9
R277
R287
49.9
49.9
RUP4A
RDN4A
2x5Header
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
15
of
1
29
B
8
7
6
5
4
3
2
1
Stratix IV E Banks 5 & 6
U19E
U19F
Stratix IVE Bank 5
E
D
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P1
HSMA_TX_D_N1
HSMA_RX_D_P3
HSMA_RX_D_N3
AE8
AE7
AF6
AF5
AC9
AC8
AL2
AL1
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMA_RX_D_P0
HSMA_RX_D_N0
AM2
AM1
AJ4
AJ3
HSMA_TX_D_P6
HSMA_TX_D_N6
HSMA_TX_D_P0
HSMA_TX_D_N0
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_RX_D_P5
HSMA_RX_D_N5
AE6
AE5
AC11
AB10
AD7
AD6
AH2
AJ1
HSMA_RX_D_P1
HSMA_RX_D_N1
HSMA_RX_D_P4
HSMA_RX_D_N4
AG4
AG3
AJ2
AK1
AE2
AE1
HSMA_RX_D_P9
HSMA_RX_D_N9
DQ1R/DIFFIO_TX_R2P
DQ1R/DIFFIO_TX_R2N
DQ1R/DIFFIO_TX_R3P
DQ1R/DIFFIO_TX_R3N
DQ2R/DIFFIO_TX_R4P
DQ2R/DIFFIO_TX_R4N
DQ2R/DIFFIO_RX_R4P
DQ2R/DIFFIO_RX_R4N
Bank 5A
DQS1R/DIFFIO_RX_R2P
DQSN1R/DIFFIO_RX_R2N
DQS2R/DIFFIO_RX_R3P
DQSN2R/DIFFIO_RX_R3N
Stratix IVE Bank 6
DQ5R/DIFFIO_TX_R8P
DQ5R/DIFFIO_TX_R8N
DQ5R/DIFFIO_TX_R9P
DQ5R/DIFFIO_TX_R9N
DQ6R/DIFFIO_TX_R10P
DQ6R/DIFFIO_TX_R10N
DQ6R/DIFFIO_RX_R10P
DQ6R/DIFFIO_RX_R10N
DQS5R/DIFFIO_RX_R8P
DQSN5R/DIFFIO_RX_R8N
DQS6R/DIFFIO_RX_R9P
DQSN6R/DIFFIO_RX_R9N
DQ3R/DIFFIO_TX_R5P
DQ3R/DIFFIO_TX_R5N
DQ3R/DIFFIO_TX_R6P
DQ3R/DIFFIO_TX_R6N
DQ4R/DIFFIO_TX_R7P
DQ4R/DIFFIO_TX_R7N
DQ4R/DIFFIO_RX_R7P
DQ4R/DIFFIO_RX_R7N
DQ7R/DIFFIO_TX_R11P
DQ7R/DIFFIO_TX_R11N
DQ7R/DIFFIO_TX_R12P
DQ7R/DIFFIO_TX_R12N
DQS7R/DIFFIO_RX_R11P
DQSN7R/DIFFIO_RX_R11N
DQS3R/DIFFIO_RX_R5P
DQSN3R/DIFFIO_RX_R5N
DQS4R/DIFFIO_RX_R6P
DQSN4R/DIFFIO_RX_R6N
RUP5A/DIFFIO_RX_R1P
RDN5A/DIFFIO_RX_R1N
AB8
AC7
AA10
AB9
AC6
AC5
AF2
AF1
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMB_TX_D_P0
HSMB_TX_D_N0
HSMB_TX_D_P7
HSMB_TX_D_N7
HSMB_TX_D_P9
HSMB_TX_D_N9
HSMB_RX_D_P9
HSMB_RX_D_N9
P11
P10
M7
M6
L5
L4
G2
H1
AF4
AF3
AG1
AH1
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMB_RX_D_P6
HSMB_RX_D_N6
HSMB_RX_D_P7
HSMB_RX_D_N7
K4
K3
J4
J3
AA12
AB11
AD4
AD3
HSMA_TX_D_P16
HSMA_TX_D_N16
HSMA_TX_D_P7
HSMA_TX_D_N7
AE4
AE3
HSMA_RX_D_P10
HSMA_RX_D_N10
AK4
AK3
RUP5A
RDN5A
HSMB_TX_D_P6
HSMB_TX_D_N6
HSMB_TX_D_P8
HSMB_TX_D_N8
HSMB_RX_D_P11
HSMB_RX_D_N11
HSMB_TX_D_P10
HSMB_TX_D_N10
N9
N8
L7
L6
H4
H3
K6
K5
HSMB_RX_D_P10
HSMB_RX_D_N10
HSMB_RX_D_P12
HSMB_RX_D_N12
F1
G1
E2
E1
E4
E3
RUP6A
RDN6A
DIFFIO_RX_R12P
DIFFIO_RX_R12N
DQ28R/DIFFIO_TX_R45P
DQ28R/DIFFIO_TX_R45N
DQ28R/DIFFIO_TX_R46P
DQ28R/DIFFIO_TX_R46N
DQ29R/DIFFIO_TX_R47P
DQ29R/DIFFIO_TX_R47N
DQ29R/DIFFIO_RX_R47P
DQ29R/DIFFIO_RX_R47N
Bank 6A
DQS28R/DIFFIO_RX_R46P
DQSN28R/DIFFIO_RX_R46N
DQS29R/DIFFIO_RX_R48P
DQSN29R/DIFFIO_RX_R48N
DQ30R/DIFFIO_TX_R49P
DQ30R/DIFFIO_TX_R49N
DQ30R/DIFFIO_TX_R48P
DQ30R/DIFFIO_TX_R48N
DQ31R/DIFFIO_RX_R50P
DQ31R/DIFFIO_RX_R50N
DQ31R/DIFFIO_TX_R50P
DQ31R/DIFFIO_TX_R50N
DQ32R/DIFFIO_TX_R52P
DQ32R/DIFFIO_TX_R52N
DQ32R/DIFFIO_TX_R51P
DQ32R/DIFFIO_TX_R51N
DQ33R/DIFFIO_TX_R53P
DQ33R/DIFFIO_TX_R53N
DQ33R/DIFFIO_RX_R53P
DQ33R/DIFFIO_RX_R53N
DQS32R/DIFFIO_RX_R52P
DQSN32R/DIFFIO_RX_R52N
DQS33R/DIFFIO_RX_R54P
DQSN33R/DIFFIO_RX_R54N
DQ34R/DIFFIO_TX_R55P
DQ34R/DIFFIO_TX_R55N
DQ34R/DIFFIO_TX_R54P
DQ34R/DIFFIO_TX_R54N
DQS34R/DIFFIO_RX_R55P
DQSN34R/DIFFIO_RX_R55N
DQS30R/DIFFIO_RX_R49P
DQSN30R/DIFFIO_RX_R49N
DQS31R/DIFFIO_RX_R51P
DQSN31R/DIFFIO_RX_R51N
DIFFIO_RX_R45P
DIFFIO_RX_R45N
J7
J6
N11
N10
K8
K7
G5
G4
HSMB_TX_D_P11
HSMB_TX_D_N11
HSMB_TX_D_P16
HSMB_TX_D_N16
HSMB_TX_D_P13
HSMB_TX_D_N13
HSMB_RX_D_P15
HSMB_RX_D_N15
F4
F3
C1
D1
HSMB_RX_D_P16
HSMB_RX_D_N16
HSMB_RX_D_P13
HSMB_RX_D_N13
HSMC PORT A
HSMA_TX_D_P[16:0]
HSMA_TX_D_N[16:0]
HSMA_RX_D_P[16:0]
HSMA_RX_D_N[16:0]
HSMA_CLK_IN_P[2:1]
HSMA_CLK_IN_N[2:1]
HSMA_CLK_OUT_P[2:1]
L9
L8
M10
M9
HSMB_TX_D_P14
HSMB_TX_D_N14
HSMB_TX_D_P15
HSMB_TX_D_N15
D3
D2
HSMB_RX_D_P14
HSMB_RX_D_N14
H2
J1
HSMB_RX_D_P8
HSMB_RX_D_N8
HSMA_CLK_OUT_N[2:1]
HSMA_SDA
HSMA_SCL
HSMA_CLK_OUT0
HSMB_TX_D_P[16:0]
HSMB_TX_D_N[16:0]
HSMB_RX_D_P[16:0]
HSMB_RX_D_N[16:0]
HSMB_CLK_OUT_P[2:1]
C
B
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_RX_D_P15
HSMA_RX_D_N15
AB6
AB5
AA7
AA6
Y10
Y9
AB4
AA3
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMA_RX_D_P11
HSMA_RX_D_N11
AC4
AB3
AC2
AD1
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_TX_D_P15
HSMA_TX_D_N15
Y8
Y7
W12
Y11
HSMA_RX_D_P12
HSMA_RX_D_N12
AB2
AC1
DQ12R/DIFFIO_TX_R19P
DQ12R/DIFFIO_TX_R19N
DQ12R/DIFFIO_TX_R20P
DQ12R/DIFFIO_TX_R20N
DQ13R/DIFFIO_TX_R21P
DQ13R/DIFFIO_TX_R21N
DQ13R/DIFFIO_RX_R21P
DQ13R/DIFFIO_RX_R21N
Bank 6B
Bank 5C
DQS12R/DIFFIO_RX_R19P
DQSN12R/DIFFIO_RX_R19N
DQS13R/DIFFIO_RX_R20P
DQSN13R/DIFFIO_RX_R20N
DQ15R/DIFFIO_TX_R24P
DQ15R/DIFFIO_TX_R24N
DQ15R/DIFFIO_RX_R24P
DQ15R/DIFFIO_RX_R24N
DQ16R/DIFFIO_TX_R25P
DQ16R/DIFFIO_TX_R25N
DQ16R/DIFFIO_TX_R26P
DQ16R/DIFFIO_TX_R26N
DQS15R/DIFFIO_RX_R23P
DQSN15R/DIFFIO_RX_R23N
DQS16R/DIFFIO_RX_R25P
DQSN16R/DIFFIO_RX_R25N
DQ14R/DIFFIO_TX_R22P
DQ14R/DIFFIO_TX_R22N
DQ14R/DIFFIO_TX_R23P
DQ14R/DIFFIO_TX_R23N
DQ17R/DIFFIO_TX_R27P
DQ17R/DIFFIO_TX_R27N
DQ17R/DIFFIO_RX_R27P
DQ17R/DIFFIO_RX_R27N
DQS14R/DIFFIO_RX_R22P
DQSN14R/DIFFIO_RX_R22N
DQS17R/DIFFIO_RX_R26P
DQSN17R/DIFFIO_RX_R26N
Y6
Y5
AA1
AB1
W8
W7
W11
W10
HSMA_TX_D_P11
HSMA_TX_D_N11
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMB_TX_D_P12
HSMB_TX_D_N12
HSMA_CLK_OUT0
FSM_A26
HSMB_RX_D_P2
HSMB_RX_D_N2
HSMB_TX_D_P2
HSMB_TX_D_N2
HSMB_TX_D_P3
HSMB_TX_D_N3
HSMB_TX_D_P1
HSMB_TX_D_N1
P2
R1
T7
U6
T5
T4
T9
T8
AA4
Y3
Y4
W3
HSMA_RX_D_P16
HSMA_RX_D_N16
CPU_RESETn
HSMB_RX_D_P3
HSMB_RX_D_N3
HSMB_RX_D_P0
HSMB_RX_D_N0
N2
P1
R4
R3
W6
W5
V4
V3
HSMB_D1
HSMA_SDA
Y2
Y1
HSMA_SCL
HSMB_RX_D_P1
HSMB_RX_D_N1
HSMB_TX_D_P5
HSMB_TX_D_N5
P4
P3
R7
R6
HSMB_RX_D_P4
HSMB_RX_D_N4
M1
N1
EP4SE530H1152
Version = 0.1 Preliminary
DQ18R/DIFFIO_RX_R30P
DQ18R/DIFFIO_RX_R30N
DQ18R/DIFFIO_TX_R30P
DQ18R/DIFFIO_TX_R30N
DQ19R/DIFFIO_TX_R32P
DQ19R/DIFFIO_TX_R32N
DQ19R/DIFFIO_TX_R31P
DQ19R/DIFFIO_TX_R31N
HSMB_CLK_OUT_N[2:1]
Bank 6C
DQS19R/DIFFIO_RX_R32P
DQSN19R/DIFFIO_RX_R32N
DQS18R/DIFFIO_RX_R31P
DQSN18R/DIFFIO_RX_R31N
DQ20R/DIFFIO_RX_R33P
DQ20R/DIFFIO_RX_R33N
DQ20R/DIFFIO_TX_R33P
DQ20R/DIFFIO_TX_R33N
DQ21R/DIFFIO_TX_R34P
DQ21R/DIFFIO_TX_R34N
DQ21R/DIFFIO_TX_R35P
DQ21R/DIFFIO_TX_R35N
DQ22R/DIFFIO_TX_R36P
DQ22R/DIFFIO_TX_R36N
DQ22R/DIFFIO_RX_R36P
DQ22R/DIFFIO_RX_R36N
DQS21R/DIFFIO_RX_R35P
DQSN21R/DIFFIO_RX_R35N
DQS22R/DIFFIO_RX_R37P
DQSN22R/DIFFIO_RX_R37N
DQ23R/DIFFIO_TX_R37P
DQ23R/DIFFIO_TX_R37N
DQ23R/DIFFIO_TX_R38P
DQ23R/DIFFIO_TX_R38N
DQS20R/DIFFIO_RX_R34P
DQSN20R/DIFFIO_RX_R34N
DQS23R/DIFFIO_RX_R38P
DQSN23R/DIFFIO_RX_R38N
HSMA_TX_D_P[16:0] 10,27
HSMA_TX_D_N[16:0] 10,27
HSMA_RX_D_P[16:0] 27
HSMA_RX_D_N[16:0]
27
HSMA_CLK_IN_P[2:1]
10,27
HSMA_CLK_IN_N[2:1]
10,27
HSMA_CLK_OUT_P[2:1]
10,27
HSMA_CLK_OUT_N[2:1]
10,27
HSMA_SDA 27
HSMA_SCL 27
HSMA_CLK_OUT0 27
D
HSMC PORT B
RUP6A/DIFFIO_RX_R56P
RDN6A/DIFFIO_RX_R56N
Bank 5B
E
P6
P5
R12
T11
R10
R9
L2
L1
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_N1
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
HSMB_TX_D_P4
HSMB_TX_D_N4
HSMB_RX_D_P5
HSMB_RX_D_N5
N4
N3
M4
M3
HSMB_TX_LED
MAX_CLK
HSMB_CLK_IN_P[2:1]
HSMB_CLK_IN_N[2:1]
HSMB_D[3:0]
HSMB_CLK_OUT0
HSMB_TX_LED
HSMB_TX_D_P[16:0] 27
HSMB_TX_D_N[16:0] 27
HSMB_RX_D_P[16:0] 27
HSMB_RX_D_N[16:0]
27
HSMB_CLK_OUT_P[2:1]
10,27
HSMB_CLK_OUT_N[2:1]
10,27
HSMB_CLK_IN_P[2:1]
10,27
HSMB_CLK_IN_N[2:1]
10,27
C
HSMB_D[3:0] 27
HSMB_CLK_OUT0 27
HSMB_TX_LED 25
CPU RESET
CPU_RESETn
P8
P7
N6
N5
HSMB_D3
HSMB_D0
HSMB_CLK_OUT0
HSMB_D2
K2
K1
MAX_TO_STRATIX4
CPU_RESETn 25
MAX INTERFACE
MAX_TO_STRATIX4
MAX_CLK
FSM_A[26:0]
EP4SE530H1152
Version = 0.1 Preliminary
MAX_TO_STRATIX4 23
MAX_CLK 23
B
FSM_A[26:0] 10,17,22,23
2.5V_B5_B6
R281
R283
49.9
49.9
RUP5A
RDN5A
49.9
49.9
RUP6A
RDN6A
2.5V_B5_B6
A
R250
R249
Title
Size
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
16
of
1
29
B
8
7
6
5
4
3
2
1
Stratix IV E Banks 7 & 8
E
U19G
Stratix IVE Bank 7
D
C
B
QDRII_Q15
QDRII_Q5
QDRII_Q11
QDRII_Q7
QDRII_Q17
QDRII_Q4
QDRII_Q16
QDRII_Q14
F6
F8
G8
F9
D6
C6
C5
B5
RUP7A
RDN7A
QDRII_CQ_N
QDRII_ODT
F7
E7
C4
C3
QDRII_Q8
QDRII_Q9
QDRII_Q6
QDRII_Q10
G10
J12
G9
J11
QDRII_CQ_P
QDRII_Q12
H11
G11
QDRII_DOFFn
K12
K11
QDRII_D4
QDRII_D13
QDRII_D15
QDRII_D17
QDRII_D14
QDRII_D8
QDRII_D7
QDRII_D6
E11
G13
F11
G12
D10
D13
D12
C12
QDRII_D16
QDRII_BWSn1
QDRII_BWSn0
F13
F12
D11
C11
QDRII_A19
QDRII_A17
QDRII_A20
QDRII_A0
QDRII_A4
QDRII_A2
QDRII_A21
QDRII_A3
D15
F15
E13
D14
C14
A15
B14
A14
QDRII_A7
QDRII_A1
QDRII_A18
F14
E14
B13
A13
DQ1T/DIFFOUT_T1P
DQ1T/DIFFOUT_T1N
DQ1T/DIFFOUT_T3P
DQ1T/DIFFOUT_T3N
DQ2T/DIFFOUT_T5P
DQ2T/DIFFOUT_T5N
DQ2T/DIFFIO_RX_T3P
DQ2T/DIFFIO_RX_T3N
Bank 7A
DQ4T/DIFFOUT_T11P
DQ4T/DIFFOUT_T11N
DQ4T/DIFFIO_RX_T6P
DQ4T/DIFFIO_RX_T6N
DQ5T/DIFFOUT_T15P
DQ5T/DIFFOUT_T15N
DQ5T/DIFFOUT_T13P
DQ5T/DIFFOUT_T13N
RUP7A/DQS1T/DIFFIO_RX_T1P
DQS4T/DIFFIO_RX_T5P
RDN7A/DQSN1T/DIFFIO_RX_T1N DQSN4T/DIFFIO_RX_T5N
DQS2T/DIFFIO_RX_T2P
DQS5T/DIFFIO_RX_T7P
DQSN2T/DIFFIO_RX_T2N
DQSN5T/DIFFIO_RX_T7N
DQ3T/DIFFOUT_T9P
DQ3T/DIFFOUT_T9N
DQ3T/DIFFOUT_T7P
DQ3T/DIFFOUT_T7N
DQ6T/DIFFOUT_T17P
DQ6T/DIFFOUT_T17N
DQ6T/DIFFIO_RX_T9P
DQ6T/DIFFIO_RX_T9N
DQS3T/DIFFIO_RX_T4P
DQSN3T/DIFFIO_RX_T4N
DQS6T/DIFFIO_RX_T8P
DQSN6T/DIFFIO_RX_T8N
DQS7T/DIFFIO_RX_T10P
DQSN7T/DIFFIO_RX_T10N
DQ7T/DIFFOUT_T19P
DQ7T/DIFFOUT_T19N
DQ9T/DIFFOUT_T27P Bank
DQ9T/DIFFOUT_T27N
DQ9T/DIFFOUT_T25P
DQ9T/DIFFOUT_T25N
DQ10T/DIFFOUT_T29P
DQ10T/DIFFOUT_T29N
DQ10T/DIFFIO_RX_T15P
DQ10T/DIFFIO_RX_T15N
DQS9T/DIFFIO_RX_T13P
DQSN9T/DIFFIO_RX_T13N
DQS10T/DIFFIO_RX_T14P
DQSN10T/DIFFIO_RX_T14N
7B
DQ17T/DIFFOUT_T51P
DQ17T/DIFFOUT_T51N
DQ17T/DIFFOUT_T49P
DQ17T/DIFFOUT_T49N
DQ18T/DIFFOUT_T53P
DQ18T/DIFFOUT_T53N
DQ18T/DIFFIO_RX_T27P
DQ18T/DIFFIO_RX_T27N
DQ11T/DIFFOUT_T31P
DQ11T/DIFFOUT_T31N
DQ11T/DIFFOUT_T33P
DQ11T/DIFFOUT_T33N
DQ12T/DIFFIO_RX_T18P
DQ12T/DIFFIO_RX_T18N
DQ12T/DIFFOUT_T35P
DQ12T/DIFFOUT_T35N
DQS11T/DIFFIO_RX_T16P
DQSN11T/DIFFIO_RX_T16N
DQS12T/DIFFIO_RX_T17P
DQSN12T/DIFFIO_RX_T17N
Bank 7C
DQ19T/DIFFOUT_T57P
DQ19T/DIFFOUT_T57N
DQ19T/DIFFOUT_T55P
DQ19T/DIFFOUT_T55N
DQS19T/DIFFIO_RX_T28P
DQSN19T/DIFFIO_RX_T28N
DQS17T/DIFFIO_RX_T25P
DQSN17T/DIFFIO_RX_T25N
DQS18T/DIFFIO_RX_T26P
DQSN18T/DIFFIO_RX_T26N
QDRII_Q[17:0]
Stratix IVE Bank 8
DIFFIO_RX_T30P
DIFFIO_RX_T30N
DIFFIO_RX_T29P
DIFFIO_RX_T29N
A3
A5
B4
A4
D8
E10
E8
D7
QDRII_Q0
QDRII_Q3
QDRII_Q1
QDRII_Q2
QDRII_A13
QDRII_A11
QDRII_A12
QDRII_A8
FSM_A0
FSM_A1
FSM_A2
FSM_A3
FSM_A7
FSM_A5
FSM_A6
FSM_A4
F22
H23
G23
F23
F26
D28
F25
D27
B2
A2
D9
C9
QDRII_Q13
QDRII_QVLD
QDRII_A10
QDRII_A16
FSM_A8
FSM_A9
FSM_A10
FSM_A11
G24
F24
E26
D26
C7
A6
B8
A8
QDRII_A5
QDRII_A6
QDRII_A9
QDRII_A15
FSM_A12
FSM_A13
FSM_A14
FSM_A15
A30
A33
B31
A31
B7
A7
QDRII_A14
FSM_A16
FSM_A17
B32
A32
L13
M13
K13
K14
L14
K15
B11
A11
A9
A12
QDRII_D11
QDRII_D12
QDRII_D9
QDRII_D10
QDRII_D2
QDRII_D3
QDRII_D0
QDRII_D5
J14
H14
B10
A10
QDRII_K_P
QDRII_K_N
QDRII_D1
E17
D17
C15
C17
QDRII_WPSn
D16
C16
H16
G16
J15
J16
EP4SE530H1152
Version = 0.1 Preliminary
RUP8A
RDN8A
H26
G26
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D15
FSM_D16
FSM_D14
FSM_D13
A24
A26
B25
A25
K21
K22
K20
J20
FSM_D17
FSM_D18
FSM_D19
FSM_D20
C26
B26
J22
J21
USER_LED4
USER_LED5
D19
C19
FLASH_RDYBSYn
FLASH_ADVn
SSRAM_BWn0
SSRAM_BWn1
SSRAM_BWn2
SSRAM_BWn3
SSRAM_ADSCn
SSRAM_ADSPn
C20
D20
D22
E22
E20
H20
G20
F20
SSRAM_ADVn
SSRAM_CLK
FLASH_RESETn
USER_LED0
D21
C21
G21
F21
E
QDRII SRAM INTERFACE
U19H
DQ33T/DIFFOUT_T112P
DQ33T/DIFFOUT_T112N
DQ33T/DIFFIO_RX_T56P
DQ33T/DIFFIO_RX_T56N
DQ34T/DIFFOUT_T116P
DQ34T/DIFFOUT_T116N
DQ34T/DIFFOUT_T114P
DQ34T/DIFFOUT_T114N
Bank 8A
DQS33T/DIFFIO_RX_T57P
DQSN33T/DIFFIO_RX_T57N
DQS34T/DIFFIO_RX_T58P
DQSN34T/DIFFIO_RX_T58N
DQ36T/DIFFOUT_T120P
DQ36T/DIFFOUT_T120N
DQ36T/DIFFOUT_T122P
DQ36T/DIFFOUT_T122N
DQ37T/DIFFOUT_T124P
DQ37T/DIFFOUT_T124N
DQ37T/DIFFIO_RX_T62P
DQ37T/DIFFIO_RX_T62N
DQS36T/DIFFIO_RX_T61P
DQSN36T/DIFFIO_RX_T61N
DQS37T/DIFFIO_RX_T63P
DQSN37T/DIFFIO_RX_T63N
DQ35T/DIFFOUT_T118P
DQ35T/DIFFOUT_T118N
DQ35T/DIFFIO_RX_T59P
DQ35T/DIFFIO_RX_T59N
DQ38T/DIFFOUT_T128P
DQ38T/DIFFOUT_T128N
DQ38T/DIFFOUT_T126P
DQ38T/DIFFOUT_T126N
DQ32T/DIFFOUT_T110P
DQ32T/DIFFOUT_T110N
DQS35T/DIFFIO_RX_T60P
DQSN35T/DIFFIO_RX_T60N
DQS32T/DIFFIO_RX_T55P
RUP8A/DQS38T/DIFFIO_RX_T64P DQSN32T/DIFFIO_RX_T55N
RDN8A/DQSN38T/DIFFIO_RX_T64N
DQ27T/DIFFOUT_T94P Bank
DQ27T/DIFFOUT_T94N
DQ27T/DIFFIO_RX_T47P
DQ27T/DIFFIO_RX_T47N
DQ28T/DIFFOUT_T98P
DQ28T/DIFFOUT_T98N
DQ28T/DIFFOUT_T96P
DQ28T/DIFFOUT_T96N
DQS27T/DIFFIO_RX_T48P
DQSN27T/DIFFIO_RX_T48N
DQS28T/DIFFIO_RX_T49P
DQSN28T/DIFFIO_RX_T49N
DIFFIO_RX_T35P
DIFFIO_RX_T35N
8B
DQ29T/DIFFOUT_T100P
DQ29T/DIFFOUT_T100N
DQ29T/DIFFIO_RX_T50P
DQ29T/DIFFIO_RX_T50N
DQ30T/DIFFOUT_T104P
DQ30T/DIFFOUT_T104N
DQ30T/DIFFOUT_T102P
DQ30T/DIFFOUT_T102N
DQS29T/DIFFIO_RX_T51P
DQSN29T/DIFFIO_RX_T51N
DQS30T/DIFFIO_RX_T52P
DQSN30T/DIFFIO_RX_T52N
DIFFIO_RX_T36P
DIFFIO_RX_T36N
DQ20T/DIFFOUT_T72P Bank 8C
DQ22T/DIFFOUT_T78P
DQ20T/DIFFOUT_T72N
DQ22T/DIFFOUT_T78N
DQ20T/DIFFOUT_T74P
DQ22T/DIFFOUT_T80P
DQ20T/DIFFOUT_T74N
DQ22T/DIFFOUT_T80N
DQ21T/DIFFOUT_T76P
DQ21T/DIFFOUT_T76N
DQ21T/DIFFIO_RX_T38P
DQ21T/DIFFIO_RX_T38N
RUP8C/DQS22T/DIFFIO_RX_T40P
RDN8C/DQSN22T/DIFFIO_RX_T40N
DQS20T/DIFFIO_RX_T37P
DQSN20T/DIFFIO_RX_T37N
DQS21T/DIFFIO_RX_T39P
DQSN21T/DIFFIO_RX_T39N
C29
B29
C31
D31
F27
G27
F28
E28
FSM_A21
FSM_A20
FSM_A22
FSM_A23
FSM_A24
FSM_D0
FSM_D1
FSM_D2
D30
C30
F29
E29
FSM_D3
FSM_D4
FSM_D5
FSM_D6
J25
K25
J24
K24
L22
K23
FSM_D8
FLASH_CEn
FSM_D7
FLASH_CLK
FLASH_WEn
FLASH_OEn
M23
L23
FSM_A18
FSM_A19
C24
E25
D25
D24
C28
A29
A27
C27
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D28
FSM_D26
FSM_D25
FSM_D27
E23
D23
B28
A28
FSM_D29
FSM_D30
FSM_D31
USER_DIPSW0
QDRII_D[17:0]
QDRII_A[21:0]
QDRII_BWSn0
QDRII_BWSn1
QDRII_K_P
QDRII_K_N
QDRII_CQ_P
QDRII_CQ_N
QDRII_QVLD
QDRII_DOFFn
QDRII_ODT
QDRII_WPSn
QDRII_Q[17:0]
19
QDRII_D[17:0]
19,21
QDRII_A[21:0]
19,21
QDRII_BWSn0
QDRII_BWSn1
19,21
19,21
QDRII_K_P 19
QDRII_K_N 19
QDRII_CQ_P 19
QDRII_CQ_N 19
QDRII_QVLD 19
QDRII_DOFFn 19
QDRII_ODT 19,21
QDRII_WPSn 19,21
D
SHARED BUS INTERFACE
FSM_D[31:0]
FSM_A[26:0]
FSM_D[31:0]
22,23
FSM_A[26:0] 10,16,22,23
SSRAM INTERFACE
SSRAM_BWn[3:0]
SSRAM_OEn
SSRAM_BWEn
SSRAM_ADVn
SSRAM_ADSCn
SSRAM_ADSPn
SSRAM_CE1n
SSRAM_CLK
USER_LED6
USER_LED7
A22
A21
B22
C23
SSRAM_OEn
SSRAM_CE1n
SSRAM_BWEn
USER_LED1
B23
A23
USER_LED2
USER_LED3
22
SSRAM_OEn 22
SSRAM_BWEn 22
SSRAM_ADVn 22
SSRAM_ADSCn 22
SSRAM_ADSPn 22
SSRAM_CE1n 22
SSRAM_CLK 22
C
USER INTERFACE
USER_LED[7:0]
F19
E19
SSRAM_BWn[3:0]
USER_DIPSW[7:0]
USER_LED[7:0]
25
USER_DIPSW[7:0]
10,25
FLASH INTERFACE
FLASH_CLK
FLASH_CEn
FLASH_ADVn
FLASH_WEn
FLASH_OEn
FLASH_RESETn
FLASH_RDYBSYn
FLASH_CLK 22,23
FLASH_CEn 22,23
FLASH_ADVn 22,23
FLASH_WEn 22,23
FLASH_OEn 22,23
FLASH_RESETn 22,23
FLASH_RDYBSYn 22,23
B
EP4SE530H1152
Version = 0.1 Preliminary
2.5V_B1_B8
1.5V_1.8V_B7
R237
R238
A
49.9
49.9
R234
R233
RUP7A
RDN7A
49.9
49.9
RUP8A
RDN8A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
17
of
1
29
B
8
7
6
5
4
3
2
1
DDR3 SDRAM UDIMM (VIO)
DDR3_VDDSPD
12V
B2
U28
1
2
3
4
C238
0.1uF
IN
NC1
NC2
GND
E
OUT
NC3
NC4
FB
PAN
8
6
7
5
9
C239
R125
1.4M
0.47uF
MT18JSF25672AY-1G1
TPS715A01
R131
806K
DDR3 DIMM on (VIO) INTERFACE
1.5V_DIMM
1.5V_DIMM
DDR3_DIMM_DQ[71:0]
J20B
VREF_DIMM
1.5V_DIMM
1.5V_DIMM
61
62
63
64
DDR3_DIMM_A2
J20A
C231
DDR3_DIMM_DQ0
DDR3_DIMM_DQ1
0.1uF
DDR3_DIMM_DQS_N0
DDR3_DIMM_DQS_P0
DDR3_DIMM_DQ2
DDR3_DIMM_DQ3
D
DDR3_DIMM_DQ8
DDR3_DIMM_DQ9
DDR3_DIMM_DQS_N1
DDR3_DIMM_DQS_P1
DDR3_DIMM_DQ10
DDR3_DIMM_DQ11
DDR3_DIMM_DQ16
DDR3_DIMM_DQ17
DDR3_DIMM_DQS_N2
DDR3_DIMM_DQS_P2
DDR3_DIMM_DQ18
DDR3_DIMM_DQ19
DDR3_DIMM_DQ24
DDR3_DIMM_DQ25
C
DDR3_DIMM_DQS_N3
DDR3_DIMM_DQS_P3
DDR3_DIMM_DQ26
DDR3_DIMM_DQ27
DDR3_DIMM_DQ64
DDR3_DIMM_DQ65
DDR3_DIMM_DQS_N8
DDR3_DIMM_DQS_P8
DDR3_DIMM_DQ66
DDR3_DIMM_DQ67
VTT_DIMM
B
DDR3_DIMM_CKE0
DDR3_DIMM_BA2
DDR3_DIMM_ERR_OUTn
DDR3_DIMM_A11
DDR3_DIMM_A7
DDR3_DIMM_A5
DDR3_DIMM_A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VREFDQ
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
CB0,NC
CB1,NC
VSS
DQS8#
DQS8
VSS
CB2,NC
CB3,NC
VSS
VTT,NC
VTT,NC
CKE0
VDD
BA2
Err_Out#,NC
VDD
A11
A7
VDD
A5
A4
VDD
VSS
DQ4
DQ5
VSS
DM0,DQS9
NC,DQS9#
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1,DQS10
NC,DQS10#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2,DQS11
NC,DQS11#
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3,DQS12
NC,DQS12#
VSS
DQ30
DQ31
VSS
CB4,NC
CB5,NC
VSS
DM8,DQS17
NC,DQS17#
VSS
CB6,NC
CB7,NC
VSS
NC(TEST)
RESET#
CKE1,NC
VDD
NC, A15
A14, NC
VDD
A12, BC#
A9
VDD
A8
A6
VDD
A3
E
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
DDR3_DIMM_CLK_P1
DDR3_DIMM_CLK_N1
DDR3_DIMM_DQ4
DDR3_DIMM_DQ5
A2
VDD
CK1,NC
CK1#,NC
A1
VDD
VDD
CK0
181
182
183
184
DDR3_DIMM_DQ[71:0]
DDR3_DIMM_A1
DDR3_DIMM_DQS_P[8:0]
DDR3_DIMM_DQS_P[8:0]
DDR3_DIMM_DQS_N[17:0]
DDR3_DIMM_CLK_P0
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VREF_DIMM
DDR3_DIMM_DQ6
DDR3_DIMM_DQ7
DDR3_DIMM_PAR_IN
C539
DDR3_DIMM_DQ12
DDR3_DIMM_DQ13
0.1uF
DDR3_DIMM_A10
DDR3_DIMM_BA0
DDR3_DIMM_WEn
DDR3_DIMM_CASn
DDR3_DIMM_DM1
DDR3_DIMM_DQS_N10
DDR3_DIMM_CSn1
DDR3_DIMM_ODT1
DDR3_DIMM_DQ14
DDR3_DIMM_DQ15
DDR3_DIMM_CSn2
DDR3_DIMM_DQ20
DDR3_DIMM_DQ21
DDR3_DIMM_DQ32
DDR3_DIMM_DQ33
DDR3_DIMM_DM2
DDR3_DIMM_DQS_N11
DDR3_DIMM_DQS_N4
DDR3_DIMM_DQS_P4
DDR3_DIMM_DQ22
DDR3_DIMM_DQ23
DDR3_DIMM_DQ34
DDR3_DIMM_DQ35
DDR3_DIMM_DQ28
DDR3_DIMM_DQ29
DDR3_DIMM_DQ40
DDR3_DIMM_DQ41
DDR3_DIMM_DM3
DDR3_DIMM_DQS_N12
DDR3_DIMM_DQS_N5
DDR3_DIMM_DQS_P5
DDR3_DIMM_DQ30
DDR3_DIMM_DQ31
DDR3_DIMM_DQ42
DDR3_DIMM_DQ43
DDR3_DIMM_DQ68
DDR3_DIMM_DQ69
DDR3_DIMM_DQ48
DDR3_DIMM_DQ49
DDR3_DIMM_DM8
DDR3_DIMM_DQS_N17
DDR3_DIMM_DQS_N6
DDR3_DIMM_DQS_P6
DDR3_DIMM_DQ70
DDR3_DIMM_DQ71
DDR3_DIMM_DQ50
DDR3_DIMM_DQ51
DDR3_DIMM_RESETn
DDR3_DIMM_CKE1
DDR3_DIMM_DQ56
DDR3_DIMM_DQ57
DDR3_DIMM_A15
DDR3_DIMM_A14
DDR3_DIMM_DQS_N7
DDR3_DIMM_DQS_P7
DDR3_DIMM_A12
DDR3_DIMM_A9
DDR3_DIMM_DQ58
DDR3_DIMM_DQ59
DDR3_DIMM_A8
DDR3_DIMM_A6
DDR3_DIMM_SCL
VTT_DIMM
DDR3_DIMM_A3
DDR3_DIMM
VDD
VDD
VREFCA
Par_In,NC
VDD
A10/ AP
BA0
VDD
WE#
CAS#
VDD
S1#,NC
ODT1,NC
VDD
S2#,NC
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
DQ58
DQ59
VSS
SA0
SCL
SA2
VTT
CK0#
VDD
EVENT#,NC
A0
VDD
BA1
VDD
RAS#
S0#
VDD
ODT0
A13, NC
VDD
S3#, NC
VSS
DQ36
DQ37
VSS
DM4,DQS13
NC, DQS13#
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5, DQS14
NC, DQS14#
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6, DQS15
NC, DQS15#
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7, DQS16
NC, DQS16#
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
SDA
VSS
VTT
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
DDR3_DIMM_DM[8:0]
DDR3_DIMM_CLK_N0
DDR3_DIMM_CLK_P[1:0]
DDR3_DIMM_EVENTn
DDR3_DIMM_A0
DDR3_DIMM_CLK_N[1:0]
DDR3_DIMM_BA1
DDR3_DIMM_BA[2:0]
DDR3_DIMM_RASn
DDR3_DIMM_CSn0
DDR3_DIMM_A[15:0]
DDR3_DIMM_CSn[3:0]
DDR3_DIMM_CSn3
DDR3_DIMM_CKE[1:0]
DDR3_DIMM_DQ36
DDR3_DIMM_DQ37
DDR3_DIMM_SDA
DDR3_DIMM_SCL
DDR3_DIMM_RESETn
DDR3_DIMM_RASn
DDR3_DIMM_CASn
DDR3_DIMM_WEn
DDR3_DIMM_PAR_IN
DDR3_DIMM_EVENTn
DDR3_DIMM_ERR_OUTn
DDR3_DIMM_DM4
DDR3_DIMM_DQS_N13
DDR3_DIMM_DQ38
DDR3_DIMM_DQ39
15
15
DDR3_DIMM_CLK_P[1:0]
15
DDR3_DIMM_CLK_N[1:0]
15
DDR3_DIMM_BA[2:0]
15
DDR3_DIMM_A[15:0]
10,15
D
DDR3_DIMM_ODT[1:0]
DDR3_DIMM_ODT0
DDR3_DIMM_A13
15
DDR3_DIMM_DQS_N[17:0]
DDR3_DIMM_DM[8:0]
DDR3_DIMM_DM0
DDR3_DIMM_DQS_N9
15
DDR3_DIMM_ODT[1:0]
15
DDR3_DIMM_CSn[3:0]
10,15
DDR3_DIMM_CKE[1:0]
10,15
DDR3_DIMM_SDA 10
DDR3_DIMM_SCL 15
DDR3_DIMM_RESETn 10
DDR3_DIMM_RASn 15
DDR3_DIMM_CASn 15
DDR3_DIMM_WEn 15
DDR3_DIMM_PAR_IN 15
DDR3_DIMM_EVENTn 15
DDR3_DIMM_ERR_OUTn 15
DDR3_DIMM_DQ44
DDR3_DIMM_DQ45
C
C538
DDR3_DIMM_DM5
DDR3_DIMM_DQS_N14
DDR3_DIMM_CLK_P0
DDR3_DIMM_CLK_N0
7.0pF
DDR3_DIMM_DQ46
DDR3_DIMM_DQ47
C541
DDR3_DIMM_DQ52
DDR3_DIMM_DQ53
DDR3_DIMM_CLK_P1
DDR3_DIMM_CLK_N1
7.0pF
DDR3_DIMM_DM6
DDR3_DIMM_DQS_N15
DDR3_DIMM_DQ54
DDR3_DIMM_DQ55
DDR3_DIMM_DQ60
DDR3_DIMM_DQ61
DDR3_VDDSPD
R114
R113
R301
DDR3_DIMM_DM7
DDR3_DIMM_DQS_N16
DDR3_DIMM_DQ62
DDR3_DIMM_DQ63
10.0K
10.0K
10.0K
B
DDR3_DIMM_SDA
DDR3_DIMM_SCL
DDR3_DIMM_EVENTn
DDR3_VDDSPD
DDR3_DIMM_SDA
VTT_DIMM
DDR3_DIMM
VTT_DIMM
PLACE CAPS NEAR DDR3 DIMM
1.5V_DIMM
1.5V_DIMM
2
C552
1
+
C236
470uF
10V
Tantalum
+
2
1
C242
A
C244
470uF
10V
Tantalum
C240 C241
C247
C248
100uF 100uF
1uF
100uF
C553
1uF
100nF
10nF
C227
C222
C243
100nF
10nF
1uF
Title
1.5V_DIMM
C219
C214
C221
Size
100uF
100uF
1uF
B
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
VTT_DIMM
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
18
of
1
29
B
8
7
6
5
4
3
2
1
QDRII+ SRAM
VREF_QDRII
QDRII+ SRAM INTERFACE
1.8V
QDRII_Q[17:0]
VDDQ_QDRII
C376
0.1uF
R19
10.0K
B7
A5
R202
0
B
VDDQ_QDRII
VDDQ_QDRII
R193
10.0K
QDRII_WPSn
QDRII_RPSn
A4
A8
QDRII_K_P
QDRII_K_N
QDRII_QVLD
QDRII_ODT
QDRII_CQ_P
QDRII_CQ_N
B6
A6
P6
R6
A11
A1
R192
10.0K
QDRII_DOFFn
QDRII_ZQ
R199
10.0K
QDRII_TMS0
R203
10.0K
QDRII_TCK0
H1
H11
R10
R11
R1
R2
E4
E8
F4
F8
G4
G8
H3
H4
H8
H9
J4
J8
K4
K8
L4
L8
H2
H10
VREF1
VREF2
QDRII_BWSn0
QDRII_BWSn1
VDDQ_QDRII
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
NC/36M
WPSn
RPSn
DOFFn
ZQ
TMS
TDI
TDO
TCK
CY7C2563KV18-550BZXC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
BWSn0
BWSn1
K_P
K_N
C_P/QVLD
C_N/ODT
CQ_P
CQ
CQ_N
QDRII_Q[17:0]
goes to Stratix IVE DLL
P11
M10
L11
K11
J10
F11
E11
C10
B11
B2
D3
E3
F2
G3
K3
L2
N3
P3
A7
B1
B5
B9
B10
C1
C2
C6
C9
D1
D9
D10
E1
E2
E9
F1
F9
F10
G1
G9
G10
J1
J2
J9
K1
K2
K9
L1
L9
L10
M1
M2
M9
N1
N9
N10
P1
P2
P9
QDRII_BWSn0
QDRII_BWSn1
QDRII_Q0
QDRII_Q1
QDRII_Q2
QDRII_Q3
QDRII_Q4
QDRII_Q5
QDRII_Q6
QDRII_Q7
QDRII_Q8
QDRII_Q9
QDRII_Q10
QDRII_Q11
QDRII_Q12
QDRII_Q13
QDRII_Q14
QDRII_Q15
QDRII_Q16
QDRII_Q17
17
E
QDRII_D[17:0]
QDRII_A[21:0]
VSS/72M
VSS/144M
R18
10.0K
A9
B4
B8
C5
C7
N5
N6
N7
P4
P5
P7
P8
R3
R4
R5
R7
R8
R9
A3
C374
0.1uF
QDRII_WPSn
QDRII_RPSn
QDRII_D[17:0]
17,21
QDRII_A[21:0]
17,21
QDRII_BWSn0
QDRII_BWSn1
17,21
17,21
QDRII_WPSn 17,21
QDRII_RPSn 10,21
QDRII_K_P
QDRII_K_N
QDRII_K_P 17
QDRII_K_N 17
QDRII_CQ_P
QDRII_CQ_N
QDRII_CQ_P
QDRII_CQ_N
QDRII_QVLD
QDRII_ODT
17
17
QDRII_QVLD 17
QDRII_ODT 17,21
D
QDRII_DOFFn
QDRII_DOFFn
17
QDRII_A21
C
B
A10
A2
C
QDRII_A0
QDRII_A1
QDRII_A2
QDRII_A3
QDRII_A4
QDRII_A5
QDRII_A6
QDRII_A7
QDRII_A8
QDRII_A9
QDRII_A10
QDRII_A11
QDRII_A12
QDRII_A13
QDRII_A14
QDRII_A15
QDRII_A16
QDRII_A17
QDRII_A18
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VDDQ_QDRII
P10
N11
M11
K10
J11
G11
E10
D11
C11
B3
C3
D2
F3
G2
J3
L3
M3
N2
C4
C8
D4
D5
D6
D7
D8
E5
E6
E7
F6
G6
H6
J6
K6
L5
L6
L7
M4
M5
M6
M7
M8
N4
N8
D
QDRII_D0
QDRII_D1
QDRII_D2
QDRII_D3
QDRII_D4
QDRII_D5
QDRII_D6
QDRII_D7
QDRII_D8
QDRII_D9
QDRII_D10
QDRII_D11
QDRII_D12
QDRII_D13
QDRII_D14
QDRII_D15
QDRII_D16
QDRII_D17
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
U11
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
F5
F7
G5
G7
H5
H7
J5
J7
K5
K7
E
QDRII_A19
QDRII_A20
QDRII+ Output Impedance
A
R26
301
R25
249
VDDQ_QDRII
J7
1
3
5
2
4
6
QDRII_ZQ
TSW-103-07-L-D
Setting
Shunt J47
60 ohms
PIN1-PIN2
50 ohms
PIN3-PIN4
Min Drive
PIN5-PIN6
Title
Size
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
19
of
1
29
B
8
7
6
5
E
R88
R95
R89
R81
R100
R94
2
56.2
56.2
56.2
56.2
56.2
56.2
PLACE THESE RESISTORS AS CLOSE AS
POSSIBLE TO THE RLDRAM II
RLDC_CK_P
RLDC_CK_N
VTT_RLD
C486
C502
C491
C501
0.1uF
0.1uF
0.1uF
0.1uF
D
VDDQ_RLD
1
3
5
301
249
J1
J2
RLDC_DK_P1
RLDC_DK_N1
K1
K2
RLDC_QK_P0
RLDC_QK_N0
D11
D10
RLDC_QK_P1
RLDC_QK_N1
R2
R3
RLDC_CSn
RLDC_WEn
RLDC_REFn
L2
M1
L1
RLDC_DM
RLDC_QVLD
P12
F12
RLDC_BA0
RLDC_BA1
RLDC_BA2
J11
K11
H1
A11
A12
V11
V12
2
4
6
RLDC_ZQ
RLDC_A0
RLDC_A1
RLDC_A2
RLDC_A3
RLDC_A4
RLDC_A5
RLDC_A6
RLDC_A7
RLDC_A8
RLDC_A9
RLDC_A10
RLDC_A11
RLDC_A12
RLDC_A13
RLDC_A14
RLDC_A15
RLDC_A16
RLDC_A17
RLDC_A18
RLDC_A19
RLDC_A20
RLDC_A21
RLDC_A22
TSW-103-07-L-D
C
Output Impedence
Setting
MAX Drive
60 Ohms
50 Ohms
J12
K12
RLDC_DK_P0
RLDC_DK_N0
J28
R57
R56
Shunt Position
PIN1-PIN2
PIN3-PIN4
PIN5-PIN6
HSTL1
B
3
1
RLDRAM II, CIO
VTT_RLD
RLDC_CK_P
RLDC_CK_N
RLDC_DK_P0
RLDC_DK_N0
RLDC_DK_P1
RLDC_DK_N1
4
BYPASS CAPS FOR RLDRAM II CIO
V2
G12
G11
G10
H12
H11
F1
G2
G3
G1
H2
M12
M11
M10
L12
L11
P1
M2
M3
N1
N12
E12
E1
D1
U24A
RLDRAM II CIO, x36
CK
CK
DQ0
DQ1
DK0
DQ2
DK0
DQ3
DQ4
DK1
DQ5
DK1
DQ6
DQ7
QK0
DQ8
QK0
DQ9
DQ10
QK1
DQ11
QK1
DQ12
DQ13
CS
DQ14
WE
DQ15
REF
DQ16
DQ17
DM
DQ18
QVLD
DQ19
DQ20
B0
DQ21
B1
DQ22
B2
DQ23
DQ24
TMS
DQ25
TCK
DQ26
TDO
DQ27
TDI
DQ28
DQ29
ZQ
DQ30
DQ31
A0
DQ32
A1
DQ33
A2
DQ34
A3
DQ35
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
DNU (A20)
DNU (A21)
DNU (A22)
RLDRAM II INTERFACE
U24B
VREF_RLD
B11
B10
C11
C10
E11
E10
F11
F10
B2
B3
C2
C3
D2
D3
E2
E3
F2
F3
U2
U3
T2
T3
P2
P3
N2
N3
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
A1
V1
RLDC_DQ0
RLDC_DQ1
RLDC_DQ2
RLDC_DQ3
RLDC_DQ4
RLDC_DQ5
RLDC_DQ6
RLDC_DQ7
RLDC_DQ8
RLDC_DQ9
RLDC_DQ10
RLDC_DQ11
RLDC_DQ12
RLDC_DQ13
RLDC_DQ14
RLDC_DQ15
RLDC_DQ16
RLDC_DQ17
RLDC_DQ18
RLDC_DQ19
RLDC_DQ20
RLDC_DQ21
RLDC_DQ22
RLDC_DQ23
RLDC_DQ24
RLDC_DQ25
RLDC_DQ26
RLDC_DQ27
RLDC_DQ28
RLDC_DQ29
RLDC_DQ30
RLDC_DQ31
RLDC_DQ32
RLDC_DQ33
RLDC_DQ34
RLDC_DQ35
H10
A2
A4
A9
H3
H4
H9
L3
L4
L9
L10
R1
R12
V4
V9
D12
B4
B9
D4
D9
F4
F9
N4
N9
R4
R9
U4
U9
RLDRAM II CIO, x36
VREF1
VREF2
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1.8V
RLDC_DQ[35:0]
RLDC_DQ[35:0]
14
J10
RLDC_QK_P[1:0]
RLDC_QK_P[1:0]
14
B1
B12
G4
G9
J3
J4
J9
K3
K4
K9
K10
M4
M9
U1
U12
RLDC_QK_N[1:0]
RLDC_QK_N[1:0]
14
RLDC_DK_P[1:0]
RLDC_DK_P[1:0]
14
RLDC_DK_N[1:0]
RLDC_DK_N[1:0]
14
RLDC_A[22:0]
RLDC_BA[2:0]
VDDQ_RLD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VTT
VTT
VTT
VTT
VEXT
VEXT
VEXT
VEXT
E
C4
C9
E4
E9
P4
P9
T4
T9
RLDC_A[22:0]
10,14,21
RLDC_BA[2:0]
14,21
RLDC_CK_P
RLDC_CK_N
RLDC_CK_P 14
RLDC_CK_N 14
RLDC_CSn
RLDC_WEn
RLDC_REFn
RLDC_CSn
RLDC_DM
RLDC_QVLD
RLDC_CSn 14,21
RLDC_WEn 14,21
RLDC_REFn 14,21
RLDC_CSn 14,21
RLDC_DM 14
RLDC_QVLD 14
D
VTT_RLD
C1
C12
T1
T12
2.5V
C
A3
A10
V3
V10
MT49H16M36HT-18
PLACE THESE CAPACITORS AS CLOSE AS
POSSIBLE TO THE RLDRAM II
VREF_RLD
C482
0.1uF
C504
0.1uF
B
MT49H16M36HT-18
2.5V
VTT_RLD
C144
C161
C154
C141
0.1uF
0.1uF
0.1uF
0.1uF
C134
1uF
1.8V
VDDQ_RLD
A
1.8V
C133
C503
C484
C179
0.33uF
0.33uF
100uF
C140
1uF
Title
100uF
1.8V
Size
B
Date:
8
7
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
20
of
1
29
B
8
7
6
5
4
3
2
1
RLDRAM II and QDRII+ TERMINATIONS
QDRII+ SRAM INTERFACE
E
Place Near RLDRAM II
On-die termination (ODT) is enabled by setting
A9 to “1” during an MRS command.
Place Near QDRII+
VTT_QDRII
PLACE THE RESISTORS WITHIN THIS BOX AS CLOSE AS
POSSIBLE TO THE RLDRAM II CIO
VTT_RLD
D
RLDC_A1
RLDC_A2
RLDC_BA2
RLDC_A11
RLDC_A16
RLDC_A12
RLDC_A7
RLDC_A17
RLDC_A14
RLDC_BA0
RLDC_A13
RLDC_A0
RLDC_A4
RLDC_A10
RLDC_A3
RLDC_A19
C
RLDC_A18
RLDC_A15
RLDC_BA1
RLDC_WEn
RLDC_A5
RLDC_A22
RLDC_REFn
RLDC_CSn
RN8A
RN8B
RN8C
RN8D
RN8E
RN8F
RN8G
RN8H
RN10A
RN10B
RN10C
RN10D
RN10E
RN10F
RN10G
RN10H
RN9A
RN9B
RN9C
RN9D
RN9E
RN9F
RN9G
RN9H
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
56
56
56
56
56
56
56
56
VTT_RLD
CN9
1
7
3
5
56
56
56
56
56
56
56
56
CN8
8
2
6
4
1
7
3
5
0.1uF x 4
CN7
1
7
3
5
56
56
56
56
56
56
56
56
1
7
3
5
8
2
6
4
0.1uF x 4
NOTE: THE FOLLOWING BYPASS CAPS
ARE 0.1uF
NOTE: THE FOLLOWING BYPASS CAPS ARE TO
BE PLACED IN PARALLEL WITH EVERY OTHER
PULL UP RESISTOR
VTT_RLD
RLDC_A8
RLDC_A21
RLDC_A20
RLDC_A6
RLDC_A9
R71
R67
R77
R69
R73
RN5A
RN5B
RN5C
RN5D
RN5E
RN5F
RN5G
RN5H
1
2
3
4
5
6
7
8
16 56
15 56
14 56
13 56
12 56
11 56
10 56
9 56
QDRII_D8
QDRII_D9
QDRII_D10
QDRII_D11
QDRII_D12
QDRII_D13
QDRII_D14
QDRII_D15
RN3A
RN4B
RN4C
RN4D
RN6A
RN6B
RN6C
RN6D
1
2
3
4
1
2
3
4
16 56
15 56
14 56
13 56
16 56
15 56
14 56
13 56
R194
R195
56.2
56.2
QDRII_D16
QDRII_D17
0.1uF x 4
CN10
8
2
6
4
0.1uF x 4
8
2
6
4
QDRII_D0
QDRII_D1
QDRII_D2
QDRII_D3
QDRII_D4
QDRII_D5
QDRII_D6
QDRII_D7
56.2
56.2
56.2
56.2
56.2
QDRII_BWSn0
QDRII_BWSn1
QDRII_WPSn
QDRII_ODT
QDRII_RPSn
QDRII_A20
QDRII_A18
QDRII_A21
RN3D
RN3E
RN3F
RN6H
RN3C
RN3H
RN3G
RN3B
4
5
6
8
3
8
7
2
13 56
12 56
11 56
9 56
14 56
9 56
10 56
15 56
QDRII_A0
QDRII_A1
QDRII_A2
QDRII_A3
QDRII_A4
QDRII_A5
QDRII_A6
QDRII_A7
RN4F
RN4A
RN4G
RN4E
RN4H
RN6G
RN6F
RN6E
6
1
7
5
8
7
6
5
11 56
16 56
10 56
12 56
9 56
10 56
11 56
12 56
QDRII_A8
QDRII_A9
QDRII_A10
QDRII_A11
QDRII_A12
QDRII_A13
QDRII_A14
QDRII_A15
RN7C
RN7E
RN7F
RN7H
RN7A
RN7B
RN7D
RN7G
3
5
6
8
1
2
4
7
14 56
12 56
11 56
9 56
16 56
15 56
13 56
10 56
R201
R200
R184
56.2
56.2
56.2
QDRII_A16
QDRII_A17
QDRII_A19
VTT_QDRII
CN6
1
7
3
5
0.1uf x 4
8
2
6
4
CN2
1
7
3
5
0.1uf x 4
8
2
6
4
QDRII_D[17:0]
QDRII_D[17:0]
17,19
QDRII_A[21:0]
QDRII_A[21:0]
17,19
QDRII_BWSn0
QDRII_BWSn1
QDRII_WPSn
QDRII_RPSn
QDRII_BWSn0 17,19
QDRII_BWSn1 17,19
QDRII_WPSn 17,19
QDRII_RPSn 10,19
QDRII_ODT
QDRII_ODT
QDRII_CQ_P
QDRII_CQ_N
QDRII_CQ_P
QDRII_CQ_N
0.1uf x 4
8
2
6
4
CN1
1
7
3
5
0.1uf x 4
8
2
6
4
RLDC_QK_N[1:0]
RLDC_A[22:0]
RLDC_BA[2:0]
RLDC_CSn
RLDC_WEn
RLDC_REFn
RLDC_QVLD
CN5
1
7
3
5
0.1uf x 4
8
2
6
4
CN3
1
7
3
5
0.1uf x 4
8
2
6
4
17,19
17,19
17,19
RLDRAM II INTERFACE
RLDC_QK_P[1:0]
CN4
1
7
3
5
E
RLDC_QK_P[1:0]
14,20
RLDC_QK_N[1:0]
14,20
RLDC_A[22:0]
10,14,20
RLDC_BA[2:0]
14,20
D
RLDC_CSn 14,20
RLDC_WEn 14,20
RLDC_REFn 14,20
RLDC_QVLD 14,20
C
1.8V
B
C407
C332
C380
C403
C335
C405
C336
C360
C372
C364
0.1uF
0.1uF
0.1uF
0.1uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C347
C391
C392
C404
C389
C350
C351
C339
0.1uF
0.1uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C344
C330
C355
C406
C375
C333
C334
C337
0.01uF
0.01uF
0.01uF
0.01uF
4.7nF
4.7nF
4.7nF
4.7nF
B
VDDQ_QDRII
VDDQ_QDRII
A
Title
Size
B
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
21
of
1
29
B
8
7
6
5
SSRAM
2.5V
4
3
2
1
SSRAM & FLASH
2.5V
J3
J9
K3
K9
L3
L9
M3
M9
N3
N9
C3
C9
D3
D9
E3
E9
F3
F9
G3
G9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U3
E
R6
P6
A2
A10
B2
B10
N6
P3
P4
P8
P9
P10
P11
R3
R4
R8
R9
R10
R11
B1
A1
B11
C10
P2
R2
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
D
C
0
SSRAM_CLK
B6
SSRAM_OEn
SSRAM_CE1n
SSRAM_CE2
SSRAM_CE3n
SSRAM_MODE
B8
A3
B3
A6
R1
SSRAM_BWn0
SSRAM_BWn1
SSRAM_BWn2
SSRAM_BWn3
SSRAM_BWEn
B5
A5
A4
B4
A7
SSRAM_GWn
B7
A8
SSRAM_ADSCn
B9
SSRAM_ADSPn
A9
SSRAM_ADVn
H11
SSRAM_ZZ
R147
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC_144M
NC_288M
NC_576M
NC_1G
NC_A
NC_B
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CLK
OE_n
CE1_n
CE2
CE3_n
MODE
BWA_n
BWB_n
BWC_n
BWD_n
BWE_n
DQPA
DQPB
DQPC
DQPD
GW_n
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
ADSC_n
ADSP_n
ADV_n
ZZ
2.5V
TCK
TDI
TDO
TMS
H2
N7
L5
K7
K6
K5
J7
J6
J5
H7
H6
H5
G7
G6
G5
F7
C8
F6
L6
F5
E7
E6
E5
D7
D6
D5
C7
C6
C5
C4
M5
L7
N8
N4
M7
M6
B
1.8V
PC28FxxxP30B85
FLASH
J10
J11
K10
K11
L10
L11
M10
M11
D10
D11
E10
E11
F10
F11
G10
G11
D1
D2
E1
E2
F1
F2
G1
G2
J1
J2
K1
K2
L1
L2
M1
M2
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
N11
C11
C1
N1
SSRAM_DQP0
SSRAM_DQP1
SSRAM_DQP2
SSRAM_DQP3
R146
R148
R179
R178
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
FLASH_CLK
E6
FLASH_RESETn
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_ADVn
FLASH_WPn
D4
B4
F8
G8
F6
C6
1.00K
1.00K
1.00K
1.00K
VPP
A1
A2
VCC
A3
VCC
A4
A5
VCCQ
A6
VCCQ
A7
VCCQ
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
NC(64M)/A23
D13
NC(64M,128M)/A24 D14
NC/A25(512M)
D15
CLK
WAIT
RESET#
CE#
OE#
WE#
ADV#
WP#
GND
GND
GND
GND
RFU0
RFU1
RFU2
RFU3
RFU4
SHARED BUS
A4
FSM_D[31:0]
A6
H3
FSM_D[31:0]
FSM_A[26:0]
FSM_A[26:0] 10,16,17,23
2.5V
D5
D6
G4
SSRAM INTERFACE
SSRAM_BWn[3:0]
F2
E2
G3
E4
E5
G5
G6
H7
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
E1
E3
F3
F4
F5
H5
G7
E7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
F7
FLASH_RDYBSYn
SSRAM_BWn[3:0]
SSRAM_OEn
SSRAM_BWEn
SSRAM_ADVn
SSRAM_ADSCn
SSRAM_ADSPn
SSRAM_CE1n
SSRAM_CLK
SSRAM_MODE
SSRAM_ZZ
SSRAM_GWn
17
SSRAM_OEn 17
SSRAM_BWEn 17
SSRAM_ADVn 17
SSRAM_ADSCn 17
SSRAM_ADSPn 17
SSRAM_CE1n 17
SSRAM_CLK 17
SSRAM_MODE 23
SSRAM_ZZ 23
SSRAM_GWn 23
FLASH INTERFACE
D
FLASH_RESETn
FLASH_WEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_CEn
FLASH_CLK
FLASH_ADVn
B2
H2
H4
H6
H1
G2
F1
E8
B8
E
17,23
FLASH_RESETn 17,23
FLASH_WEn 17,23
FLASH_OEn 17,23
FLASH_RDYBSYn 17,23
FLASH_CEn 17,23
FLASH_CLK 17,23
FLASH_ADVn 17,23
2.5V
FSM_A26
R163
R162
R150
R149
R151
10K
10K
10K
10K
10K
FLASH_WPn
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RDYBSYn
R156
10K
FLASH_RESETn
C
PC28F00AP30BF
A11
C2
H1
P1
H3
H9
H10
N2
N5
N10
2.5V
R176
DNI
R153
10.0K
R169
10.0K
R166
DNI
PLACE NEAR FLASH
1.8V
SSRAM_MODE
SSRAM_GWn
SSRAM_CE2
SSRAM_CE3n
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R7
P5
P7
R5
U2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
D4
D8
E4
E8
F4
F8
G4
G8
H4
H8
J4
J8
K4
K8
L4
L8
M4
M8
FLASH 512Mb (32M X 16)
IS61VPS51236A
R177
10.0K
R161
DNI
R173
DNI
2.5V
C295
C281
C305
C287
C290
C291
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
B
R165
10.0K
2.5V
2.5V
R167
R164
10K
10K
SSRAM_CE2
SSRAM_CE3n
C288
C309
C298
C319
C301
C317
C284
C299
C282
C294
0.1uF
0.1uF
0.1uF
0.1uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
22
of
1
29
B
8
7
6
5
4
3
2
MAX II
U10A
E
FPGA_DATA0
FPGA_DCLK
FPGA_CONF_DONE
FPGA_STATUSn
FPGA_CONFIGn
D3
C2
E3
C3
E4
D2
E5
D1
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
F3
E2
F4
E1
F5
F2
F6
F1
SENSE_SDO
SENSE_ADC_F0
SENSE_SDI
SENSE_SCK
SENSE_CS0n
SENSE_CS1n
D
IOB1_34
IOB1_35
IOB1_36
IOB1_37
IOB1_38
IOB1_39
IOB1_40
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
H1
MAX_TO_STRATIX4
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
G3
G2
G4
G1
G5
H2
IOB1_41
IOB1_42
IOB1_43
IOB1_44
IOB1_45
IOB1_46
IOB1_47
IOB1_48
IOB1_24
IOB1_49
H5
J5
MAX_CLK
TSENSE_ALERTn
IOB1/GCLK0
IOB1/GCLK1
TCK
TDI
TDO
TMS
H3
J1
H4
J2
J4
K1
J3
K2
CLK50_EN
CLK100_EN
CLK66_EN
CLK125_EN
MAX_PHASE_CLK0
MAX_PHASE_CLK180
L1
K5
L2
K4
M1
K3
M2
PHASE0
PHASE90
PHASE180
PHASE270
SSRAM_MODE
SSRAM_ZZ
SSRAM_GWn
FPGA_DATA1
FPGA_DATA2
FPGA_DATA3
FPGA_DATA4
FPGA_DATA5
FPGA_DATA6
FPGA_DATA7
L5
M3
L4
N1
L3
N2
M4
N3
C13
B16
C12
A15
D12
B14
C11
B13
D11
A13
E11
B12
C10
A12
D10
B11
E10
A11
TSENSE_SMB_DATA
TSENSE_SMB_CLK
MAX_DIP3
OVERTEMP
FACTORY_CONFIGn
B10
C9
A10
D9
B9
MAX II
BANK2
IOB2_50
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
IOB2_74
IOB2_75
IOB2_76
IOB2_77
IOB2_78
IOB2_79
IOB2_80
IOB2_81
IOB2_58
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_82
IOB2_83
IOB2_85
IOB2_86
IOB2_87
IOB2_88
IOB2_89
IOB2_66
IOB2_67
IOB2_90
IOB2_91
IOB2_92
IOB2_93
IOB2_94
IOB2_95
IOB2_96
IOB2_97
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
P2
P3
L6
M5
N4
IOB2_98
IOB2_99
IOB2_100
IOB2_101
IOB2_102
JTAG_TCK
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
JTAG_TMS
E9
A9
A8
B8
E8
A7
D8
B7
B
IOB3_103
IOB3_104
IOB3_105
IOB3_106
IOB3_107
IOB3_108
IOB3_109
IOB3_110
L16
K13
K15
K12
K16
MAX_CSn
MAX_OEn
MAX_WEn
MAX_DIP2
J15
J14
CLKIN_50
CLKIN_MAX_100
IOB3_127
IOB3_128
IOB3_129
IOB3_130
IOB3_131
IOB3_132
IOB3_133
IOB3_134
IOB3_111
IOB3_112
IOB3_113
IOB3_114
IOB3_115
IOB3_116
IOB3_117
IOB3_118
IOB3_135
IOB3_119
IOB3_120
IOB3_121
IOB3_122
IOB3_123
IOB3_143
IOB3_144
IOB3_145
IOB3_146
IOB3_147
IOB3_148
IOB3_149
IOB3_150
IOB3_125
IOB3_126
J12
H12
2.5V
R191
1.00K
3.3V_PG
2.5V_HSMC_PG
C366
0.01uF
2
EN
VCC
GND
OUT
4
3
100MHz
CLKIN_MAX_100
C358
0.01uF
C361
4.7uF
SSRAM_ZZ
SSRAM_GWn
SSRAM_MODE
OVERTEMPn
IOB3/GLCK2
IOB3/GCLK3
IOB3_137
IOB3_138
IOB3_139
IOB3_140
IOB3_141
IOB3_142
IOB3_151
IOB3_152
IOB3_153
IOB3_154
IOB3_155
J16
J13
H16
H13
H15
H14
G16
G12
FSM_A26
MAX_ERROR
MAX_LOAD
MAX_FACTORY
MAX_USER
G15
F16 HSMA_PSNTn
G13 HSMB_PSNTn
F15
G14
MAX_EMB is labeled as
E16
"USER_1" on the board
F11
E15
F12
D16
F13
D15
F14
D14
E12
MAX_EMB
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
C15
E13
C14
E14
D13
FSM_D31
FSM_A25
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
P4
R1
P5
T2
N5
R3
P6
R4
CLK50_EN
CLK66_SEL
CLK66_EN
CLK125_EN
CLK100_EN
CLKIN_50
MAX_CLK
JTAG_TCK
JTAG_TMS
JTAG_EPM2210_TDO
JTAG_FPGA_TDO
CLK50_EN 11
CLK66_SEL 11,25
CLK66_EN 11
CLK125_EN 11
CLK100_EN 11
CLKIN_50 10,11
MAX_CLK 16
PHASE0
PHASE90
PHASE180
PHASE270
MAX_PHASE_CLK0
MAX_PHASE_CLK180
MAX_PB
FPGA_DATA[7:0]
PHASE0 5
PHASE90 3,5
PHASE180 5
PHASE270 3,5
MAX_PHASE_CLK0 6
MAX_PHASE_CLK180 7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
N6
T4
M6
R5
P7
T5
N7
R6
FSM_D16
FSM_D17
M7
T6
R7
P8
T7
N8
R8
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
SYS_RESETn
IOB4_180
IOB4_181
IOB4_182
IOB4_183
IOB4_184
IOB4_185
IOB4_187
IOB4_164
IOB4_165
IOB4_166
IOB4_167
IOB4_168
IOB4_169
IOB4_170
IOB4_171
IOB4_188
IOB4_189
IOB4_190
IOB4_191
IOB4_192
IOB4_193
IOB4_194
IOB4_195
IOB4_172
IOB4_173
IOB4_196
IOB4_197
IOB4_198
IOB4_199
IOB4_200
IOB4_201
IOB4_202
IOB4_203
IOB4_175
IOB4_176
IOB4_177
IOB4_178
IOB4_179
IOB4_204
IOB4/DEV_CLRn IOB4_205
IOB4/DEV_OE
IOB4_206
M9
M8
MAX_DIP0
MAX_DIP1
SSRAM_ZZ 22
SSRAM_GWn 22
SSRAM_MODE 22
N9
T8
T9
R9
P9
T10
FSM_A0
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
R10
FSM_A7
M10
T11
N10
R11
P10
T12
M11
R12
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
N11
T13
P11
R13
M12
R14
N12
T15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FPGA_DCLK
FPGA_CONF_DONE
FPGA_STATUSn
FPGA_CONFIGn
HSMA_PSNTn
HSMB_PSNTn
JTAG_TCK 12,13,27
JTAG_TMS 12,13,27
JTAG_EPM2210_TDO 12
JTAG_FPGA_TDO 12
FPGA_DATA[7:0]
HSMA_PSNTn 27
HSMB_PSNTn 27
CURRENT SENSE
H7
H9
J8
J10
G6
F7
K11
L10
A1
A16
B2
B15
G7
G8
G9
G10
K7
K8
K9
K10
R2
R15
T1
T16
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
P12
FSM_A24
R16 RESET_CONFIGn
P13
FSM_A6
SENSE_SDO 8
SENSE_ADC_F0 8
SENSE_SDI 8
SENSE_SCK 8
SENSE_CS0n 8
SENSE_CS1n 8
FPGA OSCILLATOR CONTROL
2.5V
MAX II
Power
TSENSE_ALERTn
OVERTEMPn
OVERTEMP
MAX_TO_STRATIX4
TSENSE_SMB_DATA
TSENSE_SMB_CLK
H8
H10
J7
J9
K6
L7
G11
F10
C
TSENSE_ALERTn 8
OVERTEMPn 8
OVERTEMP 8
MAX_TO_STRATIX4 16
TSENSE_SMB_DATA 8
TSENSE_SMB_CLK 8
USER I/O's
PGM[3:0]
2.5V
MAX_DIP[6:0]
C1
H6
J6
P1
RESET_CONFIGn
A3
A14
F8
F9
FACTORY_CONFIGn
MAX_CSn
MAX_OEn
MAX_WEn
C16
H11
J11
P16
PGM[3:0] 25
MAX_DIP[6:0] 25
RESET_CONFIGn
L8
L9
T3
T14
25
B
MAX_ERROR 25
MAX_LOAD 25
MAX_FACTORY 25
MAX_USER 25
MAX_EMB
MAX_PB
2.5V_HSMC_PG
SYS_RESETn
MAX_EMB 25
MAX_PB 25
2.5V_HSMC_PG 4
SYS_RESETn 12,25
EPM2210_F256FBGA
2.5V_FPGA_PG
VDDQ_QDRII_PG
1.8V_PG
3.3V_PG
EPM2210_F256FBGA
25
FACTORY_CONFIGn
MAX_CSn 14
MAX_OEn 14
MAX_WEn 14
MAX_ERROR
MAX_LOAD
MAX_FACTORY
MAX_USER
EPM2210_F256FBGA
2.5V_FPGA_PG 4
VDDQ_QDRII_PG 4
1.8V_PG 7
3.3V_PG 3
Place near MAX II
2.5V
D
12
FPGA_DCLK 12
FPGA_CONF_DONE 12,25
FPGA_STATUSn 12,13
FPGA_CONFIGn 12
SENSE_SDO
SENSE_ADC_F0
SENSE_SDI
SENSE_SCK
SENSE_CS0n
SENSE_CS1n
U10E
MAX II
BANK4
IOB4_156
IOB4_157
IOB4_158
IOB4_159
IOB4_160
IOB4_161
IOB4_162
IOB4_163
E
FLASH_RESETn 17,22
FLASH_WEn 17,22
FLASH_OEn 17,22
FLASH_RDYBSYn 17,22
FLASH_CLK 17,22
FLASH_CEn 17,22
FLASH_ADVn 17,22
CONFIGURATION INTERFACE
CLOCK INTERFACE
C7
A4
E6
B4
D6
C4
C6
B3
C5
A2
D5
B1
D4
FLASH_RESETn
FLASH_WEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_CLK
FLASH_CEn
FLASH_ADVn
L7
DNI
Y2
C8
A6
B6
E7
A5
D7
B5
FSM_D[31:0] 17,22
FSM_A[26:0] 10,16,17,22
FLASH INTERFACE
U10D
MAX II
BANK3
N16
PGM3
L13
FLASH_ADVn
M15
FLASH_RESETn
L12
FLASH_WEn
M16
FLASH_OEn
FLASH_RDYBSYn L11
L15
FLASH_CLK
K14
FLASH_CEn
2.5V
MAX_PB is labeled as
"USER_1/USER_2" on the
board
U10C
P14
N13
P15
M14
N14
M13
N15
L14
2.5V_FPGA_PG
VDDQ_QDRII_PG
1.8V_PG
1
EPM2210_F256FBGA
FSM_D18
PGM0
PGM1
PGM2
MAX_DIP4
MAX_DIP5
MAX_DIP6
CLK66_SEL
FSM_D[31:0]
FSM_A[26:0]
EPM2210_F256FBGA
C
SHARED BUS
U10B
MAX II
BANK1
1
2.5V
A
C321
C324
C338
C370
C371
C323
C322
C362
C377
C357
C346
C384
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C387
C348
C396
C368
C399
C378
C367
C385
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
23
of
1
29
B
8
7
6
5
4
3
2
1
10/100/1000 Ethernet
SGMII Mode (default)
U15A
2.5V
J8
C394
0.01uF
TD1_P
TD1_N
TD2_P
TD2_N
TD3_P
TD3_N
GND
4
5
7
8
10
29
31
33
34
39
41
42
43
ENET_MDIO
ENET_MDC
ENET_INTn
24
25
23
HFJ11-1G02E
OUT
NC2
VCC
ENET_XTAL_25MHZ
3.3V
1
2
3
4
CS
VCC
CLK
NC1
DIN
NC2
DOUT
GND
EPAD/GND
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
COL
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
ENET_GTX_CLK
ENET_TX_CLK
ENET_TX_EN
ENET_TX_ER
11
12
14
16
17
18
19
20
ENET_TX_D0
ENET_TX_D1
ENET_TX_D2
ENET_TX_D3
ENET_TX_D4
ENET_TX_D5
ENET_TX_D6
ENET_TX_D7
2
94
3
ENET_RX_CLK
ENET_RX_DV
ENET_RX_ER
95
92
93
91
90
89
87
86
ENET_RX_D0
ENET_RX_D1
ENET_RX_D2
ENET_RX_D3
ENET_RX_D4
ENET_RX_D5
ENET_RX_D6
ENET_RX_D7
84
83
ENET_RX_CRS
ENET_RX_COL
79
80
82
81
77
75
ENET_S_CLKP
ENET_S_CLKN
ENET_TX_P
ENET_TX_N
ENET_RX_P
ENET_RX_N
68
69
70
73
74
76
ENET_LED_TX
ENET_LED_RX
ENET_LED_DUPLEX
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
ETHERNET INTERFACE
ENET_TX_D[7..0]
E
ENET_TX_D[7..0] 10,14
ENET_GTX_CLK
ENET_TX_CLK
ENET_TX_ER
ENET_TX_EN
ENET_MDC
ENET_GTX_CLK 14
ENET_TX_CLK 14
ENET_TX_ER 14
ENET_TX_EN 14
ENET_MDC 14
ENET_RX_D[7..0]
ENET_RX_D[7..0]
ENET_RX_DV
ENET_MDIO
ENET_RESETn
ENET_RX_ER
ENET_RX_CRS
ENET_RX_COL
ENET_RX_CLK
14
ENET_RX_DV 14
ENET_MDIO 14
ENET_RESETn 14
ENET_RX_ER 14
ENET_RX_CRS 14
ENET_RX_COL 14
ENET_RX_CLK 14
ENET_INTn
D
ENET_INTn 14
ENET_LED_LINK1000
ENET_LED_LINK1000
14
ETHERNET SGMII INTERFACE
ENET_TX_P
ENET_TX_N
ENET_TX_P 10
ENET_TX_N 10
ENET_RX_P
ENET_RX_N
ENET_S_CLKP
ENET_S_CLKN
ENET_RX_P 14
ENET_RX_N 14
ENET_S_CLKP 10
ENET_S_CLKN 10
EEPROM_CS
EEPROM_CLK
EEPROM_DIN
EEPROM_DOUT
EEPROM_CS 14
EEPROM_CLK 14
EEPROM_DIN 14
EEPROM_DOUT 14
C
88E1111
2.5V
U17
EEPROM_CS
EEPROM_CLK
EEPROM_DIN
EEPROM_DOUT
R218
4.7K
TRST_N
TCK
TDI
TDO
TMS
JTAG
R224
4.99K
C
125CLK
XTAL1
XTAL2
VSSC
47
49
44
50
46
25MHz
RXCLK
RX_DV
RX_ER
RSET
SEL_FREQ
22
55
54
53
X1
EN
NC1
GND
HSDAC_P
HSDAC_N
30
56
R27
10.0K
4
5
6
MDIO
MDC
INT_N
37
38
ENET_RSET
1
2
3
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
TEST
12
11
3.3V
3
6
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
MGMT
D
1
2
8
4
9
7
8
7
6
5
9
2.5V
93AA46AT-I/MC
U15B
32
36
35
40
45
78
B
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
13
51
72
66
52
0.01uF
ENET_LED_LINK10
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
VDDOH
VDDOH
VDDOH
C430
TD0_P
TD0_N
9
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
5
21
88
96
0.01uF
VCC
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
ENET_LED_TX
65
64
63
61
60
59
58
MDI INTERFACE
C414
0.01uF
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
2.5V
GND_TAB
GND_TAB
C436
R223
R222
R214
R206
R220
R217
R204
R198
ENET_LED_RX
ENET_LED_LINK10
GMII/MII/TBI INTERFACE
ENET_MDIO
ENET_MDC
ENET_INTn
ENET_RESETn
GTX_CLK
TX_CLK
TX_EN
TX_ER
VDDO
VDDO
VDDO
VDDO
4.7K
4.7K
4.7K
4.7K
26
48
R227
R226
R228
R225
COMA
RESET_N
VDDOX
VDDOX
E
ENET_RESETn
SGMII INTERFACE
2.5V
27
28
NC1
NC2
97
D11
Green_LED
1.1V
ENET_LED_TX
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
1
6
10
15
57
62
67
71
85
R243
2.5V
220
D12
Green_LED
ENET_LED_RX
R242
220
D10
Green_LED
ENET_LED_DUPLEX
R244
B
220
D9
Green_LED
VSS
ENET_LED_LINK1000 R245
220
88E1111
D8
Green_LED
ENET_LED_LINK100
R246
220
Place near 88E1111 PHY
2.5V
A
D7
Green_LED
1.1V
ENET_LED_LINK10
C438
C457
C454
C427
C412
C410
C428
C433
C456
C455
C413
C411
C434
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Size
B
Date:
7
6
5
4
220
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
8
R247
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
24
of
1
29
B
8
7
6
5
RES_MAX_ERROR R298
MAX_ERROR
3
2
1
User IO & Connector
3.3V
D20
Red_LED
4
100, 1%
3.3V
D22
FPGA_CONF_DONE
D17
E
MAX_LOAD
R292
RES_MAX_LOAD
56.2
HSMA_RX_LED
Green_LED
D18
MAX_FACTORY
RES_MAX_FACTORY R296
56.2
R297
RES_MAX_USER
Green_LED
D15
RES_MAX_EMB
Green_LED
R291
56.2
RESn_HSMB_RX_LED R186
56.2
56.2
HSMB_TX_LED
MAX_EMB is labeled as
"USER_1" on the board
RESn_HSMB_TX_LED R170
56.2
2.5V
1
2
RESET_CONFIGn R68
2
SYS_RESETn
10.0K
R135
2.5V
1.00k
R340
1.00k
2
C2
8
PGM1
1
PGM3
P2
C2
P8
4
C1
1
P4
C1
P1
R329
56.2
RESn_LED3
R330
56.2
USER_PB[3:0]
PGM2 R338
2
R96
FACTORY_CONFIGn
10.0K
USER_LED7
1
1.00k
2
CPU_RESETn
R134
B4
R331
R332
56.2
RESn_LED6
R333
56.2
RESn_LED7
R334
56.2
2
MAX_PB
R112
PBSwitch
S9
1
2
947705-012_knob
FPGA_CONF_DONE
2.5V
USER_PB0
R141
10.0K
USER_PB1
R140
10.0K
USER_PB2
R139
10.0K
2
USER_PB3
R138
10.0K
S6
1
2.5V
SEG1_DIG_SEL1
SEVEN_SEG_SEL[4:1]
14
C
SEVEN_SEG_A 14
SEVEN_SEG_B 14
SEVEN_SEG_C 14
SEVEN_SEG_D 14
SEVEN_SEG_E 14
SEVEN_SEG_F 14
SEVEN_SEG_G 14
SEVEN_SEG_DP 14
SEVEN_SEG_MINUS 14
2.5V
Q5
R306
22
SEVEN_SEG_SEL1
FDV305N
2.5V
SW4
16
15
14
13
12
11
10
9
SEG1_DIG_SEL2
QUAD_7SEG_M2212RI
U29
Q2
SEVEN_SEG_SEL2
FDV305N
1
10
4
6
SEG1_DIG_SEL1
SEG1_DIG_SEL2
SEG1_DIG_SEL3
SEG1_DIG_SEL4
2.5V
DIGIT1
DIGIT2
DIGIT3
DIGIT4
1
2
3
4
5
6
7
8
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
USER_DIPSW4
USER_DIPSW5
USER_DIPSW6
USER_DIPSW7
RN2H
RN2G
RN2F
RN2E
RN2D
RN2C
RN2B
RN2A
8
7
6
5
4
3
2
1
Q3
SEVEN_SEG_MINUS
R127
220 LED_MINUS
FDV305N
SEVEN_SEG_A
SEVEN_SEG_B
SEVEN_SEG_C
SEVEN_SEG_D
SEVEN_SEG_E
SEVEN_SEG_F
SEVEN_SEG_G
SEVEN_SEG_DP
R124
R121
R133
R117
R130
R115
R118
R116
220
220
220
220
220
220
220
220
HSMA_RX_LED
HSMA_TX_LED
HSMB_RX_LED
HSMB_TX_LED
HSMA_RX_LED
HSMA_TX_LED
HSMB_RX_LED
HSMB_TX_LED
15
10
14
16
B
DIP_SW_8
DP
G
F
E
D
C
16
15
14
13
12
11
10
9
5
7
9
2
8
A
B
3
11
12
ca
13
2.5V
SEG1_DIG_SEL4
14
an
R315
22
HSMC INTERFACE
9 10K
10 10K
11 10K
12 10K
13 10K
14 10K
15 10K
16 10K
SEG1_DIG_SEL3
FDV305N
SPEAKER_OUT 15,26
SEVEN_SEG_A
SEVEN_SEG_B
SEVEN_SEG_C
SEVEN_SEG_D
SEVEN_SEG_E
SEVEN_SEG_F
SEVEN_SEG_G
SEVEN_SEG_DP
SEVEN_SEG_MINUS
S7
2
12,23
PGM[3:0] 23
SPEAKER_OUT
SEVEN_SEG_SEL[4:1]
2
1
R317
22
Q4
FPGA_CONF_DONE
SEVEN-SEG INTERFACE
S8
1
2.5V
SEVEN_SEG_SEL3
D
RESET_CONFIGn 23
SYS_RESETn 12,23
FACTORY_CONFIGn 23
MAX_PB 23
CPU_RESETn 16
CLK66_SEL 11,23
PGM[3:0]
10.0K
10,17
17
MAX_DIP[6:0] 23
RESET_CONFIGn
SYS_RESETn
FACTORY_CONFIGn
MAX_PB
CPU_RESETn
CLK66_SEL
10.0K
MAX_PB is labeled as
"USER_1/USER_2" on the board
R316
22
USER_LED[7:0]
MAX_DIP[6:0]
RESn_LED5
10
USER_DIPSW[7:0]
USER_LED[7:0]
56.2
S3
1
B
USER_PB[3:0]
Green_LED
D23
1.00k
S4
PGM0 R341
MAX_ERROR 23
MAX_LOAD 23
MAX_FACTORY 23
MAX_USER 23
MAX_EMB 23
USER_DIPSW[7:0]
Green_LED
94HCB16WT
C
RESn_LED2
MAX_ERROR
MAX_LOAD
MAX_FACTORY
MAX_USER
MAX_EMB
S2
SW5
R339
USER I/O's
Green_LED
D24
10.0K
USER_LED6
2.5V
56.2
RESn_LED4
USER_LED5
S5
1
R328
Green_LED
D25
S1
D
RESn_LED1
E
Green_LED
D26
USER_LED4
Green_LED
56.2
Green_LED
D27
USER_LED3
Green_LED
D3
R327
Green_LED
D28
USER_LED2
Green_LED
D4
HSMB_RX_LED
RESn_LED0
Green_LED
D29
USER_LED1
RESn_HSMA_TX_LED R289
56.2
D30
USER_LED0
56.2
Green_LED
D13
Green_LED
D19
MAX_EMB
RESn_HSMA_RX_LED R290
HSMA_TX_LED
MAX_USER
3.3V
Green_LED
D14
MAX II CONTROL
SW2
1
MAX_DIP0
2
MAX_DIP1
3
MAX_DIP2
4
MAX_DIP3
5
MAX_DIP4
6
MAX_DIP5
7
MAX_DIP6
8
CLK66_SEL
2.5V
RN1H
RN1G
RN1F
RN1E
RN1D
RN1C
RN1B
RN1A
8
7
6
5
4
3
2
1
9 10K
10 10K
11 10K
12 10K
13 10K
14 10K
15 10K
16 10K
SEVEN_SEG_SEL4
A
DIP_SW_8
LED_A
LED_B
LED_C
LED_D
LED_E
LED_F
LED_G
LED_DP
Title
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
25
of
1
29
B
8
7
6
5
4
3
2
1
Speaker, LCD & Display Connectors
2x16 LED DISPLAY INTERFACE
PLACE NEAR FPC/FFC CONNECTOR
E
1.00k
B6
2x7 HDR
C68
C67
C292
0.1uF
0.01uF
0.1uF
+
2
B5
12V
LCD1_CSn
R211 LCD1_RSTn
LCD1_D_Cn
LCD1_WEn
LCD1_E_RDn
LCD1_DATA0
LCD1_DATA1
LCD1_DATA2
LCD1_DATA3
LCD1_DATA4
LCD1_DATA5
LCD1_DATA6
2.5V
LCD1_DATA7
1
2.5V
C297
10uF
25V
Tantalum
LCM-S01602DSR/C
SPACER5
B3
V5
MSPM-7-01
SPACER6
MSPM-7-01
D
128x64 LCD
V1
V2
SPACER1
SPACER3
MSPM-3-01
SPACER2
MSPM-3-01
SPACER4
MSPM-3-01
MSPM-3-01
V3
V4
V5
LCD1_BS1
LCD1_SERn
2 x 16 Display Connector
5.0V
J23
1
3
5
7
9
11
13
LCD_WEn
LCD_DATA0
LCD_DATA2
LCD_DATA4
LCD_DATA6
C
1
3
5
7
9
11
13
2
4
6
8
10
12
14
2
4
6
8
10
12
14
LCD_DATA[7:0]
J27
LCD_D_Cn
LCD_CSn
LCD_DATA1
LCD_DATA3
LCD_DATA5
LCD_DATA7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
E
15
LCD_CSn 15
LCD_D_Cn 15
LCD_WEn 15
128x64 LCD DISPLAY INTERFACE
LCD1_DATA[7:0]
LCD1_DATA[7:0]
LCD1_SERn
LCD1_CSn
LCD1_RSTn
LCD1_D_Cn
LCD1_WEn
LCD1_E_RDn
LCD1_BS1
14
LCD1_SERn 14
LCD1_CSn 14
LCD1_RSTn 15
LCD1_D_Cn 14
LCD1_WEn 14
LCD1_E_RDn 14
LCD1_BS1 14
SPEAKER_OUT
FPC_FFC_30PIN
R212
LCD_DATA[7:0]
LCD_CSn
LCD_D_Cn
LCD_WEn
D
SPEAKER_OUT 15
2.5V
10.0K
C
R1000
2.94K
HDR2X7
12V
Short 12V to old -12V rail for new positive bias voltage LCD
C276
DNI
+12SW
L6
1
2
-12SW
1
DNI
5
R208
3.32K
2.1V
V3
7.3V
V2
R209
15.4K
R210
2.94K
8.3V
V1
R213
DNI
2.5V
12V
VIN
SW1
GND
SHDN NFB
R152
80.6K
DNI
D34
U34
4
2
1.0V
V4
R207
DNI
DNI
C289
10uF
9.3V
V5
R154
8.06K
L5
1
2
3
R1001
3.01K
C293
C415
1uF
10uF
C418
1uF
C419
1uF
C420
1uF
C421
1uF
-12FB
R155
10.0K
DNI
Above power circuit was reworked to support a new graphics LCD with +12V bias voltages, not the original -12V voltages.
FOR USE WITH NEW LCDF-55472 Series ONLY (old -12V circuit for use only with F-51852 Series ONLY)
B
B
J25
R1
100
RED
1
BLACK
2
1
2
2.5V
HDR2x1
C13
Graphics LCD Backlight Power Header (Hook black wire to pin 2)
1.0uF
R4
U1
C11
R10
SPEAKER_OUT
100, 1%
SPEAKER
C17
0.22uF
C18
A
R5
1
2
3
4
SP_INp
20.0K SP_INn
R7
20.0K
0.1uF
2.5V
1.0uF
SHUTDOWN
BYPASS
IN+
IN-
VDD
VO2
VO1
GND
6
8 R3
5 R8
7
DNI
HDR4X1
4
3 4
2 3
1 2
1
J1
0
0
R9
DNI
LM4990
Title
Size
B
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-C1
Thursday, May 26, 2011
2
Rev
(6XX-41504R)
Sheet
26
of
1
29
C-1
8
7
6
5
4
3
2
High Speed Mezzanine (HSM) Interface
D
HSMA_TX_D_P0
HSMA_TX_D_N0
HSMA_TX_D_P1
HSMA_TX_D_N1
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P5
HSMA_TX_D_N5
C
HSMA_TX_D_P6
HSMA_TX_D_N6
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P10
HSMA_TX_D_N10
B
HSMA_TX_D_P11
HSMA_TX_D_N11
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_TX_D_P16
HSMA_TX_D_N16
A
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
12V
3.3V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
3.3V
ASP-122953-01
C542
10uF
C201
BANK 1
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
A
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
BANK 3
HSMA_SCL
JTAG_TMS
HSMA_JTAG_TDI
HSMA_CLK_IN0
HSMB_SDA
JTAG_TCK
HSMB_JTAG_TDO
HSMB_CLK_OUT0
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
HSMA_D1
HSMA_D3
HSMB_D0
HSMB_D2
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMB_TX_D_P0
HSMB_TX_D_N0
HSMA_RX_D_P1
HSMA_RX_D_N1
HSMB_TX_D_P1
HSMB_TX_D_N1
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMB_TX_D_P2
HSMB_TX_D_N2
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMB_TX_D_P3
HSMB_TX_D_N3
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMB_TX_D_P4
HSMB_TX_D_N4
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMB_TX_D_P5
HSMB_TX_D_N5
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMB_TX_D_P6
HSMB_TX_D_N6
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMB_TX_D_P7
HSMB_TX_D_N7
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_N1
10uF
HSMB_TX_D_P9
HSMB_TX_D_N9
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMB_TX_D_P10
HSMB_TX_D_N10
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMB_TX_D_P11
HSMB_TX_D_N11
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMB_TX_D_P12
HSMB_TX_D_N12
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMB_TX_D_P13
HSMB_TX_D_N13
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMB_TX_D_P14
HSMB_TX_D_N14
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMB_TX_D_P15
HSMB_TX_D_N15
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMB_TX_D_P16
HSMB_TX_D_N16
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMA_PSNTn
HSMB_CLK_OUT_P2
HSMB_CLK_OUT_N2
12V
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
3.3V
D16
Green_LED
HSMA_PSNTn
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
HSMB_TX_D_P8
HSMB_TX_D_N8
HSMA_RX_D_P9
HSMA_RX_D_N9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
R293
ASP-122953-01
3.3V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
BANK 1
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
B
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
BANK 3
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
HSMA_D0
HSMA_D2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
HSMA_SDA
JTAG_TCK
HSMA_JTAG_TDO
HSMA_CLK_OUT0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
161
162
163
164
165
166
167
168
169
170
171
172
E
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
HSMC JTAG INTERFACE
J9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HSMA_JTAG_TDO
HSMB_JTAG_TDO
6
4
HSMA_JTAG_TDI
HSMB_JTAG_TDI
HSMA_JTAG_TDI 12
HSMB_JTAG_TDI 12
E
HSMA_SDA 16
HSMA_SCL 16
HSMA_CLK_IN0 10
HSMA_CLK_OUT0 16
HSMA_CLK_IN_P[2:1]
HSMA_CLK_IN_N[2:1]
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
HSMB_D1
HSMB_D3
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMB_RX_D_P8
HSMB_RX_D_N8
HSMA_CLK_OUT_P[2:1]
HSMA_D[3:0]
HSMB_RX_D_P1
HSMB_RX_D_N1
HSMA_TX_D_P[16:0]
HSMA_TX_D_N[16:0]
HSMB_RX_D_P2
HSMB_RX_D_N2
HSMA_RX_D_P[16:0]
HSMB_RX_D_P3
HSMB_RX_D_N3
HSMA_RX_D_N[16:0]
HSMA_CLK_IN_P[2:1]
10
HSMA_CLK_IN_N[2:1]
10
HSMA_CLK_OUT_P[2:1]
10,16
HSMA_CLK_OUT_N[2:1]
10,16
D
HSMA_CLK_OUT_N[2:1]
HSMB_RX_D_P0
HSMB_RX_D_N0
HSMA_D[3:0] 15
HSMA_TX_D_P[16:0] 10,16
HSMA_TX_D_N[16:0] 10,16
HSMA_RX_D_P[16:0] 16
HSMA_RX_D_N[16:0]
16
HSMB_RX_D_P4
HSMB_RX_D_N4
HSMB_RX_D_P5
HSMB_RX_D_N5
HSMC PORT B
HSMB_RX_D_P6
HSMB_RX_D_N6
HSMB_SDA
HSMB_SCL
HSMB_RX_D_P7
HSMB_RX_D_N7
HSMB_CLK_IN0
HSMB_CLK_OUT0
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
HSMB_CLK_IN_P[2:1]
HSMB_CLK_IN0 10
HSMB_CLK_OUT0 16
HSMB_CLK_OUT_P[2:1]
HSMB_CLK_OUT_N[2:1]
HSMB_RX_D_P9
HSMB_RX_D_N9
HSMB_D[3:0]
12V
HSMB_RX_D_P13
HSMB_RX_D_N13
C409
C52
10uF
10uF
HSMB_RX_D_P14
HSMB_RX_D_N14
10
HSMB_CLK_OUT_P[2:1]
10,16
HSMB_CLK_OUT_N[2:1]
10,16
16
B
HSMB_RX_D_N[16:0]
3.3V
HSMB_CLK_IN_N[2:1]
HSMB_TX_D_N[16:0] 16
HSMB_RX_D_P[16:0]
HSMB_RX_D_P12
HSMB_RX_D_N12
10
HSMB_TX_D_P[16:0] 16
HSMB_TX_D_N[16:0]
HSMB_RX_D_P11
HSMB_RX_D_N11
HSMB_CLK_IN_P[2:1]
HSMB_D[3:0]
HSMB_TX_D_P[16:0]
HSMB_RX_D_P10
HSMB_RX_D_N10
C
HSMB_SDA 10
HSMB_SCL 14
HSMB_CLK_IN_N[2:1]
HSMA_PSNTn
HSMB_PSNTn
HSMB_RX_D_P[16:0]
16
HSMB_RX_D_N[16:0]
16
HSMA_PSNTn 23
HSMB_PSNTn 23
HSMB_RX_D_P15
HSMB_RX_D_N15
HSMB_RX_D_P16
HSMB_RX_D_N16
12V
HSMB_CLK_IN_P2
HSMB_CLK_IN_N2
HSMB_PSNTn
Title
D5
Green_LED
R189
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
56.2
5
JTAG_TCK 12,13,23
JTAG_TMS 12,13,23
HSMA_CLK_IN0
HSMA_CLK_OUT0
HSMB_SCL
JTAG_TMS
HSMB_JTAG_TDI
HSMB_CLK_IN0
56.2
3.3V
Size
B
Date:
7
JTAG_TCK
JTAG_TMS
HSMA_SDA
HSMA_SCL
HSMB_PSNTn
8
HSMA_JTAG_TDO 12
HSMB_JTAG_TDO 12
HSMC PORT A
161
162
163
164
165
166
167
168
169
170
171
172
J19
1
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
27
of
1
29
B
8
7
6
5
4
3
2
1
Decoupling 1
Place 6 vias minimum on each X2Y cap.
STANDOFF1
STANDOFF2
FPGA VCCL
VCCL
VCCL
STANDOFF3
STANDOFF4
E
C142
C146
10nF
C157
10nF
C97
10nF
C98
10nF
C151
22nF
C125
22nF
C156
22nF
C96
22nF
C527
22nF
C95
22nF
C521
47nF
C114
10nF
C170
10nF
C519
22nF
E
STANDOFF5
47nF
VCC
C517
C167
47nF
VCCL
C136
100nF
C152
100nF
C499
C467
C485
C523
C445
C526
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
C529
220nF
C533
C218
C546
1uF
VCCL
1uF
SCREW1
C545
1uF
SCREW2
22nF
47nF
C139
C206
C172
C208
C165
C132
C210
C173
C197
C235
C216
C204
C105
C86
C224
C194
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
C115
470uF
10V
Tantalum
+
C432
470uF
10V
Tantalum
1
1
1
+
+
C237
470uF
10V
Tantalum
SCREW4
+
2
C80
2
2
D
C498
470uF
10V
Tantalum
2
+
2
1
1
SCREW3
C193
470uF
10V
Tantalum
C192
SCREW5
D
100uF
2.5V
2.5V
2.5V
C38
C44
4.7nF
C
C55
10nF
C3
10nF
C2
22nF
C1
22nF
C28
22nF
C40
47nF
C33
180nF
C50
470nF
4.7nF
C29
C41
C42
C58
C73
C74
C22
C7
C47
C127
C64
C63
C62
C61
C4
C8
C5
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
C14
47nF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
C356
C306
C397
C398
C365
C325
C303
C286
C304
C300
C278
C277
C280
C279
C283
C296
C318
C285
C66
C43
10nF
C85
C10
10nF
C20
47nF
47nF
C6
C21
C25
C143
100uF
100uF
100uF
100uF
C
180nF
FPGA VCC
3.3V
3.3V
3.3V
VCC
C548
C382
C453
C549
C540
C516
C448
C452
C383
C381
C534
C462
B
4.7nF
10nF
22nF
22nF
47nF
180nF
470nF
4.7nF
10nF
10nF
C458
C213
C537
C230
C245
C78
C102
C60
C400
C401
C402
C71
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
47nF
47nF
180nF
C310
180nF
VCC
C531
B
22nF
C93
C443
47nF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
C302
C536
C535
C386
C311
C312
C506
C507
C543
C424
C463
C425
C426
C363
C326
C530
100uF
100uF
100uF
C223
C202
C489
C532
100uF
100uF
1uF
10uF
FPGA VCC
A
C191
C234
Title
22nF
1uF
Size
B
Date:
8
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
28
of
1
29
B
8
7
6
5
Place 6 vias minimum on each X2Y cap.
FPGA Bank 4B
1.5V_1.8V_B2
2.5V_B1_B8
3
2
1
Decoupling 2
FPGA Bank 2
FPGA Banks 1 and 8
E
4
FPGA VCCAUX
FPGA VCC_CLKIN
2.5V_B4B
2.5V_VCCAUX
2.5V_VCC_CLKIN
E
1.5V_1.8V_B2
C447
C446
C444
C186
C175
C187
C183
C128
C129
C138
C465
C113
C182
22nF
22nF
47nF
10nF
22nF
47nF
1uF
22nF
220nF
1uF
100uF
100uF
47nF
C212
C99
C466
C435
100uF
1uF
10uF
C199
C190
C65
100uF
100uF
100uF
FPGA VCCPGM
FPGA VCCPD
1uF
2.5V_VCCPD
2.5V_VCCPGM
C431
C451
C103
C505
D
C124
FPGA Banks 3 and 4, except 4B
47nF
1.5V_DDR3
1.5V_DDR3
C525
C518
4.7nF
C524
10nF
C520
22nF
C528
47nF
180nF
C220
220nF
C188
1uF
4.7nF
C189
10nF
C184
10nF
C203
C207
C217
C205
C200
C196
C195
C225
C209
C226
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
D
100uF
C185
47nF
FPGA VCCD_PLL
FPGA VCCA_PLL
VCCD_PLL
C211
220nF
100uF
2.5V_A
C123
C481
470nF
C
47nF
C471
180nF
C
C112
FPGA Banks 5 and 6
FPGA Bank 7
2.5V_B5_B6
C522
C101
C487
100uF
1uF
100uF
1.5V_1.8V_B7
C515
C130
1.5V_1.8V_B7
C100
FPGA VCCPT
47nF
180nF
22nF
100nF
VCCPT
C90
C92
C180
C91
100uF
C104
C490
100uF
100uF
1uF
1uF
1uF
VCCPT
B
B
C116
1.8V
100uF
1.8V
1.8V
C176
10nF
C177
22nF
C178
C131
100nF
C135
180nF
100nF
1.8V
C171
C121
C111
C120
C137
C122
100uF
100uF
100uF
100uF
100uF
1uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Stratix IV E FPGA Development Kit Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
150-0310904-B1
Wednesday, August 26, 2009
2
Rev
(6XX-41504R)
Sheet
29
of
1
29
B
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