8 7 6 5 4 NOTES: E 3 REV 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework 100-0320807-C1 110-0320807-C1 120-0320807-C1 130-0320807-C1 140-0320807-C1 150-0320807-C1 160-0320807-C1 170-0320807-C1 180-0320807-C1 210-0320807-C1 220-0320807-C1 320-0320807-C1 DATE 2 PAGES A1 02 B1 All All All C1 All INITIAL REVISION A RELEASE Changes for Rev B INITIAL RELEASE TO B Changes: Fixed connections for FPGA Power Monitor Added FMCB and LMK interface Added pull-ups for Power Monitor devices Added series resistor (0-ohm) between run pin and Power Monitor device Changed QSPI device to one with reset pin INITIAL RELEASE TO C Changes: Removed SPI signals from MAX device to LMK device Swapped pin locations for CLK_100M_FPGA and SPI_SDIO to remove critical warnings Added RC circuit for JTAG clocks (JTAG_MUX_TCK, JTAG_HPS_TCK) Added resistor mux for selecting clock and sync from LMK or FPGA for FMCA and FMCB Changed LTC2978 to LTC2977 Arria V SoC FPGA Development Kit Board 2. 1172 Parts, 88 Library Parts, 1330 Nets, 6643 Pins D C B 1 DESCRIPTION E PAGE DESCRIPTION 1 Title, Notes, Block Diagram, Rev. History 30 On-Board USB Blaster II 2 Blank Page 31 FPGA Power Monitor 1 3 PCI Express Edge Connector 32 FPGA Power Monitor 2 4 Arria V ST Bank 3 33 HPS Power Monitor 5 Arria V ST Bank 4 34 Power 1 - DC Input, 12V, 3.3V 6 Arria V ST Bank 6, 7G 35 Power 2 - FPGA Power 1.1V 7 Arria V ST Bank 7 36 Power 3 - FPGA Power 1.5V 8 Arria V ST Bank 8 37 Power 4 - FPGA Power 2.5V 9 Arria V ST Transceiver Banks 38 Power 5 - HPS Power 2.5V 10 Arria V ST Clocks 39 Power 6 - HPS Power 1.5V 11 PLL and Clocks 40 Power 7 - HPS Power 3.3V 12 Clock Cleaner 41 Power 8 - 5V, 1.8V, & HPS 1.1V 13 Arria V ST Configuration 42 Power 9 - Linear Regulator 14 JTAG 43 Power 10 - Arria V ST Power 15 DDR3 x40 - HPS 44 Power 11 - Arria V ST GND 16 DDR3 x32 - FPGA Port A 45 Decoupling 17 DDR3 x32 - FPGA Port B 18 Flash, EPCQ 19 5M2210 System Controller 20 10/100/1000 Ethernet PHY (HPS) 21 Dual EtherCAT PHY 22 SFP+ Port A 23 SFP+ Port B 24 FMC Port A Connector 25 FMC Port B Connector 26 QSPI Flash, Reset Circuit 27 USB 2.0 OTG, Micro SD Card 28 User I/O (LEDs, Buttons, Switches, LCD) 29 UART Ports A & B A PAGE DESCRIPTION D C B A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 1 of 1 45 C1 8 7 6 5 4 3 2 1 THIS PAGE IS INTENTIONALLY LEFT BLANK E E D D C C B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 2 of 1 45 C1 8 7 6 5 4 3 2 1 PCI Express Connector 3.3V 12V E E R680 0_Ohms 12V_EXP 3.3V_EXP R675 0_Ohms 12V_EXP 12V_EXP 3.3V_EXP PCIE_SMBCLK PCIE_SMBDAT J42 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PCIE_SMBCLK PCIE_SMBDAT 4 4 3.3V R310 D 4.70K, 1% PCIE_WAKEn 13 PCIE_TX_P0 PCIE_TX_N0 9 9 C263 0.1uF C262 0.1uF PCIE_TX_C_P0 PCIE_TX_C_N0 PCIE_PRSNT2_X1 10 9 9 PCIE_TX_P1 PCIE_TX_N1 C241 0.1uF C239 0.1uF PCIE_TX_C_P1 PCIE_TX_C_N1 9 9 PCIE_TX_P2 PCIE_TX_N2 C230 0.1uF C228 0.1uF PCIE_TX_C_P2 PCIE_TX_C_N2 9 9 PCIE_TX_P3 PCIE_TX_N3 C222 0.1uF C221 0.1uF PCIE_TX_C_P3 PCIE_TX_C_N3 C PCIE_PRSNT2_X4 10 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 +12V PRSNT1_N +12V +12V +12V +12V GND GND SMCLK JTAG_TCK SMDAT JTAG_TDI GND JTAG_TDO +3_3V JTAG_TMS JTAG_TRSTN +3_3V +3_3VAUX +3_3V WAKE_N PERST_N KEY RSVD1 GND X1 GND REFCLK+ PET0P REFCLKPET0N GND GND PER0P PRSNT2_N_X1 PER0N GND GND PET1P X4 PET1N GND GND PET2P PET2N GND GND PET3P PET3N GND RSVD3 PRSNT2_N_X4 GND RSVD2 GND PER1P PER1N GND GND PER2P PER2N GND GND PER3P PER3N GND RSVD4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 R324 3.3V_EXP R303 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 4.7K D PCIE_PERSTn 4.70K, 1% 10,13 PCIE_REFCLK_SYN_P PCIE_REFCLK_SYN_N PCIE_RX_P0 PCIE_RX_N0 9 9 PCIE_RX_P1 PCIE_RX_N1 9 9 PCIE_RX_P2 PCIE_RX_N2 9 9 PCIE_RX_P3 PCIE_RX_N3 9 9 11 11 C PCIE-064-02-F-D-TH B B 12V_EXP A 3.3V_EXP C245 C265 220uF 16V 220uF 16V C277 47uF 20V C283 47uF 20V C846 22uF 25V C844 22uF 25V C282 C264 220uF 16V 47uF 20V C276 47uF 20V C838 22uF 25V C845 22uF 25V Title Size B Date: 8 7 6 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 3 of 1 45 C1 8 7 6 5 4 3 2 1 Arria V ST Bank 3 E R499 100, 1% DDR3A_A0 DDR3A_A1 DDR3A_A2 DDR3A_A3 DDR3A_A4 DDR3A_A5 DDR3A_A6 DDR3A_A7 DDR3A_A8 DDR3A_A9 DDR3A_A10 DDR3A_A11 DDR3A_A12 DDR3A_A13 DDR3A_A14 DDR3A_BA0 DDR3A_BA1 DDR3A_BA2 AN33 AU29 AT29 AV30 AU30 AT30 AR30 AL30 AK30 AW31 AW30 AV31 AU31 AH30 AG30 AE29 AD29 AT31 AR31 AP31 AL29 DDR3A_DM0 DDR3A_DQS_P0 AJ28 DDR3A_DQS_N0 AH28 C U41O Arria V SX (SoC) Bank 3 DDR3A_RZQ D U41A DDR3A_DQ0 DDR3A_DQ1 DDR3A_DQ2 DDR3A_DQ3 DDR3A_DQ4 DDR3A_DQ5 DDR3A_DQ6 DDR3A_DQ7 AD27 AC27 AM28 AB28 AB27 AE28 AG28 AF28 AC29 DDR3A_RESETn AB29 AK29 AD28 RZQ_0,DIFFIO_TX_B1_N E Arria V SX (SoC) Bank 3 Bank 3A 1.5 Volt HMC_CK#,DIFFIO_RX_B23_N HMC_CK,DIFFIO_RX_B23_P HMC_CKE_0,HMC_RLD2_A_16,DIFFIO_TX_B22_P HMC_CKE_1,HMC_RLD2_A_17,DIFFIO_TX_B22_N HMC_A_0,DIFFIO_RX_B21_P HMC_A_1,DIFFIO_RX_B21_N HMC_A_2,DIFFIO_TX_B20_P HMC_A_3,DIFFIO_TX_B20_N HMC_A_4,DIFFIO_RX_B19_P HMC_CS#_0,DIFFIO_TX_B8_P HMC_A_5,DIFFIO_RX_B19_N HMC_CS#_1,DIFFIO_TX_B8_N HMC_A_6,DIFFIO_TX_B18_P HMC_A_7,DIFFIO_TX_B18_N HMC_ODT_0,HMC_RLD2_A_18,DIFFIO_TX_B10_P HMC_A_8,DIFFIO_RX_B17_P HMC_ODT_1,HMC_RLD2_A_20,DIFFIO_TX_B10_N HMC_A_9,DIFFIO_RX_B17_N HMC_A_10,DIFFIO_TX_B16_P HMC_RAS#,HMC_RLD2_A_21,DIFFIO_TX_B12_N HMC_A_11,DIFFIO_TX_B16_N HMC_CAS#,HMC_RLD2_REF#,HMC_QDR2_WPS#,DIFFIO_RX_B11_P HMC_A_12,DIFFIO_RX_B15_P HMC_WE#,DIFFIO_RX_B11_N HMC_A_13,DIFFIO_RX_B15_N HMC_A_14,DIFFIO_TX_B14_P HMC_A_15,DIFFIO_TX_B14_N DIFFIO_TX_B1_P,DQ1B DIFFIO_TX_B3_P,DQ1B HMC_BA_0,HMC_QDR2_A_16,DIFFIO_RX_B13_P DQ1B HMC_BA_1,HMC_QDR2_A_17,DIFFIO_RX_B13_N HMC_BA_2,HMC_QDR2_A_18,DIFFIO_TX_B12_P DIFFIO_TX_B3_N Bank 3B 1.5 Volt HMC_DM2,DIFFIO_TX_B33_P HMC_DQS2,HMC_RLD2_QK#2,HMC_QDR2_CQ2/CQ#2,DIFFIO_RX_B34_P HMC_DQS#2,HMC_RLD2_QK2,DIFFIO_RX_B34_N HMC_DM1,DIFFIO_TX_B26_P HMC_DQS1,HMC_RLD2_QK#1,HMC_QDR2_CQ1/CQ#1,DIFFIO_RX_B27_P HMC_DQS#1,HMC_RLD2_QK1,DIFFIO_RX_B27_N HMC_DQ2_0,DIFFIO_RX_B38_P HMC_DQ2_1,DIFFIO_RX_B38_N HMC_DQ1_0,DIFFIO_RX_B30_P HMC_DQ2_2,DIFFIO_TX_B37_P HMC_DQ1_1,DIFFIO_RX_B30_N HMC_DQ2_3,DIFFIO_RX_B36_P HMC_DQ1_2, HMC_DQ2_4,DIFFIO_RX_B36_N HMC_DQ1_3,DIFFIO_RX_B29_P HMC_DQ2_5,DIFFIO_TX_B35_P HMC_DQ1_4,DIFFIO_RX_B29_N HMC_DQ2_6,DIFFIO_RX_B32_P HMC_DQ1_5,DIFFIO_TX_B28_P HMC_DQ2_7,DIFFIO_RX_B32_N HMC_DQ1_6,DIFFIO_RX_B25_P HMC_DQ2_8,DIFFIO_TX_B31_P HMC_DQ1_7,DIFFIO_RX_B25_N HMC_DQ1_8,DIFFIO_TX_B24_P DIFFIO_TX_B31_N HMC_RESET#,HMC_RLD2_A_19,DIFFIO_TX_B24_N DIFFIO_TX_B33_N DIFFIO_TX_B35_N DIFFIO_TX_B26_N DIFFIO_TX_B37_N DIFFIO_TX_B28_N AN29 AP29 AP30 AN30 DDR3A_CLK_N DDR3A_CLK_P DDR3A_CKE AP32 AN32 DDR3A_CSn AM31 AL31 DDR3A_ODT AN31 AW32 AW33 DDR3A_RASn DDR3A_CASn DDR3A_WEn AP33 AL32 AK31 USB_B2_DATA0 USB_B2_DATA1 USB_B2_DATA2 AK25 DDR3A_DM3 DDR3A_DQS_P3 AU26 DDR3A_DQS_N3 AT26 AK32 USB_B2_DATA3 DDR3A_DQ24 DDR3A_DQ25 DDR3A_DQ26 DDR3A_DQ27 DDR3A_DQ28 DDR3A_DQ29 DDR3A_DQ30 DDR3A_DQ31 AK27 AW28 AW29 DDR3A_DM1 DDR3A_DQS_P1 DDR3A_DQS_N1 AW27 AV27 AN27 AU27 AT27 AR27 AV28 AU28 AR28 DDR3A_DQ8 DDR3A_DQ9 DDR3A_DQ10 DDR3A_DQ11 DDR3A_DQ12 DDR3A_DQ13 DDR3A_DQ14 DDR3A_DQ15 21 AP28 AJ27 AP27 AM27 USB_B2_DATA4 USB_B2_DATA5 21 USB_B2_DATA6 21 USB_B2_DATA7 21 DDR3A_DQ16 DDR3A_DQ17 DDR3A_DQ18 DDR3A_DQ19 DDR3A_DQ20 DDR3A_DQ21 DDR3A_DQ22 DDR3A_DQ23 ENET1_TX_D0 ENET1_TX_D1 ENET1_TX_D2 ENET1_TX_D3 ENET1_TX_EN ENET1_RX_D0 ENET1_RX_D1 ENET1_RX_D2 ENET1_RX_D3 ENET1_RX_ERROR ENET1_RX_DV ENET1_RX_CLK AV24 AV25 AL26 AW26 AW25 AT25 AN25 AM25 AP26 AU22 AT22 AE23 AD22 AP23 AL23 AW22 AW21 AV21 AH23 AF22 AE22 B 28 DIFFIO_TX_B70_N DIFFIO_TX_B72_N DIFFIO_TX_B74_N DIFFIO_TX_B77_N DIFFIO_TX_B81_N DIFFIO_TX_B83_N DIFFIO_TX_B62_N DIFFIO_TX_B64_N DIFFIO_TX_B66_N DIFFIO_TX_B68_N USER_LED_FPGA[3:0] USB_B2_DATA[7:0] USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn 30 USB_B2_DATA[7:0] 30 30 30 30 19,30 30 30 30 30 USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn Title Date: 6 5 4 USER_DIPSW_FPGA3 USER_PB_FPGA0 USER_PB_FPGA1 USER_PB_FPGA2 USER_PB_FPGA3 USER_LED_FPGA0 USER_LED_FPGA1 USER_LED_FPGA2 USER_LED_FPGA3 AG27 AE27 AC24 AD26 AN26 AJ25 AR25 AD23 AK24 AG24 AN24 USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn D AT21 ENET2_TX_D0 AR21 ENET2_TX_D1 AK21 ENET2_TX_D2 AP22 ENET2_TX_D3 AW20 ENET2_TX_EN AW19 ENET2_RX_D0 AL22 ENET2_RX_D1 AH22 ENET2_RX_D2 AU20 ENET2_RX_D3 AT20 ENET2_RX_CLK 21 AN21 AP20 AH20 ENET2_TX_CLK_FB ENET2_RX_DV P1TXERR 21 21 21 AN22 ENET2_RX_ERROR AK22 ENET_FPGA_MDIO AG22 ENET_FPGA_MDC AM21 SDI_CLK148_UP AN20 SDI_CLK148_DN AG20 PCIE_SMBCLK 21 21 21 9 9 3 C 21 16 DDR3A_DM[3:0] 16 DDR3A_DQS_P[3:0] 16 DDR3A_DQS_N[3:0] 16 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 B 7 AU23 AT23 AP24 AW24 AW23 AH24 AU24 AT24 AD24 DDR3A_DQ[31:0] 16 16 16 16 16 16 16 16 16 16 16 Size 8 USER_DIPSW_FPGA0 USER_DIPSW_FPGA1 USER_DIPSW_FPGA2 B DDR3A_A[14:0] DDR3A_BA[2:0] DDR3A_CASn DDR3A_CLK_P DDR3A_CLK_N DDR3A_CKE DDR3A_CSn DDR3A_ODT DDR3A_RASn DDR3A_RESETn DDR3A_WEn USER_PB_FPGA[3:0] 28 AL24 AF24 AE24 DDR3 PORT A USER_DIPSW_FPGA[3:0] 28 DIFFIO_RX_B73_P,DQS10B DIFFIO_RX_B73_N,DQSn10B DQ10B DIFFIO_TX_B70_P,DQ10B DIFFIO_RX_B71_P,DQ10B DIFFIO_RX_B71_N,DQ10B DIFFIO_TX_B72_P,DQ10B DIFFIO_TX_B74_P,DQ10B DIFFIO_RX_B75_P,DQ10B DIFFIO_RX_B75_N,DQ10B DIFFIO_TX_B77_P,DQ11B DIFFIO_TX_B81_P,DQ11B DIFFIO_TX_B83_P,DQ11B 5ASTFD5K3_F1517 1.5V Signals ETHERNET FPGA A DIFFIO_RX_B65_P,DQS9B DIFFIO_RX_B65_N,DQSn9B DIFFIO_RX_B63_P,DQ9B DIFFIO_RX_B63_N,DQ9B DIFFIO_TX_B62_P,DQ9B DIFFIO_TX_B64_P,DQ9B DIFFIO_TX_B66_P,DQ9B DIFFIO_RX_B67_P,DQ9B DIFFIO_RX_B67_N,DQ9B DIFFIO_TX_B68_P,DQ9B DIFFIO_RX_B69_P,DQ9B DIFFIO_RX_B69_N,DQ9B AN23 ENET1_TX_CLK_FB P0TXERR AK23 ENET_DUAL_RESETn AV22 PCIE_SMBDAT AG23 21 21 21,26 3 21 21 21 21 AH25 AG25 AE26 AH26 AG26 AD25 AC25 AB25 AH27 Bank 3D 2.5 Volt 5ASTFD5K3_F1517 ENET1_TX_D[3..0] ENET1_RX_D[3..0] ENET2_TX_D[3..0] ENET2_RX_D[3..0] Bank 3C 1.5 Volt HMC_DM3,DIFFIO_TX_B41_P HMC_DQS3,HMC_RLD2_QK#3,HMC_QDR2_CQ3/CQ#3,DIFFIO_RX_B42_P HMC_DQS#3,HMC_RLD2_QK3,DIFFIO_RX_B42_N HMC_DM5,DIFFIO_TX_B56_P HMC_DQS5,HMC_RLD2_QK#5,HMC_QDR2_CQ5/CQ#5,DIFFIO_RX_B57_P HMC_DQS#5,HMC_RLD2_QK5,DIFFIO_RX_B57_N HMC_DQ3_0,DIFFIO_RX_B46_P HMC_DQ3_1,DIFFIO_RX_B46_N HMC_DQ5_0,DIFFIO_RX_B61_P HMC_DQ3_2,DIFFIO_TX_B45_P HMC_DQ5_1,DIFFIO_RX_B61_N HMC_DQ3_3,DIFFIO_RX_B44_P HMC_DQ5_2,DIFFIO_TX_B60_P HMC_DQ3_4,DIFFIO_RX_B44_N HMC_DQ5_3,DIFFIO_RX_B59_P HMC_DQ3_5,DIFFIO_TX_B43_P HMC_DQ5_4,DIFFIO_RX_B59_N HMC_DQ3_6,DIFFIO_RX_B40_P HMC_DQ5_5,DIFFIO_TX_B58_P HMC_DQ3_7,DIFFIO_RX_B40_N HMC_DQ5_6,DIFFIO_RX_B55_P HMC_DQ3_8,DIFFIO_TX_B39_P HMC_DQ5_7,DIFFIO_RX_B55_N HMC_DQ5_8,DIFFIO_TX_B54_P HMC_DM4,DIFFIO_TX_B49_P HMC_DQS4,HMC_RLD2_QK#4,HMC_QDR2_CQ4/CQ#4,DIFFIO_RX_B50_P HMC_DQS#4,HMC_RLD2_QK4,DIFFIO_RX_B50_N DIFFIO_TX_B39_N DIFFIO_TX_B41_N HMC_DQ4_0,DIFFIO_RX_B53_P DIFFIO_TX_B43_N HMC_DQ4_1,DIFFIO_RX_B53_N DIFFIO_TX_B45_N HMC_DQ4_2 DIFFIO_TX_B47_N HMC_DQ4_3,DIFFIO_RX_B52_P DIFFIO_TX_B49_N HMC_DQ4_4,DIFFIO_RX_B52_N DIFFIO_TX_B51_N HMC_DQ4_5,DIFFIO_TX_B51_P DIFFIO_TX_B54_N HMC_DQ4_6,DIFFIO_RX_B48_P DIFFIO_TX_B56_N HMC_DQ4_7,DIFFIO_RX_B48_N DIFFIO_TX_B58_N HMC_DQ4_8,DIFFIO_TX_B47_P DIFFIO_TX_B60_N AF27 DDR3A_DM2 DDR3A_DQS_P2 AF25 DDR3A_DQS_N2 AE25 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 4 of 1 45 C1 5 4 3 2 1 Arria V ST Bank 4 D D U41B U41P Arria V SX (SoC) Bank 4 SFPA_TXDISABLE SFPA_RATESEL0 SFPA_RATESEL1 AP7 AU6 AL8 SFPA_MOD0_PRSNTn SFPA_MOD1_SCL AR9 AT8 SFPA_MOD2_SDA AH8 Arria V SX (SoC) Bank 4 Bank 4A 2.5 Volt RZQ_1,DIFFIO_TX_B167_P,DQ22B DIFFIO_TX_B163_P,DQ22B DIFFIO_TX_B165_P,DQ22B DIFFIO_TX_B146_N DIFFIO_TX_B148_N DIFFIO_TX_B163_N DIFFIO_TX_B165_N DIFFIO_TX_B167_N DIFFIO_RX_B153_P,DQ20B DIFFIO_RX_B153_N,DQ20B HMC_DM5,DIFFIO_TX_B140_P HMC_DQS5,HMC_RLD2_QK#5,HMC_QDR2_CQ5/CQ#5,DIFFIO_RX_B141_P HMC_DQS#5,HMC_RLD2_QK5,DIFFIO_RX_B141_N C AU12 AW12 AV12 AJ13 AH13 AP12 AW11 AW10 AM13 AE13 AE14 AR13 AV10 DDR3B_DM3 DDR3B_DQS_P3 AU11 DDR3B_DQS_N3 AT11 DDR3B_DQ24 DDR3B_DQ25 DDR3B_DQ26 DDR3B_DQ27 DDR3B_DQ28 DDR3B_DQ29 DDR3B_DQ30 DDR3B_DQ31 AW9 AV9 AP11 AD13 AC13 AL12 AG13 AF13 AJ12 SFPA_TXFAULT SFPA_LOS SFPB_TXDISABLE SFPB_RATESEL0 SFPB_RATESEL1 DDR3B_DM0 DDR3B_DQS_P0 DDR3B_DQS_N0 DDR3B_DQ2 DDR3B_DQ6 DDR3B_DQ7 DDR3B_DQ5 DDR3B_DQ3 DDR3B_DQ4 DDR3B_DQ0 DDR3B_DQ1 DQ21B Bank 4B 1.5 Volt DDR3B_DM2 DDR3B_DQS_P2 DDR3B_DQS_N2 DDR3B_DQ16 DDR3B_DQ17 DDR3B_DQ18 DDR3B_DQ19 DDR3B_DQ20 DDR3B_DQ21 DDR3B_DQ22 DDR3B_DQ23 AL9 AV7 AT6 AK8 AN7 HMC_DM3,DIFFIO_TX_B125_P HMC_DQS3,HMC_RLD2_QK#3,HMC_QDR2_CQ3/CQ#3,DIFFIO_RX_B126_P HMC_DQS#3,HMC_RLD2_QK3,DIFFIO_RX_B126_N HMC_DQ3_0,DIFFIO_RX_B130_P HMC_DQ5_0,DIFFIO_RX_B145_P HMC_DQ3_1,DIFFIO_RX_B130_N HMC_DQ5_1,DIFFIO_RX_B145_N HMC_DQ3_2,DIFFIO_TX_B129_P HMC_DQ5_2,DIFFIO_TX_B144_P HMC_DQ3_3,DIFFIO_RX_B128_P HMC_DQ5_3,DIFFIO_RX_B143_P HMC_DQ3_4,DIFFIO_RX_B128_N HMC_DQ5_4,DIFFIO_RX_B143_N HMC_DQ3_5,DIFFIO_TX_B127_P HMC_DQ5_5,DIFFIO_TX_B142_P HMC_DQ3_6,DIFFIO_RX_B124_P HMC_DQ5_6,DIFFIO_RX_B139_P HMC_DQ3_7,DIFFIO_RX_B124_N HMC_DQ5_7,DIFFIO_RX_B139_N HMC_DQ3_8,DIFFIO_TX_B123_P HMC_DQ5_8,DIFFIO_TX_B138_P HMC_DM4,DIFFIO_TX_B133_P HMC_DQS4,HMC_RLD2_QK#4,HMC_QDR2_CQ4/CQ#4,DIFFIO_RX_B134_P HMC_DQS#4,HMC_RLD2_QK4,DIFFIO_RX_B134_N DIFFIO_TX_B123_N DIFFIO_TX_B125_N HMC_DQ4_0,DIFFIO_RX_B137_P DIFFIO_TX_B127_N HMC_DQ4_1,DIFFIO_RX_B137_N DIFFIO_TX_B129_N HMC_DQ4_2, DIFFIO_TX_B131_N HMC_DQ4_3,DIFFIO_RX_B136_P DIFFIO_TX_B133_N HMC_DQ4_4,DIFFIO_RX_B136_N DIFFIO_TX_B135_N HMC_DQ4_5,DIFFIO_TX_B135_P DIFFIO_TX_B138_N HMC_DQ4_6,DIFFIO_RX_B132_P DIFFIO_TX_B140_N HMC_DQ4_7,DIFFIO_RX_B132_N DIFFIO_TX_B142_N HMC_DQ4_8,DIFFIO_TX_B131_P DIFFIO_TX_B144_N AU9 AH11 AG11 AD16 AH16 AG16 AH15 AP15 AW15 AW14 AL15 AW13 AV13 AU15 AT15 DDR3B_RESETn AN15 AC16 AK15 AM10 AL10 AL11 AR10 AP10 AE12 AG12 AF12 AD11 DDR3B_A0 DDR3B_A1 DDR3B_A2 DDR3B_A3 DDR3B_A4 DDR3B_A5 DDR3B_A6 DDR3B_A7 DDR3B_A8 DDR3B_A9 DDR3B_A10 AP13 AT12 AL13 AN12 AH12 AU10 AK12 AC12 AT9 AD12 AK11 DDR3B_A11 DDR3B_A12 DDR3B_A13 DDR3B_A14 DDR3B_BA0 DDR3B_BA1 DDR3B_BA2 B 5ASTFD5K3_F1517 AP16 AN16 AK16 AJ16 AV16 AU16 AT16 AR16 AP17 AN17 AH17 AG17 AM18 AL18 AG18 AU17 AE18 AD18 AC18 AV18 AN19 AH18 AE19 Bank 4C 1.5 Volt HMC_DM2,DIFFIO_TX_B117_P HMC_DQS2,HMC_RLD2_QK#2,HMC_QDR2_CQ2/CQ#2,DIFFIO_RX_B118_P HMC_DQS#2,HMC_RLD2_QK2,DIFFIO_RX_B118_N HMC_DM1,DIFFIO_TX_B110_P HMC_DQS1,HMC_RLD2_QK#1,HMC_QDR2_CQ1/CQ#1,DIFFIO_RX_B111_P HMC_DQS#1,HMC_RLD2_QK1,DIFFIO_RX_B111_N HMC_DQ2_8,DIFFIO_TX_B115_P HMC_DQ1_2, HMC_DQ2_6,DIFFIO_RX_B116_P HMC_DQ1_8,DIFFIO_TX_B108_P HMC_DQ2_7,DIFFIO_RX_B116_N HMC_DQ1_6,DIFFIO_RX_B109_P HMC_DQ2_5,DIFFIO_TX_B119_P HMC_DQ1_7,DIFFIO_RX_B109_N HMC_DQ2_3,DIFFIO_RX_B120_P HMC_DQ1_5,DIFFIO_TX_B112_P HMC_DQ2_4,DIFFIO_RX_B120_N HMC_DQ1_3,DIFFIO_RX_B113_P HMC_DQ2_2,DIFFIO_TX_B121_P HMC_DQ1_4,DIFFIO_RX_B113_N HMC_DQ2_0,DIFFIO_RX_B122_P HMC_DQ1_0,DIFFIO_RX_B114_P HMC_DQ2_1,DIFFIO_RX_B122_N HMC_DQ1_1,DIFFIO_RX_B114_N DIFFIO_TX_B115_N HMC_RESET#,HMC_RLD2_A_19,DIFFIO_TX_B108_N DIFFIO_TX_B117_N DIFFIO_TX_B110_N DIFFIO_TX_B119_N DIFFIO_TX_B112_N DIFFIO_TX_B121_N Bank 4D 1.5 Volt HMC_CK,DIFFIO_RX_B107_P HMC_A_0,DIFFIO_RX_B105_P HMC_CK#,DIFFIO_RX_B107_N HMC_A_1,DIFFIO_RX_B105_N HMC_CKE_0,HMC_RLD2_A_16,DIFFIO_TX_B106_P HMC_A_2,DIFFIO_TX_B104_P HMC_CKE_1,HMC_RLD2_A_17,DIFFIO_TX_B106_N HMC_A_3,DIFFIO_TX_B104_N HMC_A_4,DIFFIO_RX_B103_P HMC_CS#_0,DIFFIO_TX_B93_P HMC_A_5,DIFFIO_RX_B103_N HMC_CS#_1,DIFFIO_TX_B93_N HMC_A_6,DIFFIO_TX_B102_P HMC_A_7,DIFFIO_TX_B102_N HMC_ODT_0,HMC_RLD2_A_18,DIFFIO_TX_B95_P HMC_A_8,DIFFIO_RX_B101_P HMC_ODT_1,HMC_RLD2_A_20,DIFFIO_TX_B95_N HMC_A_9,DIFFIO_RX_B101_N HMC_A_10,DIFFIO_TX_B100_P HMC_RAS#,HMC_RLD2_A_15,DIFFIO_TX_B97_N HMC_CAS#,HMC_RLD2_REF#,HMC_QDR2_WPS#,DIFFIO_RX_B96_P HMC_WE#,HMC_RLD2_WE#,HMC_QDR2_RPS#,DIFFIO_RX_B96_N HMC_A_11,DIFFIO_TX_B100_N HMC_A_12,DIFFIO_RX_B99_P HMC_A_13,DIFFIO_RX_B99_N HMC_A_14 HMC_A_15,DIFFIO_RX_B94_P HMC_BA_0,DIFFIO_RX_B98_P HMC_BA_1,DIFFIO_RX_B98_N HMC_BA_2,DIFFIO_TX_B97_P DIFFIO_TX_B85_P,DQ12B DIFFIO_RX_B86_P,DQ12B DIFFIO_TX_B87_P,DQ12B DIFFIO_RX_B86_N,DQ12B DIFFIO_RX_B88_P,DQS12B DIFFIO_RX_B88_N,DQSn12B DIFFIO_TX_B89_P,DQ12B DIFFIO_RX_B90_P,DQ12B DIFFIO_RX_B90_N,DQ12B DIFFIO_TX_B91_P,DQ12B DIFFIO_RX_B92_P,DQ12B DIFFIO_RX_B92_N,DQ12B DIFFIO_RX_B94_N,DQ13B DIFFIO_TX_B85_N DIFFIO_TX_B87_N DIFFIO_TX_B89_N DIFFIO_TX_B91_N AU13 AF15 AE16 DDR3B_DM1 DDR3B_DQS_P1 DDR3B_DQS_N1 AD14 AU14 AT14 AL14 AP14 AN14 AH14 AE15 AD15 DDR3B_DQ14 DDR3B_DQ15 DDR3B_DQ13 DDR3B_DQ11 DDR3B_DQ12 DDR3B_DQ10 DDR3B_DQ8 DDR3B_DQ9 AC15 AT13 AK14 AG14 C AF16 AE17 AM16 AL16 DDR3B_CLK_P DDR3B_CLK_N DDR3B_CKE AL17 AK17 DDR3B_CSn AD19 AC19 DDR3B_ODT AD17 AR18 AP18 DDR3B_RASn DDR3B_CASn DDR3B_WEn AW18 AH19 AP19 AG19 AL19 AK19 AJ18 AT19 AU18 AF19 AW16 AW17 AT17 B 5ASTFD5K3_F1517 SFPA_TXDISABLE 22 SFPA_RATESEL0 SFPA_RATESEL1 22 SFPA_RATESEL0 22 SFPA_RATESEL1 SFPA_MOD0_PRSNTn SFPA_MOD1_SCL SFPA_MOD2_SDA SFPA_TXFAULT SFPA_LOS A SFPB_TXDISABLE SFPB_RATESEL0 SFPB_RATESEL1 SFPA_TXDISABLE 22 SFPA_MOD0_PRSNTn 22 SFPA_MOD1_SCL 22 SFPA_MOD2_SDA 22 SFPA_TXFAULT 22 SFPA_LOS DDR3B_A[14:0] DDR3B_BA[2:0] DDR3B_CASn DDR3B_CLK_P DDR3B_CLK_N DDR3B_CKE DDR3B_CSn DDR3B_ODT DDR3B_RASn DDR3B_RESETn DDR3B_WEn 23 SFPB_TXDISABLE 23 SFPB_RATESEL0 23 SFPB_RATESEL1 17 17 17 17 17 17 17 17 17 17 17 Title B Date: 4 3 17 DDR3B_DM[3:0] 17 DDR3B_DQS_P[3:0] 17 DDR3B_DQS_N[3:0] 17 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Size 5 DDR3B_DQ[31:0] 2 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 Rev (6XX-44209R) Sheet 1 5 of 45 C1 8 7 6 5 4 3 2 1 Arria V ST Bank 6 & 7G U41C Arria V SX (SoC) Bank 6 100, 1% E U41E Arria V SX (SoC) Bank 7G D FMCB_GPIO2 FMCB_GPIO3 R19 T19 U19 U20 FMCB_PRSNTn L19 DIFFIO_RX_T16_P DIFFIO_RX_T16_N DIFFIO_RX_T17_P DIFFIO_RX_T17_N Bank 7G Variable Voltage DIFFIO_TX_T18_P DIFFIO_RX_T19_P DIFFIO_RX_T19_N DIFFIO_RX_T21_P DIFFIO_RX_T21_N DIFFIO_TX_T20_P IO P20 R20 L20 M20 FMCB_GPIO4 FMCB_GPIO5 FMCB_GPIO6 FMCB_GPIO7 M19 N19 FMCB_SDA FMCB_SCL R576 DDR3_HPS_A0 DDR3_HPS_A1 DDR3_HPS_A2 DDR3_HPS_A3 DDR3_HPS_A4 DDR3_HPS_A5 DDR3_HPS_A6 DDR3_HPS_A7 DDR3_HPS_A8 DDR3_HPS_A9 DDR3_HPS_A10 DDR3_HPS_A11 DDR3_HPS_A12 DDR3_HPS_A13 DDR3_HPS_A14 N9 M9 N10 M10 A8 B7 B9 A9 D9 C10 K7 J7 F9 E9 D11 D10 DDR3_HPS_BA0 DDR3_HPS_BA1 DDR3_HPS_BA2 L7 C9 D8 DDR3_HPS_CLK_P DDR3_HPS_CLK_N DDR3_HPS_CKE 5ASTFD5K3_F1517 C B K9 DDR3_HPS_RZQIN A11 B10 R8 F5 DDR3_HPS_CSn H9 J9 DDR3_HPS_ODT H7 K6 DDR3_HPS_RASn DDR3_HPS_CASn DDR3_HPS_WEn G8 G9 J8 DDR3_HPS_DM2 DDR3_HPS_DQS_P2 DDR3_HPS_DQS_N2 D3 G4 H4 DDR3_HPS_DQ16 DDR3_HPS_DQ17 DDR3_HPS_DQ18 DDR3_HPS_DQ19 DDR3_HPS_DQ20 DDR3_HPS_DQ21 DDR3_HPS_DQ22 DDR3_HPS_DQ23 J5 K5 N7 F3 H3 J4 M5 C3 DDR3_HPS_DM3 DDR3_HPS_DQS_P3 DDR3_HPS_DQS_N3 D1 C2 D2 DDR3_HPS_DQ24 DDR3_HPS_DQ25 DDR3_HPS_DQ26 DDR3_HPS_DQ27 DDR3_HPS_DQ28 DDR3_HPS_DQ29 DDR3_HPS_DQ30 DDR3_HPS_DQ31 A2 A3 P7 C1 G2 F2 M3 E1 Bank 6A 1.5 Volt HPS_RZQ_0 HPS_A_0 HPS_A_1 HPS_A_2 HPS_A_3 HPS_A_4 HPS_A_5 HPS_A_6 HPS_A_7 HPS_A_8 HPS_A_9 HPS_A_10 HPS_A_11 HPS_A_12 HPS_A_13 HPS_A_14 HPS_A_15 E HPS_DM_0 HPS_DQS_0 HPS_DQS#_0 HPS_DQ_0 HPS_DQ_1 HPS_DQ_2 HPS_DQ_3 HPS_DQ_4 HPS_DQ_5 HPS_DQ_6 HPS_DQ_7 HPS_DM_1 HPS_DQS_1 HPS_DQS#_1 HPS_BA_0 HPS_BA_1 HPS_BA_2 HPS_DQ_8 HPS_DQ_9 HPS_DQ_10 HPS_DQ_11 HPS_DQ_12 HPS_DQ_13 HPS_DQ_14 HPS_DQ_15 HPS_CK HPS_CK# HPS_CKE_0 HPS_CKE_1 C6 F7 E7 DDR3_HPS_DM0 DDR3_HPS_DQS_P0 DDR3_HPS_DQS_N0 D7 C7 R10 G7 A6 A7 L6 D6 DDR3_HPS_DQ0 DDR3_HPS_DQ1 DDR3_HPS_DQ2 DDR3_HPS_DQ3 DDR3_HPS_DQ4 DDR3_HPS_DQ5 DDR3_HPS_DQ6 DDR3_HPS_DQ7 E4 D5 E6 DDR3_HPS_DM1 DDR3_HPS_DQS_P1 DDR3_HPS_DQS_N1 H6 G6 N8 G5 A4 A5 R9 F4 DDR3_HPS_DQ8 DDR3_HPS_DQ9 DDR3_HPS_DQ10 DDR3_HPS_DQ11 DDR3_HPS_DQ12 DDR3_HPS_DQ13 DDR3_HPS_DQ14 DDR3_HPS_DQ15 D HPS_CS#_0 HPS_CS#_1 HPS_ODT_0 HPS_ODT_1 B6 M7 B4 C4 HPS_GPI0 HPS_GPI1 HPS_GPI2 HPS_GPI3 HPS_RAS# HPS_CAS# HPS_WE# Bank 6B 1.5 Volt HPS_DM_2 HPS_DQS_2 HPS_DQS#_2 HPS_DM_4 HPS_DQS_4 HPS_DQS#_4 HPS_DQ_32 HPS_DQ_33 HPS_DQ_34 HPS_DQ_35 HPS_DQ_36 HPS_DQ_37 HPS_DQ_38 HPS_DQ_39 HPS_DQ_16 HPS_DQ_17 HPS_DQ_18 HPS_DQ_19 HPS_DQ_20 HPS_DQ_21 HPS_DQ_22 HPS_DQ_23 HPS_DM_3 HPS_DQS_3 HPS_DQS#_3 HPS_RESET# DDR3_HPS_DM4 DDR3_HPS_DQS_P4 DDR3_HPS_DQS_N4 G1 F1 P6 L1 M2 M1 N1 R6 DDR3_HPS_DQ32 DDR3_HPS_DQ33 DDR3_HPS_DQ34 DDR3_HPS_DQ35 DDR3_HPS_DQ36 DDR3_HPS_DQ37 DDR3_HPS_DQ38 DDR3_HPS_DQ39 E3 DDR3_HPS_RESETn C M6 L4 K4 K3 N6 B1 K2 J2 R7 K1 HPS_GPI4 HPS_GPI5 HPS_GPI6 HPS_GPI7 HPS_GPI8 HPS_GPI9 HPS_GPI10 HPS_GPI11 HPS_GPI12 HPS_GPI13 HPS_DQ_24 HPS_DQ_25 HPS_DQ_26 HPS_DQ_27 HPS_DQ_28 HPS_DQ_29 HPS_DQ_30 HPS_DQ_31 T7 J1 H1 B 5ASTFD5K3_F1517 FMC PORT B INTERFACE FMCB_SDA FMCB_SCL FMCB_PRSNTn A FMCB_GPIO[7:0] Si571 VCXO 25 SDI_CLK148_DN 25 25,28 25 4,9 DDR3_HPS_A[14:0] DDR3_HPS_BA[2:0] DDR3_HPS_CASn DDR3_HPS_CLK_P DDR3_HPS_CLK_N DDR3_HPS_CKE DDR3_HPS_CSn DDR3_HPS_ODT DDR3_HPS_RASn DDR3_HPS_RESETn DDR3_HPS_WEn DDR3_HPS_DQ[39:0] 15 15 15 15 15 15 15 15 15 15 15 15 DDR3_HPS_DM[4:0] 15 DDR3_HPS_DQS_P[4:0] 15 DDR3_HPS_DQS_N[4:0] 15 Title Size B Date: 8 7 6 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 6 of 1 45 C1 8 7 6 Arria V ST Bank 7 5 R11 K10 C12 MICTOR_RSTn HPS_RESETn 4.70K, 1% R550 4.70K, 1% 14 14 HEADER, 1x3-PIN J37 3.3V 1 10.0K R254 CLKSEL0 2 UARTA_TX 3 1.00K R255 TRACE_CLK_MIC TRACE_DATA0 TRACE_DATA1 TRACE_DATA2 TRACE_DATA3 TRACE_DATA4 TRACE_DATA5 TRACE_DATA6 TRACE_DATA7 3.3V N11 D12 CLK_OSC1 CLK_OSC2 11 11 1 10.0K R256 2 CLKSEL1 3 1.00K F10 G10 F11 H10 T11 JTAG_HPS_TMS JTAG_HPS_TCK JTAG_HPS_TRST JTAG_HPS_TDI JTAG_HPS_TDO 14 14 CLKSEL1 R257 R564 R558 R563 R541 22 22 22 22 22 0 22 22 22 R538 R547 R557 R540 R546 USER_LED_HPS3 HEADER, 1x3-PIN USER_DIPSW_HPS0 XJ8 881545-2 XJ9 USER_DIPSW_HPS1 881545-2 USER_DIPSW_HPS2 USER_DIPSW_HPS3 BOOTSEL2 SD_CMD JTAG_HPS_TCK SD_DAT0 SD_DAT1 SD_DAT2 SD_CD_DAT3 C849 39pF C R4001 37.4 USB_DATA4 USB_STP USB_DIR USB_NXT USB_DATA6 USB_DATA5 USB_DATA7 USB_CLK 27 SD_CMD 27 27 27 27 SD_DAT0 SD_DAT1 SD_DAT2 SD_CD_DAT3 4.70K, 1% 4.70K, 1% J17 A19 C19 G18 K17 D18 B19 C18 R17 A18 L18 ENET_HPS_MDC J18 ENET_HPS_MDIO ENET_HPS_RX_CLK G21 ENET_HPS_RX_DV H19 3.3V R75 R76 C16 G14 B17 H14 L15 P14 K15 R14 K14 C15 L14 D16 P16 C17 N16 J16 M16 USB_DATA4 USB_STP USB_DIR USB_NXT USB_DATA6 USB_DATA5 USB_DATA7 USB_CLK USER_LED_HPS0 ENET_HPS_INTn 27 27 27 27 27 27 27 27 J11 K12 K11 J12 H12 E12 G11 F12 A13 JTAG_MICTOR_TMS JTAG_MICTOR_TDI Bank 7A 3.3 Volt HPS_nRST HPS_nPOR HPS_PORSEL SPIS0_SS0,HPS_GPIO70 SPIS0_MISO,HPS_GPIO69 SPIS0_MOSI,HPS_GPIO68 SPIS0_CLK,SPIM0_SS1,HPS_GPIO67 HPS_TMS SPIM0_SS0,SPIM0_SS0,HPS_GPIO66 HPS_TCK I2C1_SCL,SPIM0_MISO,HPS_GPIO65 HPS_TRST I2C1_SDA,SPIM0_MOSI,HPS_GPIO64 HPS_TDI UART1_TX,SPIM0_CLK,HPS_GPIO63 HPS_TDO UART1_RX,SPIM1_SS1,HPS_GPIO62 SPIS1_SS0,SPIM1_SS0,HPS_GPIO70 HPS_CLK1 SPIS1_MISO,SPIM1_MISO,HPS_GPIO69 HPS_CLK2 SPIS1_MOSI,SPIM1_MOSI,HPS_GPIO68 SPIS1_CLK,SPIM1_CLK,HPS_GPIO67 UART0_TX*,CLKSEL0,UART0_TX,SPIM1_SS0,HPS_GPIO66 TRACE_CLK,HPS_GPIO48 UART0_RX*,UART0_RX,SPIM1_MISO,HPS_GPIO65 TRACE_D0,SPIS0_CLK,UART0_RX,HPS_GPIO49 I2C0_SCL,UART1_TX,SPIM1_MOSI,HPS_GPIO64 TRACE_D1,SPIS0_MOSI,UART0_TX,HPS_GPIO50 I2C0_SDA,UART1_RX,SPIM1_CLK,HPS_GPIO63 TRACE_D2,SPIS0_MISO,I2C1_SDA,HPS_GPIO51 UART0_TX,CLKSEL1,SPIM1_SS1,HPS_GPIO62 TRACE_D3,SPIS0_SS0,I2C1_SCL,HPS_GPIO52 UART0_RX,SPIM0_SS1,HPS_GPIO61 TRACE_D4,SPIS1_CLK,HPS_GPIO53 SPIM0_SS0,BOOTSEL0,UART1_RTS,HPS_GPIO60 TRACE_D5,SPIS1_MOSI,HPS_GPIO54 SPIM0_MISO,UART1_CTS,HPS_GPIO59 TRACE_D6,SPIS1_SS0,I2C0_SDA,HPS_GPIO55 SPIM0_MOSI,I2C1_SCL,UART0_RTS,HPS_GPIO58 TRACE_D7,SPIS1_MISO,I2C0_SCL,HPS_GPIO56 SPIM0_CLK,I2C1_SDA,UART0_CTS,HPS_GPIO57 Bank 7B NAND_RB,RGMII1_TXD3,USB1_D3,HPS_GPIO18 NAND_RE,RGMII1_TXD2,USB1_D2,HPS_GPIO17 3.3 Volt NAND_DQ0,RGMII1_RXD0,HPS_GPIO19 NAND_CLE,RGMII1_TXD1,USB1_D1,HPS_GPIO16 NAND_DQ1,RGMII1_MDIO,I2C3_SDA,HPS_GPIO20 NAND_CE,RGMII1_TXD0,USB1_D0,HPS_GPIO15 NAND_DQ2,RGMII1_MDC,I2C3_SCL,HPS_GPIO21 NAND_ALE,RGMII1_TX_CLK,QSPI_SS3,HPS_GPIO14 NAND_DQ3,RGMII1_RX_CTL,USB1_D4,HPS_GPIO22 QSPI_IO0,USB1_CLK,HPS_GPIO29 NAND_DQ4,RGMII1_TX_CTL,USB1_D5,HPS_GPIO23 QSPI_IO1,USB1_STP,HPS_GPIO30 NAND_DQ5,RGMII1_RX_CLK,USB1_D6,HPS_GPIO24 QSPI_IO2,USB1_DIR,HPS_GPIO31 NAND_DQ6,RGMII1_RXD1,USB1_D7,HPS_GPIO25 QSPI_IO3,USB1_NXT,HPS_GPIO32 NAND_DQ7,RGMII1_RXD2,HPS_GPIO26 QSPI_SS0,BOOTSEL1,HPS_GPIO33 NAND_WP,RGMII1_RXD3,QSPI_SS2,HPS_GPIO27 QSPI_CLK,HPS_GPIO34 NAND_WE,BOOTSEL2,QSPI_SS1,HPS_GPIO28 QSPI_SS1,HPS_GPIO35 Bank 7C SDMMC_CMD,USB0_D0,HPS_GPIO36 SDMMC_D4,USB0_D4,HPS_GPIO40 3.3 Volt SDMMC_PWREN,USB0_D1,HPS_GPIO37 SDMMC_D5,USB0_D5,HPS_GPIO41 SDMMC_D0,USB0_D2,HPS_GPIO38 SDMMC_D6,USB0_D6,HPS_GPIO42 SDMMC_D1,USB0_D3,HPS_GPIO39 SDMMC_D7,USB0_D7,HPS_GPIO43 SDMMC_D2,USB0_DIR,HPS_GPIO46 SDMMC_FB_CLK_IN,USB0_CLK,HPS_GPIO44 SDMMC_D3,USB0_NXT,HPS_GPIO47 SDMMC_CCLK_OUT,USB0_STP,HPS_GPIO45 Bank 7D RGMII0_RXD0,USB1_D4,HPS_GPIO5 RGMII0_TXD0,USB1_D0,HPS_GPIO1 3.3 Volt RGMII0_RXD1,USB1_STP,HPS_GPIO11 RGMII0_TXD1,USB1_D1,HPS_GPIO2 RGMII0_RXD2,USB1_DIR,HPS_GPIO12 RGMII0_TXD2,USB1_D2,HPS_GPIO3 RGMII0_RXD3,USB1_NXT,HPS_GPIO13 RGMII0_TXD3,USB1_D3,HPS_GPIO4 RGMII0_MDC ,USB1_D6,I2C2_SCL,HPS_GPIO7 RGMII1_TX_CLK,HPS_GPIO48 RGMII0_MDIO,USB1_D5,I2C2_SDA,HPS_GPIO6 RGMII1_TX_CTL,HPS_GPIO51 RGMII0_RX_CTL,USB1_D7,HPS_GPIO8 RGMII1_RXD0,HPS_GPIO52 RGMII0_RX_CLK,USB1_CLK,HPS_GPIO10 RGMII1_RXD1,HPS_GPIO53 RGMII0_TX_CLK,HPS_GPIO0 RGMII1_TXD0,HPS_GPIO49 RGMII0_TX_CTL,HPS_GPIO9 RGMII1_TXD1,HPS_GPIO50 Bank 7E RGMII1_MDC,SPIM0_MOSI,SPIS0_MOSI,HPS_GPIO55 3.3 Volt RGMII1_RXD2,SPIS1_MISO,SPIM1_MISO,HPS_GPIO60 RGMII1_MDIO,SPIM0_CLK,SPIS0_CLK,HPS_GPIO54 RGMII1_RXD3,SPIS1_SS0,SPIM1_SS0,HPS_GPIO61 RGMII1_RX_CLK,SPIS1_CLK,SPIM1_CLK,HPS_GPIO58 RGMII1_TXD2,SPIM0_MISO,SPIS0_MISO,HPS_GPIO56 RGMII1_RX_CTL,SPIS1_MOSI,SPIM1_MOSI,HPS_GPIO59 RGMII1_TXD3,SPIM0_SS0,SPIS0_SS0,HPS_GPIO57 5ASTFD5K3_F1517 B R150 4.70K, 1% MICTOR_RSTn 14,19,26 JTAG_MICTOR_TDI 14 J28 1 2 881545-2 CON2 U67 Logic 0 = pin 10 <--> pin 9 (TRST from JTAG) Logic 1 = pin 10 <--> pin 2 (TRST from MICTOR) A JTAG_MIC_SEL 1 MICTOR_TRST 2 3 Logic 0 = pin 6 <--> pin 7 (Bypass) Logic 1 = pin 6 <--> pin 4 (Enable) JTAG_MICTOR_TCK JTAG_MICTOR_TMS JTAG_MICTOR_TDO JTAG_MIC_SEL 4 5 IN1 COM1 NO1 NC1 GND V+ NO2 NC2 IN2 COM2 10 9 8 R397 10.0K MICTOR_RSTn JTAG_MICTOR_TDI JTAG_MICTOR_TCK JTAG_MICTOR_TMS JTAG_MICTOR_TDO MICTOR_TRST 14 14 14 MICTR_TRST 0 R406 JTAG_TRST 2.5V_REG_HPS C320 JTAG_HPS_TRST 14,19 3.3V 0.1uF C73 C72 0.1uF 0.001uf 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 5VDC GND CLKE D15E D14E D13E D12E D11E D10E D9E D8E D7E D6E D5E D4E D3E D2E D1E D0E 7 6 D14 J13 C14 H13 P13 M14 R13 N13 G13 D13 F13 E13 L12 M13 M12 L13 C13 A15 B14 B15 N12 A14 P12 MIC_34 MIC_36 R427 R430 DNI DNI TS5A23157 SCL SDA CLKO D15O D14O D13O D12O D11O D10O D9O D8O D7O D6O D5O D4O D3O D2O D1O D0O GND1 GND2 GND3 GND4 GND5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 39 40 41 42 43 ENET_HPS_TXD[3..0] UARTB_TX UARTB_RX 7 ENET_HPS_RXD[3..0] UARTA_TX UARTA_RX I2C_SCL_HPS I2C_SDA_HPS CLKSEL1 29 29 20,28,33 20,28,33 ENET_HPS_RX_CLK ENET_HPS_RX_DV ENET_HPS_MDIO ENET_HPS_INTn BOOTSEL0 HPS_RESETn F16 G16 E16 H16 K16 L16 TRACE_CLK_MIC R436 10.0K R101 MICTOR_PWR1 MICTOR_PWR2 TRACE_DATA7 TRACE_DATA6 TRACE_DATA5 TRACE_DATA4 TRACE_DATA3 TRACE_DATA2 TRACE_DATA1 R425 R426 R428 MIC_34 R429 MIC_36 TRACE_DATA0 5 4 27 27 27 27 HPS_RESETn J40 1 R260 10.0K 2 QSPI_SS0 3 1.00K BOOTSEL1 3.3V USB_DATA0 USB_DATA1 USB_DATA2 USB_DATA3 J41 1 2 3 R262 10.0K BOOTSEL2 1.00K R263 C BOOTSEL2 HEADER, 1x3-PIN 3.3V C242 C243 2.2uF 0.1uF XJ10 XJ11 XJ12 881545-2 881545-2 881545-2 B 3.3V 0_Ohms DNI R100 10K 10K 10K 10K 3.3V A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B 3 ENET_HPS_RX_CLK ENET_HPS_RX_DV ENET_HPS_MDIO ENET_HPS_INTn HEADER, 1x3-PIN 27 SD_CLK ENET_HPS_RXD2 ENET_HPS_RXD3 ENET_HPS_TXD2 ENET_HPS_TXD3 20 20 20 20 3.3V R261 SD_CLK G20 G19 K18 M18 ENET_HPS_RXD[3..0] HEADER, 1x3-PINJ39 R258 10.0K 1 BOOTSEL0 2 BOOTSEL0 3 1.00K R259 USER_LED_HPS1 USER_PB_HPS1 USER_PB_HPS2 USER_PB_HPS3 USB_DATA0 USB_DATA1 USB_DATA2 USB_DATA3 ENET_HPS_GTX_CLK ENET_HPS_TX_EN ENET_HPS_RXD0 ENET_HPS_RXD1 ENET_HPS_TXD0 ENET_HPS_TXD1 20 28 USER_PB_HPS[3:0] 3.3V F17 P17 F18 E18 D19 N18 E19 M17 H18 F19 ENET_HPS_GTX_CLK ENET_HPS_TX_EN ENET_HPS_MDC ENET_HPS_RESETn D USER_PB_HPS[3:0] 26 26 26 26 26 26 20 20 20 20,26 E 28 USER_DIPSW_HPS[3:0] USER_LED_HPS2 QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK USER_PB_HPS0 ENET_HPS_TXD[3..0] 28 USER_LED_HPS[3:0] USER_DIPSW_HPS[3:0] R15 A17 P15 A16 D15 G15 M15 H15 N15 F15 E15 20 19,26 USER_LED_HPS[3:0] Mictor38P 6 ENET_HPS_GTX_CLK ENET_HPS_TX_EN ENET_HPS_MDC ENET_HPS_RESETn 29 29 Date: 8 27 USB_DATA[7..0] ETHERNET INTERFACE J17 2.5V_REG_HPS XJ4 1 USB_DATA[7..0] Arria V SX (SoC) Bank 7 R551 D 2 Micro SD / USB INTERFACE 2.5V_HPS J38 3 U41D 3.3V E 4 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 7 of 1 45 C1 8 7 6 5 4 3 2 1 FMC PORT A INTERFACE Arria V ST Bank 8 FMC_SDA FMC_LA_TX_CLK_P FMC_LA_TX_CLK_N 24 FMC_SCL FMC_LA_TX_P[17:0] 24 FMC_PRSNTn 24 24 24 FMC_LA_TX_N[17:0] 24,28 E 24 E FMC_LA_RX_P[15:0] 10,24 FMC_LA_RX_N[15:0] U41F U41Q Arria V SX (SoC) Bank 8 D C FMCB_LA_TX_N9 F33 FMCB_LA_RX_P0 FMCB_LA_RX_N0 FMCB_LA_TX_P0 FMCB_LA_TX_N0 FMCB_LA_RX_P1 FMCB_LA_RX_N1 FMCB_LA_TX_P1 FMCB_LA_TX_N1 FMCB_LA_RX_P2 FMCB_LA_RX_N2 FMCB_LA_TX_P2 FMCB_LA_TX_N2 FMCB_LA_RX_P3 FMCB_LA_RX_N3 B31 A30 A31 A32 A33 B33 H31 J31 C31 D31 C32 D32 N31 P31 FMCB_LA_TX_P3 FMCB_LA_TX_N3 J32 K32 FMCB_GPIO1 G32 FMCB_LA_TX_P10 FMCB_LA_RX_P8 FMCB_LA_RX_N8 J30 N30 P30 FMCB_LA_RX_P9 FMCB_LA_RX_N9 FMCB_GA1 FMCB_LA_RX_P10 FMCB_LA_RX_N10 FMCB_LA_TX_CLK_P FMCB_LA_RX_P11 FMCB_LA_RX_N11 FMCB_LA_TX_P12 B28 C29 R30 A29 A28 L30 D30 D29 F30 FMCB_LA_TX_N12 G30 FMCB_LA_TX_CLK_N M30 K30 FMCB_LA_TX_N10 Bank 8A Variable Voltage RZQ_6,DIFFIO_TX_T114_N Arria V SX (SoC) Bank 8 HMC_BA_0,DIFFIO_RX_T102_P HMC_BA_1,DIFFIO_RX_T102_N HMC_BA_2,DIFFIO_TX_T103_P HMC_A_0,DIFFIO_RX_T94_P HMC_A_1,DIFFIO_RX_T94_N HMC_A_2,DIFFIO_TX_T95_P HMC_CK,DIFFIO_RX_T92_P HMC_A_3,DIFFIO_TX_T95_N HMC_CK#,DIFFIO_RX_T92_N HMC_A_4,DIFFIO_RX_T96_P HMC_CKE_0,HMC_RLD2_A_16,DIFFIO_TX_T93_P HMC_A_5,DIFFIO_RX_T96_N HMC_CKE_1,HMC_RLD2_A_17,DIFFIO_TX_T93_N HMC_A_6,DIFFIO_TX_T97_P HMC_A_7,DIFFIO_TX_T97_N HMC_CS#_0,DIFFIO_TX_T107_P HMC_A_8,DIFFIO_RX_T98_P HMC_CS#_1,DIFFIO_TX_T107_N HMC_A_9,DIFFIO_RX_T98_N HMC_A_10,DIFFIO_TX_T99_P HMC_ODT_0,HMC_RLD2_A_18,DIFFIO_TX_T105_P HMC_A_11,DIFFIO_TX_T99_N HMC_ODT_1,HMC_RLD2_A_20,DIFFIO_TX_T105_N HMC_A_12,DIFFIO_RX_T100_P HMC_A_13,DIFFIO_RX_T100_N HMC_RAS#,HMC_RLD2_A_21,DIFFIO_TX_T103_N HMC_CAS#,HMC_RLD2_REF#,HMC_QDR2_WPS#,DIFFIO_RX_T104_P HMC_WE#,HMC_RLD2_WE#,HMC_QDR2_RPS#,DIFFIO_RX_T104_N HMC_A_14,DIFFIO_TX_T101_P HMC_A_15,DIFFIO_TX_T101_N DQ11T DIFFIO_TX_T112_P,DQ11T DIFFIO_TX_T114_P,DQ11T M32 N32 J34 FMCB_LA_RX_P4 FMCB_LA_RX_N4 FMCB_LA_TX_P4 B30 C30 E31 F31 FMCB_LA_RX_P5 FMCB_LA_RX_N5 FMCB_LA_TX_P5 FMCB_LA_TX_N5 L34 M34 FMCB_LA_TX_P6 FMCB_LA_TX_N6 L31 M31 FMCB_LA_TX_P7 FMCB_LA_TX_N7 K34 L33 M33 FMCB_LA_TX_N4 FMCB_LA_RX_P6 FMCB_LA_RX_N6 J33 F32 E33 FMCB_GA0 FMCB_GPIO0 FMCB_LA_TX_P9 J29 R29 T29 FMCB_LA_TX_P16 FMCB_LA_RX_P12 FMCB_LA_RX_N12 L28 M28 H28 C28 D28 F28 M29 N29 F29 USB_FPGA_WR USB_FPGA_RDn FMCB_LA_TX_P13 FMCB_LA_RX_P14 FMCB_LA_RX_N14 FMCB_LA_TX_P14 FMCB_LA_RX_P15 FMCB_LA_RX_N15 FMCB_LA_TX_P15 J28 G28 K29 G29 FMCB_LA_TX_N13 FMCB_LA_TX_N14 FMCB_LA_TX_N16 FMCB_LA_TX_N15 DIFFIO_TX_T112_N Bank 8B HMC_DM1,DIFFIO_TX_T89_P Variable Voltage HMC_DQS1,HMC_RLD2_QK#1,HMC_QDR2_CQ1/CQ#1,DIFFIO_RX_T88_P HMC_DQS#1,HMC_RLD2_QK1,DIFFIO_RX_T88_N HMC_DM2,DIFFIO_TX_T82_P HMC_DQS2,HMC_RLD2_QK#2,HMC_QDR2_CQ2/CQ#2,DIFFIO_RX_T81_P HMC_DQS#2,HMC_RLD2_QK2,DIFFIO_RX_T81_N HMC_DQ1_0,DIFFIO_RX_T85_P HMC_DQ1_1,DIFFIO_RX_T85_N HMC_DQ2_0,DIFFIO_RX_T77_P HMC_DQ1_2 HMC_DQ2_1,DIFFIO_RX_T77_N HMC_DQ1_3,DIFFIO_RX_T86_P HMC_DQ2_2,DIFFIO_TX_T78_P HMC_DQ1_4,DIFFIO_RX_T86_N HMC_DQ2_3,DIFFIO_RX_T79_P HMC_DQ1_5,DIFFIO_TX_T87_P HMC_DQ2_4,DIFFIO_RX_T79_N HMC_DQ1_6,DIFFIO_RX_T90_P HMC_DQ2_5,DIFFIO_TX_T80_P HMC_DQ1_7,DIFFIO_RX_T90_N HMC_DQ2_6,DIFFIO_RX_T83_P HMC_DQ1_8,DIFFIO_TX_T91_P HMC_DQ2_7,DIFFIO_RX_T83_N HMC_DQ2_8,DIFFIO_TX_T84_P HMC_RESET#,HMC_RLD2_A_19,DIFFIO_TX_T91_N DIFFIO_TX_T78_N DIFFIO_TX_T87_N DIFFIO_TX_T80_N DIFFIO_TX_T89_N DIFFIO_TX_T82_N DIFFIO_TX_T84_N 5ASTFD5K3_F1517 B K27 R28 T28 FMC_LA_TX_P6 FMC_LA_RX_P0 FMC_LA_RX_N0 FMC_LA_RX_P1 FMC_LA_RX_N1 FMC_LA_TX_P0 FMC_GPIO6 FMC_GPIO7 FMC_LA_TX_P2 FMC_LA_RX_P2 FMC_LA_RX_N2 FMC_LA_TX_P3 P27 R27 H27 B27 C27 E27 M27 N27 N28 FMC_LA_TX_P1 FMC_LA_RX_P3 FMC_LA_RX_N3 FMC_LA_RX_P4 FMC_LA_RX_N4 FMC_PRSNTn FMC_LA_RX_P5 FMC_LA_RX_N5 FMC_LA_TX_P4 FMC_LA_RX_P6 FMC_LA_RX_N6 FMC_LA_TX_P5 J26 M26 N26 C26 D26 K25 R26 T27 A26 F26 G26 M25 FMC_LA_TX_P7 USB_FPGA_DATA0 FMC_LA_TX_P9 N21 D21 R21 FMC_GA0 FMC_SDA C23 D23 FMC_SCL FMC_LA_RX_P8 FMC_LA_RX_N8 FMC_LA_TX_P10 USB_FPGA_DATA1 FMC_LA_RX_P9 FMC_LA_RX_N9 FMC_LA_TX_P12 J22 E22 F22 A23 L22 N22 P22 R22 FMC_LA_TX_N7 USB_FPGA_DATA2 FMC_LA_TX_N9 FMC_LA_TX_N10 USB_FPGA_DATA3 FMC_LA_TX_N12 P21 E21 T21 A24 M22 T22 10,24 FMC_GA[1:0] 24 FMC_GPIO[7:0] Bank 8C HMC_DM3,DIFFIO_TX_T74_P Variable Voltage HMC_DQS3,HMC_RLD2_QK#3,HMC_QDR2_CQ3/CQ#3,DIFFIO_RX_T73_P HMC_DQS#3,HMC_RLD2_QK3,DIFFIO_RX_T73_N HMC_DM5,DIFFIO_TX_T59_P HMC_DQS5,HMC_RLD2_QK#5,HMC_QDR2_CQ5/CQ#5,DIFFIO_RX_T58_P HMC_DQS#5,HMC_RLD2_QK5,DIFFIO_RX_T58_N HMC_DQ3_0,DIFFIO_RX_T69_P HMC_DQ3_1,DIFFIO_RX_T69_N HMC_DQ5_0,DIFFIO_RX_T54_P HMC_DQ3_2,DIFFIO_TX_T70_P HMC_DQ5_1,DIFFIO_RX_T54_N HMC_DQ3_3,DIFFIO_RX_T71_P HMC_DQ5_2,DIFFIO_TX_T55_P HMC_DQ3_4,DIFFIO_RX_T71_N HMC_DQ5_3,DIFFIO_RX_T56_P HMC_DQ3_5,DIFFIO_TX_T72_P HMC_DQ5_4,DIFFIO_RX_T56_N HMC_DQ3_6,DIFFIO_RX_T75_P HMC_DQ5_5,DIFFIO_TX_T57_P HMC_DQ3_7,DIFFIO_RX_T75_N HMC_DQ5_6,DIFFIO_RX_T60_P HMC_DQ3_8,DIFFIO_TX_T76_P HMC_DQ5_7,DIFFIO_RX_T60_N HMC_DQ5_8,DIFFIO_TX_T61_P HMC_DM4,DIFFIO_TX_T66_P HMC_DQS4,HMC_RLD2_QK#4,HMC_QDR2_CQ4/CQ#4,DIFFIO_RX_T65_P HMC_DQS#4,HMC_RLD2_QK4,DIFFIO_RX_T65_N DIFFIO_TX_T55_N HMC_DQ4_0,DIFFIO_RX_T62_P DIFFIO_TX_T57_N HMC_DQ4_1,DIFFIO_RX_T62_N DIFFIO_TX_T59_N HMC_DQ4_2 DIFFIO_TX_T61_N HMC_DQ4_3,DIFFIO_RX_T63_P DIFFIO_TX_T64_N HMC_DQ4_4,DIFFIO_RX_T63_N DIFFIO_TX_T66_N HMC_DQ4_5,DIFFIO_TX_T64_P DIFFIO_TX_T68_N HMC_DQ4_6,DIFFIO_RX_T67_P DIFFIO_TX_T70_N HMC_DQ4_7,DIFFIO_RX_T67_N DIFFIO_TX_T72_N HMC_DQ4_8,DIFFIO_TX_T68_P DIFFIO_TX_T74_N DIFFIO_TX_T76_N Bank 8D DIFFIO_TX_T32_P,DQ1T Variable Voltage DIFFIO_TX_T34_P,DQ1T DIFFIO_RX_T50_P,DQS3T DIFFIO_TX_T38_P,DQ1T DIFFIO_RX_T50_N,DQSn3T DIFFIO_RX_T42_P,DQS2T DIFFIO_RX_T42_N,DQSn2T DIFFIO_RX_T46_P,DQ3T DIFFIO_RX_T46_N,DQ3T DIFFIO_TX_T47_P,DQ3T DIFFIO_RX_T48_P,DQ3T DIFFIO_RX_T48_N,DQ3T DIFFIO_TX_T49_P,DQ3T DIFFIO_TX_T51_P,DQ3T DIFFIO_RX_T52_P,DQ3T DIFFIO_TX_T53_P,DQ3T DIFFIO_RX_T52_N,DQ3T DQ2T DIFFIO_RX_T40_P,DQ2T DIFFIO_RX_T40_N,DQ2T DIFFIO_TX_T41_P,DQ2T DIFFIO_TX_T43_P,DQ2T DIFFIO_RX_T44_P,DQ2T DIFFIO_RX_T44_N,DQ2T DIFFIO_TX_T45_P,DQ2T DIFFIO_TX_T32_N DIFFIO_TX_T34_N DIFFIO_TX_T38_N DIFFIO_TX_T41_N DIFFIO_TX_T43_N DIFFIO_TX_T45_N DIFFIO_TX_T47_N DIFFIO_TX_T49_N DIFFIO_TX_T51_N DIFFIO_TX_T53_N 24 K24 A25 B25 FMC_LA_TX_P13 FMC_LA_RX_P10 FMC_LA_RX_N10 T26 T25 G25 N24 P24 R24 D25 E25 P25 FMC_LA_RX_P11 FMC_LA_RX_N11 FMC_LA_TX_P14 FMC_LA_RX_P12 FMC_LA_RX_N12 FMC_LA_TX_P15 FMC_LA_RX_P13 FMC_LA_RX_N13 FMC_GA1 H25 T24 L24 R25 A27 K26 N25 J27 F27 L27 P28 FMC_LA_TX_N14 FMC_LA_TX_N15 FMC_LA_TX_N13 USB_FPGA_TXEn FMC_LA_TX_N4 FMC_LA_TX_N1 FMC_LA_TX_N5 FMC_LA_TX_N0 FMC_LA_TX_N2 FMC_LA_TX_N6 FMC_LA_TX_N3 D24 E24 FMC_LA_RX_P14 FMC_LA_RX_N14 F23 G23 R23 B24 C24 M23 J23 F24 H24 G24 FMC_LA_RX_P15 FMC_LA_RX_N15 FMC_LA_TX_P16 FMC_GPIO0 FMC_GPIO1 FMC_LA_TX_CLK_P FMC_LA_TX_P17 FMC_GPIO2 FMC_GPIO4 FMC_GPIO3 T23 N23 K23 J24 FMC_LA_TX_N16 FMC_LA_TX_CLK_N FMC_LA_TX_N17 FMC_GPIO5 D C B 5ASTFD5K3_F1517 USB FPGA INTERFACE USB_FPGA_DATA[7..0] USB_FPGA_WR USB_FPGA_RDn USB_FPGA_TXEn FMC PORT B INTERFACE 10,27 27 27 27 FMCB_LA_TX_P[17:0] FMCB_LA_TX_N[17:0] FMCB_LA_RX_P[15:0] FMCB_LA_RX_N[15:0] FMCB_GA[1:0] A FMCB_LA_TX_CLK_P FMCB_LA_TX_CLK_N FMCB_GPIO[7:0] 10,25 10,25 10,25 10,25 25 Title 6,25 Size B Date: 8 7 6 5 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 25 25 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 8 of 1 45 C1 8 7 6 5 4 FMCB_DP_M2C_N[3:0] FMCB_DP_C2M_P[3:0] 25 FMC_DP_M2C_P[7:0] 25 FMC_DP_M2C_N[7:0] U41M 25 FMCB_DP_C2M_N[3:0] 24 FMCB_DP_M2C_P0 AW37 FMCB_DP_M2C_N0 AW36 AT39 AT38 FMCB_DP_M2C_P1 AP39 FMCB_DP_M2C_N1 AP38 FMCB_DP_M2C_P2 AM39 FMCB_DP_M2C_N2 AM38 AK39 AK38 FMCB_DP_M2C_P3 AH39 FMCB_DP_M2C_N3 AH38 FMCB_GBTCLK_M2C_P0 FMCB_GBTCLK_M2C_N0 FMCB_GBTCLK_M2C_P1 FMCB_GBTCLK_M2C_N1 AG32 AG33 AE31 AE32 GXB_RX_L0p,GXB_REFCLK_L0p GXB_RX_L0n,GXB_REFCLK_L0n GXB_RX_L1p,GXB_REFCLK_L1p GXB_RX_L1n,GXB_REFCLK_L1n GXB_RX_L2p,GXB_REFCLK_L2p GXB_RX_L2n,GXB_REFCLK_L2n GXB_RX_L3p,GXB_REFCLK_L3p GXB_RX_L3n,GXB_REFCLK_L3n GXB_RX_L4p,GXB_REFCLK_L4p GXB_RX_L4n,GXB_REFCLK_L4n GXB_RX_L5p,GXB_REFCLK_L5p GXB_RX_L5n,GXB_REFCLK_L5n FMC_DP_C2M_N[7:0] GXB_TX_L0p GXB_TX_L0n GXB_TX_L1p GXB_TX_L1n GXB_TX_L2p GXB_TX_L2n GXB_TX_L3p GXB_TX_L3n GXB_TX_L4p GXB_TX_L4n GXB_TX_L5p GXB_TX_L5n Arria V SX (SoC) Transceiver - Right 24 AU37 FMCB_DP_C2M_P0 AU36 FMCB_DP_C2M_N0 AR37 AR36 AN37 FMCB_DP_C2M_P1 AN36 FMCB_DP_C2M_N1 AL37 FMCB_DP_C2M_P2 AL36 FMCB_DP_C2M_N2 AJ37 AJ36 AG37 FMCB_DP_C2M_P3 AG36 FMCB_DP_C2M_N3 3 3 3 3 3 3 3 3 PCIE_RX_P0 PCIE_RX_N0 PCIE_RX_P1 PCIE_RX_N1 PCIE_RX_P2 PCIE_RX_N2 PCIE_RX_P3 PCIE_RX_N3 AU1 AU2 AR1 AR2 AN1 AN2 AL1 AL2 AJ1 AJ2 AG1 AG2 GXB_RX_R0p,GXB_REFCLK_R0p GXB_RX_R0n,GXB_REFCLK_R0n GXB_RX_R1p,GXB_REFCLK_R1p GXB_RX_R1n,GXB_REFCLK_R1n GXB_RX_R2p,GXB_REFCLK_R2p GXB_RX_R2n,GXB_REFCLK_R2n GXB_RX_R3p,GXB_REFCLK_R3p GXB_RX_R3n,GXB_REFCLK_R3n GXB_RX_R4p,GXB_REFCLK_R4p GXB_RX_R4n,GXB_REFCLK_R4n GXB_RX_R5p,GXB_REFCLK_R5p GXB_RX_R5n,GXB_REFCLK_R5n FMC_DP_M2C_P1 FMC_DP_M2C_N1 FMC_DP_M2C_P2 FMC_DP_M2C_N2 FMC_DP_M2C_P3 FMC_DP_M2C_N3 C FMC_GBTCLK_M2C_P0 FMC_GBTCLK_M2C_N0 FMC_GBTCLK_M2C_P1 FMC_GBTCLK_M2C_N1 AF39 AF38 AD39 AD38 AB39 AB38 Y39 Y38 V39 V38 T39 T38 AC31 AC32 AA31 AA32 GXB_RX_L6p,GXB_REFCLK_L6p GXB_RX_L6n,GXB_REFCLK_L6n GXB_RX_L7p,GXB_REFCLK_L7p GXB_RX_L7n,GXB_REFCLK_L7n GXB_RX_L8p,GXB_REFCLK_L8p GXB_RX_L8n,GXB_REFCLK_L8n GXB_RX_L9p,GXB_REFCLK_L9p GXB_RX_L9n,GXB_REFCLK_L9n GXB_RX_L10p,GXB_REFCLK_L10p GXB_RX_L10n,GXB_REFCLK_L10n GXB_RX_L11p,GXB_REFCLK_L11p GXB_RX_L11n,GXB_REFCLK_L11n FMC_DP_M2C_P5 FMC_DP_M2C_N5 FMC_DP_M2C_P6 FMC_DP_M2C_N6 FMC_DP_M2C_P7 FMC_DP_M2C_N7 12 12 GXB_TX_L6p GXB_TX_L6n GXB_TX_L7p GXB_TX_L7n GXB_TX_L8p GXB_TX_L8n GXB_TX_L9p GXB_TX_L9n GXB_TX_L10p GXB_TX_L10n GXB_TX_L11p GXB_TX_L11n AE37 FMC_DP_C2M_P0 AE36 FMC_DP_C2M_N0 AC37 AC36 AA37 FMC_DP_C2M_P1 AA36 FMC_DP_C2M_N1 W37 FMC_DP_C2M_P2 W36 FMC_DP_C2M_N2 U37 U36 R37 FMC_DP_C2M_P3 R36 FMC_DP_C2M_N3 REFCLK2Lp REFCLK2Ln REFCLK3Lp REFCLK3Ln W31 W32 U31 U32 LMK_FMCCLK_P LMK_FMCCLK_N CLK_148_P CLK_148_N GXB_RX_L12p,GXB_REFCLK_L12p GXB_RX_L12n,GXB_REFCLK_L12n GXB_RX_L13p,GXB_REFCLK_L13p GXB_RX_L13n,GXB_REFCLK_L13n GXB_RX_L14p,GXB_REFCLK_L14p GXB_RX_L14n,GXB_REFCLK_L14n GXB_RX_L15p,GXB_REFCLK_L15p GXB_RX_L15n,GXB_REFCLK_L15n GXB_RX_L16p,GXB_REFCLK_L16p GXB_RX_L16n,GXB_REFCLK_L16n GXB_RX_L17p,GXB_REFCLK_L17p GXB_RX_L17n,GXB_REFCLK_L17n PCIE_TX_P0 PCIE_TX_N0 PCIE_TX_P1 PCIE_TX_N1 PCIE_TX_P2 PCIE_TX_N2 PCIE_TX_P3 PCIE_TX_N3 3 3 3 3 3 3 3 3 CMU PLL (PCIe) D 22 22 SFPA_RX_P SFPA_RX_N 23 23 SFPB_RX_P SFPB_RX_N SMA_XCVR_RX_P SMA_XCVR_RX_N AE1 AE2 AC1 AC2 AA1 AA2 W1 W2 U1 U2 R1 R2 12 12 11 11 LMK_SFPCLK_P LMK_SFPCLK_N REFCLK_QR2_P REFCLK_QR2_N AB9 AB8 Y9 Y8 GXB_TX_L12p GXB_TX_L12n GXB_TX_L13p GXB_TX_L13n GXB_TX_L14p GXB_TX_L14n GXB_TX_L15p GXB_TX_L15n GXB_TX_L16p GXB_TX_L16n GXB_TX_L17p GXB_TX_L17n REFCLK4Lp REFCLK4Ln REFCLK5Lp REFCLK5Ln N37 N36 L37 L36 J37 J36 G37 G36 E37 E36 C37 C36 GXB_RX_R6p,GXB_REFCLK_R6p GXB_RX_R6n,GXB_REFCLK_R6n GXB_RX_R7p,GXB_REFCLK_R7p GXB_RX_R7n,GXB_REFCLK_R7n GXB_RX_R8p,GXB_REFCLK_R8p GXB_RX_R8n,GXB_REFCLK_R8n GXB_RX_R9p,GXB_REFCLK_R9p GXB_RX_R9n,GXB_REFCLK_R9n GXB_RX_R10p,GXB_REFCLK_R10p GXB_RX_R10n,GXB_REFCLK_R10n GXB_RX_R11p,GXB_REFCLK_R11p GXB_RX_R11n,GXB_REFCLK_R11n GXB_TX_R6p GXB_TX_R6n GXB_TX_R7p GXB_TX_R7n GXB_TX_R8p GXB_TX_R8n GXB_TX_R9p GXB_TX_R9n GXB_TX_R10p GXB_TX_R10n GXB_TX_R11p GXB_TX_R11n REFCLK2Rp REFCLK2Rn REFCLK3Rp REFCLK3Rn RREF_BR AD3 AD4 AB3 AB4 Y3 Y4 V3 V4 T3 T4 P3 P4 SFPA_TX_P SFPA_TX_N SFPB_TX_P SFPB_TX_N SMA_XCVR_TX_P SMA_XCVR_TX_N C150 SMA_XCVR_RX_P SMA_XCVR_RX_N 0.1uF C151 0.1uF SMA_XCVR_RX_C_P SMA_XCVR_RX_C_N FMC_DP_C2M_P5 FMC_DP_C2M_N5 FMC_DP_C2M_P6 FMC_DP_C2M_N6 FMC_DP_C2M_P7 FMC_DP_C2M_N7 23 23 AW2 XCVR_RREF_BR 5ASTFD5K3_F1517 FMC_DP_C2M_P4 FMC_DP_C2M_N4 22 22 CAD Note: Place resistor near RREF_TL pins. Route away frm aggressor C R575 2.00K 1% TX SMA Connector Interface RX SMA Connector Interface J24 1 J31 1 RREF_TL B39 XCVR_RREF_TL B 5ASTFD5K3_F1517 10.0K From MAXV 19 11,19 SI571_EN 2 I2C_SDA_MAX 7 8 3 A C114 C117 0.1uF 10uF Si571 Programmable Oscillator Use Clock Control GUI (Default 148.5MHz) I2C Address 55 HEX OE VDD SDA CLK+ SCL CLK- GND VC Si571 4 4 CAD Note: Place resistor near RREF_TL pins. Route away frm aggressor 6 LVDS 4 CLK_148_CP C115 0.1uF CLK_148_P 5 CLK_148_CN C116 0.1uF CLK_148_N 1 SI571_VCONTROL SDI_CLK148_UP 4.99K R127 C112 Title From FPGA SDI_CLK148_DN R129 4.99K R126 180K C104 7 0.1uF Size B 6 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 1000pF Date: 8 J25 1 J32 1 X3 I2C_SCL_MAX 11,19 2.5V_REG_HPS 2 3 4 5 R120 R505 2.00K 1% 2 3 4 5 SDI Reference Clocks 2 3 4 5 2 3 4 5 B P39 P38 M39 M38 K39 K38 H39 H38 F39 F38 D39 D38 AT3 AT4 AP3 AP4 AM3 AM4 AK3 AK4 AH3 AH4 AF3 AF4 GXB_R1 GXB_L2 FMC_DP_M2C_P4 FMC_DP_M2C_N4 GXB_TX_R0p GXB_TX_R0n GXB_TX_R1p GXB_TX_R1n GXB_TX_R2p GXB_TX_R2n GXB_TX_R3p GXB_TX_R3n GXB_TX_R4p GXB_TX_R4n GXB_TX_R5p GXB_TX_R5n REFCLK0Rp REFCLK0Rn REFCLK1Rp REFCLK1Rn GXB_L1 FMC_DP_M2C_P0 FMC_DP_M2C_N0 E GXB_R0 PCIE_REFCLK_QR0_P AF8 PCIE_REFCLK_QR0_N AF7 AD9 AD8 R593 10.0K 11 11 REFCLK0Lp REFCLK0Ln REFCLK1Lp REFCLK1Ln U41R 24 GXB_L0 24 24 24 24 1 24 FMC_DP_C2M_P[7:0] Arria V SX (SoC) Transceiver - Left 25 E D 2 Arria V ST Transceivers FMCB_DP_M2C_P[3:0] 25 25 25 25 3 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 9 of 1 45 C1 8 7 6 5 4 3 2 1 Arria V ST Clocks 24 FMC_CLK_M2C_P[1:0] 25 FMCB_CLK_M2C_P[1:0] 24 FMC_CLK_M2C_N[1:0] 25 FMCB_CLK_M2C_N[1:0] E E U41N Arria V SX (SoC) Clocks CLK_BOT1 11 CLK_TOP1 11 CLK_ENET_FPGA_PHY 11 CLK_50M_FPGA D CLK_ENET_FPGA_P CLK_ENET_FPGA_N AP34 AN34 CLK_BOT1 CLK_TOP1 AK34 AJ34 CLK_ENET_FPGA_PHY AM33 AL33 11 CLK_50M_FPGA AU32 AT32 11 11 CLK_ENET_FPGA_P CLK_ENET_FPGA_N AV19 AU19 CLK_100M_FPGA CLK_100M_FPGA 11 SFPB_TXFAULT 23 12 12 LMK_CLEAN_CLK_P LMK_CLEAN_CLK_N 12 12 LMK_SYSREF_P LMK_SYSREF_N C I2C_SCL_FPGA I2C_SDA_FPGA 1 SFPB_MOD2_SDA AK7 AJ7 FMCB_CLK_M2C_P0 FMCB_CLK_M2C_N0 C34 D34 FMCB_CLK_M2C_P1 FMCB_CLK_M2C_N1 G34 H34 SMA_CLKIN 23 CLK3_P,DIFFIO_RX_B9_P,DQ2B CLK3_N,DIFFIO_RX_B9_N,DQ2B FPLL_BL_CLKOUT2,FPLL_BL_FBp,FPLL_BL_FB1,DIFFIO_RX_B6_P,DQ1B FPLL_BL_CLKOUT3,FPLL_BL_FBn,DIFFIO_RX_B6_N,DQ1B AM34 AL34 AK33 AJ33 Bank 3D D 2.5 Volt CLK7_P,DIFFIO_RX_B84_P,DQ11B CLK7_N,DIFFIO_RX_B84_N,DQ11B FPLL_BC_CLKOUT0,FPLL_BC_CLKOUT_P,FPLL_BC_FB0,DIFFIO_TX_B79_P,DQ11B FPLL_BC_CLKOUT1,FPLL_BC_CLKOUT_N,DIFFIO_TX_B79_N CLK6_P,DIFFIO_RX_B82_P,DQ11B CLK6_N,DIFFIO_RX_B82_N,DQ11B FPLL_BC_CLKOUT2,FPLL_BC_FBp,FPLL_BC_FB1,DIFFIO_RX_B80_P,DQS11B FPLL_BC_CLKOUT3,FPLL_BC_FBn,DIFFIO_RX_B80_N,DQSn11B AC22 AD21 AH21 AG21 PCIE_PRSNT2_X1 PCIE_PRSNT2_X4 3 3 PCIE_PERSTn SFPB_LOS 3,13 23 Bank 4A CLK8_P,DIFFIO_RX_B168_P,DQ22B CLK8_N,DIFFIO_RX_B168_N,DQ22B AW4 AV4 AT7 AR7 19 J15 AL20 AK20 LMK_RESET SPI_SDIO 19 FPLL_BL_CLKOUT0,FPLL_BL_CLKOUT_P,FPLL_BL_FB0,DIFFIO_TX_B5_P,DQ1B FPLL_BL_CLKOUT1,FPLL_BL_CLKOUT_N,DIFFIO_TX_B5_N CLK5_P,DIFFIO_RX_B78_P,DQ11B CLK5_N,DIFFIO_RX_B78_N,DQ11B AR6 AP6 0 R591 0 R592 CLK2_P,DIFFIO_RX_B7_P,DQ1B CLK2_N,DIFFIO_RX_B7_N,DQ1B CLK4_P,DIFFIO_RX_B76_P,DQ10B CLK4_N,DIFFIO_RX_B76_N,DQ10B AD20 AC21 I2C_SCL I2C_SDA 19,31,32 19,31,32 1.5 Volt CLK1_P,DIFFIO_RX_B4_P,DQS1B CLK1_N,DIFFIO_RX_B4_N,DQSn1B AF21 AE21 SPI_CLK SPI_CSn 19 19 Bank 3A CLK0_P,DIFFIO_RX_B2_P,DQ1B CLK0_N,DIFFIO_RX_B2_N,DQ1B 2.5 Volt CLK9_P,DIFFIO_RX_B166_P,DQ22B CLK9_N,DIFFIO_RX_B166_N,DQ22B CLK10_P,DIFFIO_RX_B164_P,DQS22B CLK10_N,DIFFIO_RX_B164_N,DQSn22B FPLL_BR_CLKOUT0,FPLL_BR_CLKOUT_P,FPLL_BR_FB0,DIFFIO_TX_B161_P,DQ22B FPLL_BR_CLKOUT1,FPLL_BR_CLKOUT_N,DIFFIO_TX_B161_N CLK11_P,DIFFIO_RX_B160_P,DQ21B CLK11_N,DIFFIO_RX_B160_N,DQ21B FPLL_BR_CLKOUT2,FPLL_BR_FBp,FPLL_BR_FB1,DIFFIO_RX_B162_P,DQ22B FPLL_BR_CLKOUT3,FPLL_BR_FBn,DIFFIO_RX_B162_N,DQ22B C AM7 RCLOCK_OUT_P AL7 RCLOCK_OUT_N 12 RCLOCK_OUT_P 12 RCLOCK_OUT_N AP8 SFPB_MOD0_PRSNTn AN8 SFPB_MOD1_SCL 23 23 SFPB_MOD0_PRSNTn SFPB_MOD1_SCL 25 25 FMCB_LA_RX_P13 FMCB_LA_RX_N13 5 4 3 2 R353 49.9 DEVCLKB 25 25 Alt. DEVCLK 25 25 FMC PORT B B DEVCLKB 24 24 Alt. DEVCLK 24 24 FMCPORT A FMCB_LA_RX_CLK_P FMCB_LA_RX_CLK_N E34 F34 FMCB_LA_RX_P7 FMCB_LA_RX_N7 N34 N33 FMC_CLK_M2C_P0 FMC_CLK_M2C_N0 B22 C22 FMC_CLK_M2C_P1 FMC_CLK_M2C_N1 A22 A21 FMC_LA_RX_CLK_P FMC_LA_RX_CLK_N H21 J21 FMC_LA_RX_P7 FMC_LA_RX_N7 C20 D20 Bank 8A CLK20_P,DIFFIO_RX_T113_P,DQ11T CLK20_N,DIFFIO_RX_T113_N,DQ11T Variable Voltage CLK21_P,DIFFIO_RX_T111_P,DQS11T CLK21_N,DIFFIO_RX_T111_N,DQSn11T CLK22_P,DIFFIO_RX_T108_P,DQ11T CLK22_N,DIFFIO_RX_T108_N,DQ11T FPLL_TL_CLKOUT0,FPLL_TL_CLKOUT_P,FPLL_TL_FB0,DIFFIO_TX_T110_P,DQ11T FPLL_TL_CLKOUT1,FPLL_TL_CLKOUT_N,DIFFIO_TX_T110_N CLK23_P,DIFFIO_RX_T106_P,DQ10T CLK23_N,DIFFIO_RX_T106_N,DQ10T FPLL_TL_CLKOUT2,FPLL_TL_FBp,FPLL_TL_FB1,DIFFIO_RX_T109_P,DQ11T FPLL_TL_CLKOUT3,FPLL_TL_FBn,DIFFIO_RX_T109_N,DQ11T C33 FMCB_LA_TX_P17 D33 FMCB_LA_TX_N17 25 25 B34 FMCB_LA_RX_P13 A35 FMCB_LA_RX_N13 B Bank 8D CLK16_P,DIFFIO_RX_T39_P,DQ2T CLK16_N,DIFFIO_RX_T39_N,DQ2T Variable Voltage CLK17_P,DIFFIO_RX_T37_P,DQ1T CLK17_N,DIFFIO_RX_T37_N,DQ1T CLK18_P,DIFFIO_RX_T33_P,DQ1T CLK18_N,DIFFIO_RX_T33_N,DQ1T FPLL_TC_CLKOUT0,FPLL_TC_CLKOUT_P,FPLL_TC_FB0,DIFFIO_TX_T36_P,DQ1T FPLL_TC_CLKOUT1,FPLL_TC_CLKOUT_N,DIFFIO_TX_T36_N CLK19_P,DIFFIO_RX_T31_P,DQ1T CLK19_N,DIFFIO_RX_T31_N,DQ1T FPLL_TC_CLKOUT2,FPLL_TC_FBp,FPLL_TC_FB1,DIFFIO_RX_T35_P,DQS1T FPLL_TC_CLKOUT3,FPLL_TC_FBn,DIFFIO_RX_T35_N,DQSn1T K21 L21 USB_FPGA_DATA4 USB_FPGA_DATA5 A20 B21 USB_FPGA_DATA6 USB_FPGA_DATA7 5ASTFD5K3_F1517 A FMC_CLK_M2C_P0 R532 100, 1% FMC_CLK_M2C_N0 FMCB_CLK_M2C_P0 R514 100, 1% FMCB_CLK_M2C_N0 FMC_CLK_M2C_P1 R533 100, 1% FMC_CLK_M2C_N1 FMCB_CLK_M2C_P1 R512 100, 1% FMCB_CLK_M2C_N1 FMC_LA_RX_CLK_P R536 100, 1% FMC_LA_RX_CLK_N FMCB_LA_RX_CLK_P R513 FMC_LA_RX_P7 R537 100, 1% FMC_LA_RX_N7 FMCB_LA_RX_P7 R517 Title 100, 1% FMCB_LA_RX_CLK_N USB_FPGA_DATA[7..0] USB_FPGA_DATA[7..0] 8,27 Size 100, 1% FMCB_LA_RX_N7 B Date: 8 7 6 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 10 of 1 45 C1 8 7 6 5 4 3 2 1 PLL 3.3V DNI C244 PCIE_REFCLK_QR0_P C240 PCIE_REFCLK_SYN_P 2.5V_REG_HPS R284 2.5V_REG_HPS 0.1uF 2.2uF PCIE_REFCLK_QR0_N PCIE_REFCLK_SYN_N R286 E E DNI 1.00K SI570_EN DNI I2C_SDA_MAX DNI I2C_SCL_MAX C56 C55 0.1uF 2.2uF U59 1 10 X2 8 3 CLK+ SCL CLK- GND 4 REFCLK_QR2_C_P C64 100, 1% REFCLK_QR2_C_N C63 R86 5 0.1uF REFCLK_QR2_P 9 0.1uF REFCLK_QR2_N 3 9 1 NC 4 C237 DNI 4 5 SI570 Si570 Programmable Oscillator Use Clock Control GUI (Default 100MHz) I2C Address 66 HEX C143 C123 C124 C130 C133 742792780 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1 2 3 2.5V_PLL1 R148 R147 4 5 6 DNI DNI I2C_SCL_MAX I2C_SDA_MAX 9,11,19 C 12 19 VDD1 VDD2 VDDO3 VDDO2 VDDO1 VDDO0 CLKIN_P CLKIN_N CLKIN I2C_LSB FDBK_P FDBK_N INTR SCL CLK3B CLK3A SDA CLK2B CLK2A CLK1B CLK1A CLK0B CLK0A RSVD_GND EPAD 2.5V_REG_HPS C162 C166 CLK125A_EN 14,19 C167 0.1uF 0.1uF 0.1uF 2.5V_REG_HPS B DNI 3 Y4 25.00MHz 2 C152 DNI 2.5V_REG_HPS C156 0.1uF A VDD VDD XA_CLKIN XB_CLKINB VDDO0 VDDO1 VDDO2 VDDO3 1 4 1 2 12 19 3 5 6 C161 0.1uF 8 9 CLK_DIFF2_N CLK0A CLK0B P1 P2 P3 P5 P6 CLK1A CLK1B CLK2A CLK2B LOS CLK3A CLK3B GND RSVD_GND EPAD 7 24 11 15 16 20 3 3 8 9 10 13 14 2.5V_REG_HPS 2.5V_PLL1 C390 21 22 1V8_PLL L35 1V8 0.1uF R149 C423 C424 0.1uF 0.1uF 1.00K CLK_BOT1 100MHz C448 C449 18 17 0.1uF 0.1uF CLK_ENET_FPGA_N 10 3 GND 14 10 8 4 J49 25Mhz CLK_OSC1 1 SMA 7 CLK_TOP1 156.25MHz OSC2_CLK_SMA OSC2_HPS_CLK 0.01uF C261 10 2.5V_REG_HPS 2.5V_REG_HPS 3 R146 DNI CMOS R311 DNI 2.5V_REG_HPS 4 7 9 OSC2_CLK_SEL1 OSC2_CLK_SEL0 Y6 VDD OUT EN GND 3 CLK0 CLK1 CLK2 CLK3 OE SEL1 SEL0 1 CLK50_EN 2 1V8 0.1uF 0.1uF 10 9 CLK_100M_MAX 19 CLK_100M_FPGA 10 VCC GND OUT U30 4 2 3 50MHz 25Mhz C374 CLKIN_50 1V8 C375 2.2uF 0.1uF 3 6 7 5 CLKIN OE1 OE2 OE3 CLKOUT1 CLKOUT2 CLKOUT3 OE_OSC GND 4 23 25 L30 3A, 30 Ohm FB Y2 1 VC VDD GND OUT C315 C310 0.1uF 2.2uF 5 1.00K 2.5V_REG_HPS R293 1.00K 2.5V_REG_HPS R292 B 8 R132 9 R130 10 22 22 4 4 CLK_50M_MAX CLK_50M_FPGA 19 10 1V8 1 C382 C383 0.1uF 0.1uF A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 VCXO 12 Size B Date: 6 OSC2_CLK_SEL0 4 Title 2 TP8 7 3.3V_VCXO 100Mhz CP1 CLK_OSC2 CON2 VDD 3.3V 12 22 J46 CON2 OSC2_CLK_SEL1 1 2 1V8 EN 25Mhz 100Mhz C 2 6 11 13 15 NC1 NC2 NC3 NC4 NC5 1 2 SL18860DC 14 13 0.1uF 1V8 X4 C144 0.1uF 1 R681 Q 2 J45 10.0K C145 C834 OSC2_HPS_CLK ICS83054I OSC_33MHZ 19 C840 742792780 10 122.88 MHz 7 10 5 U62 R131 21 VCC 25Mhz 2.5V_REG_HPS CLK_DUAL_ENET_PHY OUTn CLK_ENET_FPGA_P OSC1_CLK_SEL = HIGH selects (OSC1_CLK_SMA) SMA input 2.5V_REG_HPS OSC1_CLK_SEL = LOW selects (OSC1_CLK_SYN) Si5356A input 2.5V_CLK_MUX L41 742792780 1V8 10 NC 4 10uF 2.5V_PLL1 Si5358 Programmable Oscillator Use Clock Control GUI (Defaults 156.25MHz, 156.25MHz,25MHz,25MHz, 25MHz, 25MHz,100MHz, 100MHz) I2C Address 70 HEX CLK_ENET_FPGA_PHY OUT 125.0MHz 23 25 20 16 15 11 22 21 C388 EN OSC2_CLK_SYN 17 18 24 7 1V8 X5 1 6 Si5335 8 0 PCIE_REFCLK_SYN_P R283 0 PCIE_REFCLK_SYN_N R285 D 2 2.5V_PLL1 1V8_PLL Si5338A-CUSTOM C160 U42 C153 CLK_DIFF2_P 9 CLK125A_EN 1 0.1uF DIFF2 8 9 16 U35 9,11,19 1V8 VSS VSS2 CLK_DIFF1_N 5 Y3 25.00MHz 2 1 DNI DIFF2 2.5V_REG_HPS R503 1.00K CLK125A_EN 4 C132 XIN/CLKIN 7 0 PCIE_REFCLK_QR0_P R289 0 PCIE_REFCLK_QR0_N R290 Si52112 2.5V_REG_HPS DNI 3 C127 DIFF1 CLK_DIFF1_P L14 5 4 3 2 D 2.5V_PLL1 XOUT 6 VDDQ I2C_SCL_MAX SDA 2 DIFF1 12 9,11,19 7 Y5 25.00MHz 2 VDD VDD2 VDD I2C_SDA_MAX VCC DNI GND 9,11,19 OE C238 3 14,19 6 1 2 SI570_EN PLL R84 R78 R85 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 11 of 1 45 C1 8 7 6 5 4 3 2 3.3V L3 C45 C30 C31 1uF 0.1uF 0.01uF C15 3900pF C14 47pF 3.3V_VCC1_5_6 CP1 11 0.1uF R28 39K R12 620 3A, 30 Ohm FB E C35 0.68uF C34 CP2 1 E C28 C29 C8 C295 C294 1uF 0.1uF 0.01uF 0.01uF 0.01uF R357 L2 R356 J9 L28 DNI 1 LMK_CLK_N 1 DNI 2 3 4 5 3A, 30 Ohm FB 3A, 30 Ohm FB LMK_CLK_P 0.01uF C293 0.01uF C313 0.01uF C314 0.01uF J11 3A, 30 Ohm FB 0.01uF L7 3.3V_VCC2 3.3V_VCC3 3.3V_VCC4 3A, 30 Ohm FB L8 D 3.3V_VCC7 3.3V_VCC8_10 3.3V_VCC9 3A, 30 Ohm FB L4 3A, 30 Ohm FB 3.3V_VCC11 3.3V_VCC12 10 17 21 26 33 36 39 42 45 47 53 64 L5 18 3A, 30 Ohm FB CLK_CLN_IN_C_P 37 CLK_CLN_IN_C_N 38 L6 3A, 30 Ohm FB SPI_CSn 19 10 J8 C RCLOCK_OUT_P R14 RCLOCK_OUT_N 10 FROM FPGA RX_CLK 1 SMA_LMK_CLK_IN C21 5 4 3 2 R16 49.9 R15 49.9 C3 MUX_OSC_IN_N R23 L1 OSC_IN_C_P R13 OSC_IN_C_N 0.1uF R24 C6 0.1uF LO_SMA 31 48 0.1uF 5 6 19 20 SPI_CLK SPI_SDIO 11 12 3.3V C5 SPI_CSn 10K SPI_SDIO 10K R61 0.1uF R58 C23 B 65 0.01uF R59 1K R66 1K U3 13 12 C12 0.1uF 2 3 C13 VCC VCC D0p D0n 0.1uF C25 6 7 VCXO C26 11 0.1uF 0.1uF LMK_OSC_SEL 1 8 A C47 D1p D1n Q0p Q0n Q1p Q1n GND SEL0 GND SEL1 GND_PAD 4 5 15 14 MUX_OSC_IN_P MUX_OSC_IN_N D1 240 CS CLKIN0p CLKIN0n SDCLKOUT3p SDCLKOUT3n CLKIN1p/FBCLKINp/FINp CLKIN1n/FBCLKINn/FINn OSCINp OSCINn DCLKOUT4p DCLKOUT4n SDCLKOUT5p SDCLKOUT5n DCLKOUT6p DCLKOUT6n CLKin_SEL0 CLKin_SEL1 SDCLKOUT7p SDCLKOUT7n STATUS_LD1 STATUS_LD2 DCLKOUT8p DCLKOUT8n RESET SYNC SCK SDIO SDCLKOUT9p SDCLKOUT9n DCLKOUT10p DCLKOUT10n LDObyp1 LDObyp2 SDCLKOUT11p SDCLKOUT11n DAP DCLKOUT12p DCLKOUT12n SDCLKOUT13p SDCLKOUT13n 40 41 1 2 LMK_OSC_SEL 1.00K 13 14 24 25 LMKR_CLK_FMC_P LMKR_CLK_FMC_N R47 R34 0 0 LMK_CLK_FMC_P LMK_CLK_FMC_N 24 24 22 23 LMKR_SYSREF_FMC_P LMKR_SYSREF_FMC_N R49 R48 0 0 LMK_SYSREF_FMC_P LMK_SYSREF_FMC_N 24 24 27 28 LMKR_CLK_FMCB_P LMKR_CLK_FMCB_N R36 R35 0 0 LMK_CLK_FMCB_P LMK_CLK_FMCB_N 25 25 29 30 LMKR_SYSREF_FMCB_P R30 LMKR_SYSREF_FMCB_N R29 0 0 LMK_SYSREF_FMCB_P LMK_SYSREF_FMCB_N 25 25 51 52 LMK_SFPCLK_C_P C27 LMK_SFPCLK_C_N 0.1uF LMK_SFPCLK_P LMK_SFPCLK_N 9 9 0.1uF LMK_FMCCLK_P LMK_FMCCLK_N 9 9 0.1uF C33 D3 54 55 LMK_CLEAN_CLK_P LMK_CLEAN_CLK_N 10 10 56 57 LMK_SYSREF_P LMK_SYSREF_N 10 10 62 63 LMK_FMCCLK_C_P LMK_FMCCLK_C_N C41 0.1uF C42 B 60 61 820,1% J16 1 R339 820,1% R338 820,1% Green_LED A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Green_LED R337 820,1% Title 2.5V_REG_HPS R11 Size B CON2 Date: 7 C 49 50 881545-2 8 DNI 15 16 Green_LED CMOS INPUT -> LVPECL OUTPUT 1 2 DNI J12 240 D4 J7 R354 3 4 NB6L72MNG XJ13 D LMK_SDCLK_N 1 R355 R7 D2 9 16 17 DCLKOUT2p DCLKOUT2n C46 LMK_SYNC_IN R6 SDCLKOUT1p SDCLKOUT1n J10 Green_LED R340 11 10 DCLKOUT0p DCLKOUT0n 10uF 25V 0.1uF LMK_RESET VTD0 VTD1 OSCOUTp OSCOUTn 32 46 2 3 4 5 5 4 3 2 0.01uF CPOUT1 CPOUT2 C24 SPI_CLK 2.0V_VTD VCC1_VCO VCC2_GC1 VCC3_SYSREF VCC4_CG2 VCC5_DIG VCC6_PLL1 VCC7_OSCout VCC8_OSCin VCC9_CP2 VCC10_PLL2 VCC11_CG3 VCC12_CG0 0.1uF LMK_RESET J2 1 43 44 0.1uF C17 100, 1% C16 19 19 3.01K 3.3V_MUX 742792780 OSC_IN_P OSC_IN_N 0.1uF 0.1uF C4 1.96K 34 35 58 59 19 3.3V 0.1uF LMK_CLK_IN_P LMK_CLK_IN_N 0.1uF C20 MUX_OSC_IN_P C19 100, 1% C18 LMK_SDCLK_P 1 U5 LMK04828 2 3 4 5 C296 2 3 4 5 C309 2 3 4 5 L29 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 12 of 1 45 C1 8 7 6 5 4 3 2 1 Arria V ST Configuration R498 FPGA_DCLK DNI C389 DNI R497 DNI E E U41G Arria V SX (SoC) Configuration C 2.5V_REG_FPGA R515 10K FPGA_nSTATUS R518 10K FPGA_CONF_DONE R507 10K FPGA_nCONFIG R511 10K JTAG_FPGA_TDI 19 19 19 FPGA_CONFIG_D5 FPGA_CONFIG_D6 FPGA_CONFIG_D7 FPGA_CONFIG_D8 FPGA_CONFIG_D9 FPGA_CONFIG_D10 FPGA_CONFIG_D11 FPGA_CONFIG_D12 FPGA_CONFIG_D13 FPGA_CONFIG_D14 FPGA_CONFIG_D15 AW8 AV6 AK9 AK10 AN9 AM9 AW7 AW6 AW5 AU7 AU8 AP9 AJ6 AJ9 AH9 CPU_RESETn MAX_FPGA_MISO A36 F35 K35 FPGA_nCONFIG FPGA_nSTATUS FPGA_CONF_DONE M35 R489 AR34 R491 FPGA_CONFIG_D4 D AS_DATA0,ASDO,DATA0 AS_DATA1,DATA1 AS_DATA2,DATA2 AS_DATA3,DATA3 R490 AV33 AU33 AR33 AU34 USB_FPGA_RXFn MAX_FPGA_MOSI 27 MAX_FPGA_MOSI 19 19,28 MAX_FPGA_MISO 19 FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 2.5V_REG_FPGA DCLK R492 D AW34 FPGA_DCLK 18,19 Bank 3A 1.5 Volt TMS TCK TDI TDO 10K 10K 10K 10K nCSO,DATA4 Bank 4A 2.5 Volt DATA5,DIFFIO_RX_B147_P,DQ20B PR_DONE,DIFFIO_RX_B155_N,DQ21B DATA6,DIFFIO_TX_B148_P,DQ20B PR_REQUEST,DIFFIO_RX_B155_P,DQ21B DATA7,DIFFIO_TX_B150_N PR_READY,DIFFIO_TX_B154_P,DQ21B DATA8,DIFFIO_TX_B150_P,DQ20B PR_ERROR,DIFFIO_TX_B154_N DATA9,DIFFIO_TX_B152_N DATA10,DIFFIO_TX_B146_P,DQ20B CvP_CONFDONE,DIFFIO_RX_B157_N,DQSn21B DATA11,DIFFIO_RX_B147_N,DQ20B DATA12,DIFFIO_RX_B149_N,DQSn20B nPERSTL0,DIFFIO_TX_B156_P,DQ21B DATA13,DIFFIO_RX_B149_P,DQS20B nPERSTR0,DIFFIO_TX_B156_N DATA14,DIFFIO_RX_B151_N,DQ20B DATA15,DIFFIO_RX_B151_P,DQ20B AF10 AE11 AJ10 AH10 FPGA_PR_DONE FPGA_PR_REQUEST FPGA_PR_READY FPGA_PR_ERROR 19 19 19 19 AH6 FPGA_CvP_CONFDONE 19 AL6 AK6 PCIE_WAKEn PCIE_PERSTn 3 3,10 C CLKUSR,DIFFIO_TX_B152_P,DQ20B CRC_ERROR,DIFFIO_RX_B157_P,DQS21B DEV_CLRn,DIFFIO_TX_B158_P,DQ21B DEV_OE,DIFFIO_TX_B158_N INIT_DONE,DIFFIO_RX_B159_N,DQ21B nCEO,DIFFIO_RX_B159_P,DQ21B Bank 8A 1.5 Volt nCONFIG nSTATUS CONF_DONE MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 AM6 MAX_FPGA_SSEL AN6 MAX_FPGA_SCK H35 A34 D35 A37 P34 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 19 MAX_FPGA_SSEL 19 MAX_FPGA_SCK 2.5V_REG_FPGA 19 19 19 19 19 SW3 1 2 3 4 5 6 nCE 5ASTFD5K3_F1517 12 11 10 9 8 7 OPEN FPGA_CONFIG_D[15:0] 18,19 AM35 AV34 AT33 AT34 JTAG_FPGA_TMS JTAG_MUX_TCK JTAG_FPGA_TDI JTAG_FPGA_TDO 14 14,19,24,25 14 14 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 R419 R418 R417 R416 R415 1.00K 1.00K 1.00K 1.00K 1.00K TDA06H0SB1 B B Logic 0 = pin 10 <--> pin 9 (FMC Bypass) Logic 1 = pin 10 <--> pin 2 (FMC Enable) U1 FMCB_JTAG_EN FMCB_JTAG_TDO 25 Logic 0 = pin 6 <--> pin 7 (FMC Bypass) Logic 1 = pin 6 <--> pin 4 (FMC Enable) JTAG_MUX_TMS 14 FMCB_JTAG_EN A 1 2 3 4 5 Logic 0 = pin 10 <--> pin 9 (MAX II Bypass) Logic 1 = pin 10 <--> pin 2 (MAX II Enable) IN1 COM1 NO1 1 0 GND NC1 V+ 1 NO2 0 IN2 NC2 COM2 10 9 MAX 0 JTAG_MAX_TDI R3 FMCB_JTAG_TDI 14,25 2.5V_REG_HPS 8 C291 14,19 0.1uF 2.5V_REG_HPS 7 6 BP_FMCB_TMS R10 FMCB_JTAG_TMS 1.00K FMCB_JTAG_TDO FMCB_JTAG_TDI JTAG_MUX_TMS BP_FMCB_TMS R1 R2 R8 R9 DNI DNI DNI DNI MAX MAX FMCB_JTAG_TMS FMCB_JTAG_TMS 25 TS5A23157 XJ14 Title J3 1 2 FMCB_JTAG_EN 1.00K 2.5V_REG_HPS R17 Size 881545-2 B CON2 Date: 8 7 6 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 13 of 1 45 C1 8 7 2.5V_REG_HPS R644 6 5 USB Blaster Programming Header (uses JTAG mode only) 1.00K 4 2.5V_REG_HPS J35 E 2 4 6 8 10 R654 0 1 3 5 7 9 JTAG_TCK JTAG_BLASTER_TDI JTAG_TMS 14,30 14,30 JTAG_BLASTER_TDO R655 1.00K R668 1.00K Logic 0 = pin 10 <--> pin 9 (HPS Bypass) Logic 1 = pin 10 <--> pin 2 (HPS Enable) JTAG_SMD JTAG_TRST MICTOR_RSTn 8 7 6 5 OPEN 1 2 3 4 HPS_JTAG_EN FPGA_JTAG_EN FMC_JTAG_EN MAX_JTAG_EN R667 DNI JTAG_BLASTER_TDI Populate R183 if you would like to Master the JTAG chain through FMC Logic 0 = pin 6 <--> pin 7 (HPS Bypass) Logic 1 = pin 6 <--> pin 4 (HPS Enable) 2.5V_REG_HPS R423 R422 R421 R420 HPS IN1 2 COM1 NO1 NC1 1 7,19 7,19,26 JTAG Chain Control SW4 0 R111 JTAG_MUX_HPS_TDI JTAG_BLASTER_TDO JTAG_MUX_TMS 1.00K 1.00K 1.00K 1.00K 1 U15 1 HPS_JTAG_EN 14,30 2 When Pins 1 & 5 are: TS5A23157 Switch FunctionsLOW --> NC to/from COM = ON and NO to/from COM = OFF HIGH --> NC to/from COM = OFF and NO to/from COM = ON JTAG 2.5V_REG_HPS USB_DISABLEn 30 3 HPS_JTAG_EN 3 NO2 5 V+ 1 JTAG_MUX_TDO 9 FPGA 2.5V_REG_HPS 8 C335 0 R92 E JTAG_FPGA_TDI 13,14 0 GND 4 10 0 IN2 NC2 COM2 Logic 0 = pin 10 <--> pin 9 (FPGA Bypass) Logic 1 = pin 10 <--> pin 2 (FPGA Enable) 0.1uF 2.5V_REG_HPS 7 6 BP_HPS_TMSR93 1.00K JTAG_HPS_TMS 7,14 TS5A23157 U16 TDA04H0SB1 SW2 D 1 2 3 4 OPEN 8 7 6 5 ON = not-in-chain OFF = in-chain CLK125A_EN SI570_EN FACTORY_LOAD SECURITY_MODE CLK125A_EN 11,19 SI570_EN 11,19 FACTORY_LOAD 19 SECURITY_MODE 19 2.5V_REG_HPS 10.0K 10.0K 1V8 10.0K 10.0K R413 R405 R404 R396 CLK125A_EN SI570_EN FACTORY_LOAD SECURITY_MODE FPGA_JTAG_EN JTAG_FPGA_TDO 13 TDA04H0SB1 3.3V JTAG_MUX_TMS 16 JTAG_MUX_TCK 13,14,19,24,25 JTAG_MICTOR_TCK JTAG_MUX_TMS JTAG_MICTOR_TMS 2 JTAG_MUX_TCK JTAG_MICTOR_TCK 7,14 5 JTAG_MUX_TMS 14 JTAG_MICTOR_TMS6 7,14 JTAG_MUX_HPS_TDI C 3 JTAG_MICTOR_TDO 7,14 10 JTAG_MICTOR_TDO JTAG_FPGA_TDI 13,14 14 JTAG_FPGA_TDI 13 JTAG_MICTOR_TDI JTAG_MICTOR_TDI 7,14 11 VCC I0A YA I1A I0B YB I1B YC I1C JTAG_HPS_TCK 7 DNI DNI 9 R472 R471 YD I1D E DNIJTAG_HPS_TMS DNIJTAG_HPS_TMS FMC_JTAG_EN R458 R459 Logic 0 = pin 6 <--> pin 7 (FMC Bypass) Logic 1 = pin 6 <--> pin 4 (FMC Enable) JTAG_MUX_TMS DNI DNI JTAG_HPS_TDO JTAG_HPS_TDO 3.3V 7 C92 C93 2.2uF 0.1uF 3 4 5 FMC_JTAG_EN 1 2 3 4 5 JTAG_HPS_SEL 1.00K JTAG_HPS_SEL 881545-2 J19 1 2 CON2 MAX_JTAG_EN JTAG_MAX_TDO 19 Logic 0 = pin 6 <--> pin 7 (HSMBBypass) Logic 1 = pin 6 <--> pin 4 (HSMB Enable) JTAG_MUX_TMS U23 16 JTAG_TCK JTAG_MICTOR_TCK JTAG_TMS JTAG_MICTOR_TMS 14,30 14,30 7,14 JTAG_MICTOR_TDI 7,14 JTAG_BLASTER_TDO A JTAG_MICTOR_TDO 7,14 JTAG_MICTOR_TCK 7,14 JTAG_BLASTER_TDI JTAG_TCK 30 3 JTAG_TMS 5 JTAG_MICTOR_TMS 6 JTAG_BLASTER_TDI JTAG_MICTOR_TDI 14,30 2 JTAG_BLASTER_TDO JTAG_MICTOR_TDO 11 10 14 13 YA I1A 4 1 2 3 4 5 DNI JTAG_MUX_TCK DNI JTAG_MUX_TCK JTAG_MUX_TCK JTAG_TMS JTAG_MICTOR_TMS I0B YB I1B 7 YC I1C 9 R476 R475 DNI JTAG_MUX_TMS DNI JTAG_MUX_TMS 0 IN2 NC2 COM2 IN1 COM1 NO1 1 NC1 0 GND NO2 V+ 1 IN2 0 NC2 COM2 8 C334 D 0.1uF 2.5V_REG_HPS 7 BP_FPGA_TMS 6 JTAG_FPGA_TMS R95 1.00K 13 10 9 0 FMCB_JTAG_TDI R96 FMCB 19 FMC_JTAG_TDI 2.5V_REG_HPS 8 C333 0.1uF 2.5V_REG_HPS 7 6 BP_FMC_TMS R97 C 1.00K FMC_JTAG_TMS 24 TS5A23157 IN1 COM1 NO1 NC1 GND V+ NO2 NC2 IN2 COM2 R473 R474 DNI DNI 10 9 MUX 0 JTAG_MUX_TDI R98 JTAG_MAX_TDI 2.5V_REG_HPS 8 C332 14 13,19 0.1uF 2.5V_REG_HPS 7 BP_MAX_TMS 6 JTAG_MAX_TMS R99 1.00K 19 B I0D YD I1D E 12 JTAG_MUX_TDO JTAG_MUX_TDO BP_HPS_TMS R452 DNI JTAG_HPS_TMS JTAG_FPGA_TDO JTAG_FPGA_TDI JTAG_MUX_TMS BP_FPGA_TMS R451 R439 R450 R449 DNI FMC DNI FMC DNI JTAG_FPGA_TMS DNI JTAG_FPGA_TMS FMC_JTAG_TDO FMC_JTAG_TDI JTAG_MUX_TMS BP_FMC_TMS R448 R438 R447 R446 DNI DNI DNI DNI FMCB FMCB FMC_JTAG_TMS FMC_JTAG_TMS JTAG_MUX_TDI JTAG_MUX_TDI 14 JTAG_MUX_TDI JTAG_BLASTER_TDO R462 JTAG_MICTOR_TDO R463 DNI DNI DNI DNI JTAG_MUX_TDO JTAG_MUX_TDO JTAG_MAX_TDO JTAG_MAX_TDI JTAG_MUX_TMS BP_MAX_TMS R445 R437 R444 R443 DNI DNI DNI DNI MUX MUX JTAG_MAX_TMS JTAG_MAX_TMS XJ6 JTAG_MUX_TDO 3.3V 1 JTAG_SEL C90 C91 15 JTAG_SEL 2.2uF 0.1uF Title Size CON2 B 1.00K JTAG_SEL 6 5 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 881545-2 J21 1 2 Date: 7 13,14 TS5A23157 R453 R440 HPS FPGA 14 JTAG_MUX_TMS JTAG_MUX_TDI IDTQS3VH257 3.3V R114 8 24 13,14,19,24,25JTAG_MUX_TCK JTAG_MUX_TMS JTAG_BLASTER_TDI JTAG_MICTOR_TDI I0C GND V+ 1 JTAG_FPGA_TDI 2.5V_REG_HPS 0 GND NO2 9 0 FMC_JTAG_TDI R94 FMC TS5A23157 I0A S 8 MAX_JTAG_EN R465 JTAG_TCK JTAG_MICTOR_TCK R464 VCC NC1 Logic 0 = pin 10 <--> pin 9 (MAX II Bypass) Logic 1 = pin 10 <--> pin 2 (MAX II Enable) U18 3.3V B NO1 10 XJ5 3.3V IDTQS3VH257 FMC_JTAG_TDO 24 DNIJTAG_HPS_TDI DNIJTAG_HPS_TDI JTAG_HPS_SEL 15 COM1 Logic 0 = pin 10 <--> pin 9 (FMC Bypass) Logic 1 = pin 10 <--> pin 2 (FMC Enable) U17 7 JTAG_HPS_TDO 1 FPGA_JTAG_EN 7,14 JTAG_HPS_TDI 12 JTAG_HPS_TCK JTAG_HPS_TCK 7 JTAG_HPS_TMS JTAG_FPGA_TDI JTAG_MICTOR_TDI I0D R113 R461 R460 JTAG_MUX_HPS_TDI R469 JTAG_MICTOR_TDO R470 I0C GND 4 JTAG_MUX_TMS JTAG_MICTOR_TMS S 8 JTAG_MUX_TCK JTAG_MICTOR_TCK 2 IN1 1 Logic 0 = pin 6 <--> pin 7 (FPGA Bypass) Logic 1 = pin 6 <--> pin 4 (FPGA Enable) U24 1 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 14 of 1 45 C1 8 7 6 DDR3_HPS_CLK_P DDR3_HPS_CLK_N 100, 1% R528 Place at end of branch DDR3_HPS_BA[2:0] 6 E 1 2 3 4 DDR3_HPS_DQS_P[4:0] 6 DDR3_HPS_DQS_N[4:0] 6 VTT_HPS_DDR3 CN6 8 7 6 5 1 2 3 4 0.1uF VTT_HPS_DDR3 CN8 8 1 7 2 6 3 5 4 CN4 0.1uF 4 2 VTT_HPS_DDR3 DDR3_HPS_A8 DDR3_HPS_A6 DDR3_HPS_A10 DDR3_HPS_A0 DDR3_HPS_A14 DDR3_HPS_A1 DDR3_HPS_RASn DDR3_HPS_A7 DDR3_HPS_CKE 8 7 6 5 0.1uF 1 4 7 2 5 8 3 6 R559 RN8A RN8D RN8G RN6B RN6E RN6H RN4C RN4F 16 51 13 51 10 51 15 51 12 51 9 51 14 51 11 51 4.70K, 1% VTT_HPS_DDR3 DDR3_HPS_BA2 DDR3_HPS_A12 DDR3_HPS_A13 DDR3_HPS_CASn DDR3_HPS_ODT DDR3_HPS_A3 DDR3_HPS_A5 DDR3_HPS_RESETn RN8B RN8E RN8H RN6C RN6F RN4A RN4D RN4G 2 5 8 3 6 1 4 7 2.00K 1 VTT_HPS_DDR3 1.5V_REG_HPS 15 51 12 51 9 51 14 51 11 51 16 51 13 51 10 51 R542 RN8C RN8F RN6A RN6D RN6G RN4B RN4E RN4H DDR3_HPS_A4 DDR3_HPS_BA1 DDR3_HPS_A9 DDR3_HPS_A2 DDR3_HPS_A11 DDR3_HPS_CSn DDR3_HPS_BA0 DDR3_HPS_WEn 3 6 1 4 7 2 5 8 14 11 16 13 10 15 12 9 51 51 51 51 51 51 51 51 E DDR3_HPS_DQ[39:0] 6 DDR3_HPS_A[14:0] 6 U51 N3 DDR3_HPS_A0 P7 DDR3_HPS_A1 P3 DDR3_HPS_A2 N2 DDR3_HPS_A3 P8 DDR3_HPS_A4 P2 DDR3_HPS_A5 R8 DDR3_HPS_A6 R2 DDR3_HPS_A7 T8 DDR3_HPS_A8 R3 DDR3_HPS_A9 DDR3_HPS_A10 L7 DDR3_HPS_A11 R7 DDR3_HPS_A12 N7 DDR3_HPS_A13 T3 DDR3_HPS_A14 T7 D K9 DDR3_HPS_CKE DDR3_HPS_CLK_P J7 DDR3_HPS_CLK_N K7 6 DDR3_HPS_CKE DDR3_HPS_CLK_P 6 DDR3_HPS_CLK_N 6 1.5V_REG_HPS C DDR3_HPS_DM4 R585 240 E7 D3 L2 L3 J3 K3 DDR3_HPS_CSn DDR3_HPS_WEn DDR3_HPS_RASn DDR3_HPS_CASn 6 6 6 6 DDR3_HPS_CSn DDR3_HPS_WEn DDR3_HPS_RASn DDR3_HPS_CASn DDR3_HPS_BA0 DDR3_HPS_BA1 DDR3_HPS_BA2 DDR3_HPS_RESETn DDR3_HPS_ODT 6 6 6 6 6 M2 DDR3_HPS_BA0 N8 DDR3_HPS_BA1 M3 DDR3_HPS_BA2 DDR3_HPS_RESETn T2 K1 DDR3_HPS_ODT L8 DDR3_HPS_ZQ1 VREF_HPS_DDR3 H1 R595 M8 C780 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_HPS A1 A8 C1 C9 D2 E9 F1 H2 H9 B 1.5V_REG_HPS U44 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N N3 DDR3_HPS_A0 P7 DDR3_HPS_A1 P3 DDR3_HPS_A2 N2 DDR3_HPS_A3 P8 DDR3_HPS_A4 P2 DDR3_HPS_A5 R8 DDR3_HPS_A6 R2 DDR3_HPS_A7 T8 DDR3_HPS_A8 R3 DDR3_HPS_A9 DDR3_HPS_A10 L7 DDR3_HPS_A11 R7 DDR3_HPS_A12 N7 DDR3_HPS_A13 T3 DDR3_HPS_A14 T7 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_HPS_DQ32 DDR3_HPS_DQ36 DDR3_HPS_DQ34 DDR3_HPS_DQ35 DDR3_HPS_DQ39 DDR3_HPS_DQ37 DDR3_HPS_DQ33 DDR3_HPS_DQ38 R623 10.0K R568 10.0K R622 10.0K R567 10.0K R620 10.0K R566 10.0K R621 10.0K R565 10.0K F3 G3 C7 B7 DDR3_HPS_DQS_P4 DDR3_HPS_DQS_N4 R594 240 R586 240 1.5V_REG_HPS CS WE RAS CAS NC1 NC2 NC3 NC4 NC5 BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ J1 J9 L1 L9 M7 DDR3_HPS_DM2 DDR3_HPS_DM3 E7 D3 DDR3_HPS_CSn DDR3_HPS_WEn DDR3_HPS_RASn DDR3_HPS_CASn L2 L3 J3 K3 CS WE RAS CAS M2 DDR3_HPS_BA0 N8 DDR3_HPS_BA1 M3 DDR3_HPS_BA2 DDR3_HPS_RESETn T2 K1 DDR3_HPS_ODT L8 DDR3_HPS_ZQ2 VREF_HPS_DDR3 H1 R560 M8 C527 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_HPS A1 A8 C1 C9 D2 E9 F1 H2 H9 B1 B9 D1 D8 E2 E8 F9 G1 G9 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 U38 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N K9 DDR3_HPS_CKE DDR3_HPS_CLK_P J7 DDR3_HPS_CLK_N K7 MT41K256M16HA-125:E A 3 1024MB DDR3 (x32 + ECC) - HPS DDR3_HPS_CLK_P DDR3_HPS_CLK_N 100, 1% R587 Place at end of branch VTT_HPS_DDR3 DDR3_HPS_DM[4:0] 6 5 BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ NC1 NC2 NC3 NC4 NC5 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_HPS_DQ21 DDR3_HPS_DQ23 DDR3_HPS_DQ16 DDR3_HPS_DQ19 DDR3_HPS_DQ17 DDR3_HPS_DQ22 DDR3_HPS_DQ18 DDR3_HPS_DQ20 DDR3_HPS_DQ31 DDR3_HPS_DQ25 DDR3_HPS_DQ26 DDR3_HPS_DQ28 DDR3_HPS_DQ27 DDR3_HPS_DQ29 DDR3_HPS_DQ30 DDR3_HPS_DQ24 F3 G3 C7 B7 DDR3_HPS_DQS_P2 DDR3_HPS_DQS_N2 DDR3_HPS_DQS_P3 DDR3_HPS_DQS_N3 J1 J9 L1 L9 M7 N3 DDR3_HPS_A0 P7 DDR3_HPS_A1 P3 DDR3_HPS_A2 N2 DDR3_HPS_A3 P8 DDR3_HPS_A4 P2 DDR3_HPS_A5 R8 DDR3_HPS_A6 R2 DDR3_HPS_A7 T8 DDR3_HPS_A8 R3 DDR3_HPS_A9 DDR3_HPS_A10 L7 DDR3_HPS_A11 R7 DDR3_HPS_A12 N7 DDR3_HPS_A13 T3 DDR3_HPS_A14 T7 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N K9 DDR3_HPS_CKE DDR3_HPS_CLK_P J7 DDR3_HPS_CLK_N K7 DDR3_HPS_DM0 DDR3_HPS_DM1 E7 D3 DDR3_HPS_CSn DDR3_HPS_WEn DDR3_HPS_RASn DDR3_HPS_CASn L2 L3 J3 K3 CS WE RAS CAS M2 DDR3_HPS_BA0 N8 DDR3_HPS_BA1 M3 DDR3_HPS_BA2 DDR3_HPS_RESETn T2 K1 DDR3_HPS_ODT L8 DDR3_HPS_ZQ VREF_HPS_DDR3 H1 R527 M8 C612 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_HPS A1 A8 C1 C9 D2 E9 F1 H2 H9 B1 B9 D1 D8 E2 E8 F9 G1 G9 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 MT41K256M16HA-125:E BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD C553 C548 C749 C654 C717 C750 C686 C769 C588 C549 C634 C610 C800 C653 C492 C652 C778 C488 C585 C748 C721 C587 C491 C552 C685 C799 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 3300pF 3300pF 4.7nF 4.7nF 4.7nF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF Title C586 C526 C684 C779 C720 C490 C611 C797 C550 C682 C777 C651 C551 C683 C798 C487 C584 C718 Size 0.01uF 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF B Date: 8 DDR3_HPS_DQS_P0 DDR3_HPS_DQS_N0 DDR3_HPS_DQS_P1 DDR3_HPS_DQS_N1 J1 J9 L1 L9 M7 DDR3 ECC TEST C TP4 DDR3_HPS_DQ14 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 R525 10.0K TP5 DDR3_HPS_DQ15 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 B TP7 R526 10.0K A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 1.5V_REG_HPS 0.01uF F3 G3 C7 B7 D MT41K256M16HA-125:E C509 C489 DDR3_HPS_DQ3 DDR3_HPS_DQ0 DDR3_HPS_DQ2 DDR3_HPS_DQ1 DDR3_HPS_DQ5 DDR3_HPS_DQ4 DDR3_HPS_DQ6 DDR3_HPS_DQ7 DDR3_HPS_DQ11 DDR3_HPS_DQ8 DDR3_HPS_DQ15 DDR3_HPS_DQ14 DDR3_HPS_DQ12 DDR3_HPS_DQ10 DDR3_HPS_DQ13 DDR3_HPS_DQ9 TP6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C486 C719 NC1 NC2 NC3 NC4 NC5 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 15 of 1 45 C1 8 7 DDR3A_CLK_P 100, 1% 6 5 VTT_FPGA_DDR3A DDR3A_DM[3:0] E 2 VTT_FPGA_DDR3A DDR3A_BA[2:0] 4 3 1024MB DDR3 (x32) - FPGA PORT A DDR3A_CLK_N R488 4 4 1 2 3 4 DDR3A_DQS_P[3:0] 4 DDR3A_DQS_N[3:0] 4 CN3 VTT_FPGA_DDR3A 8 7 6 5 1 2 3 4 CN1 0.1uF VTT_FPGA_DDR3A CN2 8 1 7 2 6 3 5 4 0.1uF 0.1uF 8 7 6 5 V21 V19 V8 V22 V25 V23 V16 V29 V7 DDR3A_A11 DDR3A_A1 DDR3A_BA1 DDR3A_A9 DDR3A_ODT DDR3A_A14 DDR3A_BA2 DDR3A_A5 DDR3A_CKE RN1A 1 4 RN1D RN1G 7 2 RN2B RN2E 5 RN2H 8 3 RN3C RN3F 6 R487 16 51 V11 13 51 V9 10 51 V14 15 51 V24 12 51 V13 9 51 V26 14 51 V28 11 51 4.70K, 1% V31 DDR3A_A8 DDR3A_A4 DDR3A_A10 DDR3A_A13 DDR3A_CASn DDR3A_CSn DDR3A_A3 DDR3A_RESETn VTT_FPGA_DDR3A 1.5V_REG_FPGA RN1B RN1E RN1H RN2C RN2F RN3A RN3D RN3G 2 5 8 3 6 1 4 7 2.00K 15 51 12 51 9 51 14 51 11 51 16 51 13 51 10 51 R502 V10 V17 V30 V15 V12 V27 V18 V20 DDR3A_A6 DDR3A_A12 DDR3A_A7 DDR3A_WEn DDR3A_RASn DDR3A_BA0 DDR3A_A0 DDR3A_A2 VTT_FPGA_DDR3A RN1C RN1F RN2A RN2D RN2G RN3B RN3E RN3H 3 6 1 4 7 2 5 8 14 51 11 51 16 51 13 51 10 51 15 51 12 51 9 51 E DDR3A_DQ[31:0] 4 DDR3A_A[14:0] 4 U37 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 DDR3A_A0 DDR3A_A1 DDR3A_A2 DDR3A_A3 DDR3A_A4 DDR3A_A5 DDR3A_A6 DDR3A_A7 DDR3A_A8 DDR3A_A9 DDR3A_A10 DDR3A_A11 DDR3A_A12 DDR3A_A13 DDR3A_A14 D C 4 DDR3A_CKE 4 DDR3A_CLK_P 4 DDR3A_CLK_N DDR3A_CKE DDR3A_CLK_P DDR3A_CLK_N K9 J7 K7 4 DDR3A_DM2 4 DDR3A_DM3 DDR3A_DM2 DDR3A_DM3 E7 D3 4 DDR3A_CSn 4 DDR3A_WEn 4 DDR3A_RASn 4 DDR3A_CASn DDR3A_CSn DDR3A_WEn DDR3A_RASn DDR3A_CASn L2 L3 J3 K3 M2 DDR3A_BA0 N8 DDR3A_BA1 M3 DDR3A_BA2 T2 DDR3A_RESETn K1 DDR3A_ODT L8 DDR3A_ZQ1 VREF_FPGA_DDR3A H1 R504 M8 C456 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_FPGA A1 A8 C1 C9 D2 E9 F1 H2 H9 4 DDR3A_BA0 4 DDR3A_BA1 4 DDR3A_BA2 4 DDR3A_RESETn 4 DDR3A_ODT B 1.5V_REG_FPGA U29 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N CS WE RAS CAS NC1 NC2 NC3 NC4 NC5 BA0 BA1 BA2 RESETn ODT ZQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3A_DQ17 DDR3A_DQ16 DDR3A_DQ21 DDR3A_DQ18 DDR3A_DQ23 DDR3A_DQ19 DDR3A_DQ22 DDR3A_DQ20 DDR3A_DQ28 DDR3A_DQ25 DDR3A_DQ26 DDR3A_DQ24 DDR3A_DQ30 DDR3A_DQ29 DDR3A_DQ31 DDR3A_DQ27 F3 G3 C7 B7 DDR3A_DQS_P2 DDR3A_DQS_N2 DDR3A_DQS_P3 DDR3A_DQS_N3 DDR3A_A0 DDR3A_A1 DDR3A_A2 DDR3A_A3 DDR3A_A4 DDR3A_A5 DDR3A_A6 DDR3A_A7 DDR3A_A8 DDR3A_A9 DDR3A_A10 DDR3A_A11 DDR3A_A12 DDR3A_A13 DDR3A_A14 4 DDR3A_DM0 4 DDR3A_DM1 J1 J9 L1 L9 M7 K9 J7 K7 DDR3A_DM0 DDR3A_DM1 E7 D3 DDR3A_CSn DDR3A_WEn DDR3A_RASn DDR3A_CASn L2 L3 J3 K3 M2 DDR3A_BA0 N8 DDR3A_BA1 M3 DDR3A_BA2 T2 DDR3A_RESETn K1 DDR3A_ODT L8 DDR3A__ZQ VREF_FPGA_DDR3A H1 R479 M8 C379 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_FPGA A1 A8 C1 C9 D2 E9 F1 H2 H9 B1 B9 D1 D8 E2 E8 F9 G1 G9 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 C364 C453 C431 C378 C402 C405 C376 C373 C455 C362 C360 C381 C363 C403 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 3300pF 3300pF 4.7nF 4.7nF 4.7nF N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 DDR3A_CKE DDR3A_CLK_P DDR3A_CLK_N MT41K256M16HA-125:E A 1 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N CS WE RAS CAS BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C454 C404 C361 C380 C458 C372 C457 C418 C369 Size 0.01uF 0.01uF 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF 0.47uF 0.47uF 0.47uF 0.47uF B Date: 8 F3 G3 C7 B7 DDR3A_DQS_P0 DDR3A_DQS_N0 DDR3A_DQS_P1 DDR3A_DQS_N1 D J1 J9 L1 L9 M7 C B1 B9 D1 D8 E2 E8 F9 G1 G9 B J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title C377 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DDR3A_DQ6 DDR3A_DQ5 DDR3A_DQ7 DDR3A_DQ1 DDR3A_DQ0 DDR3A_DQ3 DDR3A_DQ2 DDR3A_DQ4 DDR3A_DQ10 DDR3A_DQ15 DDR3A_DQ12 DDR3A_DQ8 DDR3A_DQ11 DDR3A_DQ9 DDR3A_DQ13 DDR3A_DQ14 MT41K256M16HA-125:E 1.5V_REG_FPGA C401 NC1 NC2 NC3 NC4 NC5 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 16 of 1 45 C1 8 7 DDR3B_CLK_P 100, 1% 6 5 5 E 5 5 5 5 3 2 1024MB DDR3 (x32) - FPGA PORT B DDR3B_CLK_N R545 5 4 VTT_FPGA_DDR3B DDR3B_BA[2:0] VTT_FPGA_DDR3B DDR3B_DM[3:0] 1 2 3 4 DDR3B_DQS_P[3:0] DDR3B_DQS_N[3:0] CN9 VTT_FPGA_DDR3B 8 7 6 5 1 2 3 4 CN7 0.1uF VTT_FPGA_DDR3B CN5 8 1 7 2 6 3 5 4 0.1uF 0.1uF 8 7 6 5 V56 V54 V39 V57 V60 V58 V51 V64 V38 DDR3B_A11 DDR3B_A1 DDR3B_BA1 DDR3B_A9 DDR3B_ODT DDR3B_A14 DDR3B_BA2 DDR3B_A5 DDR3B_CKE RN5A 1 4 RN5D RN5G 7 2 RN7B RN7E 5 RN7H 8 3 RN9C RN9F 6 R539 DDR3B_DQ[31:0] 16 51 V42 13 51 V40 10 51 V49 15 51 V59 12 51 V48 9 51 V61 14 51 V63 11 51 4.70K, 1% V66 DDR3B_A8 DDR3B_A4 DDR3B_A10 DDR3B_A13 DDR3B_CASn DDR3B_CSn DDR3B_A3 DDR3B_RESETn VTT_FPGA_DDR3B 1.5V_REG_FPGA RN5B RN5E RN5H RN7C RN7F RN9A RN9D RN9G 2 5 8 3 6 1 4 7 2.00K 15 51 12 51 9 51 14 51 11 51 16 51 13 51 10 51 R556 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 DDR3B_A0 DDR3B_A1 DDR3B_A2 DDR3B_A3 DDR3B_A4 DDR3B_A5 DDR3B_A6 DDR3B_A7 DDR3B_A8 DDR3B_A9 DDR3B_A10 DDR3B_A11 DDR3B_A12 DDR3B_A13 DDR3B_A14 D 5 DDR3B_CKE DDR3B_CLK_P 5 DDR3B_CLK_N 5 C DDR3B_CKE DDR3B_CLK_P DDR3B_CLK_N K9 J7 K7 DDR3B_DM2 DDR3B_DM3 5 5 DDR3B_DM2 DDR3B_DM3 E7 D3 DDR3B_CSn DDR3B_WEn DDR3B_RASn DDR3B_CASn 5 5 5 5 DDR3B_CSn DDR3B_WEn DDR3B_RASn DDR3B_CASn L2 L3 J3 K3 DDR3B_BA0 DDR3B_BA1 DDR3B_BA2 DDR3B_RESETn DDR3B_ODT 5 5 5 5 5 M2 DDR3B_BA0 N8 DDR3B_BA1 M3 DDR3B_BA2 T2 DDR3B_RESETn K1 DDR3B_ODT L8 DDR3B_ZQ1 VREF_FPGA_DDR3B H1 R562 M8 C593 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_FPGA A1 A8 C1 C9 D2 E9 F1 H2 H9 B 1.5V_REG_FPGA CS WE RAS CAS NC1 NC2 NC3 NC4 NC5 BA0 BA1 BA2 RESETn ODT ZQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3B_DQ18 DDR3B_DQ20 DDR3B_DQ17 DDR3B_DQ19 DDR3B_DQ16 DDR3B_DQ21 DDR3B_DQ22 DDR3B_DQ23 DDR3B_DQ29 DDR3B_DQ30 DDR3B_DQ24 DDR3B_DQ27 DDR3B_DQ26 DDR3B_DQ28 DDR3B_DQ25 DDR3B_DQ31 F3 G3 C7 B7 DDR3B_DQS_P2 DDR3B_DQS_N2 DDR3B_DQS_P3 DDR3B_DQS_N3 DDR3B_A0 DDR3B_A1 DDR3B_A2 DDR3B_A3 DDR3B_A4 DDR3B_A5 DDR3B_A6 DDR3B_A7 DDR3B_A8 DDR3B_A9 DDR3B_A10 DDR3B_A11 DDR3B_A12 DDR3B_A13 DDR3B_A14 DDR3B_DM0 5 DDR3B_DM1 5 J1 J9 L1 L9 M7 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 C759 C590 C730 C691 C572 C533 C694 C592 C529 C531 C692 C595 C532 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 3300pF 3300pF 4.7nF 4.7nF 4.7nF N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 DDR3B_CKE DDR3B_CLK_P DDR3B_CLK_N K9 J7 K7 DDR3B_DM0 DDR3B_DM1 E7 D3 DDR3B_CSn DDR3B_WEn DDR3B_RASn DDR3B_CASn L2 L3 J3 K3 M2 DDR3B_BA0 N8 DDR3B_BA1 M3 DDR3B_BA2 T2 DDR3B_RESETn K1 DDR3B_ODT L8 DDR3B_ZQ VREF_FPGA_DDR3B H1 R531 M8 C760 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V_REG_FPGA A1 A8 C1 C9 D2 E9 F1 H2 H9 B1 B9 D1 D8 E2 E8 F9 G1 G9 C757 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N CS WE RAS CAS BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C591 C762 C693 C594 C530 C761 C710 C560 C571 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF 0.47uF 0.47uF 0.47uF 0.47uF B Date: 8 3 6 1 4 7 2 5 8 14 51 11 51 16 51 13 51 10 51 15 51 12 51 9 51 E VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3B_DQ7 DDR3B_DQ6 DDR3B_DQ5 DDR3B_DQ1 DDR3B_DQ2 DDR3B_DQ0 DDR3B_DQ4 DDR3B_DQ3 DDR3B_DQ13 DDR3B_DQ12 DDR3B_DQ9 DDR3B_DQ15 DDR3B_DQ10 DDR3B_DQ14 DDR3B_DQ8 DDR3B_DQ11 F3 G3 C7 B7 DDR3B_DQS_P0 DDR3B_DQS_N0 DDR3B_DQS_P1 DDR3B_DQS_N1 D J1 J9 L1 L9 M7 C B1 B9 D1 D8 E2 E8 F9 G1 G9 B J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Size 0.01uF NC1 NC2 NC3 NC4 NC5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Title 0.01uF RN5C RN5F RN7A RN7D RN7G RN9B RN9E RN9H MT41K256M16HA-125:E 1.5V_REG_FPGA C690 DDR3B_A6 DDR3B_A12 DDR3B_A7 DDR3B_WEn DDR3B_RASn DDR3B_BA0 DDR3B_A0 DDR3B_A2 U43 DDR3 Device A0 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10/AP DQ9 A11 DQ10 A12/BCn DQ11 A13 DQ12 A14 DQ13 DQ14 CKE DQ15 CK_P CK_N LDQS_P LDQS_N LDM UDQS_P UDM UDQS_N MT41K256M16HA-125:E C758 V41 V52 V65 V50 V47 V62 V53 V55 VTT_FPGA_DDR3B DDR3B_A[14:0] U49 A 1 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 17 of 1 45 C1 8 7 6 5 4 3 2 1 FLASH, EPCQ FM BUS FM_A[26:1] 19 E NOR PARALLEL FLASH FM_D[15:0] 19 E FLASH 512Mb (32M X 16) U13 EPCQ 5.0V FM_A1 FM_A2 FM_A3 FM_A4 FM_A5 FM_A6 FM_A7 FM_A8 FM_A9 FM_A10 FM_A11 FM_A12 FM_A13 FM_A14 FM_A15 FM_A16 FM_A17 FM_A18 FM_A19 FM_A20 FM_A21 FM_A22 FM_A23 FM_A24 FM_A25 FM_A26 3.3V C350 C349 0.1uF 0.1uF C80 C81 0.1uF 0.1uF U21 1 2 VCC NC01 NC02 NC03 NC04 NC05 NC06 NC07 NC08 EPCQ256 DATA0 DATA1 DATA2 DATA3 DCLK nCS GND U28 3 4 5 6 11 12 13 14 FPGA_AS_DATA0 FPGA_AS_DATA1 FPGA_AS_DATA2 FPGA_AS_DATA3 FPGA_nCSO 15 8 9 1 16 7 FPGA_AS_DATA0 FPGA_AS_DATA1 FPGA_AS_DATA2 FPGA_AS_DATA3 FPGA_DCLK FPGA_nCSO 3.3V 13,19 R107 10.0K 10 D 2 3 4 5 6 7 8 9 10 11 23 NC VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BE GND 24 22 21 20 19 18 17 16 15 14 13 FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 13,19 13,19 13,19 13,19 13,19 FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 12 IDTQS3861 MAX_AS_CONF 19 9V_VPP XJ1 C J18 1 2 881545-2 VPP CON2 12V 9V_VPP C65 4.7uF 3 4.7K R433 VIN VOUT ADJ/BYPASS SHDN GND LT1761 5 4 2 D19 LT1761_CSENSE R431 19 FLASH_CLK 19 19 19 19 19 FLASH_RESETn FLASH_CEn0 FLASH_OEn FLASH_WEn FLASH_ADVn FLASH_WPn VPP U12 1 VPP PC28FxxxP30B85 FLASH 1V8 A1 B1 C1 D1 D2 A2 C2 A3 B3 C3 D3 C4 A5 B5 C5 D7 D8 A7 B7 C7 C8 A8 G1 H8 B6 B8 E6 D4 B4 F8 G8 F6 C6 VPP A1 A2 VCC A3 VCC A4 A5 VCCQ A6 VCCQ A7 VCCQ A8 A9 D0 A10 D1 A11 D2 A12 D3 A13 D4 A14 D5 A15 D6 A16 D7 A17 A18 D8 A19 D9 A20 D10 A21 D11 A22 D12 NC(64M)/A23 D13 NC(64M,128M)/A24 D14 NC/A25(512M) D15 NC/A26(1G) WAIT CLK GND RESET# GND CE# GND OE# GND WE# ADV# RFU0 WP# RFU1 RFU2 RFU3 1V8 A4 A6 H3 1V8 D5 D6 G4 D F2 E2 G3 E4 E5 G5 G6 H7 FM_D0 FM_D1 FM_D2 FM_D3 FM_D4 FM_D5 FM_D6 FM_D7 E1 E3 F3 F4 F5 H5 G7 E7 FM_D8 FM_D9 FM_D10 FM_D11 FM_D12 FM_D13 FM_D14 FM_D15 F7 FLASH_RDYBSYn 19 C B2 H2 H4 H6 H1 G2 F1 E8 36K PC28F512P30BF CMDSH-3 R432 5.62k C62 4.7uF 1V8 1V8 B R455 R434 R424 10K 10K 10K FLASH_WPn FLASH_WEn FLASH_RDYBSYn R454 10K FLASH_RESETn 1V8 B C322 C323 C328 C325 C337 C336 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF - When using a single x16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software. A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 18 of 1 45 C1 8 7 6 5 4 3 5M2210 System Controller U27A E D FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 FPGA_CONFIG_D5 FPGA_CONFIG_D6 FPGA_CONFIG_D7 D3 C2 C3 E3 D2 E4 D1 E5 FPGA_CONFIG_D8 FPGA_CONFIG_D9 FPGA_CONFIG_D10 FPGA_CONFIG_D11 FPGA_CONFIG_D12 FPGA_CONFIG_D13 FPGA_CONFIG_D14 FPGA_CONFIG_D15 F3 E1 F4 F2 F1 F6 G2 G3 MAX_FPGA_MOSI MAX_FPGA_MISO MAX_AS_CONF MAX_FPGA_SSEL MAX_FPGA_SCK G1 G4 H2 G5 H3 J1 H4 J2 H5 J5 USB_B2_CLK CLK_100M_MAX DIFFIO_L1P DIFFIO_L1N DIFFIO_L2P DIFFIO_L2N DIFFIO_L3P DIFFIO_L3N DIFFIO_L4P DIFFIO_L4N DIFFIO_L13P DIFFIO_L13N DIFFIO_L14P DIFFIO_L14N DIFFIO_L15P DIFFIO_L15N DIFFIO_L16P DIFFIO_L16N DIFFIO_L5P DIFFIO_L5N DIFFIO_L6P DIFFIO_L6N DIFFIO_L7P DIFFIO_L7N DIFFIO_L8P DIFFIO_L8N DIFFIO_L17P DIFFIO_L17N DIFFIO_L18P DIFFIO_L18N DIFFIO_L19P DIFFIO_L19N DIFFIO_L20P DIFFIO_L20N J4 FPGA_nSTATUS K1 FPGA_CONF_DONE J3 FPGA_DCLK K2 MAX_QSPI_RSTn K5 L1 L2 0 R678 JTAG_TRST K3 0 R674 MICTOR_RSTn DIFFIO_L9P DIFFIO_L21P DIFFIO_L9N DIFFIO_L21N DIFFIO_L10P DIFFIO_L10N IOB1_1 DIFFIO_L11P IOB1_2 DIFFIO_L11N IOB1_3 DIFFIO_L12P IOB1_4 DIFFIO_L12N IOB1_5 IOB1/CLK0 IOB1/CLK1 M1 M2 L4 L3 N1 M4 N2 M3 I2C_SCL_MAX I2C_SDA_MAX N3 P2 FPGA_CvP_CONFDONE FPGA_PR_ERROR E2 F5 H1 K4 L5 FPGA_PR_READY FPGA_PR_REQUEST FPGA_PR_DONE 26 7,14 7,14,26 A5 D7 B6 E7 C8 B7 D8 A7 FPGA_nCONFIG FMCB_C2M_PG FMC_C2M_PG 25 24 CLK50_EN CLK125A_EN Si570_EN M570_PCIE_JTAG_EN B8 A8 A9 E9 B9 D9 A10 C9 DIFFIO_T1P DIFFIO_T1N DIFFIO_T2P DIFFIO_T2N DIFFIO_T3P DIFFIO_T3N DIFFIO_T4P DIFFIO_T4N DIFFIO_T13P DIFFIO_T13N DIFFIO_T14P DIFFIO_T14N DIFFIO_T15P DIFFIO_T15N DIFFIO_T16P DIFFIO_T16N DIFFIO_T5P DIFFIO_T5N DIFFIO_T6P DIFFIO_T6N DIFFIO_T7P DIFFIO_T7N DIFFIO_T8P DIFFIO_T8N DIFFIO_T17P DIFFIO_T17N DIFFIO_T18P DIFFIO_T18N IOB2_6 IOB2_7 DIFFIO_T9P DIFFIO_T9N DIFFIO_T10P DIFFIO_T10N DIFFIO_T11P DIFFIO_T11N DIFFIO_T12P DIFFIO_T12N IOB2_8 IOB2_9 IOB2_10 IOB2_11 IOB2_12 IOB2_13 IOB2_14 IOB2_15 IOB2_16 IOB2_17 IOB2_18 IOB2_19 IOB2_20 JTAG_MUX_TCK P3 L6 M5 N4 TCK TDI TDO TMS D4 B1 C5 C4 B4 D6 E6 B5 SI571_EN MAX V BANK2 13,14,24,25 14 14 14 JTAG_MAX_TDI JTAG_MAX_TDO JTAG_MAX_TMS E10 A11 B11 A12 E11 B12 C11 B13 F13 E15 E16 F15 G14 F16 G13 G15 FM_A8 FM_A9 FM_A10 FM_A11 FM_A12 FM_A13 FM_A14 FM_A15 B G12 G16 H14 H15 H13 H16 J13 J16 FM_A16 FM_A17 FM_A18 FM_A19 FM_A20 FM_A21 FM_A22 FM_A23 CLK_50M_MAX J12 H12 13 13 13 13 13 PGM_CONFIG PGM_LED0 PGM_LED1 PGM_LED2 MAX_FPGA_SSEL MAX_FPGA_SCK 27 A2 FACTORY_LOAD A4 MAX_ERROR A6 MAX_LOAD B10 MSEL0 B3 MSEL1 C10 MSEL2 C12 MSEL3 C6 MSEL4 I2C_SCL_MAX I2C_SDA_MAX 2.5V_REG_HPS R484 R483 DIFFIO_R1P DIFFIO_R1N DIFFIO_R2P DIFFIO_R2N DIFFIO_R3P DIFFIO_R3N DIFFIO_R4P DIFFIO_R4N DIFFIO_R13P DIFFIO_R13N DIFFIO_R14P DIFFIO_R14N DIFFIO_R15P DIFFIO_R15N DIFFIO_R16P DIFFIO_R16N DIFFIO_R5P DIFFIO_R5N DIFFIO_R6P DIFFIO_R6N DIFFIO_R7P DIFFIO_R7N DIFFIO_R8P DIFFIO_R8N DIFFIO_R17P DIFFIO_R17N DIFFIO_R18P DIFFIO_R18N DIFFIO_R19P DIFFIO_R19N DIFFIO_R20P DIFFIO_R20N DIFFIO_R9P DIFFIO_R9N DIFFIO_R10P DIFFIO_R10N DIFFIO_R11P DIFFIO_R11N DIFFIO_R12P DIFFIO_R12N DIFFIO_R21P DIFFIO_R21N DIFFIO_R22P DIFFIO_R22N IOB3/CLK2 IOB3/CLK3 IOB3_21 IOB3_22 IOB3_23 IOB3_24 IOB3_25 IOB3_26 IOB3_27 L15 L12 M16 L13 M15 L14 N16 M13 R1 P4 T2 P5 R3 N5 P6 N6 FM_D0 FM_D1 FM_D2 FM_D3 FM_D4 FM_D5 FM_D6 FM_D7 R5 M6 T5 P7 R6 N7 M7 R7 FM_D8 FM_D9 FM_D10 FM_D11 FM_D12 FM_D13 FM_D14 FM_D15 N15 N14 P15 P14 FLASH_WEn FLASH_CEn0 FLASH_OEn FLASH_RDYBSYn D13 D14 F11 FLASH_RESETn FLASH_CLK FLASH_ADVn F12 K12 M14 N13 FM_A24 FM_A25 FM_A26 USB_CFG2 USB_CFG3 USB_CFG4 USB_CFG5 USB_CFG6 USB_CFG7 USB_CFG8 USB_CFG9 P8 T7 N8 R8 T8 T9 R9 P9 MAX_RESETn USB_CFG10 M9 M8 DIFFIO_B1P DIFFIO_B1N DIFFIO_B2P DIFFIO_B2N DIFFIO_B3P DIFFIO_B3N DIFFIO_B4P DIFFIO_B4N DIFFIO_B14P DIFFIO_B14N DIFFIO_B15P DIFFIO_B15N DIFFIO_B16P DIFFIO_B16N DIFFIO_B17P DIFFIO_B17N DIFFIO_B5P DIFFIO_B5N DIFFIO_B6P DIFFIO_B6N DIFFIO_B7P DIFFIO_B7N DIFFIO_B8P DIFFIO_B8N DIFFIO_B19P DIFFIO_B19N DIFFIO_B18P DIFFIO_B18N DIFFIO_B20P DIFFIO_B20N DIFFIO_B21P DIFFIO_B21N DIFFIO_B9P DIFFIO_B22P DIFFIO_B9N DIFFIO_B22N DIFFIO_B10P IOB4_28 DIFFIO_B10N IOB4_29 DIFFIO_B11P IOB4_30 DIFFIO_B11N IOB4_31 DIFFIO_B12P IOB4_32 DIFFIO_B12N IOB4_33 F7 G6 H7 H9 J10 J8 K11 L10 T13 R13 R12 P11 N12 R14 P12 T15 R16 P13 M11 M12 N9 R4 T10 T4 EXTRA_SIG1 SECURITY_MODE M570_CLOCK FACTORY_STATUS FACTORY_REQUEST EXTRA_SIG2 TRST RST 30 30 USB_CFG0 USB_CFG11 USB_CFG1 DIFFIO_B13N/DEV_CLRn DIFFIO_B13P/DEV_OE A1 A16 B15 B2 G10 G7 G8 G9 K10 K7 K8 K9 R15 R2 T1 T16 T6 18 18 FLASH_OEn FLASH_RDYBSYn 18 18 FLASH_RESETn FLASH_CLK FLASH_ADVn 18 18 18 CLK125A_EN CLK50_EN Si570_EN SI571_EN 11,14 11 11,14 9 E 10,31,32 MAX_FPGA_MOSI MAX_FPGA_MISO 9,11 9,11 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 F10 G11 H10 H8 J7 J9 K6 L7 13,28 C MAX_AS_CONF 18,19 ON-BOARD USB BLASTER II USB_CFG[11:0] 30 USB_CFG[11:0] EXTRA_SIG[2:0] 30 EXTRA_SIG[2:0] 2.5V_REG_HPS USB_B2_CLK C1 H6 J6 P1 4,30 M570_PCIE_JTAG_EN M570_CLOCK FACTORY_STATUS FACTORY_REQUEST A14 A3 F8 F9 30 30 30 30 MAXV DIPSWITCH 1V8 C16 H11 J11 P16 13 MAX_FPGA_MOSI 13 MAX_FPGA_MISO CPU_RESETn 1V8 MAX V Power GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO D 10,31,32 I2C_SCL_MAX I2C_SDA_MAX GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT 13 13 13 13 13 18,19 U27E M10 R10 N10 T11 P10 R11 T12 N11 EXTRA_SIG0 FLASH_WEn FLASH_CEn0 11 11 0 I2C_SCL R486 0 I2C_SDA R485 10K I2C_SCL_MAX 10K I2C_SDA_MAX 18 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 MAX_AS_CONF MAX V BANK4 J14 J15 K16 K13 K15 K14 L16 L11 13 MAX_FPGA_SSEL 13 MAX_FPGA_SCK CLK_50M_MAX CLK_100M_MAX C7 D10 CPU_RESETn D11 D5 E8 18 FM_A[26:0] USB_FPGA_RESET U27D MAX V BANK3 E14 C14 C15 E13 E12 D15 F14 D16 PGM_SEL FPGA_PR_DONE FPGA_PR_REQUEST FPGA_PR_READY FPGA_PR_ERROR FPGA_CvP_CONFDONE 31 27 7,26 A13 USB_FPGA_RESET A15 5M2210ZF256 U27C 13 13 13,18 13 MAX_CONF_DONE D12 B14 C13 B16 5M2210ZF256 FM_A0 FM_A1 FM_A2 FM_A3 FM_A4 FM_A5 FM_A6 FM_A7 13,18 FPGA_nSTATUS FPGA_CONF_DONE FPGA_DCLK FPGA_nCONFIG OVERTEMP USB_RESET HPS_RESETn 1 FM_D[15:0] FPGA_CONFIG_D[15:0] U27B MAX V BANK1 C 2 B FACTORY_LOAD SECURITY_MODE 14 14 PUSH BUTTON INTERFACE 1.5V_REG_HPS PGM_SEL PGM_CONFIG MAX_RESETn L8 L9 T14 T3 1V8 PGM_LED[2:0] 5M2210ZF256 MAX_ERROR MAX_LOAD MAX_CONF_DONE 5M2210ZF256 2.5V_REG_HPS VCCINT 1.5V_REG_HPS 1V8 2.5V VCCIO PGM_SEL PGM_CONFIG MAX_RESETn 28 PGM_LED[2:0] 28 28 28 MAX_ERROR MAX_LOAD MAX_CONF_DONE LED INTERFACE 5M2210ZF256 A 28 28 28 1.5V VCCIO A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 C370 C356 C354 C344 C353 C352 C355 C366 C371 C345 C341 C342 C346 C357 C343 C385 C351 C386 C365 C384 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 19 of 1 45 C1 8 7 6 5 4 3 2 10/100/1000 Ethernet - HPS ETHERNET INTERFACE ENET_HPS_TXD[3..0] U7A 36 37 ENET_HPS_MDC ENET_HPS_MDIO E ENET_HPS_LED2_LINK ENET_HPS_RESETn 42 3.3V_REG_HPS J13 13 YK Yellow TD3_P CT3 TD3_N Orange D 15 17 OK GK Green 220 RESET_N 4 6 5 CT1 3 1 2 CT2 8 7 9 CT3 INT_N 2 3 5 6 7 8 10 11 MDI_HPS_P0 MDI_HPS_N0 MDI_HPS_P1 MDI_HPS_N1 MDI_HPS_P2 MDI_HPS_N2 MDI_HPS_P3 MDI_HPS_N3 4.99K ENET_HPS_RSET 48 3.3V_REG_HPS TXRXP_A TXRXM_A TXRXP_B TXRXM_B TXRXP_C TXRXM_C TXRXP_D TXRXM_D 17 15 ENET_HPS_LED1_LINK ENET_HPS_LED2_LINK DNI 3 C38 ENET_HPS_LED1_LINK C40 0.01uF CT1 DNI Y1 25.00MHz 2 35 ENET_HPS_RX_CLK 24 ENET_HPS_GTX_CLK 25 ENET_HPS_TX_EN 33 ENET_HPS_RX_DV 22 21 20 19 ENET_HPS_TXD3 ENET_HPS_TXD2 ENET_HPS_TXD1 ENET_HPS_TXD0 32 31 28 27 ENET_HPS_RXD0 ENET_HPS_RXD1 ENET_HPS_RXD2 ENET_HPS_RXD3 ENET_HPS_RXD[3..0] ENET_HPS_RX_CLK ENET_HPS_RX_DV ENET_HPS_MDIO ENET_HPS_INTn 2.5V_REG_HPS U34 1 2 A0 3 A1 4 A2 GND 7 ENET_HPS_TXD[3..0] 7 7 7,20 20,26 ENET_HPS_GTX_CLK ENET_HPS_TX_EN ENET_HPS_MDC ENET_HPS_RESETn 7 ENET_HPS_RXD[3..0] 7 7 7,20 7,20 ENET_HPS_RX_CLK ENET_HPS_RX_DV ENET_HPS_MDIO ENET_HPS_INTn 2.5V_REG_HPS VCC WP SCL SDA 8 7 6 5 I2C_SCL_HPS I2C_SDA_HPS 7,28,33 7,28,33 24LC32A 41 E D CLK125_NDO_LED_MODE LED1_PHYAD0 LED2_PHYAD1 3.3V_REG_HPS 46 45 XI XO 1 4 C36 RXD0_MODE0 RXD1_MODE1 RXD2_MODE2 RXD3_MODE3 CLK125_NDO_LED_MODE 220 CT0 TXD3 TXD2 TXD1 TXD0 ISET R31 0.01uF GTX_CLK RX_DV_CLK125_EN 16 C37 RX_CLK_PHYAD2 TX_EN ENET_L829-1J1T-43 C MDC MDIO CT0 R37 GOA ENET_HPS_GTX_CLK ENET_HPS_TX_EN ENET_HPS_MDC ENET_HPS_RESETn MDI INTERFACE TD2_P CT2 TD2_N GND_TAB GND_TAB R74 11 12 10 TD0_P CT0 TD0_N TD1_P CT1 TD1_N 18 19 38 ENET_HPS_INTn 14 YA 1 3.3V_REG_HPS L10 KSZ9021RN C51 C52 10uF 10uF 3.3V_AVDDH 3A, 30 Ohm FB 3.3V_REG_HPS C74 22uF L33 1.2V_AVDLL_PLL C77 C68 2.2uF 0.1uF C95 22uF C109 C96 2.2uF 0.1uF L13 3.3V_DVDDH 1.2V_AVDDL C 1.2V_AVDLL_PLL C53 0.01uF U7B CT2 3.3V_AVDDH C54 0.01uF 47 12 1 CT3 3.3V_DVDDH 40 16 34 1.2V AVDLL_PLL 2.5V_REG_HPS 5.0V 49 13 29 U26 C103 4 10uF 6 B 2.5V_REG_HPS R116 BST OUT2 OUT1 SW SHDN 3 11 10.0K IN1 IN2 GND GND 1 2 ADJ PG 5 C99 1uF 1.2V_AVDLL_PLL 10 9 AVDDL_PLL LDO_O AVDDH AVDDH AVDDH AVDDL AVDDL DVDDH DVDDH DVDDH DVDDL DVDDL DVDDL DVDDL DVDDL DVDDL P_GND VSS_PS VSS 44 43 1.2V_AVDDL 3A, 30 Ohm FB C331 22uF C338 C329 2.2uF 0.1uF 3A, 30 Ohm FB C110 22uF 9 4 C111 C113 2.2uF 0.1uF L12 1.2V_DVDDL 18 14 39 30 26 23 1.2V_DVDDL 3A, 30 Ohm FB C107 22uF C108 C106 2.2uF 0.1uF KSZ9021RN 8 7 R125 R124 1.00K LTC3026 Place near KSZ9021RN PHY 2.00K B 3.3V C97 22uF C98 2.2uF R368 R379 R366 R365 R361 R360 R351 R352 R344 DNI DNI 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% DNI 4.70K, 1% 4.70K, 1% ENET_HPS_LED2_LINK ENET_HPS_LED1_LINK ENET_HPS_RXD3 ENET_HPS_RXD2 ENET_HPS_RXD1 ENET_HPS_RXD0 ENET_HPS_RX_DV ENET_HPS_RX_CLK CLK125_NDO_LED_MODE R367 R378 R364 R363 R359 R358 R349 R350 R343 1.00K 1.00K DNI DNI DNI DNI 4.70K, 1% DNI DNI 3.3V_REG_HPS R40 R50 R39 R38 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% ENET_HPS_MDIO ENET_HPS_MDC ENET_HPS_INTn ENET_HPS_RESETn 7,20 7,20 7,20 20,26 BOOT-STRAPS A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 20 of 1 45 C1 8 7 6 5 4 3 2 1 10/100M Ethernet - FPGA 4 4 4 4 ENET2_RX_ERROR ENET2_RX_DV ENET2_RX_CLK ENET2_TX_CLK_FB 11 CLK_DUAL_ENET_PHY 3.3V C R629 R646 R612 R637 R636 80 1 ENET_DUAL_RESETn 4,26 P1TXP P1TXN P1RXP P1RXN XCLK0 XCLK1 DNI P0100BTLED P0ACTLED P0LINKED REGOFF RESETB P1100BTLED P1ACTLED P1LINKED 3.3V DNI REG_FB R631 R630 R663 P1RXD0 P1RXD1 P1RXD2 P1RXD3 P1RXERR P1RXDV P1RXCLK P1CRS P1COL 33 34 R251 R252 0 R242 35 36 37 38 40 39 41 42 22 ENET2_RX_D0 ENET2_RX_D1 ENET2_RX_D2 ENET2_RX_D3 ENET2_RX_ERROR ENET2_RX_DV ENET2_RX_CLK DNI 4.70K, 1% 4.70K, 1% DNI DNI DNI ENET_DUAL_RESETn P0TXERR_PHY P1TXERR_PHY 63 62 4.70K, 1% 4.70K, 1% MDIO MDC EXTRES REGAGND REGBGND1 REGBGND2 P0AGND P1AGND GNDIO GND15 VSSAPLL ENET_FPGA_MDIO ENET_FPGA_MDC 4 4 R649 R658 R643 ENET2_TX_CLK_FB 79 13 2 DNI 4.70K, 1% 4.70K, 1% DR ATP TEST TCT 3 17 18 ENET1_MDI_RX_P ENET1_MDI_RX_N C254 0.01uF 12pF 12pF 12pF 12pF RD- 8 13 14 C256 0.01uF R278 10 GND GND_TAB GND_TAB C260 0.01uF 7 6 ENET2_MDI_TX_P ENET2_MDI_TX_N 5 4 ENET2_MDI_RX_P ENET2_MDI_RX_N 64 68 69 ENET1_ACT_LED ENET1_LINK_LED P0TXERR 4,21 R648 DNI R331 ENET1_LINK_LED ENET2_ACT_LED R328 3.3V 61 65 67 ENET2_ACT_LED ENET2_LINK_LED 12 R657 J47 12.4K R268 10 R270 49.9 R269 49.9 R266 49.9 R265 49.9 R267 10 76 74 75 14 8 31 51 9 1 TD+ 2 TCT 3 RD+ 5 4.70K, 1% ENET2_RX_D0 4.70K, 1% ENET2_RX_D1 DNI ENET2_RX_CLK 4.70K, 1% ENET1_RX_ERROR DNI ENET2_RX_ERROR 4.70K, 1% ENET1_RX_CLK 4.70K, 1% ENET1_RX_DV 4.70K, 1% ENET2_RX_DV DNI ENET1_RX_D0 DNI ENET1_RX_D1 R628 R609 R611 R617 R599 R618 R616 R608 R614 R615 DNI DNI 4.70K, 1% DNI 4.70K, 1% DNI DNI DNI 4.70K, 1% 4.70K, 1% C250 C252 C251 C248 C247 0.01uF 12pF 12pF 12pF 12pF RCT R271 10 4,21 C142 4.7uF C140 C139 C138 C823 C821 C819 C818 C816 C814 C813 C811 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C804 22uF 25V P1TXERR C822 C820 C817 C815 C812 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Title PLACE NEAR LEVEL TRANSLATORS B Date: 7 6 5 R647 DNI ENET2_LINK_LED R329 220 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 C805 22uF 25V Size 8 C253 0.01uF Green Place near uPD60620 PHY A C141 GND GND_TAB GND_TAB B 3.3V BOOT-STRAPS 1V5_ECAT2 RD- 8 13 14 C249 0.01uF Yellow TD- 4 3.3V Place near uPD60620 PHY C 3.3V B 3.3V 220 220 6 1.5V_REG_HPS D 3.3V uPD60621 R627 R607 R610 R603 R598 R604 R602 R606 R600 R601 Green GA GK ENET1_MDI_TX_P ENET1_MDI_TX_N C255 11 12 15 16 C258 9 10 RCT 6 ENET-7499011121A 5 C259 YA YK RD+ 1V5_ECAT2 C257 Yellow TD- 4 REG_FB 30 52 11 19 3 15 TD+ 2 0_Ohms GND_TAB1 1 ENET-7499011121A ENET2_RX_D0 ENET2_RX_D1 ENET2_RX_D2 ENET2_RX_D3 R274 10 9 10 ENET2_RX_D[3..0] 4 P0RXP P0RXN 78 R272 49.9 1 10uH L26 72 73 R273 49.9 YA YK 0 P0TXP P0TXN 2 R275 10 R238 R276 49.9 GA GK 4 4,21 D32 J48 R277 49.9 11 12 R642 ENET2_TX_EN P1TXERR P1TXD0 P1TXD1 P1TXD2 P1TXD3 P1TXERR P1TXEN P1TXCLK 32 50 66 40V GND_TAB2 D 23 24 25 26 27 28 29 ENET2_TX_D0 ENET2_TX_D1 ENET2_TX_D2 ENET2_TX_D3 P1TXERR_PHY ENET2_TX_EN ENET2_TX_CLK_FB VDD15_1 VDD15_2 VDDAPLL P0VDDMEDIA P1VDDMEDIA 1V5_ECAT E R237 16 ENET2_TX_D0 ENET2_TX_D1 ENET2_TX_D2 ENET2_TX_D3 REGFB DNI 15 ENET2_TX_D[3..0] 4 REGLX1 REGLX2 1.5V_REG_HPS GND_TAB1 ENET1_RX_ERROR ENET1_RX_DV ENET1_RX_CLK ENET1_TX_CLK_FB 4 4 4 4 P0RXD0 P0RXD1 P0RXD2 P0RXD3 P0RXERR P0RXDV P0RXCLK P0CRS P0COL 3.3V 3.3V GND_TAB2 53 ENET1_RX_D0 54 ENET1_RX_D1 55 ENET1_RX_D2 56 ENET1_RX_D3 58 ENET1_RX_ERROR 57 ENET1_RX_DV 59 ENET1_RX_CLK 60 R619 DNI R656 4.70K, 1% 21 ENET1_RX_D0 ENET1_RX_D1 ENET1_RX_D2 ENET1_RX_D3 VDDIO1 VDDIO2 VDDIO3 70 71 77 20 10 16 0 ENET1_RX_D[3..0] 4 REGBVDD1 REGBVDD2 REGAVDD VCC33ESD VDDACB 7 4 4,21 P0TXD0 P0TXD1 P0TXD2 P0TXD3 P0TXERR P0TXEN P0TXCLK NC R613 ENET1_TX_EN P0TXERR 43 44 45 46 47 48 49 ENET1_TX_D0 ENET1_TX_D1 ENET1_TX_D2 ENET1_TX_D3 P0TXERR_PHY ENET1_TX_EN ENET1_TX_CLK_FB 220 3.3V 7 E ENET1_ACT_LED R330 U55 ENET1_TX_D0 ENET1_TX_D1 ENET1_TX_D2 ENET1_TX_D3 NC ENET1_TX_D[3..0] 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 21 of 1 45 C1 8 7 6 5 4 3 2 1 Small Form Factor Pluggable Plus (SFP+) Port A E E 3.3V SFPA_VCCT L37 1.0uH SFPB_VCCT C791 C810 C792 0.1uF 10uF 0.1uF SFPA_VCCR L40 1.0uH SFPB_VCCR C802 C801 0.1uF 10uF D Optical (SFP+) Transceiver Cage & Connector 0 SFPA_VCCR SFPA_VCCT SFPA_TX_P SFPA_TX_N 9 9 SFPA_TX_P SFPA_TX_N SFPA_RX_P SFPA_RX_N 9 9 SFPA_RX_P SFPA_RX_N SFPA_TXDISABLE 5 SFPA_RATESEL0 SFPA_RATESEL1 5 5 J44 16 15 13 12 SFPA_RX_P SFPA_RX_N C R239 R243 R244 R282 R253 R231 R281 3 7 9 SFPA_MOD0_PRSNTn SFPA_MOD1_SCL SFPA_MOD2_SDA 6 5 4 21 22 23 24 25 26 27 28 29 30 31 2.5V_REG_FPGA SFPA_MOD2_SDA SFPA_MOD1_SCL SFPA_MOD0_PRSNTn SFPA_RATESEL1 SFPA_RATESEL0 SFPA_TXFAULT SFPA_LOS SFPA_TXDISABLE SFPA_RATESEL0 SFPA_RATESEL1 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K VCCT VCCR TD_P TD_N RD_P RD_N RX_LOS TX_FAULT TX_DISABLE RS0 RS1 VEET VEET VEET MOD_ABS SCL SDA VEER VEER VEER CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND MH1 MH2 18 19 SFPA_TX_P SFPA_TX_N 8 2 SFPA_LOS SFPA_TXFAULT SFPA_MOD0_PRSNTn SFPA_MOD1_SCL SFPA_MOD2_SDA SFPA_TXFAULT SFPA_LOS 1 17 20 10 11 14 D SFPA_TXDISABLE SFPA_RATESEL0 SFPA_RATESEL1 5 5 5 5 5 SFPA_MOD0_PRSNTn SFPA_MOD1_SCL SFPA_MOD2_SDA SFPA_TXFAULT SFPA_LOS C 32 33 34 35 36 37 38 39 40 41 42 B5 SFP+_CAGE SFP+_AND_CAGE GND_CAGE GND_CAGE Optical (SFP) Transceiver Cage & Connector 1 B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 22 of 1 45 C1 8 7 6 5 4 3 2 1 Small Form Factor Pluggable Plus (SFP+) Port B E E 3.3V SFPB_VCCT L39 1.0uH SFPB_VCCT C795 C774 C796 0.1uF 10uF 0.1uF SFPB_VCCR L38 1.0uH SFPB_VCCR C794 C793 0.1uF 10uF D Optical (SFP+) Transceiver Cage & Connector 0 SFPB_VCCR SFPB_VCCT SFPB_TX_P SFPB_TX_N 9 9 SFPB_TX_P SFPB_TX_N SFPB_RX_P SFPB_RX_N 9 9 SFPB_RX_P SFPB_RX_N SFPB_TXDISABLE 5 SFPB_RATESEL0 SFPB_RATESEL1 5 5 J43 16 15 13 12 SFPB_RX_P SFPB_RX_N C R305 R304 R291 R288 R287 R280 R279 3 7 9 SFPB_MOD0_PRSNTn SFPB_MOD1_SCL SFPB_MOD2_SDA 6 5 4 21 22 23 24 25 26 27 28 29 30 31 2.5V_REG_FPGA SFPB_MOD2_SDA SFPB_MOD1_SCL SFPB_MOD0_PRSNTn SFPB_RATESEL1 SFPB_RATESEL0 SFPB_TXFAULT SFPB_LOS SFPB_TXDISABLE SFPB_RATESEL0 SFPB_RATESEL1 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K VCCT VCCR TD_P TD_N RD_P RD_N RX_LOS TX_FAULT TX_DISABLE RS0 RS1 VEET VEET VEET MOD_ABS SCL SDA VEER VEER VEER CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND MH1 MH2 18 19 SFPB_TX_P SFPB_TX_N 8 2 SFPB_LOS SFPB_TXFAULT SFPB_MOD0_PRSNTn SFPB_MOD1_SCL SFPB_MOD2_SDA SFPB_TXFAULT SFPB_LOS 1 17 20 10 11 14 D SFPB_TXDISABLE SFPB_RATESEL0 SFPB_RATESEL1 10 SFPB_MOD0_PRSNTn 10 SFPB_MOD1_SCL 10 SFPB_MOD2_SDA 10 SFPB_TXFAULT 10 SFPB_LOS C 32 33 34 35 36 37 38 39 40 41 42 B6 SFP+_CAGE SFP+_AND_CAGE GND_CAGE GND_CAGE Optical (SFP) Transceiver Cage & Connector 1 B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 23 of 1 45 C1 8 7 6 5 4 3 2 FMC PORT A G6 FMC_LA_RX_CLK_P FMC_LA_RX_CLK_N G7 D8 FMC_DEVCLK_P D9 FMC_DEVCLK_N H7 FMC_LA_TX_P0 H8 FMC_LA_TX_N0 (M->C) FMC_LA_RX_P0 G9 FMC_LA_RX_N0 G10 DEVCLKB DEVCLK E SYSREF SYSREF (C->M) SYNC (C->M) D FMC_LA_TX_P1 FMC_LA_TX_N1 FMC_SYSREF_P FMC_SYSREF_N FMC_LA_RX_P1 FMC_LA_RX_N1 FMC_LA_TX_P3 FMC_LA_TX_N3 H10 H11 D11 D12 C10 C11 H13 H14 FMC_LA_TX_P16 FMC_LA_TX_N16 FMC_LA_TX_P4 FMC_LA_TX_N4 FMC_LA_RX_P3 FMC_LA_RX_N3 FMC_LA_TX_P5 FMC_LA_TX_N5 G12 G13 D14 D15 C14 C15 H16 H17 FMC_LA_RX_P4 G15 FMC_LA_RX_N4 G16 FMC_LA_TX_P6 D17 FMC_LA_TX_N6 D18 FMC_LA_RX_P5 C18 FMC_LA_RX_N5 C19 FMC_LA_TX_P7 H19 FMC_LA_TX_N7 H20 J26F J26C Blue means change from current Altera FMC spec J26A LA_P0_CC LA_P16 LA_N0_CC LA_N16 LA_P1_CC LA_P17 LA_N1_CC LA_N17 LA_P2 LA_P18_CC LA_N2 LA_N18_CC LA_P3 LA_P19 LA_N3 LA_N19 LA_P4 LA_N4 LA_P5 LA_N5 LA_P6 LA_N6 LA_P7 LA_N7 LA_P20 LA_N20 LA_P21 LA_N21 LA_P22 LA_N22 LA_P23 LA_N23 LA_P8 LA_N8 LA_P9 LA_N9 LA_P10 LA_N10 LA_P11 LA_N11 LA_P24 LA_N24 LA_P25 LA_N25 LA_P26 LA_N26 LA_P27 LA_N27 LA_P12 LA_N12 LA_P13 LA_N13 LA_P14 LA_N14 LA_P15 LA_N15 LA_P28 LA_N28 LA_P29 LA_N29 LA_P30 LA_N30 LA_P31 LA_N31 LA_P32 LA_N32 LA_P33 LA_N33 G18 G19 D20 D21 C22 C23 H22 H23 FMC_LA_RX_P6 FMC_LA_RX_N6 FMC_LA_RX_P7 FMC_LA_RX_N7 G21 G22 H25 H26 G24 G25 D23 D24 FMC_LA_RX_P8 FMC_LA_RX_N8 FMC_LA_TX_P10 FMC_LA_TX_N10 FMC_LA_RX_P9 FMC_LA_RX_N9 FMC_LA_RX_P11 FMC_LA_RX_N11 H28 H29 G27 G28 D26 D27 C26 C27 FMC_LA_TX_P12 FMC_LA_TX_N12 FMC_LA_RX_P10 FMC_LA_RX_N10 FMC_LA_TX_P13 FMC_LA_TX_N13 H31 H32 G30 G31 H34 H35 G33 G34 H37 H38 G36 G37 FMC_LA_TX_P17 FMC_LA_TX_N17 FMC_LA_RX_P12 FMC_LA_RX_N12 FMC_LA_TX_P14 FMC_LA_TX_N14 FMC_LA_RX_P13 FMC_LA_RX_N13 FMC_LA_TX_P15 FMC_LA_TX_N15 FMC_LA_RX_P14 FMC_LA_RX_N14 K25 K26 J24 J25 F22 F23 E21 E22 FMC INTERFACE FMC_LA_RX_CLK_P FMC_LA_RX_CLK_N Alt. DEVCLKB 10 10 FMC_LA_TX_CLK_P FMC_LA_TX_CLK_N Alt. DEVCLK FMC_LA_TX_P9 FMC_LA_TX_N9 8 8 FMC_LA_RX_P[15:0] 8,10 FMC_LA_RX_N[15:0] 8 FMC_LA_TX_N[17:0] 8 FMC_CLK_M2C_P[1:0] 10 FMC_CLK_M2C_N[1:0] 9 FMC_DP_C2M_N[7:0] 9 FMC_GA[1:0] 8 FMC_C2M_PG 19 FMC_GPIO[7:0] 8 ASP-134486-01 C 0 R4007 0 R4009 FMC_SYSREF_N FMC_SYSREF_P FMC_LA_TX_N2 FMC_LA_TX_P2 SYNC (M->C) 0 R4003 0 R4004 FMC_DEVCLK_N FMC_DEVCLK_P FMC_LA_TX_CLK_N FMC_LA_TX_CLK_P FMC_LA_RX_P2 FMC_LA_RX_N2 3.3V DNI R4008 DNI R4010 LMK_SYSREF_FMC_P LMK_SYSREF_FMC_N LMK_CLK_FMC_P LMK_CLK_FMC_N DNI R4005 DNI R4006 12 12 D32 12 12 D40 C39 D36 D38 J26D FMC_DP_C2M_P0 FMC_DP_C2M_N0 FMC_DP_C2M_P1 FMC_DP_C2M_N1 FMC_DP_C2M_P2 FMC_DP_C2M_N2 FMC_DP_C2M_P3 FMC_DP_C2M_N3 FMC_DP_C2M_P4 FMC_DP_C2M_N4 B FMC_DP_C2M_P5 FMC_DP_C2M_N5 FMC_DP_C2M_P6 FMC_DP_C2M_N6 FMC_DP_C2M_P7 FMC_DP_C2M_N7 C2 C3 A22 A23 A26 A27 A30 A31 A34 A35 A38 A39 B36 B37 B32 B33 B28 B29 B24 B25 DP0_C2M_P DP0_C2M_N DP1_C2M_P DP1_C2M_N DP2_C2M_P DP2_C2M_N DP3_C2M_P DP3_C2M_N DP4_C2M_P DP4_C2M_N DP5_C2M_P DP5_C2M_N DP6_C2M_P DP6_C2M_N DP7_C2M_P DP7_C2M_N DP8_C2M_P DP8_C2M_N DP9_C2M_P DP9_C2M_N DP0_M2C_P DP0_M2C_N DP1_M2C_P DP1_M2C_N DP2_M2C_P DP2_M2C_N DP3_M2C_P DP3_M2C_N DP4_M2C_P DP4_M2C_N DP5_M2C_P DP5_M2C_N DP6_M2C_P DP6_M2C_N DP7_M2C_P DP7_M2C_N DP8_M2C_P DP8_M2C_N DP9_M2C_P DP9_M2C_N GBTCLK0_M2C_P GBTCLK0_M2C_N GBTCLK1_M2C_P GBTCLK1_M2C_N A C6 C7 A2 A3 A6 A7 A10 A11 A14 A15 FMC_DP_M2C_P0 FMC_DP_M2C_N0 FMC_DP_M2C_P1 FMC_DP_M2C_N1 FMC_DP_M2C_P2 FMC_DP_M2C_N2 FMC_DP_M2C_P3 FMC_DP_M2C_N3 FMC_DP_M2C_P4 FMC_DP_M2C_N4 A18 A19 B16 B17 B12 B13 B8 B9 B4 B5 FMC_DP_M2C_P5 FMC_DP_M2C_N5 FMC_DP_M2C_P6 FMC_DP_M2C_N6 FMC_DP_M2C_P7 FMC_DP_M2C_N7 D4 D5 B20 B21 FMC_GBTCLK_M2C_P0 FMC_GBTCLK_M2C_N0 FMC_GBTCLK_M2C_P1 FMC_GBTCLK_M2C_N1 F7 F8 E6 E7 K10 K11 J9 J10 VAR_VCCIOP J26E 3P3VAUX VADJ VADJ VADJ VADJ 3P3V 3P3V 3P3V 3P3V VIO_B_M2C VIO_B_M2C 12V C35 C37 12P0V 12P0V VREF_B_M2C VREF_A_M2C 3.3V R90 10.0KFMC_C2M_PG 8,28 8 8 FMC_PRSNTn FMC_SDA FMC_SCL CLK2_BIDIR, CLK3_BIDIR, and CLK_DIR only on High Pincount versions. D1 H2 C31 C30 K4 K5 J2 J3 B1 C34 D35 FMC_GA0 FMC_GA1 9 9 9 9 PG_C2M PG_M2C PRSNT_M2C_L SDA SCL TRST TMS TDO TDI TCK CLK2_BIDIR_P CLK2_BIDIR_N CLK3_BIDIR_PCLK0_M2C_P CLK3_BIDIR_NCLK0_M2C_N CLK1_M2C_P CLK_DIR CLK1_M2C_N GA0 GA1 RES0 HB_P11 HB_N11 HB_P12 HB_N12 HB_P13 HB_N13 HB_P14 HB_N14 HB_P4 HB_N4 HB_P5 HB_N5 HB_P6_CC HB_N6_CC HB_P7 HB_N7 HB_P15 HB_N15 HB_P16 HB_N16 HB_P17_CC HB_N17_CC HB_P18 HB_N18 HB_P8 HB_N8 HB_P9 HB_N9 HB_P10 HB_N10 HB_P19 HB_N19 HB_P20 HB_N20 HB_P21 HB_N21 E39 F40 G39 H40 K40 J39 F10 F11 E9 E10 K13 K14 J12 J13 VREF_FMC HA_P0_CC HA_N0_CC HA_P1_CC HA_N1_CC HA_P2 HA_N2 HA_P3 HA_N3 HA_P4 HA_N4 HA_P5 HA_N5 HA_P6 HA_N6 HA_P7 HA_N7 HA_P12 HA_N12 HA_P13 HA_N13 HA_P14 HA_N14 HA_P15 HA_N15 HA_P16 HA_N16 HA_P17_CC HA_N17_CC HA_P18 HA_N18 HA_P19 HA_N19 HA_P8 HA_N8 HA_P9 HA_N9 HA_P10 HA_N10 HA_P11 HA_N11 HA_P20 HA_N20 HA_P21 HA_N21 HA_P22 HA_N22 HA_P23 HA_N23 ASP-134486-01 PG_M2C only on High Pincount versions. F1 FMC_M2C_PG R89 D34 D33 D31 D30 D29 FMC_JTAG_RST R184 FMC_JTAG_TMS FMC_JTAG_TDO FMC_JTAG_TDI JTAG_MUX_TCK H4 H5 G2 G3 FMC_CLK_M2C_P0 FMC_CLK_M2C_N0 FMC_CLK_M2C_P1 FMC_CLK_M2C_N1 F13 F14 E12 E13 J15 J16 F16 F17 E15 E16 K16 K17 J18 J19 F19 F20 FMC_LA_RX_P15 FMC_LA_RX_N15 E18 E19 K19 K20 J21 J22 K22 K23 FMC_GPIO0 FMC_GPIO1 FMC_GPIO2 FMC_GPIO3 FMC_GPIO4 FMC_GPIO5 FMC_GPIO6 FMC_GPIO7 Alt. SYNC (M->C) 10.0K 14 14 14 13,14,19,25 VAR_VCCIOP B40 R88 DNI E20 E23 E26 E29 E38 E32 E35 E40 K2 K3 K6 K9 K12 K15 K18 K21 K24 K27 K30 K33 K36 K39 J1 J4 J5 J8 J11 J14 J17 J20 J23 J26 J29 J32 J35 J38 J40 H3 H6 H9 H12 H15 H18 H21 H24 H27 H30 H33 H36 H39 D2 D3 D6 D7 D10 D13 D16 D19 D22 D25 D28 D37 D39 C1 C4 C5 C8 C9 C12 C13 C16 C17 C20 C21 C24 C25 C28 C29 C32 C33 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND E17 E14 E11 E8 E5 E4 E1 F39 F36 F33 F30 F27 F24 F21 F18 F15 F12 F9 F6 F3 F2 G40 G38 G35 G32 G29 G26 G23 G20 G17 G14 G11 G8 G5 G4 G1 A40 A37 A36 A33 A32 A29 A28 A25 A24 A21 A20 A17 A16 A13 A12 A9 A8 A5 A4 A1 B39 B38 B35 B34 B31 B30 B27 B26 B23 B22 B19 B18 B15 B14 B11 B10 B7 B6 B3 B2 C40 C38 C36 E D C B ASP-134486-01 VREF_FMC C67 C66 0.1uF 0.1uF R87 DNI Title Date: 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 B 6 E33 E34 F37 F38 E36 E37 3.3V 10.0K Size 7 J33 J34 F34 F35 K37 K38 J36 J37 TRANSLATOR K1 H1 ASP-134486-01 ASP-134486-01 8 J30 J31 F31 F32 E30 E31 K34 K35 J26B F4 F5 E2 E3 K7 K8 J6 J7 9 FMC_DP_M2C_N[7:0] HB_P0_CC HB_N0_CC HB_P1 HB_N1 HB_P2 HB_N2 HB_P3 HB_N3 ASP-134486-01 9 FMC_DP_M2C_P[7:0] Alt. SYNC (C->M) F28 F29 E27 E28 K31 K32 10 FMC_DP_C2M_P[7:0] Alt. SYSREF (C->M) F25 F26 E24 E25 K28 K29 J27 J28 8,10 FMC_LA_TX_P[17:0] Alt. SYSREF (M->C) 1 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 24 of 1 45 C1 5 4 3 2 1 FMC PORT B FMCB_LA_RX_CLK_P G6 FMCB_LA_RX_CLK_N G7 D8 FMCB_DEVCLK_P D9 FMCB_DEVCLK_N FMCB_LA_TX_P16 H7 FMCB_LA_TX_N16 H8 (M->C) FMCB_LA_RX_P12 G9 FMCB_LA_RX_N12G10 DEVCLK D SYSREF SYSREF (C->M) SYNC (C->M) FMCB_LA_TX_P7 H10 FMCB_LA_TX_N7 H11 FMCB_SYSREF_P D11 FMCB_SYSREF_N D12 FMCB_LA_RX_P8 C10 FMCB_LA_RX_N8 C11 FMCB_LA_TX_P10H13 FMCB_LA_TX_N10H14 FMCB_LA_TX_P6 FMCB_LA_TX_N6 FMCB_LA_TX_P0 FMCB_LA_TX_N0 FMCB_LA_RX_P7 FMCB_LA_RX_N7 FMCB_LA_TX_P4 FMCB_LA_TX_N4 G12 G13 D14 D15 C14 C15 H16 H17 FMCB_LA_RX_P6 G15 FMCB_LA_RX_N6 G16 FMCB_LA_TX_P15D17 FMCB_LA_TX_N15D18 FMCB_LA_RX_P15C18 FMCB_LA_RX_N15C19 FMCB_LA_TX_P3 H19 FMCB_LA_TX_N3 H20 C J4C Blue means change from current Altera FMC spec J4A DEVCLKB J4F LA_P0_CC LA_P16 LA_N0_CC LA_N16 LA_P1_CC LA_P17 LA_N1_CC LA_N17 LA_P2 LA_P18_CC LA_N2 LA_N18_CC LA_P3 LA_P19 LA_N3 LA_N19 LA_P4 LA_N4 LA_P5 LA_N5 LA_P6 LA_N6 LA_P7 LA_N7 LA_P20 LA_N20 LA_P21 LA_N21 LA_P22 LA_N22 LA_P23 LA_N23 LA_P8 LA_N8 LA_P9 LA_N9 LA_P10 LA_N10 LA_P11 LA_N11 LA_P24 LA_N24 LA_P25 LA_N25 LA_P26 LA_N26 LA_P27 LA_N27 LA_P12 LA_N12 LA_P13 LA_N13 LA_P14 LA_N14 LA_P15 LA_N15 LA_P28 LA_N28 LA_P29 LA_N29 LA_P30 LA_N30 LA_P31 LA_N31 LA_P32 LA_N32 LA_P33 LA_N33 G18 G19 D20 D21 C22 C23 H22 H23 FMCB_LA_RX_P4 FMCB_LA_RX_N4 FMCB_LA_RX_P11 FMCB_LA_RX_N11 G21 G22 H25 H26 G24 G25 D23 D24 FMCB_LA_RX_P2 FMCB_LA_RX_N2 FMCB_LA_TX_P12 FMCB_LA_TX_N12 FMCB_LA_RX_P1 FMCB_LA_RX_N1 FMCB_LA_RX_P5 FMCB_LA_RX_N5 H28 H29 G27 G28 D26 D27 C26 C27 FMCB_LA_TX_P9 FMCB_LA_TX_N9 FMCB_LA_RX_P13 FMCB_LA_RX_N13 FMCB_LA_TX_P14 FMCB_LA_TX_N14 H31 H32 G30 G31 H34 H35 G33 G34 H37 H38 G36 G37 FMCB_LA_TX_P5 FMCB_LA_TX_N5 FMCB_LA_RX_P0 FMCB_LA_RX_N0 FMCB_LA_TX_P17 FMCB_LA_TX_N17 FMCB_LA_RX_P9 FMCB_LA_RX_N9 FMCB_LA_TX_P2 FMCB_LA_TX_N2 FMCB_LA_RX_P10 FMCB_LA_RX_N10 K25 K26 J24 J25 F22 F23 E21 E22 FMC PORT B INTERFACE FMCB_LA_RX_CLK_P FMCB_LA_RX_CLK_N Alt. DEVCLKB 10 10 FMCB_LA_TX_CLK_P FMCB_LA_TX_CLK_N Alt. DEVCLK FMCB_LA_TX_P1 FMCB_LA_TX_N1 10 10 FMCB_LA_RX_P[15:0] 8,10 FMCB_LA_RX_N[15:0] FMCB_LA_TX_P[17:0] 8,10 FMCB_LA_TX_N[17:0] 8,10 FMCB_CLK_M2C_P[1:0] Alt. SYSREF (M->C) 10 FMCB_CLK_M2C_N[1:0] 9 FMCB_DP_C2M_N[3:0] 8 FMCB_C2M_PG 19 FMCB_GPIO[7:0] 6 ASP-134486-01 FMCB_SYSREF_N FMCB_SYSREF_P 0 R4011 0 R4013 FMCB_LA_TX_N13 FMCB_LA_TX_P13 SYNC (M->C) 0 R4015 0 R4016 FMCB_DEVCLK_N FMCB_DEVCLK_P J4E 3.3V D32 DNI R4012 DNI R4014 LMK_SYSREF_FMCB_P LMK_SYSREF_FMCB_N DNI R4017 DNI R4018 12 12 LMK_CLK_FMCB_P LMK_CLK_FMCB_N 12 12 D40 C39 D36 D38 J4D B FMCB_DP_C2M_P0 C2 FMCB_DP_C2M_N0 C3 FMCB_DP_C2M_P1 A22 FMCB_DP_C2M_N1 A23 FMCB_DP_C2M_P2 A26 FMCB_DP_C2M_N2 A27 FMCB_DP_C2M_P3 A30 FMCB_DP_C2M_N3 A31 A34 A35 A38 A39 B36 B37 B32 B33 B28 B29 B24 B25 DP0_C2M_P DP0_C2M_N DP1_C2M_P DP1_C2M_N DP2_C2M_P DP2_C2M_N DP3_C2M_P DP3_C2M_N DP4_C2M_P DP4_C2M_N DP5_C2M_P DP5_C2M_N DP6_C2M_P DP6_C2M_N DP7_C2M_P DP7_C2M_N DP8_C2M_P DP8_C2M_N DP9_C2M_P DP9_C2M_N DP0_M2C_P DP0_M2C_N DP1_M2C_P DP1_M2C_N DP2_M2C_P DP2_M2C_N DP3_M2C_P DP3_M2C_N DP4_M2C_P DP4_M2C_N DP5_M2C_P DP5_M2C_N DP6_M2C_P DP6_M2C_N DP7_M2C_P DP7_M2C_N DP8_M2C_P DP8_M2C_N DP9_M2C_P DP9_M2C_N GBTCLK0_M2C_P GBTCLK0_M2C_N GBTCLK1_M2C_P GBTCLK1_M2C_N A C6 C7 A2 A3 A6 A7 A10 A11 A14 A15 FMCB_DP_M2C_P0 FMCB_DP_M2C_N0 FMCB_DP_M2C_P1 FMCB_DP_M2C_N1 FMCB_DP_M2C_P2 FMCB_DP_M2C_N2 FMCB_DP_M2C_P3 FMCB_DP_M2C_N3 C35 C37 3P3V 3P3V 3P3V 3P3V VIO_B_M2C VIO_B_M2C 12P0V 12P0V VREF_B_M2C VREF_A_M2C 3.3V R480 6,28 6 6 10.0K FMCB_C2M_PG D1 FMCB_PRSNTn FMCB_SDA FMCB_SCL CLK2_BIDIR, CLK3_BIDIR, and CLK_DIR only on High Pincount versions. H2 C31 C30 K4 K5 J2 J3 B1 FMCB_GA0 FMCB_GA1 FMCB_GBTCLK_M2C_P0 FMCB_GBTCLK_M2C_N0 FMCB_GBTCLK_M2C_P1 FMCB_GBTCLK_M2C_N1 VADJ VADJ VADJ VADJ 12V A18 A19 B16 B17 B12 B13 B8 B9 B4 B5 D4 D5 B20 B21 3P3VAUX 9 9 9 9 C34 D35 PG_C2M PG_M2C PRSNT_M2C_L TRST TMS TDO TDI TCK SDA SCL CLK2_BIDIR_P CLK2_BIDIR_N CLK3_BIDIR_PCLK0_M2C_P CLK3_BIDIR_NCLK0_M2C_N CLK1_M2C_P CLK_DIR CLK1_M2C_N GA0 GA1 RES0 E39 F40 G39 H40 K40 J39 F7 F8 E6 E7 K10 K11 J9 J10 HA_P4 HA_N4 HA_P5 HA_N5 HA_P6 HA_N6 HA_P7 HA_N7 FMCB_LA_RX_P3 F10 FMCB_LA_RX_N3 F11 E9 E10 K13 K14 J12 J13 VREF_FMCB HA_P20 HA_N20 HA_P21 HA_N21 HA_P22 HA_N22 HA_P23 HA_N23 E15 E16 K16 K17 J18 J19 F19 F20 FMCB_LA_RX_P14 FMCB_LA_RX_N14 E18 E19 K19 K20 J21 J22 K22 K23 FMCB_GPIO0 FMCB_GPIO1 FMCB_GPIO2 FMCB_GPIO3 FMCB_GPIO4 FMCB_GPIO5 FMCB_GPIO6 FMCB_GPIO7 ASP-134486-01 K1 H1 PG_M2C only on High Pincount versions. F1 FMCB_M2C_PG R342 Alt. SYNC (M->C) TRANSLATOR 3.3V 10.0K JTAG_MUX_TCK D34 D33 D31 D30 D29 FMCB_JTAG_RST R345 FMCB_JTAG_TMS FMCB_JTAG_TDO FMCB_JTAG_TDI JTAG_MUX_TCK H4 H5 G2 G3 FMCB_CLK_M2C_P0 FMCB_CLK_M2C_N0 FMCB_CLK_M2C_P1 FMCB_CLK_M2C_N1 C848 10.0K 39pF 13 13 13,14 13,14,19,24 R4002 37.4 VAR_VCCIOP B40 R5 DNI GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND E17 E14 E11 E8 E5 E4 E1 F39 F36 F33 F30 F27 F24 F21 F18 F15 F12 F9 F6 F3 F2 G40 G38 G35 G32 G29 G26 G23 G20 G17 G14 G11 G8 G5 G4 G1 A40 A37 A36 A33 A32 A29 A28 A25 A24 A21 A20 A17 A16 A13 A12 A9 A8 A5 A4 A1 B39 B38 B35 B34 B31 B30 B27 B26 B23 B22 B19 B18 B15 B14 B11 B10 B7 B6 B3 B2 C40 C38 C36 D C B ASP-134486-01 A VREF_FMCB C1 C2 0.1uF 0.1uF Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 R4 DNI Title Size B Date: 4 E33 E34 F37 F38 E36 E37 F13 F14 E12 E13 J15 J16 F16 F17 HA_P12 HA_N12 HA_P13 HA_N13 HA_P14 HA_N14 HA_P15 HA_N15 HA_P16 HA_N16 HA_P17_CC HA_N17_CC HA_P18 HA_N18 HA_P19 HA_N19 HA_P8 HA_N8 HA_P9 HA_N9 HA_P10 HA_N10 HA_P11 HA_N11 ASP-134486-01 ASP-134486-01 5 J33 J34 F34 F35 K37 K38 J36 J37 HB_P19 HB_N19 HB_P20 HB_N20 HB_P21 HB_N21 HA_P0_CC HA_N0_CC HA_P1_CC HA_N1_CC HA_P2 HA_N2 HA_P3 HA_N3 VAR_VCCIOP FMCB_LA_TX_CLK_N FMCB_LA_TX_CLK_P HB_P15 HB_N15 HB_P16 HB_N16 HB_P17_CC HB_N17_CC HB_P18 HB_N18 J30 J31 F31 F32 E30 E31 K34 K35 J4B 9 FMCB_GA[1:0] HB_P4 HB_N4 HB_P5 HB_N5 HB_P6_CC HB_N6_CC HB_P7 HB_N7 HB_P8 HB_N8 HB_P9 HB_N9 HB_P10 HB_N10 F4 F5 E2 E3 K7 K8 J6 J7 9 FMCB_DP_M2C_N[3:0] HB_P11 HB_N11 HB_P12 HB_N12 HB_P13 HB_N13 HB_P14 HB_N14 ASP-134486-01 9 FMCB_DP_M2C_P[3:0] Alt. SYNC (C->M) F28 F29 E27 E28 K31 K32 10 FMCB_DP_C2M_P[3:0] Alt. SYSREF (C->M) F25 F26 E24 E25 K28 K29 J27 J28 8,10 HB_P0_CC HB_N0_CC HB_P1 HB_N1 HB_P2 HB_N2 HB_P3 HB_N3 E20 E23 E26 E29 E38 E32 E35 E40 K2 K3 K6 K9 K12 K15 K18 K21 K24 K27 K30 K33 K36 K39 J1 J4 J5 J8 J11 J14 J17 J20 J23 J26 J29 J32 J35 J38 J40 H3 H6 H9 H12 H15 H18 H21 H24 H27 H30 H33 H36 H39 D2 D3 D6 D7 D10 D13 D16 D19 D22 D25 D28 D37 D39 C1 C4 C5 C8 C9 C12 C13 C16 C17 C20 C21 C24 C25 C28 C29 C32 C33 3 2 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 Rev (6XX-44209R) Sheet 1 25 of 45 C1 8 7 6 5 4 3 2 1 QSPI Flash & Reset Circuit E E QSPI FLASH RESET CIRUIT D D 3.3V 3.3V 3.3V 0.1uF C319 U19 U66 7 7 7 7 QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 15 8 9 1 7 QSPI_CLK 16 7 QSPI_SS0 7 C 3 MAX_QSPI_RSTn 19 VCC DQ0 DQ1 DQ2/VPP/W# DQ3/HOLD# C S# DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 RESET VSS 2 4 R403 20.0K 4 5 6 11 12 13 14 3 S9 1 2 PB Switch VCC MR PB_COLD_RESETn GND RESET 1 2 MAX811 COLD_RESETn R402 100K R401 0 USB_RESET IS ACTIVE HIGH AND IS INVERTED THROUGH THE MAX V SYSTEM CONTROLLER DNI R407 RESET_HPS_UARTA_N DNI R408 RESET_HPS_UARTB_N 29 0 R409 ENET_HPS_RESETn 20 29 C 10 N25Q512A83GSF40F 3.3V TP2 DNI R659 ENET_DUAL_RESETn R481 2.00K 1% MAX_QSPI_RSTn 4,21 HPS_RESETn 7,19 HPS_RESETn Input only to AV device cold reset 3.3V 3.3V B 0.1uF B C318 U65 3.3V 4 PLACE NEAR QSPI FLASH R400 20.0K 3 C340 C339 4.7uF S10 1 0.1uF 2 PB Switch PB_WARM_RESETn VCC MR GND RESET 1 2 WARM_RESETn MAX811 R399 100K R398 4.70K, 1% Input/output to AV device warm reset MICTOR_RSTn A 7,14,19 MICTOR_RSTn A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 26 of 1 45 C1 8 7 6 5 4 3 2 1 USB 2.0 OTG , Micro SD Card Current limit for Rseti of 137k is 1.013A USB INTERFACE USB_RESET 19 7 USB_CLK 7 USB_NXT 7 USB_DIR 7 USB_STP USB_DATA[7..0] 7 E 5.0V USB_RESET USB_CLK USB_NXT USB_DIR USB_STP USB_DATA[7..0] E USB_5.0V U2 C7 5 1 6 2.2uF USB 2.0 OTG 3.3V IN NC1 NC2 2 USB_5.0V USB_EXTVBUS R20 DNI OUT SETI 7 ON 1% 3 R341 C292 137K FLAG USB_VDD 4 GND GND_PAD 0.1uF 8 9 MAX14523B USB_VDDA R21 DNI C48 4.7uF 0.1uF C312 C44 4.7uF 0.1uF 3.3V 0.1uF R32 DNI USB_DATA0 USB_DATA1 USB_DATA2 USB_DATA3 USB_DATA4 USB_DATA5 USB_DATA6 USB_DATA7 USB_CLK USB_NXT USB_DIR USB_STP 14 11 12 13 USB_RBIAS 32 USB_RESET_PHY USB FPGA INTERFACE C USB_FPGA_RESET USB_FPGA_WR USB_FPGA_RDn USB_FPGA_TXEn USB_FPGA_RXFn USB_FPGA_DATA[7..0] USB_FPGA_5.0V USB_FPGA_2.5V U6 USB_FPGA_RESET USB_FPGA_WR USB_FPGA_RDn USB_FPGA_TXEn USB_FPGA_RXFn USB_FPGA_DATA[7..0] 19 8 8 8 13 8,10 8 7 6 5 C303 1uF IN OUT NC7 SENSE NC6 NC3 SHDNn GND EPAD 1 2 3 4 9 R22 12.0K 24 23 22 21 20 19 18 17 9 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 15 26 29 REG_EN CPEN EXTVBUS VBUS DM DP ID CLKOUT NXT DIR STP XO XI RBIAS GND GND GND_FLAG RESET 31 3 10 USB_CPEN USB_EXTVBUS 4 8 7 5 27 28 R26 100K USB_VBUS USB_DM_N USB_DP_P USB_ID USB_XO USB_XI R19 4 1 2 33 C9 J1 MICRO_USB_CONN 1 VBUS 2 D3 D+ 4 ID 5 820,1% C39 X1 2 30pF R27 1M 24MHz C32 D 4.7uF 6 7 8 9 C43 4.7uF C317 R43 R54 R53 R52 R51 R42 R41 R33 3 C316 USB_FPGA_3.3V USB_5.0V 1 USB_FPGA_2.5V PLACE NEAR FT245RQ 3.3V VDDA1.8 USB_FPGA_5.0V D VDD3.3 VDD3.3 VDD3.3 VDD3.3 10.0K VDD1.8 VDD1.8 30 25 16 6 3.3V U4 30pF USB3300 R25 10.0K USB_RESET R18 0 C USB_RESET_PHY C304 R347 5.11K C308 0.01uF 1uF 3.3V USB_VDD PLACE NEAR USB3300 USB_VDDA LT3010 R346 5.23K USB_FPGA_2.5V C297 C299 4.7uF USB_FPGA_5.0V 0.1uF C307 C306 0.1uF 0.1uF C298 C300 C311 4.7uF 0.1uF USB_FPGA_5.0V 26 R62 4.70K, 1% USB_FPGA_2.5V RESET# TEST FT245RQ 7 8 1 2 1 2 1 2 1 2 K1 K2 K1 K2 K2 ESD5V3U2U D5 ESD5V3U2U D7 ESD5V3U2U 3 D6 A 10.0K 4 17 20 24 33 VDD CMD DAT0 DAT1 DAT2 CD/DAT3 CAGE CAGE CAGE CAGE VSS 4 9 10 11 12 6 C22 C10 C11 2.2uF 0.1uF 0.1uF B TP3 SD_DAT2 SD_CD_DAT3 SD_DAT0 SD_DAT1 SD_CMD SD_DAT2 SD_CD_DAT3 SD_DAT0 SD_DAT1 SD_CMD 7 7 7 7 7 SD_CLK 7 SD_CLK A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 0 USB_F_RESET_PHY Size B Date: 7 3.3V CLK Micro SD / USB INTERFACE Title USB_FPGA_RESET R67 8 0.1uF MicroSD_skt 6 7 8 9 USB_FPGA_2.5V R60 3 A 9 SD_CMD SD_DAT0 SD_DAT1 SD_DAT2 SD_CD_DAT3 3 GND GND GND AGND GND_PAD USB_FPGA_TXEn USB_FPGA_RXFn 27 28 5 A PWREN# WR RD# 21 22 J14 MICRO_USB_CONN 1 2 VBUS D3 D+ 4 ID 5 K1 16 3V3VOUT 19 VCC OSCI OSCO 3A, 30 Ohm FB L9 USB_F_DM_N USB_F_DP_P 0 R65 15 14 SD_CLK 4.7uF 3 18 USBDM USBDP TXE# RXF# NC0 NC1 NC2 NC3 NC4 NC5 11 10 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 C50 0.01uF 5 12 13 25 29 23 USB_F_RESET_PHY 30 2 32 8 31 6 7 3 VCCIO 10.0K USB_FPGA_WR USB_FPGA_RDn A 1 U8 USB_FPGA_DATA0 USB_FPGA_DATA1 USB_FPGA_DATA2 USB_FPGA_DATA3 USB_FPGA_DATA4 USB_FPGA_DATA5 USB_FPGA_DATA6 USB_FPGA_DATA7 0.1uF J5 5V_F_USB C49 R71 R70 R73 R63 R72 R68 R64 R69 C301 C305 4.7uF USB_FPGA_3.3V FPGA USB B 0.1uF C302 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 27 of 1 45 C1 8 7 6 5 4 3 2 1 User I/O, RTC 3.3V R4000 49.9 Green_LED R690 HEADER 3X1 HEADER 6X1 Note to assembler: Use this resistor to attach to LCD Header (follow assembly instructions). 49.9 10K 10K 49.9 5.0V J29 Green_LED PGM_LED1 R694 49.9 R695 49.9 Green_LED PGM_LED2 I2C_SCL_DISP I2C_SDA_DISP D 8 1 2 I2C_SCL_DISP I2C_SDA_DISP 1 2 3 4 5 6 7 8 9 10 D20 5 4 I2C_SCL_HPS I2C_SDA_HPS R91 49.9 2 PGM_CONFIG PB Switch R692 2 PGM_SEL PB Switch R691 4.70K, 1% 2 MAX_RESETn PB Switch R435 4.70K, 1% 2 CPU_RESETn PB Switch R687 3 0.1uF 0 0 16 1 4.70K, 1% 15 13 12 11 10 VCC VBACKUP SDA SCL SQW/INT 14 2 R103 4.70K, 1% 3.3V 4 5 6 7 8 9 NC5 NC6 NC7 NC8 NC9 NC10 GND NC1 NC2 NC3 NC4 VBAT BT1 DS1339C C S14 1 4.70K, 1% LED INTERFACE PGM_LED[2:0] 2.5V_REG_FPGA 19 Green_LED R348 FMCB_PRSNTn 2.5V_REG_HPS 49.9 USER_LED_FPGA[3:0] S8 1 2 USER_PB_HPS0 PB Switch R388 4.70K, 1% 2 USER_PB_HPS1 PB Switch R389 4.70K, 1% 3.3V R369 2 USER_PB_HPS2 PB Switch R390 4.70K, 1% 2 USER_PB_HPS3 PB Switch R391 4.70K, 1% 19 19 19 S6 1 Green_LED USER_LED_HPS0 4 MAX_ERROR MAX_LOAD MAX_CONF_DONE S7 1 D16 7,20,33 7,20,33 Green_LED FMC_PRSNTn D8 0 U11 C79 S11 2.5V_REG_FPGA VL_IO1 VL_IO2 R500 I2C ADDRESS: 0x40 S13 1 VCCIO1 VCCIO2 GND 3 6 3.3V I2C_SDA_HPS R83 I2C_SCL_HPS R104 S12 1 VL TRI_STATE D 2.5V_REG_HPS C VCC MAX3373 LCD_HEADER 1 3.3V R501 DNI U31 7 Green_LED R693 D41 2x16 LCD I2C I2C ADDRESS: 0x50 E 2.5V_REG_HPS 5.0V PGM_LED0 D42 B4 1 D43 R688 B2 Green_LED MAX_LOAD D38 MAX_CONF_DONE 49.9 R495 D40 R689 2 MAX_ERROR E B1 Red_LED R496 D39 49.9 S5 1 B D15 Green_LED R370 USER_LED_HPS1 49.9 USER_LED_HPS[3:0] 1.5V_REG_FPGA 1 Green_LED USER_LED_HPS2 R371 49.9 2 USER_PB_FPGA0 PB Switch R392 2 USER_PB_FPGA1 PB Switch R393 4.70K, 1% 2 USER_PB_FPGA2 PB Switch R394 4.70K, 1% 2 USER_PB_FPGA3 PB Switch R395 4.70K, 1% 4.70K, 1% USER_PB_HPS[3:0] 1 D13 Green_LED R372 USER_LED_HPS3 49.9 2.5V_REG_FPGA R373 USER_DIPSW_FPGA[3:0] 4 PUSH BUTTON INTERFACE PGM_SEL PGM_CONFIG MAX_RESETn S1 1 Green_LED USER_LED_FPGA0 6,25 S2 1 D12 49.9 3.3V 19 19 19 USER_PB_FPGA[3:0] D11 Green_LED R374 16 15 14 13 12 11 10 9 49.9 A D10 USER_LED_FPGA2 D9 Green_LED R375 49.9 Green_LED R376 USER_LED_FPGA3 1 2 3 4 5 6 7 8 USER_DIPSW_HPS0 USER_DIPSW_HPS1 USER_DIPSW_HPS2 USER_DIPSW_HPS3 USER_DIPSW_FPGA0 USER_DIPSW_FPGA1 USER_DIPSW_FPGA2 USER_DIPSW_FPGA3 R380 R381 R382 R383 R384 R385 R386 R387 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% 4.70K, 1% CPU_RESETn 2.5V_REG_FPGA Title Size 49.9 B Date: 7 6 5 4 13,19 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 TDA08H0SB1 8 4 SW1 USER_LED_FPGA1 B DIPSW INTERFACE 7 S3 8,24 FMCB_PRSNTn 7 S4 D14 FMC_PRSNTn 7 USER_DIPSW_HPS[3:0] 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 28 of 1 45 C1 8 7 6 5 4 3 2 1 UARTS PORT A and PORT B E E UART U25 3.3V D CON2 RESET_HPS_UARTA_N 26 Green_LED D21 220 R442 Green_LED D22 220 R441 3.3V_USB_UARTA R112 UARTA_TX_LED UARTA_RX_LED 18 22 21 10 11 9 10.0K PWR_ENA 5V_USB_UARTA RESET_HPS_UARTA_N R117 10.0K CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 26 20 17 4 24 33 R115 RESET NC1 NC2 NC3 NC4 NC5 NC6 OSCI OSCO VIO_USB_UARTA 0 DNI R119 15 14 5V_USB_UARTA DMA_N DPA_P 742792780 R108 25 23 5 12 13 29 27 28 C82 C83 39pF 39pF J22 USB MINI-B L11 0 1 2 3 4 5 6 7 881545-2 USBDM USBDP 3.3V_USB_UARTA R118 D U20 3.3V_USB_UARTA VIO_USB_UARTA 5V_USB_UARTA TP1 C94 C86 C102 C105 C87 C84 0.1uF 2.2uF 0.1uF 2.2uF 0.1uF 4.7uF TPD4S012DRYR 4 1 2 16 1 6 3 1 2 5 J23 3V3OUT VCCIO 19 VBUS ID D+ DGND NC XJ2 VCC TXD RXD RTS CTS DTR DSR DCD RI TEST GND3 GND2 GND1 AGND EPAD_GND 30 2 32 8 31 6 7 3 UARTA_RX UARTA_TX 7 7 FT232R 4.70K, 1% C C U36 RESET_HPS_UARTB_N 26 Green_LED D23 220 R494 Green_LED D24 220 R493 3.3V_USB_UARTB R136 10.0K UARTB_TX_LED UARTB_RX_LED PWR_ENB 5V_USB_UARTB R135 RESET_HPS_UARTB_N R139 10.0K 18 22 21 10 11 9 RESET CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 NC1 NC2 NC3 NC4 NC5 NC6 OSCI OSCO VIO_USB_UARTB 0 DNI R141 15 14 5V_USB_UARTB DMB_N DPB_P 742792780 R133 25 23 5 12 13 29 27 28 C120 C121 39pF 39pF J27 USB MINI-B L15 0 1 2 3 4 5 6 7 3.3V B CON2 3.3V_USB_UARTB R140 B U32 3.3V_USB_UARTB VIO_USB_UARTB 5V_USB_UARTB TP9 C128 C125 C134 C146 C126 C122 0.1uF 2.2uF 0.1uF 2.2uF 0.1uF 4.7uF TPD4S012DRYR 4 881545-2 USBDM USBDP 16 1 6 3 1 2 5 1 2 19 VBUS ID D+ DGND NC J30 3V3OUT VCCIO TEST GND3 GND2 GND1 AGND EPAD_GND XJ3 VCC TXD RXD RTS CTS DTR DSR DCD RI 26 20 17 4 24 33 30 2 32 8 31 6 7 3 UARTB_RX UARTB_TX 7 7 FT232R 4.70K, 1% A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 29 of 1 45 C1 8 7 6 5 4 3 2 On-Board USB Blaster II 1 FPGA USB INTERFACE USB_B2_DATA[7:0] R662 FX2_SDA 0 J50 USB MINI-B 3.3V 1 2 3 4 5 VBUS_5V FX2_D_N FX2_D_P R315 C246 0.1uF 1 DNI 100K R264 GND 2 FX2_RESETn VCC RESET MR 4 U56B R334 D+ D- 1 2 3.3V U61 TPD2EUSB30 D1 D2 4.7nF G1 A5 B5 C5 E7 E8 C287 D E1 E2 4 Y7 3 2 1 G2 C1 C2 USB_B2_CLK 24M_XTALIN 24M_XTALOUT 24.00MHz C266 C267 12pF 12pF G8 G6 F8 F7 F6 C8 C7 C6 FX2_PA1 FX2_PA2 FX2_PA3 FX2_PA4 FX2_PA5 FX2_PA6 FX2_PA7 C H2 F1 F2 H1 A4 B4 C4 D7 D8 3.3V AVCC AVCC RESET SCL SDA VCC VCC VCC VCC VCC VCC WAKEUP CTL0 CTL1 CTL2 DMINUS DPLUS RDY0 RDY1 IFCLK XTALIN XTALOUT CLKOUT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 RESERVED PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 AGND AGND GND GND GND GND GND GND B8 F3 G3 FX2_RESETn FX2_SCL R679 FX2_SDA R677 B7 FX2_WAKEUP H7 G7 H8 FX2_FLAGA FX2_FLAGB FX2_FLAGC A1 B1 FX2_SLRDn FX2_SLWRn 2.00K 2.00K 10.0K H3 F4 H4 G4 H5 G5 F5 H6 FX2_PB0 FX2_PB1 FX2_PB2 FX2_PB3 FX2_PB4 FX2_PB5 FX2_PB6 FX2_PB7 A8 A7 B6 A6 B3 A3 C3 A2 FX2_PD0 FX2_PD1 FX2_PD2 FX2_PD3 FX2_PD4 FX2_PD5 FX2_PD6 FX2_PD7 MAX_SDA C_USB_MAX_TDI C_USB_MAX_TCK C_USB_MAX_TMS C_USB_MAX_TDO 20.0K 0.1uF FX2_PB1 FX2_PB3 FX2_SCL FX2_PD6 FX2_PD4 J7 H2 H3 J1 J2 IO1/DEV_OE M570_PCIE_JTAG_EN FX2_SLWRn FX2_SLRDn FX2_PD7 FX2_PD5 FX2_PA5 C_JTAG_TDO C_JTAG_TMS C_JTAG_TDI C_JTAG_TCK TDI TCK TMS TDO IO1/GCLK0p IO1/GCLK1p IO2/GCLK2p IO2/GCLK3p K9 E 19 M570_PCIE_JTAG_EN MAX V USB INTERFACE USB_CFG[11:0] 19 USB_CFG[11:0] EXTRA_SIG[2:0] 19 EXTRA_SIG[2:0] D USB_DISABLEn M570_CLOCK FACTORY_STATUS FACTORY_REQUEST R684 R682 R666 R683 C_USB_MAX_TCK C_USB_MAX_TDI C_USB_MAX_TDO C_USB_MAX_TMS IO1/DEV_CLRn 4 USB_FULL 4 USB_EMPTY 4 USB_SCL 4 USB_SDA 4,19 USB_B2_CLK 4 USB_RESETn 4 USB_OEn 4 USB_RDn 4 USB_WRn 0 0 0 0 14 USB_DISABLEn 19 M570_CLOCK 19 FACTORY_STATUS 19 FACTORY_REQUEST FX2_PD0 FX2_PD2 FX2_PD3 FX2_PD1 FX2_RESETn JTAG INTERFACE E2 USB_B2_CLK E1 FX2_PB7 F8 USB_CFG7 E10 M570_CLOCK JTAG_TCK JTAG_TMS JTAG_BLASTER_TDI JTAG_BLASTER_TDO 14 14 14 14 EPM570GF100 JTAG_TCK JTAG_TMS JTAG_BLASTER_TDI JTAG_BLASTER_TDO C U56C A1 JTAG_TX A2 JTAG_RX FACTORY_REQUEST A3 A4 USB_CFG5 A7 USB_RESETn B8 USB_OEn D10 USB_RDn D9 USB_WRn A9 FACTORY_STATUS A10 SC_RX B2 SC_TX B3 USB_CFG4 B4 EXTRA_SIG1 B5 USB_CFG6 B9 USB_B2_DATA0 C9 USB_B2_DATA1 C8 USB_B2_DATA2 B7 USB_B2_DATA3 C7 USB_B2_DATA4 PLACE NEAR CY7C68013A C842 H8 J3 J4 J5 J6 J8 J9 K1 K2 K3 K4 K5 K6 K7 K8 K10 MAX II CONFIGURATION FX2_WAKEUP R686 IO_B1_H8 IO_B1_J3 IO_B1_J4 IO_B1_J5 IO_B1_J6 IO_B1_J8 IO_B1_J9 IO_B1_K1 IO_B1_K2 IO_B1_K3 IO_B1_K4 IO_B1_K5 IO_B1_K6 IO_B1_K7 IO_B1_K8 IO_B1_K10 U56D B2 3.3V B IO_B1_B1 IO_B1_C1 IO_B1_C2 IO_B1_D1 IO_B1_D2 IO_B1_D3 IO_B1_E3 IO_B1_F1 IO_B1_F2 IO_B1_F3 IO_B1_G1 IO_B1_G2 IO_B1_G3 IO_B1_H1 IO_B1_H4 IO_B1_H7 EPM570GF100 CY7C68013A_VFBGA VBUS_5V R685 B1 C1 C2 D1 D2 D3 E3 F1 F2 F3 G1 G2 G3 H1 H4 H7 FX2_PA2 FX2_FLAGC FX2_PA7 FX2_FLAGA FX2_PA3 FX2_PA4 EXTRA_SIG0 FX2_PB4 FX2_PA6 FX2_PB2 FX2_FLAGB FX2_PB0 FX2_PA1 FX2_PB5 USB_DISABLEn FX2_PB6 U63 GND MAX II BANK 1 3 MAX811 3 USB_FULL USB_EMPTY USB_SCL USB_SDA USB_B2_CLK USB_RESETn USB_OEn USB_RDn USB_WRn U57 7 6 E 1M 4 USB_B2_DATA[7:0] MAX_SDA C837 C835 C833 C843 C831 C832 C836 C841 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF MAX II BANK 2 IO_B2_A1 IO_B2_A2 IO_B2_A3 IO_B2_A4 IO_B2_A7 IO_B2_B8 IO_B2_D10 IO_B2_D9 IO_B2_A9 IO_B2_A10 IO_B2_B2 IO_B2_B3 IO_B2_B4 IO_B2_B5 IO_B2_B9 IO_B2_C9 IO_B2_C8 IO_B2_B7 IO_B2_C7 1V8 U56A IO_B2_C3 IO_B2_C4 IO_B2_A6 IO_B2_F10 IO_B2_F9 IO_B2_B10 IO_B2_E8 IO_B2_C10 IO_B2_D8 IO_B2_B6 IO_B2_E9 IO_B2_A8 IO_B2_A5 IO_B2_G8 IO_B2_G9 IO_B2_G10 IO_B2_H9 IO_B2_H10 IO_B2_J10 C3 USB_CFG3 C4 M570_PCIE_JTAG_EN A6 USB_B2_DATA7 F10 USB_B2_DATA5 F9 USB_B2_DATA6 B10 RST E8 USB_CFG8 C10 TRST D8 USB_FULL B6 USB_EMPTY E9 USB_CFG11 A8 USB_SCL A5 USB_SDA G8 EXTRA_SIG2 G9 USB_CFG10 G10 USB_CFG0 V77 H9 V81 USB_CFG1 H10 USB_CFG2 V80 J10 USB_CFG9 MAX II POWER C5 E6 F5 H5 D5 D7 E5 F6 G5 G7 GNDINT GNDINT GNDINT GNDINT VCCINT VCCINT VCCINT VCCINT GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 C6 E7 F4 H6 3.3V E4 G4 G6 1.5V_REG_HPS D4 D6 F7 EPM570GF100 B EPM570GF100 1V8 1.5V_REG_HPS D35 JTAG_RX RESn_JTAG_RX R651 56.2 Green_LED D36 JTAG_TX RESn_JTAG_TX R650 56.2 Green_LED D34 SC_RX RESn_SC_RX R652 TRST RST 56.2 R672 R670 R673 R671 1.00K 1.00K 1.00K 1.00K R669 1.00K FACTORY_REQUEST USB_SCL USB_SDA USB_FULL USB_EMPTY 3.3V J51 SC_TX RESn_SC_TX R653 56.2 R660 R661 R664 R665 JTAG_TCK JTAG_TMS JTAG_BLASTER_TDI JTAG_BLASTER_TDO DNI JTAG_BLASTER_TDI R377 Green_LED 1.00K C_USB_MAX_TCK 1 C_USB_MAX_TDO 3 1.00K C_USB_MAX_TMS 5 7 C_USB_MAX_TDI 9 1 3 5 7 9 2 4 6 8 10 R645 C825 C826 C827 C829 C828 C830 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Title Size Date: 6 5 4 3 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 B 7 1V8 2.5V_REG_HPS 2 4 6 8 10 DNI 8 PLACE NEAR MAX II (U14) 3.3V 1.5V_REG_HPS 3.3V R362 Green_LED D33 A 0 0 0 0 C_JTAG_TCK C_JTAG_TMS C_JTAG_TDI C_JTAG_TDO 19 19 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 30 of 1 45 C1 5 4 V1 1 VAR_VCC_N RSNS SNS 1 RSNS SNS 2 12V VAR_VCCIO 2 J20 1 2 SENSE_PAD D V78 1 1.1V_VCC_N RSNS SNS 1 RSNS SNS 1 RSNS SNS 1 RSNS SNS OVERTEMP 1 RSNS SNS 2 1.5V_FPGA 2 1 RSNS SNS FAN_2pin_Conn 1.5V_REG_FPGA 2 2.5V_FPGA 2 SENSE_PAD V67 2.5V_FPGA_P 3.3V_PM_FPGA R307 R313 2.5V_REG_FPGA R301 R300 1K 1K C274 0.1uF C275 0.1uF R299 R298 1K 1K C272 0.1uF C273 0.1uF 10K 10K SCL_PM SDA_PM SCL_PM SDA_PM 0 0 I2C_SCL I2C_SDA 10,19,32 10,19,32 2 SENSE_PAD C 19 FDV305N 1.1V_REG_VCC SENSE_PAD V68 2.5V_FPGA_N Q1 B3 SENSE_PAD V71 1.5V_FPGA_P D 22_23_2021 1.1V_VCC SENSE_PAD V72 1.5V_FPGA_N TSENSE_FAN_CNTL 2 SENSE_PAD V79 1.1V_VCC_P 1 FPGA Power Monitor 1 VAR_VCCIOP 2 SENSE_PAD V4 VAR_VCC_P 3 12V R308 R312 C U64 B 14 R297 R296 1K 1K C270 0.1uF C271 0.1uF R295 R294 1K 1K C268 0.1uF C269 0.1uF R316 R317 1K 1K C279 0.1uF C278 0.1uF R325 R326 1K 1K C281 0.1uF C280 0.1uF R332 R333 R335 R336 1K 1K 1K 1K C285 0.1uF C284 0.1uF 36 37 42 43 46 47 48 49 52 53 62 63 64 1 2 3 2.5V_FPGA_V_0_P 2.5V_FPGA_V_0_N 2.5V_FPGA_I_P 2.5V_FPGA_I_N 1.5V_FPGA_V_P 1.5V_FPGA_V_N 1.5V_FPGA_I_P 1.5V_FPGA_I_N 1.1V_VCC_V_P 1.1V_VCC_V_N 1.1V_VCC_I_P 1.1V_VCC_I_N VAR_VCC_V_P VAR_VCC_V_N VAR_VCC_I_P VAR_VCC_I_N SCL_PM SDA_PM PM2_ASEL0 PM2_ASEL1 PM_CNTL0 PM_CNTL1 PM_RSTn C289 0.1uF C288 0.1uF 28 27 32 33 30 31 22 PM2_FAULTB00 PM2_FAULTB01 PM2_FAULTB10 PM2_FAULTB11 23 24 25 26 PM_SHARE_CLK 21 19 65 3.3V_PM_FPGA VIN_SNS VSENSEP0 VSENSEM0 VSENSEP1 VSENSEM1 VSENSEP2 VSENSEM2 VSENSEP3 VSENSEM3 VSENSEP4 VSENSEM4 VSENSEP5 VSENSEM5 VSENSEP6 VSENSEM6 VSENSEP7 VSENSEM7 R327 10K R302 10K REFP REFM NC VDACP0 VDACM0 VDACP1 VDACM1 VDACP2 VDACM2 VDACP3 VDACM3 VDACP4 VDACM4 VDACP5 VDACM5 VDACP6 VDACM6 VDACP7 VDACM7 SCL SDA ASEL0 ASEL1 CONTROL0 CONTROL1 WDI/RESET VOUT_EN0 VOUT_EN1 VOUT_EN2 VOUT_EN3 VOUT_EN4 VOUT_EN5 VOUT_EN6 VOUT_EN7 FAULTB00 FAULTB01 FAULTB10 FAULTB11 SHARE_CLK ALERTB PWRGD VPWR VDD25 WP E-PAD GND pad R306 R318 R319 10K 10K 10K VIN_EN LTC2977 VDD33_OUT VDD33_IN 12 2.5V_FPGA_VDACP0 1.5V_FPGA_VDACP2 1.1V_FPGA_VDACP4 VAR_FPGA_VDACP6 C839 0.1uf 34 35 13 2.5V_FPGA_VDACP0 1.5V_FPGA_VDACP2 1.1V_FPGA_VDACP4 VAR_FPGA_VDACP6 39 38 40 41 44 45 50 51 55 54 56 57 59 58 60 61 2.5V_FPGA_VDACP0 SCL_PM SDA_PM 32,33 32,33 SCL_PM SDA_PM 1.5V_FPGA_VDACP2 PM_SHARE_CLK PM_CNTL0 PM_CNTL1 PM_RSTn 32,33 32,33 32,33 32,33 PM_SHARE_CLK PM_ALERTB PM_PWRGD 32,33 32,33 PM_ALERTB PM_PWRGD 4 5 6 7 8 9 10 11 2.5V_FPGA_RUN 37 1.5V_FPGA_RUN 36 1.5V_FPGA_RUN 1.1V_FPGA_RUN 35 1.1V_FPGA_RUN VAR_FPGA_RUN 35 VAR_FPGA_RUN 29 20 15 18 1.1V_FPGA_VDACP4 PM_CNTL0 PM_CNTL1 PM_RSTn VAR_FPGA_VDACP6 B 2.5V_FPGA_RUN PM_ALERTB PM_PWRGD 3.3V_PM_FPGA 16 17 C847 C290 C286 LTC2977 Address Select PWRMON2 = 7'h5E A PM2_ASEL0 PM2_FAULTB00 PM2_FAULTB01 PM2_FAULTB10 PM2_FAULTB11 0.1uf 0.1uf 0.1uf A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 PM2_ASEL1 Title Size B Date: 5 37 36 35 35 4 3 2 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 Rev (6XX-44209R) Sheet 1 31 of 45 C1 8 7 6 5 4 3 2 1 FPGA Power Monitor 2 V3 1 1.5V_VCCD_N RSNS SNS 1.5V_VCCD_VCCH 2 SENSE_PAD V2 E 1 1.5V_VCCD_P RSNS SNS SENSE_PAD V5 1 1.15V_VCCT_N RSNS SNS SENSE_PAD V6 1 1.15V_VCCT_P RSNS SNS SENSE_PAD V74 1 1.15V_GXB_N RSNS SNS SENSE_PAD V73 1 1.15V_GXB_P D RSNS SNS E 1.5V_VCCD_VCCHP 2 1.15V_VCCT 2 1.15V_VCCTP 2 1.15V_GXB 2 3.3V_PM_FPGA R240 R234 1.15V_GXBP 2 1K 1K C232 0.1uF C231 0.1uF R248 R249 1K 1K C234 0.1uF C233 0.1uF SCL_PM SDA_PM 0 SCL_PM SDA_PM 0 12V SENSE_PAD R246 R247 10K 10K I2C_SCL I2C_SDA 10,19,31 10,19,31 D R233 R229 U54 C 14 R250 R241 1K 1K C236 0.1uF C235 0.1uF R236 R235 1K 1K C227 0.1uF C229 0.1uF R230 R226 1K 1K C220 0.1uF C226 0.1uF R221 R220 1K 1K C212 0.1uF C216 0.1uF 36 37 42 43 46 47 48 49 52 53 62 63 64 1 2 3 1.1.5V_GXB_V_P 1.15V_GXB_V_N 1.15V_GXB_I_P 1.15V_GXB_I_N 1.15V_VCCT_V_P 1.15V_VCCT_V_N 1.15V_VCCT_I_P 1.15V_VCCT_I_N 1.5V_VCCD_V_P 1.5V_VCCD_V_N 1.5V_VCCD_I_P 1.5V_VCCD_I_N SCL_PM SDA_PM PM3_ASEL0 PM3_ASEL1 PM_CNTL0 PM_CNTL1 PM_RSTn B 28 27 32 33 30 31 22 PM3_FAULTB00 PM3_FAULTB01 PM3_FAULTB10 PM3_FAULTB11 23 24 25 26 PM_SHARE_CLK 21 19 65 3.3V_PM_FPGA VIN_SNS VSENSEP0 VSENSEM0 VSENSEP1 VSENSEM1 VSENSEP2 VSENSEM2 VSENSEP3 VSENSEM3 VSENSEP4 VSENSEM4 VSENSEP5 VSENSEM5 VSENSEP6 VSENSEM6 VSENSEP7 VSENSEM7 SCL SDA ASEL0 ASEL1 CONTROL0 CONTROL1 WDI/RESET FAULTB00 FAULTB01 FAULTB10 FAULTB11 R219 10K R245 10K REFP REFM NC VDACP0 VDACM0 VDACP1 VDACM1 VDACP2 VDACM2 VDACP3 VDACM3 VDACP4 VDACM4 VDACP5 VDACM5 VDACP6 VDACM6 VDACP7 VDACM7 VOUT_EN0 VOUT_EN1 VOUT_EN2 VOUT_EN3 VOUT_EN4 VOUT_EN5 VOUT_EN6 VOUT_EN7 SHARE_CLK ALERTB PWRGD VPWR VDD25 WP E-PAD GND pad R228 R225 R224 10K 10K 10K VIN_EN LTC2977 VDD33_OUT VDD33_IN 12 1.15V_GXB_VDACP0 1.15V_VCCT_VDACP2 1.5V_VCCD_VCCH_VDACP4 C807 0.1uf 34 35 13 42 1.15V_GXB_VDACP0 42 1.15V_VCCT_VDACP2 42 1.5V_VCCD_VCCH_VDACP4 39 38 40 41 44 45 50 51 55 54 56 57 59 58 60 61 1.15V_GXB_VDACP0 SCL_PM SDA_PM 31,33 31,33 SCL_PM SDA_PM 1.15V_VCCT_VDACP2 PM_SHARE_CLK PM_CNTL0 PM_CNTL1 PM_RSTn 31,33 31,33 31,33 31,33 PM_SHARE_CLK PM_ALERTB PM_PWRGD 31,33 31,33 PM_ALERTB PM_PWRGD 4 5 6 7 8 9 10 11 1.15V_GXB_RUN 42 1.15V_VCCT_RUN 42 1.15V_VCCT_RUN 1.5V_VCCD_VCCH_RUN 42 1.5V_VCCD_VCCH_RUN 1.5V_VCCD_VCCH_VDACP4 29 20 15 18 PM_CNTL0 PM_CNTL1 PM_RSTn C 1.15V_GXB_RUN B PM_ALERTB PM_PWRGD 3.3V_PM_FPGA 16 17 C210 C209 C211 LTC2977 Address Select PWRMON2 = 7'h62 PM3_ASEL1 PM3_FAULTB00 PM3_FAULTB01 PM3_FAULTB10 PM3_FAULTB11 0.1uf 0.1uf 0.1uf PM3_ASEL1 PM3_ASEL0 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 32 of 1 45 C1 5 4 V33 1 3.3V_HPS_N RSNS SNS 1 RSNS SNS 1 2.5V_HPS_N RSNS SNS 3.3V_REG_HPS 2.5V_HPS 1 RSNS SNS 2.5V_REG_HPS 1 RSNS SNS 1 RSNS SNS 1 RSNS SNS 1 RSNS SNS 2 4 6 8 10 12 2 4 6 8 10 12 D SDA_PM SCL_PM PM_ALERTB 1.5V_REG_HPS 2 3.3V_PM_HPS 1.1V_HPS 2 SENSE_PAD V37 1.1V_HPS_P 1 3 5 7 9 11 2x6HDR 1.5V_HPS SENSE_PAD V36 1.1V_HPS_N J36 1 3 5 7 9 11 2 SENSE_PAD V34 1.5V_HPS_P PM_CNTL1 2 SENSE_PAD V35 1.5V_HPS_N I2C Interface 2 SENSE_PAD V44 2.5V_HPS_P 1 2 SENSE_PAD V43 D 2 HPS Power Monitor 3.3V_HPS 2 SENSE_PAD V32 3.3V_HPS_P 3 1.1V_REG_HPS R211 R212 R206 R203 10K 10K 10K 10K 2 R204 R205 R207 R208 R209 R210 R213 R214 10K 10K 10K 10K 10K 10K 10K 10K SENSE_PAD C C 12V B R196 R195 1K 1K C200 0.1uF C201 0.1uF R194 R191 1K 1K C192 0.1uF C197 0.1uF 1K 1K C185 0.1uF C191 0.1uF R177 R176 1K 1K C181 0.1uF C182 0.1uF R175 R174 1K 1K C179 0.1uF C180 0.1uF R173 R172 1K 1K C177 0.1uF C178 0.1uF R171 R170 R185 R189 1K 1K 1K 1K U50 14 R190 R186 SDA_PM SCL_PM PM_RSTn PM_PWRGD 1.1V_HPS_V_P 1.1V_HPS_V_N 1.1V_HPS_I_P 1.1V_HPS_I_N 1.5V_HPS_V_P 1.5V_HPS_V_N 1.5V_HPS_I_P 1.5V_HPS_I_N 2.5V_HPS_V_P 2.5V_HPS_V_N 2.5V_HPS_I_P 2.5V_HPS_I_N 3.3V_HPS_V_P 3.3V_HPS_V_N 3.3V_HPS_I_P 3.3V_HPS_I_N C175 0.1uF C176 0.1uF SCL_PM SDA_PM PM1_ASEL0 PM1_ASEL1 PM_CNTL0 PM_CNTL1 PM_RSTn C190 0.1uF C184 0.1uF these GND connections to each VSENSEMx pin needs to be placed close to a GND pin of the BGA! 36 37 42 43 46 47 48 49 52 53 62 63 64 1 2 3 28 27 32 33 30 31 22 PM1_FAULTB00 PM1_FAULTB01 PM1_FAULTB10 PM1_FAULTB11 23 24 25 26 PM_SHARE_CLK 21 19 65 VIN_SNS VIN_EN LTC2977 VSENSEP0 VSENSEM0 VSENSEP1 VSENSEM1 VSENSEP2 VSENSEM2 VSENSEP3 VSENSEM3 VSENSEP4 VSENSEM4 VSENSEP5 VSENSEM5 VSENSEP6 VSENSEM6 VSENSEP7 VSENSEM7 REFP REFM NC VDACP0 VDACM0 VDACP1 VDACM1 VDACP2 VDACM2 VDACP3 VDACM3 VDACP4 VDACM4 VDACP5 VDACM5 VDACP6 VDACM6 VDACP7 VDACM7 SCL SDA ASEL0 ASEL1 CONTROL0 CONTROL1 WDI/RESET VOUT_EN0 VOUT_EN1 VOUT_EN2 VOUT_EN3 VOUT_EN4 VOUT_EN5 VOUT_EN6 VOUT_EN7 FAULTB00 FAULTB01 FAULTB10 FAULTB11 SHARE_CLK ALERTB PWRGD VPWR VDD25 WP E-PAD GND pad VDD33_OUT VDD33_IN A 12 C783 0.1uf 34 35 13 39 38 40 41 44 45 50 51 55 54 56 57 59 58 60 61 1.1V_HPS_VDACP0 4 5 6 7 8 9 10 11 EN_1.1V_HPS 29 20 15 18 PM_ALERTB PM_PWRGD PM_SHARE_CLK PM_ALERTB PM1_FAULTB00 PM1_FAULTB01 PM1_FAULTB10 PM1_FAULTB11 PM_CNTL0 PM_CNTL1 1.5V_HPS_VDACP2 2.5_HPS_VDACP4 3.3_HPS_VDACP6 PM_SHARE_CLK PM_CNTL0 PM_CNTL1 PM_RSTn 31,32 31,32 31,32 31,32 PM_SHARE_CLK PM_CNTL0 PM_CNTL1 PM_RSTn PM_ALERTB PM_PWRGD 31,32 31,32 PM_ALERTB PM_PWRGD EN_1.1V_HPS EN_1.5V_HPS EN_2.5V_HPS EN_3.3V_HPS 41 39 38 40 EN_1.1V_HPS EN_1.5V_HPS EN_2.5V_HPS EN_3.3V_HPS 1.1V_HPS_VDACP0 1.5V_HPS_VDACP2 2.5_HPS_VDACP4 3.3_HPS_VDACP6 41 39 38 40 1.1V_HPS_VDACP0 1.5V_HPS_VDACP2 2.5_HPS_VDACP4 3.3_HPS_VDACP6 B EN_1.5V_HPS EN_2.5V_HPS EN_3.3V_HPS 3.3V_PM_HPS 16 17 A C196 C199 C204 SCL_PM 31,32 R624 0 I2C_SCL_HPS SCL_PM SDA_PM 31,32 R625 0 7,20,28 I2C_SDA_HPS LTC2977 Address Select PWRMON1 = 7'h5C SDA_PM 0.1uf 0.1uf 0.1uf Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title PM1_ASEL0 PM1_ASEL1 Size B 7,20,28 Date: 5 4 3 2 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 Rev (6XX-44209R) Sheet 1 33 of 45 C1 8 7 6 5 4 3 2 1 Power 1 - DC Input & 12V, 3.3V Output DC_INPUT U48 FDMC8878 J34 CONN JACK PWR 2 1 3 E 1 2 3 5 19V DC Input E 4 DC_IN U72 5 GATE IN 1 6 4 7 OUT VDD GND EP_GND NC LTC4357 D31 C198 C168 47uF 35V 47uF 35V C174 22uF 25V C189 22uF 25V DC_IN INTVCC_1 U47 FDMC8878 D45 CMDSH-3 U71 RJK0305DPB 5 3 2 C708 22uF 25V Q10 drain-tab BOOST1 4.7uF 38 37 14 2 1 3.3V_SHDNn 4 J33 1 2 COM COM +12V +12V 3 U70 3 2 4 5 ATX-POWER_4P GATE IN NC OUT VDD GND EP_GND 1 6 4 7 R583 20.0K 13 36 15 6 7 12V_SHDNn LTC4357 SW1 RUN1 ITEMP1 ILIM1 ITH1 TK/SS1 BG1 VFB1 RUN2 ITEMP2 ILIM2 ITH2 TK/SS2 SENSE1+ SENSE1PGOOD1 30 4 L25 C709 0.1uF 29 31 Q9 RJK0301DPB 4 27 2 3.3V 3 1.5uH V70 drain-tab 2 1 SNS RSNS SENSE_PAD 39 40 R584 3.09K R577 4.02K LTC3855_S1P LTC3855_S1N C723 16 V69 C208 C195 100uF 6.3v 0.1uF R578 DIFFOUT 11.5K TG2 BOOST2 SW2 gnd-pad 82pF 4 C753 22pF R552 57.6K BG2 VFB2 4 21 drain-tab C635 0.1uF 5 B GATE IN 1 6 4 7 OUT VDD GND EP_GND NC 22pF L21 2 19 RJK0301DPB 4 5 VFB2 1 V46 drain-tab 23 2 SNS RSNS SENSE_PAD R579 52.3K 3.3V DIFFOUT 12 10 11 SENSE2+ SENSE2- DIFFOUT DIFFP DIFFN PGOOD2 8 9 LTC3855_S2P LTC3855_S2N 12V_REG 0.68uH Q8 U60 3 2 RJK0305DPB 4 R543 C636 3.92K DNI R544 17 PG_12V 0.1uF 1 R561 V45 215.0K 2 C659 100pF SGND1 SGND2 PGND1 PGND2 NC 20 RSNS SNS C687 Q2 C R570 2.55K C656 22uF 25V 1 C724 Q7 drain-tab 4 41 28 22 18 5 RJK0305DPB 5 R581 169.0K R582 20.0K 5 1000pF DC_IN 1 2 3 1 2 3 12V_ATX 1000pF CMDSH-3 D44 1 2 3 Q6 FDMC8878 C658 5 12V C752 FREQ MODE/PLLIN PHSASMD CLKOUT 1 2 3 C 330uF 10V SENSE_PAD INTVCC_1 35 34 33 32 D 1 2 C657 TG1 RSNS SNS 5 INTVCC_1 PWR1_EXTVCC VIN INTVCC EXTVCC 1 12V_ATX 26 25 24 1 2 3 1 2 3 5 D 1 2 3 MMBD1205 C163 C173 C556 68uF 25V 68uF 25V 68uF 25V VFB2 R569 11.3K SENSE_PAD B LTC4357 Q5 FDMC8878 1 2 3 12V_REG LTC3855EUJ R548 100K 5 3.3V 5.0V 4 U58 3 2 5 A GATE IN NC OUT VDD GND EP_GND R676 1.00K 1 6 4 7 POWER LED LTC4357 D37 BLUE LED SW5 SW SLIDE-4P2T DC_IN DC_IN 100K R321 12V_SHDNn R320 20.0K 12V_ATX R309 100K 7 1 8 9 2 3 3.3V_SHDNn 10 4 12V_ATX 11 12 5 6 R323 100K R322 20.0K R314 Title 100K Size B Date: 8 7 6 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 34 of 1 45 C1 8 7 6 5 4 3 2 Power 2 1.15V FPGA CORE P02-11401R RESISTORS • RES,1.15K OHMS,1.0%,1/16W,0402 1.1V_VCC 1.15V_VCCP P02-14067R RESISTORS • RES - 665 OHMS 1.0% 1/16W 0402 E E L34 C395 3A, 30 Ohm FB 100uF 6.3V 12V 1.1V_FPGA_VDACP4 215.0K 31 R640 1.1V_FPGA_RUN 31 C824 22uF 25V 1210 VFB 0 R634 1 C784 22uF 25V 1210 Vout=1.15V 12V SW_VCCP 1.1V_REG U74 C806 0.1uF 2 3 21 5 4 6 7 8 VFB DIFF_O 1.1V_VCC DIFF_O ITH R641 C809 220pF R638 10K C808 1500pF C 1.1V_REG SNSAP 15K 1% VFB C803 0.22uF R639 16.2K 9 INTVCC R626 3.09K 25 665 R217 FREQ TK_SS ITH ITEMP INTVCC VFB DIFFOUT MODE_PLLIN DIFFP DIFFN SNSDP SNSM SNSAP ILIM EXTVCC BOOST TG SW BG C785 16 4.7uF P2_EXT BST C786 PGND Q4 V76 SENSE_PAD drain-tab 0.1uf 4 RJK0305DPB 14 13 12 10 2 D46 19 18 15 D C215 22uF 25V L27 2 SW_VCC V75 SENSE_PAD 1.1V_REG_VCC 1 0.22uH 744308033 Q3 1.1V_VCC R232 0.001 drain-tab RJK0301DPB CLKOUT SGND CMDSH-3 INTVCC RSNS SNS 22 24 1 17 20 1 R632 VIN PGOOD 2 137K A5_VCC_TRACK ITH 1% RUN RSNS SNS 23 5 LTC3866_1.1V_RUN 1 2 3 10.0K 5 R633 1 3.3V 4 C214 1 2 3 D 11 C225 C224 C223 C218 C219 100uF 6.3V C LTC3866 22uF 4V R218 1.15K 22uF 4V 22uF 4V 100uF 6.3V 470uF 6.3V SW_VCCP U9B B A5 A6 A7 B5 B6 B7 C5 C6 C7 D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 U9A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND F7 F6 F5 F4 F3 F2 F1 G1 G2 G3 G4 G6 H6 J5 J6 K5 K6 L7 G5 H5 12V J1 J2 J3 K1 K2 K3 L1 L2 L3 C326 10uF 25V VAR_FPGA_RUN L5 0 R414 31 3.3V R410 10.0K R412 40.2K G7 H7 L6 AUX BIAS VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 RUNN/SS RT SHARE SYNC J7 PGOOD VAR_VCCIO C330 10uF 25V C321 B C327 2.2uF 0.1uf 3.3V_SET R46 154K 2.5V_SET R45 226K XJ7 881545-2 1.8V_SET R56 82K 1.5V_SET R55 549K 1.2V_SET R44 953K R57 300K J6 1 3 5 7 9 K7 ADJ LTM8025 VAR_VCCIOP 0.003 R102 A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13 VOUT14 VOUT15 VOUT16 LTM8025 1 3 5 7 9 2 4 6 8 10 2 4 6 8 10 2x5Header 215.0K A 1.2V 1.5V 1.8V 2.5V 3.3V R411 31 953k P02-16417R 549k P02-14713R (0603) 383k P02-14133R + P02-15998R 226k P02-14130R 154k P02-15947R VAR_FPGA_VDACP6 Title Size B Date: 8 7 6 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 35 of 1 45 C1 8 7 6 5 4 3 2 1 Power 3 - 1.5V FPGA D28 E E LTC3605C_INTVCC C638 1.0UF C666 2.2uF CMDSH-3 LTC3605C_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 12V 1.5V_FPGA_RUN LTC3605C_SS 5 LTC3605C_INTVCC C193 3300pF R182 DNI 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 SW TRACK/SS SW EXPOSED PAD ITH SW 24.0K 1% 1200pF R183 C689 LTC3605C_ITH 6 33pF C171 22uF 25V 1210 C665 0.1UF 50V 18 16 C169 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller D 17 Design Note: Prefer 0603 size cap 25V rated voltage is sufficient LTC3605C_SW 1.5V_REG_FPGA L22 15 R197 1.2uH Isat = 11A 14 13 PGND C688 FB SW 4 C186 R188 39pF 15K 1% LTC3605C_FB C194 C727 C726 C728 22uF 22uF 22uF 22uF R572 1.5V_FPGA_VDACP2 215.0K 1.5V_FPGA 0.003 Cad Note: Place output caps near inductor 31 1.5V_FPGA_RUN 3.3V logic signal 31 R573 0 25 12 11 10 9 C 8 C LTC3605C_FB SW RUN CAD Note: Overlap R182 & R183 pads at 1 of the pins Place resistor & cap near pin 6 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us MODE 7 Design Note: Ith is tied to INTVCC for internal compensation 3 PVIN SW 169.0K R167 PHMODE PGND 2 PVIN VON D 10 R168 C616 0.1uF 25V RT PGOOD 1 LTC3605C_RT CLKOUT CLKIN 24 LTC3605C_SVIN U46 LTC3605EUF R187 10.0K LTC3605C_RUN 3.3V R574 10.0K 3.3V Design Note: DNI for ES device R571 100K PGOOD_FPGA_1.5V Cad Note: 1 overlapping pad B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 36 of 1 45 C1 8 7 6 5 4 3 2 1 Power 3 - 2.5V FPGA E E D30 LTC3605D_INTVCC C790 1.0UF C789 2.2uF CMDSH-3 LTC3605D_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 12V LTC3605D_SVIN R192 10 2.5V_FPGA_FILT 2.5V_FPGA_RUN 560pF 2.5V_FPGA_RUN 31 10pF R596 0 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 ITH SW 47.5K 1% R201 C787 LTC3605D_ITH 6 EXPOSED PAD C773 0.1UF 50V 18 17 16 C188 22uF 25V 1210 L24 3A, 30 Ohm FB Design Note: DCR = 40m ohms CAD Note: Regulator input caps Place near regulator controller D 2.5V_REG_FPGA Design Note: Prefer 0603 size cap 25V rated voltage is sufficient LTC3605D_SW 2.5V_FPGA R193 0.001 L23 15 1.2uH Isat = 11A 14 13 C202 R198 39pF 15K 1% C754 C772 C203 C725 22uF 22uF 22uF 22uF Cad Note: Place output caps near inductor C PGND C207 DNI SW 25 LTC3605D_INTVCC R200 TRACK/SS SW 5 12 LTC3605D_SS 3300pF SW SW C788 FB 11 4 SW PGND CAD Note: Overlap R200 & R201 pads at 1 of the pins Place resistor & cap near pin 6 LTC3605D_FB MODE RUN C Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us PVIN 7 Design Note: Ith is tied to INTVCC for internal compensation 3 PHMODE 10 1% PVIN VON 2 137K C755 0.1uF 25V RT 9 R199 1 PGOOD LTC3605D_RT 8 D CLKOUT CLKIN 24 2.5V_FPGA C187 22uF 25V 1210 LTC3605D_FB R589 215.0K 2.5V_FPGA_VDACP0 31 U52 LTC3605EUF R202 4.70K, 1% LTC3605D_RUN 3.3V R597 10.0K 3.3V Design Note: DNI for ES device R590 100K PGOOD_FPGA_2.5V Cad Note: 1 overlapping pad B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 37 of 1 45 C1 8 7 6 5 4 3 2 1 Power 3 - 2.5V HPS E E Cad Note: Place near INTVCC pin D29 LTC3605E_INTVCC C664 D 1.0UF CMDSH-3 D LTC3605E_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 C663 12V 2.2uF LTC3605E_SVIN R165 10 2.5V_HPS_FILT R180 560pF C661 LTC3605E_ITH 6 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 EXPOSED PAD ITH SW 47.5K 1% 10pF C637 0.1UF 50V 18 17 16 C164 22uF 25V 1210 3A, 30 Ohm FB CAD Note: Regulator input caps Place near regulator controller EN_2.5V_HPS 33 0 R554 Design Note: DCR = 40m ohms 2.5V_REG_HPS 2.5V_HPS R166 C 0.001 L20 15 1.2uH Isat = 11A 14 13 C170 R169 39pF 15K 1% C589 C172 C660 C614 22uF 22uF 22uF 22uF Cad Note: Place output caps near inductor LTC3605E_FB R553 U45 LTC3605EUF B EN_2.5V_HPS L19 Design Note: Prefer 0603 size cap 25V rated voltage is sufficient LTC3605E_SW PGND C183 DNI SW 25 LTC3605E_INTVCC R179 TRACK/SS SW 5 12 LTC3605E_SS 3300pF SW SW C662 FB 11 4 PGND LTC3605E_FB SW RUN CAD Note: Overlap R179 & R180 pads at 1 of the pins Place resistor & cap near pin 6 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us MODE 7 Design Note: Ith is tied to INTVCC for internal compensation 3 10 1% PVIN VON C PHMODE 9 2 PVIN PGOOD R178 137K C615 0.1uF 25V RT 8 1 LTC3605E_RT CLKOUT CLKIN 24 2.5V_HPS C165 22uF 25V 1210 178K 1% 2.5_HPS_VDACP4 33 B R181 4.70K, 1% RUN_2.5V_HPS 3.3V R555 10.0K 3.3V R549 100K PGOOD_HPS_2.5V A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 38 of 1 45 C1 8 7 6 5 4 3 2 1 Power 3 - 1.5V & 1.5V FPGA D27 E E LTC3605_INTVCC C470 1.0UF C471 2.2uF CMDSH-3 LTC3605_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 12V EN_1.5V_HPS 33pF EN_1.5V_HPS 33 R520 0 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 SW 7 C473 ITH C493 0.1UF 50V 18 16 C159 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller D 17 Design Note: Prefer 0603 size cap 25V rated voltage is sufficient LTC3605_SW 1.5V_REG_HPS L17 15 R159 1.2uH Isat = 11A 14 13 PGND 24.0K 1% 6 25 1200pF R153 LTC3605_ITH EXPOSED PAD SW DNI SW 12 LTC3605_INTVCC R154 TRACK/SS SW 5 SW 11 LTC3605_SS 3300pF FB PGND C472 SW 10 4 MODE VON LTC3605_FB C136 CAD Note: Overlap R153 & R154 pads at 1 of the pins Place resistor & cap near pin 6 C Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us PVIN RUN Design Note: Ith is tied to INTVCC for internal compensation 3 PHMODE 9 169.0K R155 PVIN PGOOD 2 C158 22uF 25V 1210 C510 0.1uF 25V RT 8 D CLKOUT 24 CLKIN 1 LTC3605_RT 10 R163 LTC3605_SVIN C149 R157 39pF 15K 1% C148 C511 C528 C494 22uF 22uF 22uF 22uF 1.5V_HPS 0.003 Cad Note: Place output caps near inductor LTC3605_FB R521 U40 LTC3605EUF 1.5V_HPS_VDACP2 215.0K C 33 R152 10.0K RUN_1.5V_HPS 3.3V R519 10.0K 3.3V R523 100K PGOOD__HPS_1.5V B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 39 of 1 45 C1 8 7 6 5 4 3 2 1 Power 3 - 3.3V HPS E E Cad Note: Place near INTVCC pin D25 LTC3605A_INTVCC C429 D 1.0UF CMDSH-3 C428 12V 2.2uF R144 220pF LTC3605A_ITH 6 19 SVIN 20 BOOST 21 INTVCC 22 SGND 23 EXPOSED PAD ITH SW 69.8K 1% 5pF 7 C426 DNI 10 C119 22uF 25V 1210 C415 0.1UF 50V 18 17 16 C118 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller EN_3.3V_HPS 33 R509 0 3.3V_HPS R138 C 0.001 L16 15 1.2uH Isat = 11A 14 C129 39pF 13 R137 11.5K C425 C131 C391 C399 22uF 22uF 22uF 22uF Cad Note: Place output caps near inductor 1% LTC3605A_FB R508 U33 LTC3605EUF B EN_3.3V_HPS 3.3V_REG_HPS Design Note: Prefer 0603 size cap 25V rated voltage is sufficient LTC3605A_SW PGND C137 CAD Note: Overlap R143 & R144 pads at 1 of the pins Place resistor & cap near pin 6 R143 SW 25 LTC3605A_INTVCC TRACK/SS SW 5 12 LTC3605A_SS 3300pF SW SW C427 FB 11 4 PGND LTC3605A_FB SW 10 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us MODE RUN Design Note: Ith is tied to INTVCC for internal compensation 3 PVIN VON 1% PHMODE 9 C PVIN PGOOD 2 90.9K R134 C400 0.1uF 25V RT 8 R142 1 CLKOUT CLKIN 24 LTC3605A_SVIN LTC3605A_RT D LTC3605A_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 66.5K 3.3_HPS_VDACP6 33 B R145 2.55K 1% RUN_3.3V_HPS 3.3V R510 10.0K 3.3V logic signal 3.3V R506 100K PGOOD_3.3V A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 40 of 1 45 C1 8 7 6 5 4 3 2 1 Power - 1.15V_HPS, 5.0V, 1.8V CAD Note: Regulator input caps Place near regulator controller D26 12V 1.15V_HPS_INTVCC C474 E 1.0UF CMDSH-3 C61 22uF 25V 1210 1.15V_HPS_BOOST Design Note: Added extra 1uF at INTVCC due to sourcing Vbias pin of LTC3025-1 C496 12V 2.2uF 1 1.15V_HPS_RT 19 10 R151 C147 22uF 25V 1210 C450 0.1uF 25V SVIN 20 BOOST 21 INTVCC 22 SGND 23 CLKIN CLKOUT 24 LTC3605B_SVIN RT PVIN PHMODE PVIN C495 0.1UF 50V 18 C324 22uF 25V 1210 C417 22uF 25V 1210 E C416 22uF 25V 1210 C135 22uF 25V 1210 CAD Note: Regulator input caps Place near regulator controller Design Note: 0.001 ohm sense resistor minimized IR drop @ 3A R156 25 C513 17 16 1.15V_HPS_SW EN_1.1V_HPS 33 0 R530 15 R164 D 0.001 1.2uH Isat = 11A 14 C155 39pF 13 R162 13.7K C557 C558 22uF 22uF Cad Note: C157 Place output caps 47UF near inductor 6.3V 1.15V_HPS_FB R535 U39 LTC3605EUF 215.0K 1.1V_HPS_VDACP0 33 C R160 RUN_1.15V_HPS 15K 1% 3.3V R534 1.1V_HPS L18 C EN_1.1V_HPS 1.1V_REG_HPS Design Note: Prefer 0603 size cap 25V rated voltage is sufficient PGND SW SW 10.0K ITH 12 R161 1.15V_HPS_ITH 6 EXPOSED PAD 7 68pF DNI SW SW C154 R158 TRACK/SS 11 1.0nF CAD Note: Overlap R158 & R161 pads at 1 of the pins Place resistor & cap near pin 6 5 SW PGND 1.15V_HPS_INTVCC 1.15V_HPS_SS FB 10 Design Note: Ith is tied to INTVCC for internal compensation 1000pF 4 RUN C512 1.15V_HPS_FB SW 8 Design Note: tss = Css x 0.6V/2uA Ramp rate ~990us MODE VON 3 9 D PGOOD 2 316k 1% 10.0K 3.3V R529 CAD Note: Regulator input caps Place near regulator controller 100K PGOOD_1.1V_HPS 12V B C76 25V 4 22uF 2 5.0V L32 1 C57 22uF 25V 2 6.5uH R80 Isat = 6A 52.3K C70 0.1uF D17 1 3 DFLS230 2 C58 R79 10K R81 VIN BD BOOST1 BOOST2 Fsw=1.7MHz SW1 SW2 B 12 6 5 C71 0.1uF L31 1 DNI 16.2K 11 10 DA1 DA2 FB1 FB2 RUN/SS1 RUN/SS2 SYNC RT GND DFLS230 D18 7 2 1 8 9 DNI C59 15 1V8 2 6.5uH Isat = 6A 1 14 13 FB_5.0V 5.0V U10 R77 12.4K C60 22uF 4V R82 10K LT3509EDE A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 41 of 1 45 C1 8 7 6 5 4 3 2 1 Power 4 - Linear Regulators 2.5V_REG_FPGA 1.5V_REG_HPS 1.5V_REG_FPGA R467 10.0K E C751 C782 10.0K VIN EN PGOOD VLDOIN REFIN VREF_HPS_DDR3 6 1uF REFOUT 0.1uF 10.0K R466 VO VOSNS 3 5 10uF C555 C613 C655 C722 R588 10.0K C771 10 7 9 10.0K VIN EN PGOOD 6 1uF C348 C554 10uF 10uF 10uF 10uF 0.1uF 2 1 10.0K R482 VTT_FPGA_DDR3A REFOUT TPS51200 10uF VLDOIN REFIN VREF_FPGA_DDR3A C347 1.0nF 10uF DDR3 FPGA VTT, VREF U68 R580 C770 11 4 8 C781 TPS51200 2 1 VTT_HPS_DDR3 GND_PAD PGND GND R605 10 7 9 3.3V GND_PAD PGND GND 10uF DDR3 HPS VTT, VREF U73 R478 10.0K C359 VO VOSNS 3 5 11 4 8 3.3V E C367 10uF C430 C392 C387 C368 C451 10uF 10uF 10uF 10uF 10uF C358 1.0nF D D 1.5V_REG_FPGA C475 10uF DDR3 HPS VTT, VREF U69 6 REFOUT C514 C R522 0.1uF R516 10.0K C476 3 5 VO VOSNS 10uF 11 4 8 TPS51200 1.15V_GXB 3.3V 10.0K VTT_FPGA_DDR3B C477 VREF_FPGA_DDR3B 1uF 2 1 VLDOIN REFIN C667 C729 C617 C559 C756 10uF 10uF 10uF 10uF 10uF C452 1.0nF C 5.0V U53 1 2 C213 4 10uF 1.15V_GXB_RUN OUT2 OUT1 SW SHDN 0 R222 32 BST 3 11 B IN1 IN2 GND GND 6 ADJ PG C217 1uF 8 7 1.15V_GXBP R216 VCCGXB 1 2 1.15V_GXB 0.003 C88 4 45.3K 1% 10uF 6 R215 R223 24.0K 1% LTC3026 1.15V_VCCT_RUN C205 22uF C206 0 R121 32 2.2uF 10.0K IN1 IN2 BST OUT2 OUT1 SW SHDN 1.5V VCCD VCCH 3.3V C100 5.0V C78 4 10uF 6 IN1 IN2 BST OUT2 OUT1 SW SHDN GND GND 1 2 3 11 0 R109 1.5V_VCCD_VCCH_RUN ADJ PG LTC3026 5 C85 1uF 10 9 8 7 1.5V_VCCD_VCCHP 1.5V_VCCD_VCCH 0.003 R106 VCCDH 1uF 1.15V_VCCT 10 9 8 7 1.15V_VCCTP R128 VCCT 45.3K 1% R123 R122 24.0K 1% LTC3026 B C89 22uF C101 2.2uF VCCGXB 215.0K R635 32 1.15V_GXB_VDACP0 VCCT 215.0K R477 32 1.15V_VCCT_VDACP2 VCCDH 215.0K R457 32 1.5V_VCCD_VCCH_VDACP4 13.7K R105 R110 4.99K 3.3V C75 22uF Title 10.0K Size B Date: 8 7 6 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 C69 2.2uF R456 0.003 10.0K U14 32 ADJ PG 5 3.3V R468 A 5.0V U22 10 9 3.3V R227 1.15V_VCCT 3.3V 5 GND GND 10.0K VIN EN PGOOD GND_PAD PGND GND R524 10 7 9 3 11 3.3V 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 42 of 1 45 C1 8 7 6 5 4 3 2 Power 7 - Arria V ST Power U41L U41J 2.5V_FPGA_FILT U41K 2.5V_FPGA Arria V SX (SoC) Power 1.1V_VCC E D AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA24 AA26 AB11 AB17 U18 V17 V22 V23 V29 W18 W20 W22 W24 W26 W28 Y11 Y15 Y17 Y19 Y21 Y23 Y25 Y29 1.5V_VCCD_VCCH R33 VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCCPD3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPD4A VCCPD4A VCCPD4BCD VCCPD4BCD VCCPD4BCD VCCPD4BCD VCCPD4BCD VCCPD7FG VCCPD8 VCCPD8 VCCPD8 VCCPD8 VCCPD8 VCCPD8 VCCPGM VCCPGM VCCBAT VCC_AUX_SHARED C AB20 AD31 AE9 T31 V19 W30 W9 AH29 AJ30 AK35 AM30 AP35 AT35 AJ31 VREF_FPGA_DDR3A AC10 AE10 AK28 AL27 AN28 AT28 AL28 AB12 AB13 AB16 AB18 AB19 2.5V_FPGA U21 AU5 AR5 AN5 AL5 AJ5 AG10 AH7 R32 T30 U22 U24 U26 U29 VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL 2.5V_HPS_FILT 2.5V_VCCAUX_SHARED 2.5V_FPGA_FILT 3A, 30 Ohm FB B35 G31 G33 K31 K33 P33 H33 E28 E30 H30 K28 R31 5ASTFD5K3_F1517 2.5V_HPS AT10 AR12 AN13 AN10 AM12 AK13 AN11 VAR_VCCIO U15 AA9 AB21 AC30 AC9 V20 V31 Y30 VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3A VREFB3AN0 VCCIO3C VCCIO3C VCCIO3C VCCIO3C VCCIO3C VCCIO3C VREFB3CN0 VCCIO3B VCCIO3B VCCIO3B VCCIO3B VREFB3BN0 VCCIO3D VCCIO3D VCCIO3D VCCIO3D VCCIO3D VCCIO3D VREFB3DN0 VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4A VREFB4AN0 VCCIO4C VCCIO4C VCCIO4C VCCIO4C VREFB4CN0 1.5V_FPGA AG29 J19 AB14 AB26 U28 AF33 AB33 V33 AE7 AA7 1.5V_FPGA AA27 AA28 AA29 AB22 AB23 AB24 AB30 VREF_FPGA_DDR3B VCC_AUX VCC_AUX VCC_AUX 1.5V_FPGA Arria V SX (SoC) Power 2.5V_VCCAUX_SHARED L36 VCCIO4D VCCIO4D VCCIO4D VCCIO4D VCCIO4D VCCIO4D VREFB4DN0 VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4B VCCIO4B VREFB4BN0 VCCIO7G VREFB7GN0 VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8A VREFB8AN0 VCCIO8C VCCIO8C VCCIO8C VCCIO8C VCCIO8C VCCIO8C VREFB8CN0 VCCIO8B VCCIO8B VCCIO8B VCCIO8B VREFB8BN0 VCCIO8D VCCIO8D VCCIO8D VCCIO8D VCCIO8D VCCIO8D VREFB8DN0 AU25 AR24 AP25 AM24 AL25 AJ24 AK26 1.5V_VCCD_VCCH AJ15 AM15 AR15 AV15 AG15 1.15V_GXB AA34 AB35 AC35 AE34 AF35 U34 W34 AA5 AB5 AB6 V5 V6 Y6 1.5V_FPGA VREF_FPGA_DDR3B AJ19 AK18 AM19 AN18 AR19 AT18 AF18 VAR_VCCIO K19 P19 C25 D27 F25 G27 J25 M24 L25 C21 D22 F21 G22 K22 M21 H22 AD33 Y33 T33 AC7 W7 VREF_FPGA_DDR3A 2.5V_FPGA AU21 AR22 AP21 AM22 AL21 AJ22 AJ21 1 1.15V_VCCP AA21 AA25 AB15 U10 U16 V25 V27 W10 Y27 Arria V SX (SoC) Transceiver Power VCCA_GXBL0 VCCL_GXBL0 VCCA_GXBL1 VCCA_GXBL2 VCCA_GXBR0 VCCA_GXBR1 VCCL_GXBL0 VCCL_GXBL1 VCCL_GXBL1 VCCL_GXBL2 VCCL_GXBL2 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBR1 VCCL_GXBR1 VCCH_GXBL0 VCCH_GXBL1 VCCH_GXBL2 VCCH_GXBR0 VCCH_GXBR1 VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBL VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCR_GXBR VCCT_GXBL0 VCCT_GXBL0 VCCT_GXBL1 VCCT_GXBL1 VCCT_GXBL2 VCCT_GXBL2 VCCT_GXBR0 VCCT_GXBR0 VCCT_GXBR1 VCCT_GXBR1 1.15V_GXB AD34 AD35 Y34 Y35 T34 T35 AC5 AC6 W5 W6 E 1.15V_VCCT AG34 AG35 V35 W35 AC34 R35 AD6 AE5 AF5 AF6 D VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP 5ASTFD5K3_F1517 U41T Arria V SX (SoC) HPS Power 1.1V_HPS 2.5V_HPS T8 T6 T10 L9 5ASTFD5K3_F1517 R12 3.3V_HPS T14 R16 T17 B R18 VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS U8 2.5V_HPS L10 J10 U12 V11 V12 V13 V15 W12 W14 Y13 VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VCCIO6A_HPS VREFB6AN0_HPS VCCPD6A6B_HPS VCCPD6A6B_HPS VCCPD6A6B_HPS VCCPD6A6B_HPS VCCPD7A_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VCCIO6B_HPS VREFB6BN0_HPS VCCPD7B_HPS VCCPD7C_HPS VCCPD7D_HPS VCCPD7E_HPS 2.5V_HPS_FILT 1.1V_HPS C 1.5V_HPS T13 U14 U9 V10 V16 VCCPLL_HPS VCCRSTCLK_HPS VCCRSTCLK_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCC_HPS VCCIO7A_HPS VCCIO7A_HPS VCCIO7A_HPS VCCIO7A_HPS VCCIO7B_HPS VCCIO7B_HPS VCCIO7C_HPS VCCIO7D_HPS VCCIO7D_HPS VCCIO7E_HPS VREFB7A7B7C7D7EN0_HPS A10 C5 C8 F6 F8 J6 K8 M8 P9 P10 VREF_HPS_DDR3 1.5V_HPS B3 D4 G3 J3 L3 N2 N5 M4 B 3.3V_HPS B13 E10 G12 K13 E14 J15 D17 B18 G17 J20 P18 5ASTFD5K3_F1517 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 43 of 1 45 C1 8 7 6 5 4 3 2 1 Power 8 - Arria V ST Ground E U41H U41I Arria V SX (SoC) GND A12 AA11 AA13 AA15 AA17 AA19 AA23 AA3 AA30 AA33 AA35 AA38 AA39 AA4 AA6 AA8 AB1 AB10 AB2 AB31 AB32 AB34 AB36 AB37 AB7 AC11 AC14 AC17 AC20 AC23 AC26 AC28 AC3 AC33 AC38 AC39 AC4 AC8 AD1 AD10 AD2 AD30 AD32 AD36 AD37 AD5 AD7 AE3 AE30 AE33 AE35 AE38 AE39 AE4 AE6 AE8 AF1 AF11 AF14 AF17 AF2 D C B GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Arria V SX (SoC) GND AF20 AF23 AF26 AF29 AF30 AF31 AF32 AF34 AF36 AF37 AF9 AG3 AG31 AG38 AG39 AG4 AG5 AG6 AG7 AG8 AG9 AH1 AH2 AH32 AH33 AH34 AH35 AH36 AH37 AH5 AJ11 AJ14 AJ17 AJ20 AJ23 AJ26 AJ29 AJ3 AJ32 AJ35 AJ38 AJ39 AJ4 AJ8 AK1 AK2 AK36 AK37 AK5 AL3 AL35 AL38 AL39 AL4 AM1 AM11 AM14 AM17 AM2 AM20 AM23 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 5ASTFD5K3_F1517 AM26 AM29 AM32 AM36 AM37 AM5 AM8 AN3 AN35 AN38 AN39 AN4 AP1 AP2 AP36 AP37 AP5 AR11 AR14 AR17 AR20 AR23 AR26 AR29 AR3 AR32 AR35 AR38 AR39 AR4 AR8 AT1 AT2 AT36 AT37 AT5 AU3 AU35 AU38 AU39 AU4 AV1 AV11 AV14 AV17 AV2 AV20 AV23 AV26 AV29 AV32 AV35 AV36 AV37 AV38 AV39 AV5 AV8 AW35 AW38 B11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND E U41S Arria V SX (SoC) GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND B16 B2 B20 B23 B26 B29 B32 B36 B37 B5 B8 C11 C35 C38 C39 D36 D37 E11 E17 E2 E20 E23 E26 E29 E32 E35 E38 E39 E5 E8 F14 F36 F37 G35 G38 G39 H11 H17 H2 H20 H23 H26 H29 H32 H36 H37 H5 H8 J14 J35 J38 J39 K20 K36 K37 L11 L17 L2 L23 L26 L29 L32 L35 L38 L39 L5 L8 M11 M36 M37 N14 N17 N20 N3 N35 N38 N39 N4 P1 P11 P2 P23 P26 P29 P32 P35 P36 P37 P5 P8 R3 R34 R38 R39 R4 R5 T1 T12 T15 T16 T18 T2 T20 T32 T36 T37 T5 T9 U11 U13 U17 U23 U25 U27 U3 U30 U33 U35 A38 AE20 AH31 AV3 5ASTFD5K3_F1517 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 U38 U39 U4 U5 U6 U7 V1 V14 V18 V2 V21 V24 V26 V28 V30 V32 V34 V36 V37 V7 V8 V9 W11 W13 W15 W16 W17 W19 W21 W23 W25 W27 W29 W3 W33 W38 W39 W4 W8 Y1 Y10 Y12 Y14 Y16 Y18 Y2 Y20 Y22 Y24 Y26 Y28 Y31 Y32 Y36 Y37 Y5 Y7 D C B AW3 B12 B38 F20 5ASTFD5K3_F1517 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 44 of 1 45 C1 8 7 6 5 4 3 2 1 Decoupling 1.15V_vcc 1.1V_VCC 1.15V_VCCP 2.5V_fpga 2.5V_FPGA 1.15V_vccp C497 E C596 100uF 6.3V C763 100uF 6.3V 100uF 6.3V C668 C459 C419 100uF 6.3V C394 100uF 100uF 6.3V 6.3V C775 100uF 6.3V C765 C764 100uF 6.3V C393 C711 100uF 6.3V C498 100uF 6.3V C507 C534 2.2uF 100uF 6.3V 0.47uF C646 C522 C607 C604 0.22uF 0.1uF 47nF 47nF C669 4.7uF C736 D C406 C396 2.2uF C412 C695 C732 1uF C413 C411 1uF C409 0.47uF C714 C414 0.47uF C731 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF C735 C739 C734 C737 C738 C408 C410 0.1uF 0.1uF 100uF 6.3V 1.5V_FPGA 100uF 6.3V C733 C563 C460 4.7uF 100uF 6.3V 0.47uF C696 C575 C502 C601 0.22uF 0.1uF 47nF 0.22uF C436 C603 C480 C621 C622 C501 47nF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF C713 0.22uF C481 C600 0.1uF 22nF C602 4.7nF C517 0.1uF C421 C407 C422 C432 C434 C435 C564 0.1uF 0.1uF 0.1uF 0.1uF 4.7nF 4.7nF 4.7nF C479 C499 C500 C461 C433 C462 C671 47nF 47nF 47nF 47nF 47nF 47nF 47nF C670 47nF 47nF 47nF 47nF 47nF 4.7nF 4.7nF C641 C484 C485 C568 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 4.7nF C540 C697 C469 C624 C483 C482 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 100uF 6.3V C505 C521 C519 C542 C543 C566 C567 C580 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF C746 C706 C650 C649 4.7uF 4.7nF 0.1uF 0.01uF 3.3V_HPS 2.5V_VCCAUX_SHARED 3.3v_HPS C582 C645 C576 C577 C503 C506 C520 C579 C578 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF C561 C581 C535 C574 C536 C623 C644 C515 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF 22nF C599 C516 C541 C562 C573 C598 22nF 22nF 22nF 22nF 22nF 22nF C674 C463 C676 10uF 22nF 22nF 47nF 0.01uF C633 100uF 6.3V 1.5V_hps C547 C609 2.2uF 22nF C608 1uF C618 C518 4.7uF 47nF 1.1V_HPS 4.7uF 1.5V_HPS C678 0.47uF C716 1.15V_VCCT 330uF 2.5V A 4.7uF C675 C704 C702 0.1uF 47nF C465 C441 C705 C446 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF C445 C444 C440 C439 C464 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 47nF C 100uF 6.3V 0.47uF C631 C606 C605 0.1uF 47nF 47nF 0.1uF 0.01uF C626 C627 C648 C632 C628 C647 C630 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 22nF C672 C768 C742 0.22uF 0.22uF 0.22uF C741 C398 C743 C642 C525 C524 C569 10uF 2.2uF 47nF 10uF 47nF 4.7nF 0.47uF C700 C447 C701 C437 C438 C443 0.01uF 0.01uF 4.7nF 4.7nF 4.7nF 22nF SCREW2 STANDOFF1 SCREW4 STANDOFF2 SPACER1 SCREW5 STANDOFF3 SPACER2 SCREW1 SCREW6 SCREW7 SCREW8 STANDOFF4 STANDOFF5 STANDOFF6 VAR_VCCIO 47nF 100uF 6.3V C679 0.47uF C629 C703 C767 0.22uF 100uF 6.3V C680 C707 1.15V_GXB C442 1uF C715 B 1.5V_VCCD_VCCH C744 C747 1.15V_hps C681 C583 C625 C468 2.5V_HPS_FILT 47nF C504 C740 2.5V_HPS_FILT 100uF 6.3V C776 E 2.5V_fpga_filt 2.5V_FPGA_FILT 4.7nF C620 C B 47nF D 2.5V_HPS C745 47nF 47nF C538 2.5V_hps C544 0.1uF C643 C397 C639 C539 22nF 0.1uF C640 C565 C508 0.1uF C478 0.47uF 0.22uF C699 C537 0.47uF 0.1uF C619 C698 C766 C420 C597 4.7uF 100uF 6.3V 1.5V_vccio 100uF 6.3V C570 C712 C545 C546 C523 22nF 22nF 22nF SCREW3 PCB1 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 C466 C467 C673 C677 4.7nF 4.7nF 22nF 22nF Title Size B Date: 8 7 6 5 4 3 Arria V SoC FPGA Development Kit Board Copyright (c) 2013, Altera Corporation. All Rights Reserved. Document Number 150-0320807-C1 Thursday, December 12, 2013 2 Rev (6XX-44209R) Sheet 45 of 1 45 C1