DEMO MANUAL DC1974 LTC2123, LTC2122 14-Bit, 250Msps to 170Msps Dual ADCs with JESD204B Outputs DESCRIPTION Demonstration circuit 1974 supports the LTC®2123 14-bit dual ADC family with JESD204B compliant CML outputs. It was specially designed for applications that require single-ended AC coupled inputs. The DC1974 supports the LTC2123 and LTC2122 with sample rates from 250Msps to 170Msps. Refer to the data sheet for proper input networks for different input frequencies. Design files for this circuit board are available at http://www.linear.com/demo/DC1974 L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. The specific ADC characteristics are listed in the DC1974 Variants section. The circuitry on the analog inputs is optimized for analog input frequencies from 5MHz to 400MHz. DC1974 VARIANTS DC1974 VARIANTS ADC PART NUMBER RESOLUTION (Bit) MAXIMUM SAMPLE RATE (Msps) INPUT FREQUENCY (MHz) 1974A-B LTC2123 14 250 5 to 400 1974A-C LTC2122 14 170 5 to 400 PERFORMANCE SUMMARY Specifications are at TA = 25°C PARAMETER CONDITION ADC Supply Voltage This Supply Must Provide Up to 700mA Analog Input Range MIN TYP MAX UNIT 4 6 1.35 1.5 VPP 250 MHz 3.6 V Sampling Frequency (Device Clock Frequency) Depending on ADC (1X CLK Mode) 10 Device Clock Level (Single-Ended at J3) Minimum Logic Levels (DEVCLK+ Tied to GND) 0 V Maximum Logic Levels (DEVCLK+ Tied to GND) Device Clock Level (Differential Signal Across J3 and J4) Minimum Logic Levels (DEVCLK+ Not Tied to GND, 1.2V Common Mode) 0.2 Digital Inputs (ADC_SYS_REF_N, ADC_SYS_REF_P, SYNC_N, SYNC_P) Differential Input Voltage 0.2 Common Mode Input Range 1.1 V V 1.2 1.8 V 1.5 V dc1974fa 1 DEMO MANUAL DC1974 QUICK START PROCEDURE Demonstration circuit 1974 is easy to set up to evaluate the performance of the LTC2123 A/D converter family. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below: SETUP The DC1974 evaluation system uses standard, off the shelf FPGA evaluation boards for data capture and communication with the host computer. Follow the instructions in Appendix A for the Xilinx KC705 based system. Verilog code may be downloaded from the respective ADC landing page. www.linear.com/LTC2123 OPTIONAL FPGA REFERENCE CLOCK INPUT 4V TO 6V OPTIONAL FPGA REFERENCE SIGNAL INPUT THE DC1974 CONNECTS TO KC705 VIA AN FMC CONNECTOR CHANNEL 1 SINGLE-ENDED ANALOG INPUT CHANNEL 2 SINGLE-ENDED ANALOG INPUT dc1974 F01 JUMPERS SHOWN IN THEIR DEFAULT POSITIONS SINGLE-ENDED DEVICE CLOCK INPUT OPTIONAL SYS_REF INPUT FOR ADC (SUB CLASS 1 ONLY) OPTIONAL SYS_REF INPUT FOR FPGA (SUB CLASS 1 ONLY) Figure 1. DC1974 Setup dc1974fa 2 DEMO MANUAL DC1974 HARDWARE SETUP SMAs TURRETS J1: AINA – Analog input for channel A – Apply a signal to J1 from a 50Ω driver. Filters are required for data sheet performance. V+: Positive supply voltage for the ADC and digital logic – This voltage feeds a regulator that supplies the proper voltages for the ADC and buffers. The voltage range for this turret is 4V to 6V. The supply should be able to deliver 700mA of current. J2: AINB – Analog input for channel B – Apply a signal to J2 from a 50Ω driver. Filters are required for data sheet performance. J3: DEVCLK– – Encode clock input for single-ended clocks – By default the DC1974 is defined to accept a single-ended clock signal on J3. It can be modified to accept a differential clock signal through J3 and J4. Some component changes are required, see the encode clock section for more information. J4: DEVCLK+ – Encode clock input for differential signals – By default the DC1974 is defined to accept a single-ended clock signal on J3. It can be modified to accept a differential clock signal through J3 and J4. Some component changes are required, see the encode clock section for more information. J5 and J6: ADC_SYS_REF – JESD204B Subclass 1 only – When testing the ADC in subclass 1 operation a SYS_REF input is required to synchronize the ADC and FPGA. Apply a SYS_REF signal to this input from a SYS_REF driver board. This input drives the SYS_REF of the ADC. J11 and J12: FPGA_SYS_REF – JESD204B Subclass 1 only – When testing the ADC in subclass 1 operation a SYS_REF input is required to synchronize the ADC and FPGA. Apply a SYS_REF signal to this input from a SYS_REF driver board. This input drives the SYS_REF of the FPGA. J7 and J8: FPGA_GBT_REF – This is an optional reference port for the FPGA. It is used for testing purposes only. In the default configuration these SMAs are not used. SENSE: Optional reference voltage – This pin is connected directly to the SENSE pin of the ADC. Connecting SENSE to VDD selects the internal reference and a ±0.66V input range. The same input voltage range can be achieved by applying an external 1.25V reference to SENSE. If no external voltage is supplied this pin will be pulled up to VDD through a 1k pull-up resistor. 1.8V OUT: Optional 1.8V turret – This pin is connected directly to the VDD pin of the ADC. It requires a supply that can deliver up to 500mA. Driving this pin will shutdown the on board regulator. It can also be a test point to measure the voltage at the output of the regulators. GND: Ground Connection – This demo board only has a single ground plane. This turret should be tied to the GND terminal of the power supply being used. JUMPERS: JP1 EEPROM: EEPROM write protect. For factory use only. Should be left in the enable (PROG) position. JP2 SYNC: This jumper is provided to manually force the SYNC~ signal of the ADC to a known value. By default, the resistors connecting this jumper are removed. If R20 and R21 are installed the SYNC jumper can be used to force SYNC~ high or low depending on the position of the jumper. Position 0 is for low and 1 is for high. J9 and J10: FPGA_CLK – This is an optional clock input port for the FPGA. It is used for testing purposes only. In the default configuration these SMAs are not used. dc1974fa 3 DEMO MANUAL DC1974 APPLYING POWER AND SIGNALS TO THE DC1974 DEMONSTRATION CIRCUIT If a Kintex 7 FPGA board is used to acquire data from the DC1974, the Kintex 7 FPGA board must FIRST be powered BEFORE applying 4V to 6V across the pins marked “V+” and “GND” on the DC1974. For more information about the Kintex 7 board, please see the demo manual at www.xilinx.com. The DC1974 requires at least 4V for proper operation. Regulators on the board produce the voltages required for the ADC and the required logic devices. The DC1974 requires up to 700mA. The DC1974 should not be removed or connected to the Kintex 7 FPGA board while power is applied. The DC2159 should also be connected to the Kintex 7 board and the supplied mini USB cable should be connected to the DC2159. The Kintex 7 board should be powered on BEFORE the mini USB connector is connected to the DC2159. See Figure 5 in Appendix A. ANALOG INPUT NETWORK Apply the analog input signal of interest to the SMA connector on the DC1974 board marked J1 or J2. In the default setup, the DC1974 has a single SMA input that is meant to be driven with a 50Ω source. The DC1974 is populated with an input network that has 50Ω characteristic impedance over a wide frequency range. This can be modified to produce different frequency responses as needed. Although the input of the DC1974 is single-ended, there is a transformer on the board that translates the single-ended signal to a differential signal to drive the ADC. In almost all cases, off board filters with good return loss will be required on the analog input of the DC1974 to produce data sheet SNR. The off board filter should be located close to the input of the demo board to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50Ω outside the passband. In some cases, 3dB to 10dB pads may be required to make the filter look more like 50Ω to obtain low distortion. ENCODE CLOCK Apply an encode clock to the SMA connector on the DC1974 marked J3. By default, the DC1974 is configured to have a single-ended clock input. Although the clock input of the DC1974 is single-ended, there is a transformer on the board that translates the single-ended signal to a differential signal to drive the ADC. For the best noise performance, the encode input must be driven with a very low jitter signal generator source. The amplitude should be as large as possible up to 2VP-P or 10dBm. The DC1974 is designed to accept single-ended signals by default. To modify the DC1974 to accept a differential signal, remove C33, R44, R45 and R46. Populate R49, R43, R48 and R47 with 0Ω resistors. Drive the demo board with a differential signal on J3 and J4. These SMAs are positioned 0.5" apart to accommodate LTC differential clock boards. dc1974fa 4 DEMO MANUAL DC1974 SOFTWARE The DC1974 is controlled by the PScope™ System Software provided or downloaded from the Linear Technology website at http://www.linear.com/software/. If a Kintex 7 FPGA board and DC2159 were provided, follow the demo manual of these boards for proper setup. Manual Configuration settings: The Kintex 7 FPGA board will act as the data collection board and the DC2159 is used to connect the FPGA to the computer. These boards both are designed to work seamlessly with PScope, Linear Technology’s data collection software. Bipolar: Unchecked To start the data collection software and if “PScope.exe” is installed (by default) at \Program Files\LTC\PScope\, double click the PScope icon or bring up the run window under the start menu and browse to the PScope directory and select PScope. If the DC1974 is properly connected to the Kintex 7 FPGA board and the DC2159, PScope should automatically detect the DC1974 and configure itself accordingly. If necessary the procedure below explains how to manually configure PScope. Under the “Configure” menu, go to “ADC Configuration...” Check the “Config Manually” box and use the following configuration options, shown in Figure 2: Bits: 14 Alignment: 16 Channs: 2 Positive-Edge Clk: Unchecked If everything is hooked up properly, powered and a suitable encode clock is present, clicking the “Collect” button should result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the KC705 guide and in the online help available within the PScope program itself. NOTE: If a PRBS error occurs hit connect again. This is a bug in the first version of the software. SERIAL PROGRAMMING PScope has the ability to program the DC1974 board serially through the DC2159. There are several options available for the LTC2123 family that are only available through serial programming. PScope allows all of these features to be tested. These options are available by first clicking on the “Set Demo Bd Options” icon on the PScope toolbar (Figure 3). This will bring up the menu shown in Figure 4. Figure 3: PScope Toolbar Figure 2: ADC Configuration dc1974fa 5 DEMO MANUAL DC1974 SOFTWARE Nap Mode – Selects between normal operation and nap mode. n Off (Default) – Entire ADC is powered and active. n On – The entire ADC is put into nap mode. Channel B Power Down – Selects between normal operation and powering down channel B. Off (Default) – Normal operation. n On – Channel B is powered down. n Channel A Power Down – Selects between normal operation and powering down channel B. Off (Default) – Normal operation. n On – Channel A is powered down. n 2x Clock – Selects between a sample rate equal to the device clock, or device clock twice the sample rate. Off (Default) – DEVCLK is equal to the sample rate. n On – DEVCLK is twice the sample rate. n Overflow – Enables or disables the overflow bit in the output data. Disabled (Default) – Over flow bit is disabled. n Enabled – Overflow bit is enabled. n Duty Cycle Stabilizer – Enables or disables Duty Cycle Stabilizer. Stabilizer off (Default) – Duty Cycle Stabilizer Disabled. n Stabilizer on – Duty Cycle Stabilizer Enabled. n Figure 4: Demo Bd Configuration Options This menu allows any of the options available for the LTC2123 to be programmed serially. The LTC2123 family has the following options: Sleep Mode – Selects between normal operation and sleep mode. Off (Default) – Entire ADC is powered and active. n On – The entire ADC is powered down. n Device ID – Sets the device ID defined in JESD204B 8.3. Default is 00000000, but can be set to whatever the user chooses. Bank ID – Sets the bank ID defined in JESD204B 8.3. Default is 0000, but can be set to whatever the user chooses. Frames per MultiFrame – Selects number of frames in each multiframe as defined in JESD204B 5.3.3.5. The user selects the number of desired frames per multiframe and PScope configures the ADC accordingly. Valid values for number of frames per multiframe are 9 to 32. dc1974fa 6 DEMO MANUAL DC1974 SOFTWARE Lane Alignment Sequence – Enables or disables the lane alignment sequence. Enabled (Default) – Lane alignment sequence is enabled. n Disabled - Lane alignment sequence is disabled. n Lane Alignment Monitor – Enables or disables the lane monitor sequence. Enabled (Default) – Lane alignment monitor sequence is enabled. n Disabled – Lane alignment monitor sequence is disabled. n Frame Alignment Monitor – Enables or disables the Frame monitor sequence Enabled (Default) – Frame alignment monitor sequence is enabled. n Disabled – Frame alignment monitor sequence is disabled. n Reset Dividers (Subclass 1 or 2 Only) – Enables or disables SYSREF reset of dividers. Enabled (Default) – Subclass 1 – Enables the SYSREF reset of dividers. Subclass 2 – Enables SYNC~ reset of dividers. n Disabled – Subclass 1 – Disables the SYSREF reset of dividers. Subclass 2 – Disables SYNC~ reset of dividers. n Scrambling – Enables or disables the scrambling of the output data. Disabled (Default) – Scrambling is disabled. n Enabled – Scrambling is enabled. n Alert Mode De-arm Length (Subclass 1 Only) – Selects the de-arming length in multiframe periods to trigger the alert in subclass 1. Valid values are 1 to 8. Alert Mode (Subclass 1 Only) – Enables or disables the alert mode. TX Sync – Enables or disables Transmitter induced synchronization. Disabled (Default) – Transmitter induced synchronization is disabled. n Enabled - Transmitter induced synchronization is enabled. n Test Pattern – Selects the data presented at the output of the ADC Normal ADC Data (Default) – The data that is sampled by the input of the ADC K28.5 Pattern – A repeating SYNC comma. K28.7 Pattern – 1111100000. D21.5 Pattern – 1010101010. PRBS15 Pattern – A Pseudorandom bit sequence pattern described by 1 + x14 + x15. Lane Alignment Sequence – The lane alignment sequence is transmitted according to tables 3a to 3h from the datasheet. Test Samples Sequence – The test samples are repeatedly transmitted according to tables 4a to 4b from the datasheet. Modified RPAT Pattern – A modified RPAT pattern as described in IEEE Std. 802.3-2008 Annex 48A. CML Output Magnitude – Magnitude of the CML output signals. Value selections are: 10mA (250mV) Default 12mA (300mV) 14mA (350mV) 16mA (400mV) Once the desired settings are selected hit OK and PScope will automatically update the register of the device on the DC1974 demo board. Disabled (Default) – Alert mode is disabled. n Enabled – Alert mode is enabled. n dc1974fa 7 DEMO MANUAL DC1974 APPENDIX A XILINX KC705 BASED EVALUATION SYSTEM The demonstration system for the LTC2123 family consists of the DC1974, a Xilinx KC705 FPGA evaluation board, a DC2159 USB communication board and a host PC running the PScope software. Complete systems that ship from Linear Technology will have the KC705 board configured to automatically load the default subclass 0 FPGA image from the onboard configuration EEPROM. The procedure for bringing up the system is as follows: 1)If the boards were obtained separately, assemble them as shown in Figure 5 (FMC connectors are fragile, make sure they are properly aligned before seating.) 2)Connect power supply to the KC705 board and turn on the power switch. If the assembled system was obtained from Linear Technology, the subclass 0 image will load automatically from the onboard configuration memory. 3)Boards not obtained from Linear Technology will need to be configured as described in the Alternate FPGA Configuration section. 4)Apply power, encode clock and analog input signals to the DC1974 board. 5)Verify that PScope software is installed. Connect DC2159 to the host PC with a USB-mini cable. Driver installation will start automatically and PScope will recognize the DC1974 when installation finishes. NOTE: Power must be applied to the KC705 board when the USB cable is connected or the driver installation will not complete properly. ALTERNATE FPGA CONFIGURATION KC705 boards not obtained from Linear Technology will need to be configured via JTAG. FPGA images are located in the PScope installation directory in the FPGA_images folder. Connect a USB micro cable to the JTAG USB connector on the KC705 board and use a Xilinx tool such as Impact to load the Subclass 0, 2 lane bitfile. Once the FPGA is configured, remove the USB cable and exit the software. (The onboard JTAG adapter and the DC2159 USB communication board use the same USB controller and they may interfere with one another.) dc1974fa 8 DEMO MANUAL DC1974 APPENDIX A 5. CONNECT DC2159 TO PC 4. POWER-UP DC1974, TURN ON CLOCK AND ANALOG INPUTS 1. ASSEMBLE BOARDS 2. POWER-UP KC705 3. CONFIGURE FPGA VIA JTAG (IF NECESSARY), THEN REMOVE USB CABLE dc1974 F05 Figure 5. KC705 Based Demonstration System dc1974fa 9 DEMO MANUAL DC1974 PARTS LIST ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART # Required Circuit Components 1 2 C1, C2 CAP., X5R, 1µF, 10V, 10%, 0402 AVX, 0402ZD105KAT2A 2 1 C3 CAP., TANT, 100µF, 10V, 10%, 6032 AVX, TAJW107K010RNJ 3 1 C4 CAP., X7R, 47µF,10V, 10%, 1210 MURATA, GRM32ER71A476KE15L 4 4 C5, C11, C25, C26 CAP., X5R, 2.2µF, 10V, 20%, 0603 AVX, 0603ZD225MAT2A 5 7 C6, C33-C35, C50-C52 CAP., X7R, 0.01µF, 16V, 10%, 0402 AVX, 0402YC103KAT2A 6 1 C7 CAP., X5R, 10µF, 6.3V, 20%, 0805 AVX, 08056D106MAT2A 7 22 C10, C12-C24, C27-C32, C41, C53 CAP., X5R, 0.1µF, 10V, 10%, 0402 AVX, 0402ZD104KAT2A 8 4 C37, C38, C39, C40 CAP., C0G, 47pF, 16V, 10%, 0402 AVX, 0402YA470KAT2A 9 8 C42-C49 CAP., X7R, 1000pF, 50V, 10%, 0402 AVX, 04025C102KAT2A 10 4 E1, E2, E3, E4 TESTPOINT, TURRET, 0.094" MILL-MAX, 2501-2-00-80-00-00-07-0 11 2 JP1, JP2 HEADER, HD1X3-079 SULLINS, NRPN031PAEN-RC 12 10 J1-J6, J9-J12 CONN., SMA 50Ω, EDGE-LAUNCH EF JOHNSON, 142-0701-851 13 0 J7, J8 (OPT) CONN., SMA 50Ω, EDGE-LAUNCH EF JOHNSON, 142-0701-851 14 1 J13 CONN., BGA 40X10 SAMTEC, SEAM-40-02.0-S-10-2-A-K-TR 15 1 L1 RES., CHIP, 0Ω, 1206 VISHAY, CRCW12060000Z0EA 16 1 L2 IND., FERRITE BEAD, 33Ω, 1206 MURATA, BLM31PG330SN1L 17 0 L3 RES., 1206 OPT 18 2 R1,R59 RES., CHIP, 3.01k, 1/16W, 1%, 0402 VISHAY, CRCW04023K01FKED 19 1 R2 RES., CHIP, 10k, 1/16W, 1%, 0402 VISHAY, CRCW040210K0FKED 20 1 R4 RES., CHIP, 182k, 1/16W, 1%, 0402 VISHAY, CRCW0402182KFKED 21 4 R5, R24, R25, R58 RES., CHIP, 1k, 1/16W, 1%, 0402 NIC, NRC04F1001TRF 22 10 R6-R11, R32-R35 RES., CHIP, 24.9Ω, 1/16W, 1%, 0402 VISHAY, CRCW040224R9FKED 23 11 R12, R13, R15, R16, R18, R39, R40, R44, R45, R46, R57 RES., CHIP, 0Ω, 1/16W, 0402 NIC, NRC04Z0TRF 24 5 R14, R17, R41, R56, R61 RES., CHIP, 100Ω, 1/16W, 1%, 0402 NIC, NRC04F1000TRF 25 0 R19-R23, R42, R43, R48-R53, R54, R55, R60 RES., 0402 OPT 26 2 R26, R29 RES., CHIP, 20Ω, 1/16W, 1%, 0402 NIC, NRC04F20R0TRF 27 2 R27, R28 RES., CHIP, 49.9Ω, 1/16W, 1%, 0402 VISHAY, CRCW040249R9FKED 28 2 R30, R31 RES., CHIP, 300Ω, 1/16W, 1%, 0402 NIC, NRC04F3000TRF 29 3 R36, R37,R38 RES., CHIP, 4.99k, 1/16W, 1%, 0402 VISHAY, CRCW04024K99FKED 30 5 R47, R62,R63,R64,R65 RES., CHIP, 4.99Ω, 1/16W, 1%, 0402 NIC, NRC04F4R99TRF 31 2 R66, R67 RES., CHIP, 100Ω, 1/20W, 1%, 0201 NIC, NRC02F1000TRF 32 3 T1, T2, T3 XFMR., MABA-007159-000000 M/A-COM, MABA-007159-000000 33 1 U2 I.C., LT3080EDD#PBF, DFN 3X3 LINEAR TECH., LT3080EDD#PBF 34 1 U3 I.C., LT1763CDE-3.3#PBF, DFN12DE-4X3 LINEAR TECH., LT1763CDE-3.3#PBF 35 1 U6 I.C. EEPROM 32KBIT 400KHz, TSSOP8 MICROCHIP, 24LC32A-I/ST dc1974fa 10 DEMO MANUAL DC1974 PARTS LIST ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART # 36 1 U7 I.C., NC7WZ14P6X, SC70-6 FAIRCHILD SEMI., NC7WZ14P6X 37 1 U9 I.C., LTC6957IDD-2#PBF, DFN12DD-3X3 LINEAR TECH., LTC6957IDD-2#PBF 38 1 SHUNTS FOR JP1 & JP2 SHUNT, 0.079" CENTER SAMTEC, 2SN-BK-G 39 0 MH1, MH2 SCREW, M3 THREAD, #4-40x5/8" KEYSTONE, 29316 (DO NOT INSTALL) 40 0 MH1, MH2 STAND-OFF, ALUM., M3 THREAD, 5.0 HEX, #4-40X1" KEYSTONE, 24438 (DO NOT INSTALL) 41 2 STENCILS STENCILS (TOP & BOTTOM) STENCIL DC1974A-3 DC1974A-B Required Circuit Components 1 1 DC1974A GENERAL BOM 2 1 U1 I.C., 14-BIT, 250Msps, QFN48UK-7X7 LINEAR TECH., LTC2123IUK#PBF DC1974A-C Required Circuit Components 1 1 DC1974A GENERAL BOM 2 1 U1 I.C., 14-BIT, 170Msps, QFN48UK-7X7 LINEAR TECH., LTC2122IUK#PBF dc1974fa 11 A B C D SMA J4 SMA J3 SMA J2 SMA J1 E3 E2 C34 0.01uF C33 0.01uF C28 0.1uF C27 0.1uF C23 0.1uF R43 OPT R44 0 C1 1uF C22 0.1uF R49 OPT C4 47uF 1210 V+ 6 VCTRL NC IN T2 2 3 1 4 2 T3 2 3 3 MABA-007159-000000 1 5 4 MABA-007159-000000 5 1 4 5 T1 5 MABA-007159-000000 C2 1uF LT3080EDD 7 8 IN SET OUT OUT OUT EP 4 3 2 1 9 5 1. ALL RESISTORS ARE IN OHMS, 0402. ALL CAPACITORS ARE IN MICROFARADS, 0402. 2. INSTALL SHUNTS AS SHOWN. 3. R18 IS OPTIONAL AT THE FINAL VERSION. E4 C35 0.01uF C29 0.1uF C24 0.1uF R22 OPT R19 OPT R11 45.3 R10 45.3 R7 45.3 R6 45.3 C10 0.1uF R4 182K 4 R47 4.99 R46 0 R45 0 R48 OPT R65 4.99 R64 4.99 R63 4.99 R62 4.99 * C5 + 2.2uF 0603 R67 100 0201 R66 100 0201 C3 100uF 10V 6032 L3 OPT ASSY -B -C R53 OPT R52 OPT R13 0 R42 OPT CLK- CLK+ AINBAINB+ -Bit 14 14 VDD VDD AINA- 12 3 VDD VDD GND 7 8 VCM 9 GND 10 AINB11 AINB+ VREF 5 6 SENSE Msps 250 170 VCM 8 SHDN IN NC 1 4 NC 9 NC 12 NC BYP SENSE OUT OUT LT1763CDE-3.3 10 11 IN 2 3 GND 4 AINA+ 1 C11 2.2uF 0603 R5 1k R2 10k VDD V+ SENSE VDD 0603 C25 2.2uF AINA+ AINA- U1 LTC2123IUK-14 LTC2122IUK-14 VDD C26 2.2uF 0603 1206 R12 0 R50 OPT C53 0.1uF R51 OPT 1206 OVDD L2 33 Ohm FB 1206 R9 24.9 R8 24.9 R1 3.01k VDD L1 0 Ohm RES GND E1 NOTES: UNLESS OTHERWISE SPECIFIED DEVCLK+ DEVCLK- AINB AINA SENSE V+ 4V - 6V GND U3 R18 0 [3] 6 5 2 3 * QFN48UK-7X7 U1 GND 7 EP 13 13 14 VDD 15 GND 16 DEVCLK17 DEVCLK+ 3 SYSREF_N 49 48 47 GND VDD GND 46 45 44 43 CS SCK SDI SDO R29 20 R26 20 18 19 SYSREF_P 4 GND 20 1.8V OUT R28 49.9 R27 49.9 +3.3V OVDD OVDD C31 0.1uF C32 0.1uF R17 100 R14 100 1 2 3 4 5 6 R16 0 R15 0 R21 OPT R20 OPT C13 0.1uF VDD FILTA V+ IN+ INGND FILTB SD1 OUT1+ OUT1OUT2OUT2+ SD2 VDD C17 0.1uF R61 100 2 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NONE C19 0.1uF GND DATE: N/A SIZE J6 J5 J9 ADC_SYS_REF_P FPGA_CLK_N 1 SHEET 1 OF 2 DUAL 14-BIT HIGH SPEED ADC WITH JESD204B SERIAL OUTPUTS REV. LTC212XIUK FAMILY 3 DEMO CIRCUIT 1974A FPGA_CLK_P FPGA_CLK_N 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only SMA DATE 02-25-15 ADC_SYS_REF_N FPGA_CLK_P J10 SMA SMA TECHNOLOGY R23 OPT R54 OPT SYNC_P APPROVED CLARENCE M. CML* CONNECTIONS ARE 50 OHMS SMA SYNC 0 1 JP2 SYNC_N 3 2 1 CMLB1_P CMLB1_N CMLB2_P CMLB2_N CMLA2_P CMLA2_N CMLA1_P CMLA1_N C21 0.1uF OF+ OF- CS SCK SDI SDO Wednesday, February 25, 2015 IC NO. TITLE: SCHEMATIC R40 0 R39 0 2 3 5 4 1 REVISION HISTORY DESCRIPTION PRODUCTION VDD C20 0.1uF OVDD 3 REV 1 VCC NC7WZ14P6X U7 C42 - C49 1000pF C18 0.1uF __ ECO 6 R41 100 R60 OPT APPROVALS R56 100 R55 OPT +3.3V 0.1uF C30 C16 0.1uF +3.3V C15 0.1uF 12 11 10 9 8 7 R25 1k R24 1k C14 0.1uF LTC6957IDD-2 U9 C12 0.1uF CUSTOMER NOTICE C51 0.01uF C50 0.01uF 26 25 30 29 28 27 34 33 32 31 36 35 VDD 2 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. CLARENCE M. APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. R31 300 C52 0.01uF R30 300 VDD OVDD OVDD CMLB1_P CMLB1_N CMLB2_P CMLB2_N CMLA2_P CMLA2_N CMLA1_P CMLA1_N OVDD OVDD C7 10uF 0805 VDD C6 0.01uF +3.3V VDD 42 41 40 39 21 22 SYNC_P VDD VDD 38 37 SYNC_N OFN+ OFNDNC DNC 23 24 VDD U2 EP 12 13 5 A B C D DEMO MANUAL DC1974 SCHEMATIC DIAGRAM dc1974fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B C D GND HA01_P_CC HA01_N_CC GND GND HA05_P HA05_N GND HA09_P HA09_N GND HA13_P HA13_N GND HA16_P HA16_N GND HA20_P HA20_N GND HB03_P HB03_N GND HB05_P HB05_N GND HB09_P HB09_N GND HB13_P HB13_N GND HB21_P HB21_N GND HB20_P HB20_N GND VADJ GND SEAM-10X40PIN J13E SEAM-10X40PIN GND DP1_M2C_P DP1_M2C_N GND GND DP2_M2C_P DP2_M2C_N GND GND DP3_M2C_P DP3_M2C_N GND GND DP4_M2C_P DP4_M2C_N GND GND DP5_M2C_P DP5_M2C_N GND GND DP1_C2M_P DP1_C2M_N GND GND DP2_C2M_P DP2_C2M_N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 5 CMLB2_P CMLB2_N CMLB1_P CMLB1_N CMLA2_P CMLA2_N PG_M2C GND GND HA00_P_CC HA00_N_CC GND HA04_P HA04_N GND HA08_P HA08_N GND HA12_P HA12_N GND HA15_P HA15_N GND HA19_P HA19_N GND HB02_P HB02_N GND HB04_P HB04_N GND HB08_P HB08_N GND HB12_P HB12_N GND HB16_P HB16_N GND HB19_P HB19_N GND VADJ SEAM-10X40PIN J13F F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 SEAM-10X40PIN RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND DP6_M2C_P DP6_M2C_N GND GND GBTCLK1_M2C_P GBTCLK1_M2C_N GND GND DP9_C2M_P DP9_C2M_N GND GND DP8_C2M_P DP8_C2M_N GND GND DP7_C2M_P DP7_C2M_N GND GND DP6_C2M_P DP6_C2M_N GND GND RES0 J13B VDD B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 SMA SMA J8 J7 GND CLK1_C2M_P CLK1_C2M_N GND GND HA03_P HA03_N GND HA07_P HA07_N GND HA11_P HA11_N GND HA14_P HA14_N GND HA18_P HA18_N GND HA22_P HA22_N GND HB01_P HB01_N GND PB07_P HB07_N GND HB11_P HB11_N GND HB15_P HB15_N GND HB18_P HB18_N GND VIO_B_M2C GND 4 SEAM-10X40PIN J13J FPGA_GBT_REF_N OPT FPGA_GBT_REF_P OPT GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 SEAM-10X40PIN J13C C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 SEAM-10X40PIN VREF_B_M2C GND GND CLK1_M2C_P CLK1_M2C_N GND HA02_P HA02_N GND HA06_P HA06_N GND HA10_P HA10_N GND HA17_P_CC HA17_N_CC GND HA21_P HA21_N GND HA23_P HA23_N GND HB00_P_CC HB00_N_CC GND HB06_P_CC HB06_N_CC GND HB10_P HB10_N GND HB14_P HB14_N GND HB17_P_CC HB17_N_CC GND VIO_B_M2C J13K SCL SDA SDI_FMC SCK_FMC CS_FMC SDO_FMC CMLA1_P CMLA1_N 3 WP PROG K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 R38 4.99K R35 24.9 R34 24.9 R33 24.9 R32 24.9 JP1 1 2 3 SMA R37 4.99K C40 47pF C39 47pF C38 47pF C37 47pF 6 5 7 3 2 1 R36 4.99K SDO SCK SDI GND SCL SDA WP A2 A1 A0 R59 3.01k R58 1k +3.3V CS FPGA_SYS_REF_N J12 FPGA_SYS_REF_P J11 SMA EEPROM 3 ARRAY C41 0.1uF SCK SDI SDO CS EEPROM 4 8 VCC GND D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 R57 0 FPGA_CLK_P FPGA_CLK_N CUSTOMER NOTICE U6 24LC32A 3P3VAUX SEAM-10X40PIN PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_N GA1 3P3V GND 3P3V GND 3P3V J13D 2 APPROVALS 2 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NONE G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 DATE: N/A SIZE H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 1 SHEET 2 OF 2 DUAL 14-BIT HIGH SPEED ADC WITH JESD204B SERIAL OUTPUTS REV. LTC212XIUK FAMILY 3 DEMO CIRCUIT 1974A LTC Confidential-For Customer Use Only 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com SEAM-10X40PIN VREF_A_M2C PRSNT_M2C_N GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ TECHNOLOGY Fax: (408)434-0507 OF+ OF- SYNC_P SYNC_N 1 J13H Wednesday, February 25, 2015 IC NO. TITLE: SCHEMATIC SEAM-10X40PIN GND CLK0_C2M_P CLK0_C2M_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND J13G LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. CLARENCE M. APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. 4 J13A 5 A B C D DEMO MANUAL DC1974 SCHEMATIC DIAGRAM dc1974fa 13 DEMO MANUAL DC1974 DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright © 2004, Linear Technology Corporation dc1974fa 14 Linear Technology Corporation LT 0315 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2014