DK-DEV-3CLS200N Dev Kit Schematic

8
7
6
5
4
NOTES:
E
3
REV
1. Project Drawing Numbers:
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic Drawing
PCB Film
Bill of Materials
Schematic Design Files
Functional Specification
PCB Layout Guidelines
Assembly Rework
A-1
B-1
100-0320911-B1
110-0320911-B1
120-0320911-B1
130-0320911-B1
140-0320911-B1
150-0320911-B1
160-0320911-B1
170-0320911-B1
180-0320911-B1
210-0320911-B1
220-0320911-B1
320-0320911-B1
2
DATE
PAGES
07/24/2009
09/10/2009
ALL
8,10,18,20
1
DESCRIPTION
INITIAL
Add CRC_ERROR push-button. Connect the CRC_ERROR_LED through MAX II
rather than direct to FPGA. DNI LVDS termination resistors on HSMC's.
E
2. 690 Parts, 58 Library Parts, 768 Nets, 3895 Pins
PAGE
D
Cyclone III LS F780 Development Kit Host
Block Diagram
C
B
DESCRIPTION
1
Title, Notes, Block Diagram, Revision History
2
C3 LS FPGA Package Top
3
Cyclone III LS Bank 1 & 2
4
Cyclone III LS Bank 3 & 4
5
Cyclone III LS Bank 5 & 6
6
Cyclone III LS Bank 7 & 8
7
Cyclone III LS Config, JTAG
8
Cyclone III LS Clocks
9
Clock Circuitry
10
EPM2210 System Controller
11
SRAM & FLASH
12
USB 2.0
13
10/100/1000 Ethernet (Port 0)
14
10/100/1000 Ethernet (Port 1)
15
DDR2 SDRAM
16
DDR2 SDRAM POWER & TERM
17
HSM Connectors
18
HSM Termination
19
User IO Cyclone III LS
20
User IO EPM2210
21
Power 1
22
Power 2
23
Power Monitor
24
Cyclone III LS Power
25
Decoupling
D
C
B
26
27
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Digital Ground
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
1
B-1
of
1
25
8
7
6
E
4
3
2
1
Cyclone III LS FPGA Package Top
Notes:
1.
5
FPGA Schematic Symbol Breakdown:
(A) Bank 1 - HSMB
(B) Bank 2 - HSMB, EEPROM, FLASH
(C) Bank 3 - FSM_A, FSM_D, ETHERNET, FLASH, SSRAM, MAX IO
(D) Bank 4 - CLOCK OUT, FSM_A, FSM_D, ETHERNET, FLASH, SSRAM, HSMA_CLKIN_P1/N1
(E) Bank 5 - HSMA
(F) Bank 6 - HSMA, MAX IO, ETHERNET
(G) Bank 7 - DDR2 SDRAM, USER LED, USER PB, HSMA_CLKIN0
(H) Bank 8 - DDR2 SDRAM, USER DIPSW, USER LED, HSMB_CLKIN0
(I) VCCINT
(J) VCCIO, VREF, VCCA, VCCD_PLL
(K) Ground, NC
(L) Clocks
(M) Configuration
BANK 8
BANK 7
VCCIO = 1.8V
VCCIO = 1.8V
DDR2 SDRAM, USER DIPSW,
USER LED, HSMB_CLKIN0
E
DDR2 SDRAM, USER LED,
USER PB, HSMA_CLKIN0
D
D
BANK 1
VCCIO = 2.5V
BANK 6
HSMB
VCCIO = 2.5V
HSMA, MAX IO,
ETHERNET
C
C
BANK 2
VCCIO = 2.5V
BANK 5
HSMB, EEPROM, FLASH
VCCIO = 2.5V
HSMA
B
B
BANK 3
BANK 4
VCCIO = 2.5V
VCCIO = 2.5V
FSM_A, FSM_D, ETHERNET,
FLASH, SSRAM, MAX IO
A
CLOCK OUT, FSM_A, FSM_D, ETHERNET,
FLASH, SSRAM, HSMA_CLKIN_P1/N1
Title
Size
B
Date:
8
7
6
5
4
3
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
2
B-1
of
1
25
8
7
6
5
4
3
2
1
Cyclone III LS Bank 1 & 2
E
E
HSMB SIGNALS
HSMB_D[75:0]
HSMB_D[75:0]
LCD_HSMB_D[75:65]
17,19,24
LCD_HSMB_D[75:65]
HSMB_CLKOUT_P2
HSMB_CLKOUT_N2
19,24
HSMB_CLKOUT_P2 17
HSMB_CLKOUT_N2 17
HSMB_CLKOUT0
HSMB_CLKOUT0 17
HSMB_SDA
HSMB_SDA 17
FLASH/LCD SIGNALS
U15A
D
U15B
Cyclone III LS, Bank 1
EP3CLS200
HSMB_D12
HSMB_D14
HSMB_D4
HSMB_D6
HSMB_D29
HSMB_D19
HSMB_D18
HSMB_D20
J7
J6
L5
L4
H3
K3
H2
H1
DQ0L0/DIFFIO_L10p
DQ0L1/DIFFIO_L10n
DQ0L2/DIFFIO_L11p
DQ0L3/DIFFIO_L11n
DQ0L4/DIFFIO_L12n
DQ0L5/DIFFIO_L13n
DQ0L6/DIFFIO_L16p
DQ0L7/DIFFIO_L16n
HSMB_D2
HSMB_D24
M4
G3
DM0L/DIFFIO_L17n
DQS0L/DIFFIO_L12p
HSMB_D21
HSMB_D0
K2
M5
DIFFIO_L13p
DIFFIO_L17p
DQ2L0/DIFFIO_L1p
DQ2L1/DIFFIO_L2p
DQ2L2/DIFFIO_L2n
DQ2L3/DIFFIO_L4n
DQ2L4/DIFFIO_L5p
DQ2L5
DQ2L6/DIFFIO_L6n
DQ2L7/DIFFIO_L7p
H6
F5
F4
D1
G5
E2
E3
E1
HSMB_D16
HSMB_D34
HSMB_D30
HSMB_D35
HSMB_SDA
HSMB_D38
HSMB_D31
HSMB_D36
DM2L/DIFFIO_L9p
DQS2L/DIFFIO_L4p
G2
C1
HSMB_D28
HSMB_D39
G6
HSMB_D22
p/n matches from the above DQ groups
C
DIFFIO_L1n
DIFFIO_L5n in CONFIG block
DIFFIO_L6p
DIFFIO_L7n
DIFFIO_L9n
HSMB_D8
K5
DIFFIO_L8p in CONFIG block
DIFFIO_L8n
HSMB_D37
HSMB_CLKOUT0
HSMB_D11
HSMB_D13
D3
D2
P4
P3
DIFFIO_L3p
DIFFIO_L3n
DIFFIO_L18p
DIFFIO_L18n
FLASH_RDYBSYn
E4
F1
G1
DIFFIO_L14p
DIFFIO_L14n
DIFFIO_L15p
DIFFIO_L15n
J2
J1
M6
N6
IOB1_0
IOB1_1
IOB1_2
J4
L1
P1
HSMB_D33
HSMB_D32
HSMB_D26
HSMB_D27
HSMB_D25
HSMB_D17
HSMB_D15
LCD_HSMB_D67
LCD_HSMB_D71
LCD_HSMB_D65
EP3CLS200F780
EP3CLS200
T3
T4
U4
T6
T5
U1
V4
W3
W1
DQ1L0/DIFFIO_L19p
DQ1L1/DIFFIO_L19n
DQ1L2
DQ1L3/DIFFIO_L20p
DQ1L4/DIFFIO_L20n
DQ1L5/DIFFIO_L21p
DQ1L6/DIFFIO_L22p
DQ1L7/DIFFIO_L22n
DQ1L8
DQ3L0/DIFFIO_L27p
DQ3L1/DIFFIO_L27n
DQ3L2/DIFFIO_L29n
DQ3L3/DIFFIO_L30p
DQ3L4/DIFFIO_L30n
DQ3L5/DIFFIO_L32p
DQ3L6/DIFFIO_L32n
DQ3L7/DIFFIO_L33p
DQ3L8/DIFFIO_L33n
AB1
AC1
AB2
AD2
AD1
AE2
AE1
W7
V6
HSMB_D54
HSMB_D1
Y2
W5
DM1L/DIFFIO_L23p
DQS1L/DIFFIO_L26p
DM3L/DIFFIO_L36n
DQS3L/DIFFIO_L35p
AA5
AA4
ENET_1_TX_EN
HSMB_D56
LCD_HSMB_D73
V1
Y1
W4
DIFFIO_L21n
DIFFIO_L23n
DIFFIO_L26n
DIFFIO_L29p
DIFFIO_L35n
DIFFIO_L36p
AB3
AA3
AA6
U3
U2
AA2
AA1
Y3
W2
DIFFIO_L24p
DIFFIO_L24n
DIFFIO_L25p
DIFFIO_L25n
DIFFIO_L28p
DIFFIO_L28n
DIFFIO_L31p
DIFFIO_L31n
DIFFIO_L34p
DIFFIO_L34n
AB4
AC4
AD4
AE3
IOB2_0
IOB2_1
IOB2_2
IOB2_3
AB6
AD3
AE4
AF1
LCD_HSMB_D74
HSMB_D58
p/n matches from the above DQ groups
W6
Y6
10,11
Cyclone III LS, Bank 2
ENET_1_TXD0
ENET_1_TXD1
ENET_1_TXD2
HSMB_CLKOUT_P2
HSMB_CLKOUT_N2
ENET_1_TXD3
FLASH_RDYBSYn
HSMB_D64
HSMB_D60
HSMB_D7
HSMB_D5
HSMB_D48
HSMB_D50
HSMB_D61
HSMB_D62
FLASH_RDYBSYn
RUP1
RDN1
HSMB_D51
HSMB_D49
HSMB_D44
LCD_HSMB_D70
HSMB_D45
HSMB_D41
LCD_HSMB_D68
LCD_HSMB_D75
HSMB_D3
D
EEPROM SIGNALS
EEPROM_SCL
EEPROM_SCL 19
HSMB_D59
HSMB_D63
HSMB_D55
EEPROM_SCL
HSMB_D52
ETHERNET INTERFACE (Cyclone III)
ENET_1_TXD[3..0]
HSMB_D46
HSMB_D42
HSMB_D47
HSMB_D40
C
ENET_1_TXD[3..0] 14
ENET_1_TX_EN
ENET_1_TX_EN 14
HSMB_D57
HSMB_D43
LCD_HSMB_D66
LCD_HSMB_D69
EP3CLS200F780
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
3
B-1
of
1
25
8
7
6
5
4
3
2
Cyclone III LS Bank 3 & 4
EEPROM SIGNALS
EEPROM_SDA
MAX2_BEn[3:0]
HSMA_D[3:0]
MAX2_BEn[3:0] 10
MAX2_OEn
MAX2_WEn
EEPROM_SDA 19
HSMC PORT A
MAXII CONTROL INTERFACE
E
1
E
HSMA_D[3:0] 7,8,17
ANTI-TAMPER INTERFACE
MAX2_OEn 10
MAX2_WEn 10
CRC_LATCH_SIG
HEARTBEAT
SECURITY
CRC_LATCH_SIG
HEARTBEAT 10
SECURITY 10
10
ETHERNET INTERFACE
ENET_TXD[3..0]
ENET_GTX_CLK
ENET_TX_EN
ENET_MDC
D
C
B
EP3CLS200
AH3
AH4
AG2
AH2
AF6
AD7
AE7
AF5
DQ1B1/DIFFIO_B7p
DQ1B0/DIFFIO_B7n
DQ1B3/DIFFIO_B5p
DQ1B2/DIFFIO_B5n
DQ1B4
DQ1B6/DIFFIO_B4p
DQ1B5/DIFFIO_B4n
DQ1B7/DIFFIO_B3n
FSM_D14
FSM_A19
AD6
AE6
DM1B/DIFFIO_B2n
DQS1B
SRAM_BWEn
FSM_D24
FSM_A25
FSM_D6
FSM_A0
FLASH_CLK
FSM_D21
FSM_D28
FLASH_RESETn
AH8
AG9
AE9
AF9
AG6
AH6
AB10
AG5
AH5
MAX2_OEn
HEARTBEAT
AC10
AH7
ENET_TXD3
FSM_D3
FSM_D0
AC6
AE5
AH9
DQ5B0/DIFFIO_B23p
DQ5B2/DIFFIO_B22p
DQ5B1/DIFFIO_B22n
DQ5B3/DIFFIO_B21n
DQ5B5/DIFFIO_B20p
DQ5B4/DIFFIO_B20n
DQ5B6/DIFFIO_B19p
DQ5B7/DIFFIO_B18p
DQ5B8/DIFFIO_B17n
AF13
AD14
AE14
AD12
AG12
AH12
AB14
AH10
AC12
ENET_RXD0
FSM_A1
ENET_TXD0
ENET_TXD1
SECURITY
ENET_MDC
ENET_RXD1
SRAM_CEn
SRAM_BWn0
DM5B/DIFFIO_B17p
DQS5B/DIFFIO_B18n
AB13
AH11
SRAM_OEn
SRAM_BWn1
DQ3B1/DIFFIO_B15n
DQ3B0/DIFFIO_B16p
DQ3B3/DIFFIO_B14p
DQ3B2/DIFFIO_B14n
DQ3B5/DIFFIO_B12p
DQ3B4/DIFFIO_B12n
DQ3B6/DIFFIO_B10p
DQ3B8/DIFFIO_B9p
DQ3B7/DIFFIO_B9n
DM3B/DIFFIO_B10n
DQS3B/DIFFIO_B15p
p/n matches from the above DQ groups
MAX2_BEn1
FSM_A24
ENET_RXD3
SRAM_ZZ
AF11
AG11
AG8
AH14
DIFFIO_B2p
DIFFIO_B3p
DIFFIO_B16n
IOB3_0
IOB3_1
IOB3_2
IOB3_3
ENET_RXD[3..0]
U15D
Cyclone III LS, Bank 3
EEPROM_SDA
SRAM_BWn2
MAX2_BEn2
FSM_A5
ENET_TX_EN
FLASH_OEn
FSM_D7
CRC_LATCH_SIG
DIFFIO_B19n
DIFFIO_B21p
DIFFIO_B23n
AC14
AE12
AE13
ENET_GTX_CLK
FSM_A3
FSM_A23
DIFFIO_B1p
DIFFIO_B1n
DIFFIO_B6p
DIFFIO_B6n
DIFFIO_B8p
DIFFIO_B8n
DIFFIO_B11p
DIFFIO_B11n
DIFFIO_B13p
DIFFIO_B13n
AA8
AA9
AB9
AC9
AD9
AE8
AD10
AE10
AB11
AB12
MAX2_WEn
FSM_A18
FSM_D29
FSM_A11
FSM_D30
SRAM_DQP2
FSM_D23
FSM_A13
FSM_D4
FSM_A6
ENET_GTX_CLK 13
ENET_TX_EN 13
ENET_MDC 13
Cyclone III LS, Bank 4
EP3CLSS200
HSMA_D0
FSM_A14
ENET_MDIO
SRAM_ADVn
SRAM_GWn
SRAM_CLK
FSM_D12
ENET_RESETn
AC22
AH26
AH27
AB20
AC19
AG25
AH25
AF24
DQ0B0/DIFFIO_B45n
DQ0B3/DIFFIO_B44p
DQ0B1/DIFFIO_B44n
DQ0B4/DIFFIO_B42p
DQ0B2/DIFFIO_B42n
DQ0B6/DIFFIO_B41p
DQ0B5/DIFFIO_B41n
DQ0B7/DIFFIO_B40p
DQ4B0/DIFFIO_B29p
DQ4B1/DIFFIO_B28p
DQ4B2/DIFFIO_B27n
DQ4B3
DQ4B5/DIFFIO_B26p
DQ4B4/DIFFIO_B26n
DQ4B7/DIFFIO_B25p
DQ4B6/DIFFIO_B25n
FSM_D15
AG20
FSM_A20
AG18
FSM_A22
AB16
MAX2_BEn3
AC16
FLASH_WEn
AH17
FSM_D17
AH18
AG15 ENET_1_RX_CLK
ENET_RX_DV
AH15
SRAM_ADSPn
FSM_A7
AB18
AG24
DM0B/DIFFIO_B39p
DQS0B/DIFFIO_B40n
DM4B/DIFFIO_B24p
DQS4B/DIFFIO_B28n
AF16 ENET_1_RX_DV
SRAM_ADSCn
AH19
FSM_D11
FSM_A4
FSM_A17
FLASH_ADVn
FSM_D1
FSM_A15
FLASH_CEn
FSM_A9
AF20
AF21
AE19
AF18
AH24
AG22
AH22
AH21
DQ2B1/DIFFIO_B38p
DQ2B0/DIFFIO_B38n
DQ2B3/DIFFIO_B36p
DQ2B2/DIFFIO_B36n
DQ2B4/DIFFIO_B34n
DQ2B6/DIFFIO_B32p
DQ2B5/DIFFIO_B32n
DQ2B7/DIFFIO_B30n
MAX2_BEn0
FSM_D22
AG21
AC17
DM2B/DIFFIO_B30p
DQS2B/DIFFIO_B33p
AD17
AH23
AB19
AC21
DIFFIO_B33n
DIFFIO_B34p
DIFFIO_B39n
DIFFIO_B45p
FSM_D5
FSM_A10
FSM_D19
FSM_D9
AD24
AD25
AE20
AF15
IOB4_0
IOB4_1
IOB4_2
IOB4_3
FSM_D8
SRAM_DQP1
AE23
AF22
RUP2
RDN2
AE16 ENET_1_GTX_CLK
CLKOUT_SMA
AC15
FSM_D16
AH20
DIFFIO_B31p
DIFFIO_B31n
DIFFIO_B35p
DIFFIO_B35n
DIFFIO_B37p
DIFFIO_B37n
DIFFIO_B43p
DIFFIO_B43n
AA17
AB17
AE17
AE18
AE21
AE22
AE25
AF25
8,13
ENET_RX_DV 13
ENET_MDIO 13
ENET_RESETn 13
FSM_D[31:0]
FSM_A[25:0]
D
FSM_D[31:0] 8,10,11,24
FSM_A[25:0] 8,10,11,24
SSRAM INTERFACE
SRAM_CLK
SRAM_OEn
SRAM_CEn
SRAM_BWEn
SRAM_ADVn
SRAM_GWn
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_ZZ
SRAM_DQP[3:0]
DIFFIO_B24n
DIFFIO_B27p
DIFFIO_B29n
ENET_RXD[3..0]
SHARED BUS
SRAM_BWn[3:0]
p/n matches from the above DQ groups
FSM_D10
FSM_D27
FSM_D20
HSMA_D1
ENET_RX_DV
ENET_MDIO
ENET_RESETn
SRAM_CLK 11
SRAM_OEn 11
SRAM_CEn 11
SRAM_BWEn 11
SRAM_ADVn 11
SRAM_GWn 11
SRAM_ADSCn 11
SRAM_ADSPn 11
SRAM_ADVn 11
SRAM_ZZ 10,11
C
SRAM_BWn[3:0] 11
SRAM_DQP[3:0]
11,24
J15
1
LTI-SASF546-P26-X1
2
3
4
5
U15C
ENET_TXD[3..0] 13
FSM_A2
ENET_TXD2
SRAM_DQP3
FSM_D13
FSM_D25
SRAM_BWn3
FSM_A8
FSM_D2
FLASH INTERFACE
FLASH_RESETn
FLASH_WEn
FLASH_OEn
FLASH_CEn
FLASH_CLK
FLASH_ADVn
EP3CLS200F780
EP3CLS200F780
B
FLASH_RESETn 10,11
FLASH_WEn 10,11
FLASH_OEn 10,11
FLASH_CEn 10,11
FLASH_CLK 10,11
FLASH_ADVn 10,11
ETHERNET INTERFACE (Cyclone III)
ENET_1_RX_CLK
ENET_1_RX_DV
ENET_1_GTX_CLK
A
ENET_1_RX_CLK 14
ENET_1_RX_DV 14
ENET_1_GTX_CLK 14
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
4
B-1
of
1
25
8
7
6
5
4
3
2
1
Cyclone III LS Bank 5 & 6
HSMC PORT A
HSMA_SDA
HSMA_SCL
HSMA_SDA 17
HSMA_SCL 17
E
HSMA_CLKOUT0
HSMA_CLKOUT0 17
HSMA_CLKOUT_P[2:1]
HSMA_CLKOUT_N[2:1]
HSMA_TX_P[16:0]
D
ENET_1_RXD0
HSMA_TX_N5
HSMA_TX_P6
HSMA_TX_N6
HSMA_TX_P11
HSMA_TX_N11
HSMA_TX_N7
HSMA_TX_N9
HSMA_TX_P12
HSMA_TX_N12
ENET_1_RXD1
C
EP3CLS200
Y28
U26
V23
V24
AB27
AB28
W26
Y26
AD28
AC28
Y27
DQ1R0/DIFFIO_R24n
DQ1R1/DIFFIO_R25n
DQ1R2/DIFFIO_R29p
DQ1R3/DIFFIO_R29n
DQ1R4/DIFFIO_R30p
DQ1R5/DIFFIO_R30n
DQ1R6/DIFFIO_R31n
DQ1R7/DIFFIO_R32n
DQ1R8/DIFFIO_R33p
DM1R/DIFFIO_R33n
DQS1R/DIFFIO_R24p
DQ3R0/DIFFIO_R36p
DQ3R1/DIFFIO_R36n
DQ3R2/DIFFIO_R37n
DQ3R3/DIFFIO_R38p
DQ3R4/DIFFIO_R38n
DQ3R5/DIFFIO_R40p
DQ3R6/DIFFIO_R40n
DQ3R7
DQ3R8/DIFFIO_R41p
AD26
AD27
W25
AF28
AE28
AF27
AE26
AC24
AA23
DM3R/DIFFIO_R41n
DQS3R
AA24
AE27
p/n matches from the above DQ groups
HSMA_TX_P5
HSMA_TX_P7
HSMA_TX_P9
U25
V25
AA26
DIFFIO_R25p
DIFFIO_R31p
DIFFIO_R32p
DIFFIO_R37p
W24
HSMA_CLKOUT_P1
HSMA_CLKOUT_N1
ENET_1_RXD2
HSMA_SDA
HSMA_TX_P3
HSMA_TX_N3
HSMA_TX_P10
HSMA_TX_N10
V28
U28
R25
T26
R27
R28
AA27
AA28
DIFFIO_R21p
DIFFIO_R21n
DIFFIO_R22p
DIFFIO_R22n
DIFFIO_R26p
DIFFIO_R26n
DIFFIO_R27p
DIFFIO_R27n
DIFFIO_R28p
DIFFIO_R28n
DIFFIO_R34p
DIFFIO_R34n
DIFFIO_R35p
DIFFIO_R35n
DIFFIO_R39p
DIFFIO_R39n
R23
R24
AA25
AB26
U23
U24
Y23
W23
ENET_1_RXD3
ENET_1_MDC
AB24
AB25
RUP3
RDN3
R26
IOB5_0
HSMA_TX_P16
HSMA_TX_N16
HSMA_TX_N8
HSMA_TX_P14
HSMA_TX_N14
HSMA_TX_P15
HSMA_TX_N15
ENET_1_MDIO
HSMA_TX_P0
HSMA_TX_N0
ENET_1_RESETn
HSMA_TX_P8
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P13
HSMA_TX_N13
HSMA_TX_P4
HSMA_TX_N4
HSMA_TX_P1
HSMA_TX_N1
HSMA_CLKOUT_N[2:1]
17
HSMA_RX_P[16:0] 17,18
HSMA_RX_N[16:0]
U15F
17
HSMA_TX_N[16:0] 17
HSMA_RX_P[16:0]
Cyclone III, Bank 5
HSMA_CLKOUT_P[2:1]
HSMA_TX_P[16:0] 17
HSMA_TX_N[16:0]
U15E
E
HSMA_RX_N[16:0] 17,18
Cyclone III LS, Bank 6
EP3CLS200
D
HSMA_RX_N9
HSMA_RX_P13
HSMA_RX_N13
HSMA_RX_P10
HSMA_RX_N10
HSMA_RX_P14
HSMA_RX_N14
HSMA_RX_P12
J28
K25
K26
K27
K28
L24
L25
M26
DQ0R0/DIFFIO_R13n
DQ0R1/DIFFIO_R14p
DQ0R2/DIFFIO_R14n
DQ0R3/DIFFIO_R15p
DQ0R4/DIFFIO_R15n
DQ0R5/DIFFIO_R16p
DQ0R6/DIFFIO_R16n
DQ0R7/DIFFIO_R17p
DQ2R0/DIFFIO_R4p
DQ2R1/DIFFIO_R6n
DQ2R2/DIFFIO_R9p
DQ2R3/DIFFIO_R9n
DQ2R4/DIFFIO_R11p
DQ2R5/DIFFIO_R11n
DQ2R6/DIFFIO_R12p
DQ2R7/DIFFIO_R12n
H26
K23
M23
L23
G27
G28
J25
J26
HSMA_RX_P8
HSMA_RX_N16
HSMA_RX_P15
HSMA_RX_N15
HSMA_RX_P7
HSMA_RX_N7
HSMA_RX_P11
HSMA_RX_N11
HSMA_CLKOUT_P2
HSMA_CLKOUT_N2
M25
N26
DM0R/DIFFIO_R18p
DQS0R/DIFFIO_R18n
DM2R
DQS2R/DIFFIO_R4n
H28
G26
HSMA_RX_N8
HSMA_RX_P9
HSMA_RX_N12
J27
M27
DIFFIO_R13p
DIFFIO_R17n
DIFFIO_R6p
K22
HSMA_RX_P16
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P6
HSMA_RX_N6
HSMA_RX_P4
HSMA_RX_N4
G23
G24
D26
D27
G25
F25
E27
E26
DIFFIO_R1p
DIFFIO_R1n
DIFFIO_R2p
DIFFIO_R2n
DIFFIO_R3p
DIFFIO_R3n
DIFFIO_R5p
DIFFIO_R5n
DIFFIO_R7p
DIFFIO_R7n
DIFFIO_R8p
DIFFIO_R8n
DIFFIO_R10p
DIFFIO_R10n
D28
C28
K24
J24
F28
E28
HSMA_RX_P3
HSMA_RX_N3
HSMA_RX_P0
HSMA_RX_N0
HSMA_RX_P5
HSMA_RX_N5
IOB6_0
IOB6_1
H27
P28
HSMA_CLKOUT0
p/n matches from the above DQ groups
ETHERNET INTERFACE (Cyclone III)
ENET_1_RXD[3..0]
ENET_1_RXD[3..0]
ENET_1_MDC
ENET_1_MDIO
ENET_1_RESETn
14
ENET_1_MDC 14
ENET_1_MDIO 14
ENET_1_RESETn 14
C
EP3CLS200F780
HSMA_SCL
EP3CLS200F780
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
5
B-1
of
1
25
8
7
6
5
4
3
2
1
Cyclone III LS Bank 7 & 8
LCD_HSMB_SEL
E
LCD_HSMB_SEL 19
E
DDR2 SDRAM SIGNALS
DDR2_DQ[31:0]
DDR2_DQS[3:0]
DDR2_DM[3:0]
U15G
D
C
B
U15H
Cyclone III LS, Bank 7
EP3CLS200
DDR2_DQ12
DDR2_DQ14
DDR2_DQ10
DDR2_DQ11
DDR2_DQ9
DDR2_DQ15
DDR2_DQ8
DDR2_DQ13
F21
E21
D23
D22
B27
A27
A26
A25
DQ0T0/DIFFIO_T47p
DQ0T1/DIFFIO_T45n
DQ0T3/DIFFIO_T43p
DQ0T2/DIFFIO_T43n
DQ0T5/DIFFIO_T42p
DQ0T4/DIFFIO_T42n
DQ0T7/DIFFIO_T41p
DQ0T6/DIFFIO_T41n
DDR2_DM1
DDR2_DQS1
B25
E22
DM0T/DIFFIO_T40n
DQS0T/DIFFIO_T45p
DDR2_DQ0
DDR2_DQ3
DDR2_DQ4
DDR2_DQ1
DDR2_DQ7
DDR2_DQ6
DDR2_DQ5
DDR2_DQ2
G20
G19
C19
B19
B22
B18
A21
B21
DQ2T1/DIFFIO_T39p
DQ2T0/DIFFIO_T39n
DQ2T3/DIFFIO_T38p
DQ2T2/DIFFIO_T38n
DQ2T4/DIFFIO_T35n
DQ2T5/DIFFIO_T33n
DQ2T7/DIFFIO_T32p
DQ2T6/DIFFIO_T32n
DDR2_DM0
DDR2_DQS0
C22
C18
DM2T/DIFFIO_T35p
DQS2T/DIFFIO_T33p
DDR2_B8_CKE
DDR2_B8_ODT
DDR2_B8_CSn
USER_LED3
USER_DIPSW1
USER_DIPSW2
DDR2_B8_A0
DDR2_B8_A11
G9
F8
E7
C7
B7
D7
C5
B5
DQ1T1/DIFFIO_T7p
DQ1T0/DIFFIO_T7n
DQ1T2/DIFFIO_T5n
DQ1T4/DIFFIO_T4p
DQ1T3/DIFFIO_T4n
DQ1T5/DIFFIO_T3n
DQ1T7/DIFFIO_T2p
DQ1T6/DIFFIO_T2n
DM4T/DIFFIO_T25p
DQS4T/DIFFIO_T26p
A18
A20
DDR2_B7_ODT
DDR2_B7_A8
DDR2_B8_A7
DDR2_B8_WEn
B4
E8
DM1T
DQS1T/DIFFIO_T3p
p/n matches from the above DQ groups
C24
F22
DIFFIO_T40p
DIFFIO_T47n
DIFFIO_T25n
DIFFIO_T28n
A17
A15
DDR2_B7_A9
DDR2_B7_A7
DDR2_B7_A2
DDR2_B7_A6
USER_LED1
USER_PB1
DDR2_B7_A15
DDR2_B7_CASn
A23
A22
G18
G17
E17
F17
DIFFIO_T30p
DIFFIO_T30n
DIFFIO_T31p
DIFFIO_T31n
DIFFIO_T34p
DIFFIO_T34n
DIFFIO_T36p
DIFFIO_T36n
DIFFIO_T37p
DIFFIO_T37n
DIFFIO_T44p
DIFFIO_T44n
DIFFIO_T46p
DIFFIO_T46n
F19
E19
D18
D17
D25
C25
F24
E24
DDR2_B7_BA1
DDR2_B7_A0
DDR2_B7_A11
DDR2_B7_A13
DDR2_B7_CLK_P
DDR2_B7_CLK_N
USER_PB0
USER_LED0
IOB7_0
IOB7_1
B24
E25
DDR2_B7_WEn
USER_PB2
D19
D20
RDN4
RUP4
EP3CLS200
DQ4T1/DIFFIO_T29p
DQ4T0/DIFFIO_T29n
DQ4T2/DIFFIO_T28p
DQ4T3
DQ4T5/DIFFIO_T27p
DQ4T4/DIFFIO_T27n
DQ4T6/DIFFIO_T26n
DQ4T7
DDR2_B7_A14
DDR2_B7_A5
DDR2_B7_CKE
DDR2_B7_A3
DDR2_B7_RASn
DDR2_B7_BA2
DDR2_B7_CSn
DDR2_B7_A12
DDR2_B7_A1
DDR2_B7_BA0
DDR2_B7_A4
LCD_HSMB_SEL
Cyclone III LS, Bank 8
E16
D16
B15
C15
G16
F16
A19
D15
DDR2_DQ19
DDR2_DQ16
DDR2_DQ22
DDR2_DQ17
DDR2_DQ20
DDR2_DQ18
DDR2_DQ23
DDR2_B8_RASn
C11
B11
D12
C12
A6
G10
F10
C8
DQ3T1/DIFFIO_T16p
DQ3T0/DIFFIO_T16n
DQ3T3/DIFFIO_T14p
DQ3T2/DIFFIO_T14n
DQ3T4/DIFFIO_T13n
DQ3T7/DIFFIO_T9p
DQ3T6/DIFFIO_T9n
DQ3T8/DIFFIO_T8n
DDR2_DM2
DDR2_DQS2
D8
G13
DM3T/DIFFIO_T8p
DQS3T/DIFFIO_T15n
DDR2_B8_A1
F7
DDR2_B8_A3
G12
DIFFIO_T5p
DIFFIO_T13p in CONFIG block
DIFFIO_T15p
DDR2_B8_A12
USER_DIPSW0
DDR2_B8_A15
DDR2_B8_A4
DDR2_B8_BA0
DDR2_B8_A5
A2
B2
D4
C4
D11
D10
DIFFIO_T1p
DIFFIO_T1n
DIFFIO_T6p
DIFFIO_T6n
DIFFIO_T11p
DIFFIO_T11n
DQ5T1/DIFFIO_T24p
DQ5T0/DIFFIO_T24n
DQ5T3/DIFFIO_T23p
DQ5T2/DIFFIO_T23n
DQ5T4/DIFFIO_T22n
DQ5T6/DIFFIO_T21p
DQ5T5/DIFFIO_T21n
DQ5T8/DIFFIO_T20p
DQ5T7/DIFFIO_T20n
B12
A12
E14
D13
A10
G14
F14
C13
D14
DDR2_DQ25
DDR2_DQ28
DDR2_DQ24
DDR2_DQ31
DDR2_DQ27
DDR2_DQ26
DDR2_DQ29
DDR2_B8_BA2
DDR2_DQ30
DM5T in CONFIG block
DQS5T/DIFFIO_T22p
A11
DDR2_DQS3
DDR2_DQ[31:0]
7,15,16
DDR2_DQS[3:0]
15,16
DDR2_DM[3:0]
7,15,16
DDR2 SDRAM BANK 7 SIGNALS
DDR2_B7_A[15:0]
DDR2_B7_BA[2:0]
DDR2_B7_RASn
DDR2_B7_CASn
DDR2_B7_WEn
DDR2_B7_CSn
DDR2_B7_ODT
DDR2_B7_CKE
D
DDR2_B7_A[15:0]
15,16,24
DDR2_B7_BA[2:0]
15,16
DDR2_B7_RASn
DDR2_B7_CASn
DDR2_B7_WEn
DDR2_B7_CSn
DDR2_B7_ODT
DDR2_B7_CKE
DDR2_B7_CLK_P
DDR2_B7_CLK_N
15,16
15,16
15,16
15,16
15,16
15,16
DDR2_B7_CLK_P 15
DDR2_B7_CLK_N 15
DDR2 SDRAM BANK 8 SIGNALS
DDR2_B8_A[15:0]
DDR2_B8_BA[2:0]
DDR2_B8_RASn
p/n matches from the above DQ groups
DIFFIO_T12p
DIFFIO_T12n
DIFFIO_T17p
DIFFIO_T17n
DIFFIO_T18p in CONFIG block
DIFFIO_T18n
IOB8_0
IOB8_1
D9
C9
E12
F12
DDR2_B8_BA1
DDR2_B8_A9
C
DDR2_B8_A[15:0]
7,8,15,16,24
DDR2_B8_BA[2:0]
15,16
DDR2_B8_RASn
DDR2_B8_CSn
DDR2_B8_ODT
DDR2_B8_CKE
DDR2_B8_WEn
DDR2_B8_CSn
DDR2_B8_ODT
DDR2_B8_CKE
DDR2_B8_WEn
DDR2_B8_CLK_N
15,16
15,16
15,16
15,16
15,16
DDR2_B8_CLK_N
15
USER I/O
A8
DDR2_B8_CLK_N
A5
E5
DDR2_B8_A8
DDR2_B8_A2
EP3CLS200F780
USER_LED[3:0]
USER_LED[3:0]
USER_PB[3:0]
USER_PB[3:0]
USER_DIPSW[3:0]
8,19
8,19
USER_DIPSW[3:0]
B
8,19
EP3CLS200F780
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
6
B-1
of
1
25
8
7
6
U15M
2.5V
FPGA_DCLK
R176
R183
R201
E
10.0K
10.0K
10.0K
L6
FPGA_nSTATUS
FPGA_nCONFIG
FPGA_CONF_DONE
ENET_1_INTn
K6
FPGA_CONFIG_D0
DDR2_DM3
DDR2_B8_CLK_P
DDR2_DQ21
DDR2_B8_A14
DDR2_B8_A13
2.5V
D
R65
100, 1%
M1
M3
P22
EP3CLS200
DCLK
nSTATUS
nCONFIG
CONF_DONE
BANK6
DATA2/DM5T/DIFFIO_T19n
DATA3/DIFFIO_T19p
DATA4/DIFFIO_T18p
DATA5/DQ3T5/DIFFIO_T13p
DATA6/DIFFIO_T10n
DATA7/DIFFIO_T10p
BANK8
DEV_CLRn/DIFFIO_R23p
DEV_OE/DIFFIO_R23n
BANK5
P26
P27
M2
CRC_ERROR/DIFFIO_R20p
INIT_DONE/DIFFIO_R20n
nCE
BANK1
Green_LED
BANK6
MSEL0
MSEL1
MSEL2
MSEL3
1
3
5
2
4
6
J6
EPM2210_JTAG_EN
HSMA_JTAG_EN
HSMB_JTAG_EN
XJ1
XJ5
R37
R43
R55
1.00k
1.00k
1.00k
XJ2
JTAG_TCK 10,12,17
JTAG_TMS 10,12,17
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
JTAG_FPGA_TDO 10
JTAG_EPM2210_TDO 10
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
JTAG_BLASTER_TDI 12
JTAG_BLASTER_TDO 12
HSMA_JTAG_TDO
HSMA_JTAG_TDI
HSMB_JTAG_TDO
HSMB_JTAG_TDI
XJ3
881545-2 881545-2 881545-2
881545-2
HSMA_JTAG_TDO
HSMA_JTAG_TDI
HSMB_JTAG_TDO
HSMB_JTAG_TDI
FPGA_CONFIG_D0
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_DCLK
FPGA_nCONFIG
FPGA_INIT_DONE
Passive Serial Standard (PS Standard POR) => MSEL[3:0] = "0000"
Passive Serial Fast (PS Fast POR) => MSEL[3:0] = "1100"
E
17
17
17
17
FPGA_CONFIG_D0 10
FPGA_nSTATUS 10
FPGA_CONF_DONE 10
FPGA_DCLK 10
FPGA_nCONFIG 10
FPGA_INIT_DONE 10
HSMC PORT A
BANK6
HSMA_D[3:0]
M28
L28
CLKUSR/DIFFIO_R19p
nCEO/DIFFIO_R19n
JTAG_TCK
USB Blaster Programming Header
(uses JTAG mode only)
USB_DISABLEn
R44
DNI
C54
DNI
2.5V
R45
1.00k
2.5V
J8
2
4
6
8
10
1
3
5
7
9
JTAG_TCK
JTAG_BLASTER_TDI
JTAG_TMS
V+
DDR2_DM[3:0]
EN
HSMA_JTAG_TDI
1
COM
EPM2210_JTAG_EN
5
IN
L : COM=NC
H : COM=NO
R33
1.00k
JTAG_BLASTER_TDO R29
1.00k
NC
7
JTAG_EPM2210_TDO
NO
6
3
4
JTAG_FPGA_TDO
GND
GND
HSMB_JTAG_TDI
1
HSMA_JTAG_EN
5
V+
NC
7
HSMA_JTAG_TDO
NO
6
3
4
HSMA_JTAG_TDI
COM
IN
L : COM=NC
H : COM=NO
GND
GND
2.5V
JTAG_BLASTER_TDI
C67
2.5V
XJ6
R64
10.0K
J12
1
2
HSMB_JTAG_EN
U23
ANALOG SWITCH
0.1uF
B
881545-2
U19
8
2
16
VDD
2
3
FPGA_EPM2210_TCK
JTAG_TCK
4
COM1
FPGA_JTAG_TDI
7
COM2
NC2
NO2
5
6
FPGA_EPM2210_TDI
JTAG_BLASTER_TDO
FPGA_JTAG_TDO
9
COM3
NC3
NO3
11
10
FPGA_EPM2210_TDO
JTAG_FPGA_TDO
FPGA_JTAG_TMS
12
COM4
NC4
NO4
14
13
FPGA_EPM2210_TMS
JTAG_TMS
JTAG_AT_SEL
1
15
L:COMx=NCx
SEL H:COMx=NOx
EN
D6
IN
7
HSMB_JTAG_TDO
NO
6
3
4
HSMB_JTAG_TDI
GND
GND
JTAG_AT_SEL 10
USER IO
CPU_RESETn
CPU_RESETn 10,19
R203
R206
R205
R204
ENET_1_INTn 14
B
DNI
JTAG_TCK
DNI JTAG_BLASTER_TDO
DNI
JTAG_FPGA_TDO
DNI
JTAG_TMS
LED_JTAG_AT_SEL
2.5V
R24
56.2
Title
Size
B
Date:
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
JTAG_AT_SEL = '1' Jumper Off -> Select JTAG Chain Signals.
JTAG_AT_SEL = '0' Jumper On -> Select EMP2210 GPIO JTAG Signals.
5
10
FPGA_EPM2210_TCK 10
FPGA_EPM2210_TDI 10
FPGA_EPM2210_TMS 10
FPGA_EPM2210_TDO 10
ENET_1_INTn
FPGA_JTAG_TCK
FPGA_JTAG_TDI
FPGA_JTAG_TDO
FPGA_JTAG_TMS
C
CRC_ERROR
ETHERNET INTERFACE (Cyclone III)
TS5A2053
Green_LED
6
CRC_ERROR
GND
TS3A5018
A
NC
COM
H : COM=NO
FPGA_JTAG_TCK
8
5
EN
L : COM=NC
NC1
NO1
CON2
1
ANTI-TAMPERING INTERFACE
JTAG_AT_SEL
V+
6,8,15,16,24
DDR2_B8_CLK_P 15
FPGA_EPM2210_TCK
FPGA_EPM2210_TDI
FPGA_EPM2210_TMS
FPGA_EPM2210_TDO
TS5A2053
2.5V
6,15,16
DDR2_B8_A[15:0]
DDR2_B8_CLK_P
EN
6,15,16
DDR2_DQ[31:0]
DDR2_B8_A[15:0]
U18
8
2
DDR2_DM[3:0]
DDR2_DQ[31:0]
DDR2 SDRAM BANK 8 SIGNALS
TS5A2053
2.5V
D
HSMA_D[3:0] 4,8,17
DDR2 SDRAM SIGNALS
U16
8
2
C
7
JTAG_TCK
JTAG_TMS
FPGA CONFIGURATION
1
2
70247-1051
8
1
JTAG SIGNALS
TSW-103-07-L-D
CON2
2.5V
10,12,20 USB_DISABLEn
2
2.5V
J11
R202
1.00k
P25 MSEL0_1
P23
P24
MSEL2_3
N22
BANK1
EP3CLS200F780
3
2.5V
FLASH_nCE/nCSO/DIFFIO_L8p
A9
B9
B8
A7
A3
A4
CRC_ERROR
FPGA_INIT_DONE
FPGA_JTAG_TCK
FPGA_JTAG_TDI
FPGA_JTAG_TDO
FPGA_JTAG_TMS
P2
P5
P6
N3
TCK
TDI
TDO
TMS
BANK1
DATA0
DATA1/ASDO/DIFFIO_L5n
W27
W28
D14
BANK1
4
Cyclone III LS Config, JTAG
Cyclone III LS Configuration
K1
G4
CPU_RESETn
HSMA_D3
FPGA_INIT_DONE = HIGH = USER MODE
5
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Friday, September 25, 2009
2
Sheet
7
B-1
of
1
25
8
7
6
5
4
3
2
1
Cyclone III LS Clocks
HSMA_CLKIN_P1
E
R188
E
CLKIN_LEFT_P
HSMA_CLKIN_N1
HSMA_CLKIN_P2
HSMA_CLKIN_N2
DNI
R181
100, 1%
CLOCK SIGNALS
CLKIN_LEFT_N
R180
CLKIN_RIGHT_P
R179
100, 1%
DNI
CLKIN_RIGHT_N
CLKIN_LEFT_P
CLKIN_LEFT_N
CLKIN_LEFT_P 9
CLKIN_LEFT_N 9
CLKIN_RIGHT_P
CLKIN_RIGHT_N
CLKIN_RIGHT_P
CLKIN_RIGHT_N
CLKIN_66
ENET_RX_CLK
CLKIN_66 9
ENET_RX_CLK 13
9
9
HSMC PORT A
D
U15L
HSMB_CLKIN_P2
HSMB_CLKIN_N2
R182
DNI
C
HSMA_CLKIN_P[2:1]
HSMA_CLKIN_N[2:1]
Cyclone III LS, Clocks
EP3CLS200
CLKIN_LEFT_P
CLKIN_LEFT_N
N2
N1
CLK0/DIFFCLK_0p
CLK1/DIFFCLK_0n
Bank 1
HSMB_CLKIN_P2
HSMB_CLKIN_N2
T2
T1
CLK2/DIFFCLK_1p
CLK3/DIFFCLK_1n
Bank 2
17
HSMA_CLKIN_N[2:1]
17
D
HSMA_CLKIN0 17
HSMA_D[3:0]
HSMA_D[3:0]
4,7,17
HSMC PORT B
ENET_RX_CLK
ENET_RXD2
AG13
AH13
CLK15/DIFFCLK_6p
CLK14/DIFFCLK_6n
Bank 3
Bank 3
HSMA_CLKIN_P1
HSMA_CLKIN_N1
AG16
AH16
CLK13/DIFFCLK_7p
CLK12/DIFFCLK_7n
Bank 4
Bank 4
HSMA_CLKIN_P2
HSMA_CLKIN_N2
T27
T28
CLK6/DIFFCLK_3p
CLK7/DIFFCLK_3n
Bank 5
CLKIN_RIGHT_P
CLKIN_RIGHT_N
N27
N28
CLK4/DIFFCLK_2p
CLK5/DIFFCLK_2n
Bank 6
CLKIN_66
HSMA_CLKIN0
B16
A16
CLK9/DIFFCLK_5p
CLK8/DIFFCLK_5n
Bank 7
HSMB_CLKIN0
USER_DIPSW3
B13
A13
CLK11/DIFFCLK_4p
CLK10/DIFFCLK_4n
Bank 8
HSMA_CLKIN0
HSMA_CLKIN_P[2:1]
PLL1_CLKOUTp
PLL1_CLKOUTn
AF4
AG4
FSM_A12
MAX2_CSn
HSMB_CLKIN_P2
HSMB_CLKIN_N2
HSMB_CLKIN_P2 17
HSMB_CLKIN_N2 17
PLL4_CLKOUTp
PLL4_CLKOUTn
AD22
AD21
FSM_D26
HSMA_D2
HSMB_CLKIN0
HSMB_CLKIN0 17
DDR2 SDRAM BANK 8 SIGNALS
DDR2_B8_A[15:0]
DDR2_B8_CASn
Bank 7
PLL2_CLKOUTp
PLL2_CLKOUTn
D21
C21
Bank 8
PLL3_CLKOUTp
PLL3_CLKOUTn
D5
D6
USER_PB3
USER_LED2
DDR2_B8_A[15:0]
6,7,15,16,24
DDR2_B8_CASn
15,16
ENET_RXD[3..0]
4,13
C
ETHERNET INTERFACE
ENET_RXD[3..0]
DDR2_B8_A6
DDR2_B8_CASn
SHARED BUS
FSM_D[31:0]
EP3CLS200F780
FSM_A[25:0]
FSM_D[31:0] 4,10,11,24
FSM_A[25:0] 4,10,11,24
MAXII CONTROL INTERFACE
MAX2_CSn
MAX2_CSn 10
USER I/O
B
USER_LED[3:0]
USER_PB[3:0]
USER_DIPSW[3:0]
A
B
USER_LED[3:0]
USER_PB[3:0]
6,19
6,19
USER_DIPSW[3:0]
6,19
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
8
B-1
of
1
25
5
Clock Circuitry
3.3V
3.3V
C56
C50
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
J7
1 CLKIN_SMA_P
LTI-SASF546-P26-X1
3.3V_PLL
C51
C39
0.1uF
0.1uF
0.1uF
D
3.3V
BLM15AG221SN1
U17
18
16
9
20
VCC_PLL1
VCC_PLL2
VCC_VCO
VCC_IN
VCC_OUT
4
OUTP0
OUTN0
6
5
1
2
12pF
Y2
XIN
25.00MHz
PLL_PR0
PLL_PR1
C
R192
R191
CLKIN_SMA_CP
CLKIN_SMA_CP
CLKIN_SMA_CN
124
124
R190
R193
CLKIN_SMA_CN
21
XIN
25
26
PR0
PR1
PLL_OS0
PLL_OS1
11
10
OS0
OS1
PLL_OD0
PLL_OD1
PLL_OD2
13
14
15
OD0
OD1
OD2
PLL_CE
PLL_RSTn
7
12
CE
RSTn
22
33
GND1
GND_PAD
OSC_OUT
23
REG_CAP1
REG_CAP2
19
17
3.3V
R194
R189
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
1
2
3
8
24
27
28
29
30
31
32
C41
PROG_CLK_P
R47
R46
PROG_CLK_N
C40
10uF
C45
10uF
R52
DNI
R34
R35
1 CLKIN_SMA_N
LTI-SASF546-P26-X1
100, 1%
100, 1%
CLOCK SIGNALS
4.7K
4.7K
8
2
OE
CLK_EN
0.1uF
CLKIN_SMA_CP
4
C42
0.1uF CLKIN_SMA_CN 5
C58
0.1uF
C57
0.1uF
3.3V
Place near U6.
124
R197
124
R198
84.5
84.5
U20
PROG_CLK_CP
PROG_CLK_CN
CLK_SEL
CLKp
CLKn
ALLOWS THE
PART TO BE
POPULATED WITH
THE 2 OR 4
OUTPUT PARTS IF
NEEDED.
PLL_RSTn
PLL_CE
PLL_RSTn 10
PLL_CE 10
C60
C64
C236
0.1uF
0.1uF
2.2uF
CLKIN_LEFT_P
CLKIN_LEFT_N
Q1p
Q1n
17
16
CLKIN_RIGHT_P
CLKIN_RIGHT_N
15
14
3
CLK_SEL
Q3p
Q3n
12
11
SMA_OUT_P 1
LTI-SASF546-P26-X1
R63
100, 1%
E
PLL_OD[2:0] 10
PLL_PR[1:0]
20
19
Q2p
Q2n
To Board Settings DIP Switch.
CLK_SEL = '1' -> PCLKp/PCLKn
CLK_SEL = '0' -> CLKp/CLKn
CLK66_EN 10
CLK50_EN 10
CLK_SEL 10,20
Q0p
Q0n
PCLKp
PCLKn
ICS8543
3.3V
LVDS
6
7
R196
R199
CLK66_EN
CLK50_EN
CLK_SEL
PLL_OD[2:0]
3.3V
LVPECL INPUT CLOCK
3.3V
C44
J9
84.5
84.5
5
4
3
2
C52
10uF
C48
L3
100, 1%
100, 1%
The LVPECL termination can be
replaced with the 100 ohm LVDS
termination.
1
PLL_PR[1:0] 10
CLKIN_LEFT_P 8
CLKIN_LEFT_N 8
CLKIN_RIGHT_P
CLKIN_RIGHT_N
D
8
8
J14
2
3
4
5
C55
2
SMA_OUT_N 1
LTI-SASF546-P26-X1
J13
2
3
4
5
C47
5
4
3
2
C46
10uF
C38
3
10
18
E
4
VDD
VDD
6
GND
GND
GND
7
1
9
13
8
3.3V
CLKIN_66
C61
C63
0.1uF
0.1uF
CLKIN_66 8
CLKIN_50
CLK_CONFIG
C
CLKIN_50 10
CLK_CONFIG 10
CDCM61001
3.3V
LVPECL OUT
3.3V
R50
10.0K
PLL_OS1
R49
10.0K
PLL_OS0
R42
R48
3.3V
B
10.0K
10.0K
PLL_RSTn
PLL_CE
2.5V
DEFAULT 125 MHz OUT
R38
R39
R41
R40
10.0K
10.0K
10.0K
10.0K
PLL_PR0
PLL_PR1
PLL_OD0
PLL_OD1
R36
10.0K
PLL_OD2
R76
1.00K
Configuration Clock
2.5V
Y3
C81
0.01uF
1
EN
VCC
4
To EPM2210
2
GND
OUT
3
CLK_CONFIG
100MHz
C80
0.01uF
3.3V
3.3V
From EPM2210
R30
4.7K
CLK66_EN
C37
C36
2.2uF
0.1uF
X3
1
EN
VCC
4
2
GND
OUT
3
From EPM2210
2.5V
R59
4.7K
CLK50_EN
CLKIN_66
C79
4.7uF
2.5V
X5
1
EN
VCC
4
2
GND
OUT
3
ECS-3525-500-B
66.6MHz
A
B
To EPM2210
CLKIN_50
C66
C65
2.2uF
0.1uF
Title
Size
B
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
9
B-1
of
1
25
8
7
6
5
4
EPM2210 System Controller
U22A
FPGA_CONFIG_D0
E
D
D3
C2
E3
C3
E4
D2
E5
D1
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
MAX2_OEn
MAX2_CSn
MAX2_WEn
MAX2_CLK
MAX2_BEn0
MAX2_BEn1
MAX2_BEn2
MAX2_BEn3
F3
E2
F4
E1
F5
F2
F6
F1
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
MAX_ERROR
MAX_LOAD
MAX_FACTORY
G3
G2
G4
G1
G5
H2
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
H1
IOB1_24
H5
J5
CLKIN_50
MAX II
BANK1
IOB1/GCLK0
IOB1/GCLK1
U22B
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_DCLK
PGM_LED0
PGM_LED1
PGM_LED2
PGM_SEL
PGM_CONFIG
H3
J1
H4
J2
J4
K1
J3
K2
IOB1_34
IOB1_35
IOB1_36
IOB1_37
IOB1_38
IOB1_39
IOB1_40
L1
K5
L2
K4
M1
K3
M2
IOB1_41
IOB1_42
IOB1_43
IOB1_44
IOB1_45
IOB1_46
IOB1_47
IOB1_48
L5
M3
L4
N1
L3
N2
M4
N3
IOB1_49
P2
TCK
TDI
TDO
TMS
P3
L6
M5
N4
SECURITY_LED0
CRC_ERROR
SECURITY_LED1
CRC_LATCH_SIG
HEARTBEAT
SECURITY
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_CS0n
SENSE_ADC_F0
FSM_A0
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
C13
B16
C12
A15
D12
B14
C11
B13
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
D11
A13
E11
B12
C10
A12
D10
B11
FSM_A16
FSM_A17
E10
A11
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
B10
C9
A10
D9
B9
C
FPGA_TCK
FPGA_TMS
FPGA_TDI
FPGA_TDO
SRAM_ZZ
PLL_RSTn
PLL_CE
PLL_OD0
PLL_OD1
PLL_OD2
PLL_PR0
PLL_PR1
B
CRC_ERROR_MAX
JTAG_AT_SEL
CLK_CONFIG
P14
N13
P15
M14
N14
M13
N15
L14
IOB3_103
IOB3_104
IOB3_105
IOB3_106
IOB3_107
IOB3_108
IOB3_109
IOB3_110
N16
L13
M15
L12
M16
L11
L15
K14
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
IOB2_58
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_82
IOB2_83
C8
A6
FSM_D8
FSM_D9
IOB2_85
IOB2_86
IOB2_87
IOB2_88
IOB2_89
B6
E7
A5
D7
B5
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
IOB2_66
IOB2_67
IOB2_90
IOB2_91
IOB2_92
IOB2_93
IOB2_94
IOB2_95
IOB2_96
IOB2_97
C7
A4
E6
B4
D6
C4
C6
B3
FSM_D15
FLASH_WEn
FLASH_CEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
IOB2_98
IOB2_99
IOB2_100
IOB2_101
IOB2_102
C5
A2
D5
B1
D4
FSM_A25
FSM_A24
FSM_A23
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
U22D
MAX II
BANK3
HSMA_PRSNTn
HSMB_PRSNTn
CLK50_EN
CLK66_EN
IOB3_127
IOB3_128
IOB3_129
IOB3_130
IOB3_131
IOB3_132
IOB3_133
IOB3_134
IOB3_111
IOB3_112
IOB3_113
IOB3_114
IOB3_115
IOB3_116
IOB3_117
IOB3_118
IOB3_135
G15
IOB3_137
IOB3_138
IOB3_139
IOB3_140
IOB3_141
IOB3_142
F16
G13
F15
G14
E16
F11
MAX_DIP0
MAX_DIP1
AT_ACTIVE
USB_DISABLEn
L16
K13
K15
K12
K16
IOB3_119
IOB3_120
IOB3_121
IOB3_122
IOB3_123
IOB3_125
IOB3_126
E15
F12
D16
F13
D15
F14
D14
E12
MAX_CONF_DONE
USB_LED
J15
J14
IOB3_143
IOB3_144
IOB3_145
IOB3_146
IOB3_147
IOB3_148
IOB3_149
IOB3_150
IOB3/GLCK2
IOB3/GCLK3
IOB3_151
IOB3_152
IOB3_153
IOB3_154
IOB3_155
C15
E13
C14
E14
D13
FPGA_EPM2210_TCK
FPGA_EPM2210_TDI
FPGA_EPM2210_TMS
FPGA_EPM2210_TDO
SRAM_MODE
FPGA_nCONFIG
FPGA_INIT_DONE
USER_PGM
JTAG_SECURE
CLK_SEL
CLK_ENABLE
VCCA_SHDNn_PB
VCCA_SHDNn
CPU_RESETn
EPM2210_F256FBGA
A
E9
A9
A8
B8
E8
A7
D8
B7
MAX_RESETn
P4
R1
P5
T2
N5
R3
P6
R4
IOB4_156
IOB4_157
IOB4_158
IOB4_159
IOB4_160
IOB4_161
IOB4_162
IOB4_163
N6
T4
M6
R5
P7
T5
N7
R6
JTAG_TCK
JTAG_TMS
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
FPGA_TCK
FPGA_TMS
FPGA_TDI
FPGA_TDO
FPGA_EPM2210_TCK
FPGA_EPM2210_TDI
FPGA_EPM2210_TMS
FPGA_EPM2210_TDO
CRC_LATCH_SIG
HEARTBEAT
SECURITY
VCCA_SHDNn
JTAG_AT_SEL
CRC_ERROR
CRC_ERROR_PB
20
20
20
20
FSM_D[31:0]
7
7
7
7
FLASH_WEn
FLASH_CEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
PLL_RSTn 9
PLL_CE 9
CLKIN_50 9
CLK_CONFIG
SENSE_ADC_F0
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_CS0n
FPGA CONFIGURATION
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
IOB4_180
IOB4_181
IOB4_182
IOB4_183
IOB4_184
IOB4_185
IOB4_187
R10
IOB4_164
IOB4_165
IOB4_166
IOB4_167
IOB4_168
IOB4_169
IOB4_170
IOB4_171
IOB4_188
IOB4_189
IOB4_190
IOB4_191
IOB4_192
IOB4_193
IOB4_194
IOB4_195
M10
T11
N10
R11
P10
T12
M11
R12
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
M7
T6
IOB4_172
IOB4_173
IOB4_175
IOB4_176
IOB4_177
IOB4_178
IOB4_179
N11
T13
P11
R13
M12
R14
N12
T15
FSM_D30
FSM_D31
R7
P8
T7
N8
R8
IOB4_196
IOB4_197
IOB4_198
IOB4_199
IOB4_200
IOB4_201
IOB4_202
IOB4_203
M9
M8
IOB4_204
IOB4/DEV_CLRn IOB4_205
IOB4/DEV_OE
IOB4_206
P12
R16
P13
U22E
MAX2_BEn[3:0]
M2Z_CONF_DONE
M2Z_nSTATUS
M2Z_nCONFIG
M2Z_DCLK
M2Z_D0
CRC_ERROR_PB
H7
H9
J8
J10
G6
F7
K11
L10
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
A1
A16
B2
B15
G7
G8
G9
G10
K7
K8
K9
K10
R2
R15
T1
T16
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
EPM2210_F256FBGA
H8
H10
J7
J9
K6
L7
G11
F10
VCCIO1
VCCIO1
VCCIO1
VCCIO1
C1
H6
J6
P1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
A3
A14
F8
F9
VCCIO3
VCCIO3
VCCIO3
VCCIO3
C16
H11
J11
P16
VCCIO4
VCCIO4
VCCIO4
VCCIO4
L8
L9
T3
T14
PGM_SEL
PGM_CONFIG
MAX_RESETn
VCCA_SHDNn_PB
CPU_RESETn
4
8
4
24
C
PGM_SEL 20
PGM_CONFIG 20
MAX_RESETn 20
VCCA_SHDNn_PB 20
CPU_RESETn 7,19
LED INTERFACE
PGM_LED[2:0]
PGM_LED[2:0] 20
MAX_ERROR
MAX_LOAD
MAX_FACTORY
USB_LED
MAX_CONF_DONE
2.5V
MAX_ERROR 20
MAX_LOAD 20
MAX_FACTORY 20
USB_LED 12,20
MAX_CONF_DONE 20
SECURITY_LED0
CRC_ERROR_MAX
SECURITY_LED1
HSMA_PRSNTn 17
HSMB_PRSNTn 17
DIP SWITCH INTERFACE
MAX_DIP[1:0]
MAX_DIP[1:0] 20
CLK_SEL
CLK_ENABLE
USB_DISABLEn
JTAG_SECURE
USER_PGM
AT_ACTIVE
CLK_SEL 9,20
CLK_ENABLE 20
USB_DISABLEn 7,12,20
JTAG_SECURE
20
USER_PGM 20
AT_ACTIVE 20
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
C226
C234
C237
C227
C228
C257
C253
C250
C256
C258
C252
C233
C244
C246
C245
C247
C248
C249
C235
C254
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size
B
Date:
8
7
6
5
4
3
B
SECURITY_LED0 20
CRC_ERROR_MAX 20
SECURITY_LED1 20
HSMA_PRSNTn
HSMB_PRSNTn
EPM2210_F256FBGA
From EPM2210
MAX2_OEn
MAX2_CSn
MAX2_WEn
MAX2_CLK
PUSH BUTTON INTERFACE
2.5V
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
MAX2_BEn[3:0] 4
MAX2_OEn
MAX2_CSn
MAX2_WEn
MAX2_CLK
M2Z_CONF_DONE 12
M2Z_nSTATUS 12
M2Z_nCONFIG 12
M2Z_DCLK 12
M2Z_D0 12
MAX II
Power
FPGA_CONFIG_D0 7
FPGA_nSTATUS 7
FPGA_CONF_DONE 7
FPGA_DCLK 7
FPGA_nCONFIG 7
FPGA_INIT_DONE 7
MAXII CONTROL INTERFACE
MAXII USB PASSIVE SERIAL
MAX II
BANK4
SRAM_ZZ 4,11
SRAM_MODE 11
FPGA_CONFIG_D0
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_DCLK
FPGA_nCONFIG
FPGA_INIT_DONE
9
SENSE_ADC_F0 23
SENSE_SDO 23
SENSE_SDI 23
SENSE_SCK 23
SENSE_CS0n 23
M2Z_CONF_DONE
M2Z_nSTATUS
M2Z_nCONFIG
M2Z_DCLK
M2Z_D0
D
SRAM_ZZ
SRAM_MODE
PLL_PR[1:0] 9
CLKIN_50
CLK_CONFIG
FLASH_WEn 4,11
FLASH_CEn 4,11
FLASH_OEn 4,11
FLASH_RDYBSYn 3,11
FLASH_RESETn 4,11
FLASH_CLK 4,11
FLASH_ADVn 4,11
SRAM INTERFACE
PLL_OD[2:0] 9
PLL_PR[1:0]
FSM_A[25:0] 4,8,11,24
FLASH INTERFACE
CLK50_EN 9
CLK66_EN 9
PLL_OD[2:0]
E
FSM_D[31:0] 4,8,11,24
FSM_A[25:0]
CLOCK INTERFACE
PLL_RSTn
PLL_CE
CRC_LATCH_SIG 4
HEARTBEAT 4
SECURITY 4
VCCA_SHDNn 22
JTAG_AT_SEL 7
CRC_ERROR 7
CRC_ERROR_PB 20
SHARED BUS
FPGA_EPM2210_TCK
FPGA_EPM2210_TDI
FPGA_EPM2210_TMS
FPGA_EPM2210_TDO
CLK50_EN
CLK66_EN
1
ANTI-TAMPER INTERFACE
JTAG_TCK 7,12,17
JTAG_TMS 7,12,17
JTAG_FPGA_TDO 7
JTAG_EPM2210_TDO 7
CURRENT & SENSE INTERFACES
N9
T8
T9
R9
P9
T10
Place near MAX II
2.5V
JTAG SIGNALS
2
FPGA_TCK
FPGA_TMS
FPGA_TDI
FPGA_TDO
EPM2210_F256FBGA
J16
J13
H16
H13
H15
H14
G16
G12
J12
H12
IOB2_74
IOB2_75
IOB2_76
IOB2_77
IOB2_78
IOB2_79
IOB2_80
IOB2_81
IOB2_50
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
JTAG_TCK
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
JTAG_TMS
EPM2210_F256FBGA
U22C
MAX II
BANK2
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
10
B-1
of
1
25
A
8
7
6
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
R6
P6
A2
A10
B2
B10
N6
P3
P4
P8
P9
P10
P11
R3
R4
R8
R9
R10
R11
B1
A1
B11
C10
P2
R2
SRAM_CLK
B6
CLK
SRAM_OEn
SRAM_CEn
SRAM_CE2
SRAM_CE3n
SRAM_MODE
B8
A3
B3
A6
R1
OE_n
CE1_n
CE2
CE3_n
MODE
SRAM_BWn0
SRAM_BWn1
SRAM_BWn2
SRAM_BWn3
SRAM_BWEn
B5
A5
A4
B4
A7
BWA_n
BWB_n
BWC_n
BWD_n
BWE_n
SRAM_GWn
B7
GW_n
D
C
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_ZZ
A8
B9
A9
H11
1
SHARED BUS
TCK
TDI
TDO
TMS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
DQPA
DQPB
DQPC
DQPD
N11
C11
C1
N1
SRAM_DQP0
SRAM_DQP1
SRAM_DQP2
SRAM_DQP3
4,8,10,24
FSM_A[25:0] 4,8,10,24
FLASH 512Mb (32M X 16)
U9
1.8V
PC28FxxxP30B85
FLASH
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
VPP
A1
A2
VCC
A3
VCC
A4
A5
VCCQ
A6
VCCQ
A7
VCCQ
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
NC(64M)/A23
D13
NC(64M,128M)/A24 D14
NC/A25(512M)
D15
A4
FLASH_CLK
E6
CLK
WAIT
F7
FLASH_RESETn
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_ADVn
FLASH_WPn
D4
B4
F8
G8
F6
C6
RESET#
CE#
OE#
WE#
ADV#
WP#
GND
GND
GND
GND
B2
H2
H4
H6
RFU0
RFU1
RFU2
RFU3
RFU4
H1
G2
F1
E8
B8
A11
C2
H1
P1
H3
H9
H10
N2
N5
N10
SSRAM INTERFACE
A6
H3
SRAM_CLK
SRAM_OEn
SRAM_CEn
SRAM_MODE
SRAM_BWEn
SRAM_ADVn
SRAM_GWn
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_ZZ
2.5V
D5
D6
G4
F2
E2
G3
E4
E5
G5
G6
H7
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
E1
E3
F3
F4
F5
H5
G7
E7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
SRAM_CLK 4
SRAM_OEn 4
SRAM_CEn 4
SRAM_MODE 10
SRAM_BWEn 4
SRAM_ADVn 4
SRAM_GWn 4
SRAM_ADSCn 4
SRAM_ADSPn 4
SRAM_ADVn 4
SRAM_ZZ 4,10
SRAM_BWn[3:0]
D
SRAM_BWn[3:0] 4
SRAM_DQP[3:0]
SRAM_DQP[3:0]
4,24
FLASH INTERFACE
FLASH_RESETn
FLASH_WEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_CEn
FLASH_CLK
FLASH_ADVn
FLASH_RDYBSYn
FLASH_RESETn 4,10
FLASH_WEn 4,10
FLASH_OEn 4,10
FLASH_RDYBSYn 3,10
FLASH_CEn 4,10
FLASH_CLK 4,10
FLASH_ADVn 4,10
C
PC48F4400P0ZBQ0
1.8V
2.5V
H2
N7
L5
K7
K6
K5
J7
J6
J5
H7
H6
H5
G7
G6
G5
F7
C8
F6
L6
F5
E7
E6
E5
D7
D6
D5
C7
C6
C5
C4
M5
L7
N8
N4
M7
M6
FSM_D[31:0]
FSM_A[25:0]
J10
J11
K10
K11
L10
L11
M10
M11
D10
D11
E10
E11
F10
F11
G10
G11
D1
D2
E1
E2
F1
F2
G1
G2
J1
J2
K1
K2
L1
L2
M1
M2
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
ADSC_n
ADSP_n
ADV_n
ZZ
E
FSM_D[31:0]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B
2
J3
J9
K3
K9
L3
L9
M3
M9
N3
N9
C3
C9
D3
D9
E3
E9
F3
F9
G3
G9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC_144M
NC_288M
NC_576M
NC_1G
NC_A
NC_B
2.5V
R7
P5
P7
R5
3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
U14
E
SRAM & Flash
4
2.5V
D4
D8
E4
E8
F4
F8
G4
G8
H4
H8
J4
J8
K4
K8
L4
L8
M4
M8
2.5V
5
IS61VPS51236A
R157
R152
R154
R155
10K
10K
10K
10K
FLASH_WPn
FLASH_WEn
FLASH_RDYBSYn
FLASH_RESETn
R156
R153
10K
10K
FLASH_CEn
FLASH_OEn
2.5V
B
C162
C164
C184
C163
C169
C170
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2.5V
2.5V
2.5V
R162
R161
10K
10K
SRAM_CE2
SRAM_CE3n
C206
C214
C213
C203
C221
C222
C196
C197
C207
C215
0.1uF
0.1uF
0.1uF
0.1uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
11
B-1
of
1
25
8
7
6
5
4
3
2
1
Embedded USB Blaster
U13B
E
L1
USB
J4
USB CON
C24
10uF
1
2
3
4
6
U13A
USB_5.0V
USB_5.0V
BLM21PG331SN1
R19
470
R21
SN65220DBV
USB_XTAL1
USB_XTAL2
USB_5.0V
R159
18pF
10.0K
USB_RESETn
USB_EECS
USB_EESK
EEDATA
USB_XTAL1
2
C7
1.5K
RSTOUT#
XTIN
XTOUT
4
RESET#
32
1
2
EECS
EESK
EEDATA
TEST
USB_XTAL2
USB_EECS
USB_EESK
EEDATA
USB_SI_WU
USB_DISABLEn
USB_PWR_ENn
13
VCC-IO
5
27
28
3
26
30
USBDM
USBDP
9
17
18pF
1
C6
8
7
31
Y1
6.000MHz
C
3V3OUT
VCC1
VCC2
27
27
6
AGND
R18
R17
6
4
5
NC1
A
NC2
B
GNDGND
U11
D0
D1
D2
D3
D4
D5
D6
D7
25
24
23
22
21
20
19
18
USB_D0
USB_D1
USB_D2
USB_D3
USB_D4
USB_D5
USB_D6
USB_D7
RD#
WR
16
15
USB_RDn
USB_WR
TXE#
RXF#
14
12
USB_TXEn
USB_RXFn
SI/WU
PWREN#
11
10
USB_SI_WU
USB_PWR_ENn
USB_2.5V
CLKIN_24MHZ
USB_RESETn
R160
1.00k
1uF
USB_5.0V
C190
0.1uF
10uF
IOB1_1
IOB1_9
IOB1_3
IOB1_11
IOB1_5
IOB1_6
IOB1_7
IOB1/DEV_CLRn
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
J7
K10
K3
K4
K5
K6
K7
K9
L2
D1
C1
H1
G1
F1
J5
J6
IOB1_28
IOB1_4
IOB1_2
IOB1_12
IOB1_10
IOB1_8
IOB1_15
IOB1_16
IOB1_25
IOB1_26
IOB1_27
IOB1_13
IOB1_29
IOB1_30
IOB1_31
IOB1_32
L1
L10
L11
H2
L3
L4
L5
L6
IOB1_33
IOB1_34
L7
L9
JTAG_TCK
TCK
TDI
TDO
TMS
K1
J2
K2
J1
USB_MAX_TCK
USB_MAX_TDI
USB_MAX_TDO
USB_MAX_TMS
F2
E1
IOB1/CLK0
IOB1/CLK1
L8
H3
IOB1/DEV_OE
IOB1_14
1
2
3
4
C191
0.1uF
8
IN
OUT1
6
7
9
SHDN1
SHDN2
BYP1
ADJ1
5
4
OUT2
10
VCC
NC1
NC2
GND
8
7
6
5
BYP2
ADJ2
1
2
3
11
GND
EPAD_GND
LT3023
USB_2.5V
AT93C46DN-SH-B
R23
2.2K
B
CS
SK
DIN
DOUT
R22
USB_EEDATA
USB_D4
USB_D3
USB_LED
USB_D2
JTAG_BLASTER_TDO
IOB2_35
IOB2_36
IOB2_37
IOB2_38
IOB2_39
IOB2_40
IOB2_41
IOB2_42
A7
A8
A9
B10
B5
B2
B3
B4
F10
G11
MAX IIZ
BANK2
IOB2_47
IOB2_57
IOB2_62
IOB2_65
IOB2_66
IOB2_56
IOB2_52
IOB2_58
B11
C11
D11
E11
F11
C10
B6
C5
IOB2_43
IOB2_44
IOB2_45
IOB2_46
IOB2_51
IOB2_48
IOB2_49
IOB2_50
IOB2_59
IOB2_60
IOB2_61
IOB2_53
IOB2_63
IOB2_64
IOB2_55
IOB2_54
C6
C7
D10
B7
D9
E10
B9
B8
IOB2/CLK2
IOB2/CLK3
IOB2_67
IOB2_68
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
IOB2_74
F9
G10
H10
H11
H9
J10
J11
K11
M2Z_CONF_DONE
M2Z_nSTATUS
M2Z_nCONFIG
M2Z_DCLK
M2Z_D0
E
D
JTAG_TMS
JTAG_BLASTER_TDI
EPM240ZM100
MAXII USB INTERFACE
USB_2.5V
U7
U12
DECOUPLING CAPS
C19
B1
F3
C2
G2
D2
D3
E2
K8
A1
A10
A11
A2
A3
A4
A5
A6
EPM240ZM100
USB_5.0V
C8
USB_5.0V
USB_TXEn
USB_D1
USB_D0
USB_WR
USB_RDn
USB_D7
USB_D6
USB_D5
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
FT245BL
29
1
3
2
C18
0.1uF
AVCC
C195
33nF
GND1
GND2
5
C194
0.1uF
U8
D
USB_RXFn
USB_5.0V USB_2.5V
MAX IIZ
BANK1
R14
C16
9.53K
M2Z_CONF_DONE
M2Z_nSTATUS
M2Z_nCONFIG
M2Z_DCLK
M2Z_D0
4.7K
0.01uF
U13C
M2Z_VCCINT
C13
C11
1uF
1uF
USB_DISABLEn 7,10,20
USB_LED 10,20
C
MAXII USB PASSIVE SERIAL
R13
M2Z_VCCINT
R12
C12
USB_DISABLEn
USB_LED
10.0K
0.01uF
JTAG_TCK 7,10,17
JTAG_TMS 7,10,17
JTAG_BLASTER_TDI 7
JTAG_BLASTER_TDO 7
R11
10.0K
D5
D7
E4
E8
G4
G8
H5
H7
10.0K
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
M2Z_CONF_DONE 10
M2Z_nSTATUS 10
M2Z_nCONFIG 10
M2Z_DCLK 10
M2Z_D0 10
MAX IIZ
Power
M2Z_VCCINT
VCCINT
VCCINT
E9
G3
VCCIO1
VCCIO1
VCCIO1
E3
J4
J8
VCCIO2
VCCIO2
VCCIO2
C4
C8
G9
USB_2.5V
B
EPM240ZM100
USB_2.5V
USB_2.5V
X2
C32
EN
VCC
4
2
GND
OUT
3
24MHz
0.01uF
USB_2.5V
USB_2.5V
R195
1
CLKIN_24MHZ
C33
0.01uF
C31
PLACE NEAR MAX II
USB_2.5V
M2Z_VCCINT
1.00K USB_MAX_TCK
USB_MAX_TDO
1.00K USB_MAX_TMS
R200
4.7uF
USB_MAX_TDI
J20
1
3
5
7
9
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
DNI
A
Size
B
Date:
7
6
C209
C210
C202
C217
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
8
C212
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
12
B-1
of
1
25
8
7
6
5
4
10/100/1000 Ethernet (Port 0)
3
2
1
ETHERNET INTERFACE
E
E
ENET_TXD[3..0]
COMA
RESET_N
65
64
63
61
60
59
58
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
29
31
33
34
39
41
42
43
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
ENET_MDIO
ENET_MDC
ENET_INTn
24
25
23
MDIO
MDC
INT_N
MGMT
37
38
HSDAC_P
HSDAC_N
30
56
RSET
SEL_FREQ
C69
0.01uF
C68
0.01uF
C115
0.01uF
C116
0.01uF
ENET_MDIO
ENET_MDC
ENET_INTn
ENET_RESETn
R70
R69
R68
R67
R95
R96
R98
R97
2.5V
J16
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
2.5V
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
GND_TAB
GND_TAB
4.7K
4.7K
4.7K
4.7K
12
11
9
TD0_P
TD0_N
1
2
TD1_P
TD1_N
3
6
TD2_P
TD2_N
4
5
TD3_P
TD3_N
7
8
GND
10
HFJ11-1G02E
ENET_RSET
R99
10.0K
X7
C
1
2
3
EN
NC1
GND
OUT
NC2
VCC
4
5
6
ENET_XTAL_25MHZ
3.3V
25MHz
B
13
51
NC1
NC2
97
VSS
5
21
88
96
72
66
52
VDDOH
VDDOH
VDDOH
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VDDO
VDDO
VDDO
VDDO
32
36
35
40
45
78
VDDOX
VDDOX
U24B
26
48
R83
4.99K
R86
4.7K
47
49
44
50
46
TRST_N
TCK
TDI
TDO
TMS
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
11
12
14
16
17
18
19
20
ENET_TXD0
ENET_TXD1
ENET_TXD2
ENET_TXD3
RXCLK
RX_DV
RX_ER
2
94
3
ENET_RX_CLK
ENET_RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
95
92
93
91
90
89
87
86
ENET_RXD0
ENET_RXD1
ENET_RXD2
ENET_RXD3
CRS
COL
84
83
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
79
80
82
81
77
75
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
68
69
70
73
74
76
ENET_TX_EN
ENET_GTX_CLK 4
ENET_TX_EN 4
ENET_MDC 4
ENET_RXD[3..0]
ENET_RXD[3..0]
ENET_RX_CLK
ENET_RX_DV
ENET_MDIO
ENET_RESETn
ENET_INTn
ENET_RX_CLK 8
ENET_RX_DV 4
ENET_MDIO 4
ENET_RESETn 4
ENET_INTn 24
C
ENET_LED_TX
ENET_LED_RX
ENET_LED_DUPLEX
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
ENET_LED_TX
1
6
10
15
57
62
67
71
85
ENET_LED_RX
R115
R108
ENET_LED_LINK1000 R93
ENET_LED_LINK100
R100
220
220
220
220
88E1111
ENET_LED_LINK10
Place near 88E1111 PHY
2.5V
A
R111
220
D22
Green_LED
2.5V
D18
Green_LED
D15
Green_LED
B
D16
Green_LED
D20
Green_LED
1.2V
C74
C102
C104
C93
C89
C76
C82
C98
C75
C77
C90
C103
C105
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Size
B
Date:
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
8
4,8
D
88E1111
1.2V
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
125CLK
XTAL1
XTAL2
VSSC
JTAG
2.5V
22
55
54
53
ENET_GTX_CLK
TEST
3.3V
VCC
ENET_LED_DUPLEX
ENET_LED_LINK100
ENET_LED_RX
8
4
9
7
GTX_CLK
TX_CLK
TX_EN
TX_ER
SGMII INTERFACE
ENET_RESETn
R71
R81
R72
R82
D
27
28
MDI INTERFACE
2.5V
U24A
ENET_GTX_CLK
ENET_TX_EN
ENET_MDC
RGMII Mode
GMII/MII/TBI INTERFACE
MDIO PHY Address Bits (4:0) = 00000
ENET_TXD[3..0] 4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
13
B-1
of
1
25
8
7
6
5
4
10/100/1000 Ethernet (Port 1)
Only populated on C3 Industrial Board
3
2
1
ETHERNET INTERFACE
E
U25A
27
ENET_1_RESETn 28
DNI
DNI
DNI
DNI
C128
DNI
C73
DNI
C72
DNI
J17
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
2.5V
ENET_1_MDI_P0
ENET_1_MDI_N0
ENET_1_MDI_P1
ENET_1_MDI_N1
ENET_1_MDI_P2
ENET_1_MDI_N2
ENET_1_MDI_P3
ENET_1_MDI_N3
9
TD0_P
TD0_N
1
2
TD1_P
TD1_N
3
6
TD2_P
TD2_N
4
5
TD3_P
TD3_N
7
8
GND
ENET_1_MDI_P0
ENET_1_MDI_N0
ENET_1_MDI_P1
ENET_1_MDI_N1
ENET_1_MDI_P2
ENET_1_MDI_N2
ENET_1_MDI_P3
ENET_1_MDI_N3
ENET_1_MDIO
ENET_1_MDC
ENET_1_INTn
10
12
11
DNI
ENET_1_RSET
R75
10.0K
X6
C
65
64
63
61
ENET_1_LED_DUPLEX 60
ENET_1_LED_LINK100 59
ENET_1_LED_RX
58
1
2
3
EN
NC1
GND
OUT
NC2
VCC
4
5
6
ENET_1_XTAL_25MHZ
3.3V
DNI
B
13
51
NC1
NC2
97
VSS
5
21
88
96
72
66
52
VDDOH
VDDOH
VDDOH
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VDDO
VDDO
VDDO
VDDO
32
36
35
40
45
78
VDDOX
VDDOX
U25B
26
48
R91
DNI
R85
DNI
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
11
12
14
16
17
18
19
20
ENET_1_TXD0
ENET_1_TXD1
ENET_1_TXD2
ENET_1_TXD3
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
RXCLK
RX_DV
RX_ER
2
94
3
ENET_1_RX_CLK
ENET_1_RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
95
92
93
91
90
89
87
86
ENET_1_RXD0
ENET_1_RXD1
ENET_1_RXD2
ENET_1_RXD3
24
25
23
MDIO
MDC
INT_N
37
38
HSDAC_P
HSDAC_N
30
56
RSET
SEL_FREQ
CRS
COL
84
83
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
79
80
82
81
77
75
22
55
54
53
125CLK
XTAL1
XTAL2
VSSC
47
49
44
50
46
TRST_N
TCK
TDI
TDO
TMS
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
68
69
70
73
74
76
ENET_1_GTX_CLK 4
ENET_1_TX_EN 3
ENET_1_MDC 5
ENET_1_RXD[3..0]
ENET_1_RXD[3..0]
ENET_1_TX_EN
ENET_1_RX_CLK
ENET_1_RX_DV
ENET_1_MDIO
ENET_1_RESETn
ENET_1_INTn
ENET_1_RX_CLK 4
ENET_1_RX_DV 4
ENET_1_MDIO 5
ENET_1_RESETn 5
ENET_1_INTn 7
C
ENET_1_LED_TX
ENET_1_LED_RX
ENET_1_LED_DUPLEX
ENET_1_LED_LINK1000
ENET_1_LED_LINK100
ENET_1_LED_LINK10
R114
ENET_1_LED_TX
1
6
10
15
57
62
67
71
85
R118
ENET_1_LED_RX
ENET_1_LED_LINK1000
ENET_1_LED_LINK100
R101
R110
DNI
DNI
DNI
DNI
DNI
ENET_1_LED_LINK10
Place near 88E1111 PHY
2.5V
A
R117
DNI
2.5V
D21
DNI
D24
DNI
D17
DNI
B
D19
DNI
D23
DNI
1.2V
C88
C86
C97
C101
C114
C112
C99
C96
C113
C111
C100
C85
C87
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
Size
B
Date:
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
8
5
D
DNI
1.2V
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
29
31
33
34
39
41
42
43
JTAG
2.5V
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
TEST
3.3V
VCC
ENET_1_LED_TX
MGMT
DNI
R104
R105
R106
R107
R80
R79
R77
R78
2.5V
ENET_1_GTX_CLK
GTX_CLK
TX_CLK
TX_EN
TX_ER
MDI INTERFACE
C127
ENET_1_MDIO
ENET_1_MDC
ENET_1_INTn
ENET_1_RESETn
GND_TAB
GND_TAB
R103
R94
R102
R92
8
4
9
7
COMA
RESET_N
SGMII INTERFACE
2.5V
ENET_1_TXD[3..0] 3
ENET_1_GTX_CLK
ENET_1_TX_EN
ENET_1_MDC
RGMII Mode
GMII/MII/TBI INTERFACE
MDIO PHY Address Bits (4:0) = 00001
D
E
ENET_1_TXD[3..0]
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
14
B-1
of
1
25
8
7
6
5
4
3
2
1
DDR2 SDRAM
DDR2 SDRAM SIGNALS
E
DDR2_DQ[31:0]
D
U6A
DDR2_B7_A0
DDR2_B7_A1
DDR2_B7_A2
DDR2_B7_A3
DDR2_B7_A4
DDR2_B7_A5
DDR2_B7_A6
DDR2_B7_A7
DDR2_B7_A8
DDR2_B7_A9
DDR2_B7_A10
DDR2_B7_A11
DDR2_B7_A12
DDR2_B7_A13
DDR2_B7_A14
DDR2_B7_A15
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU/A13
RFU/A14
RFU/A15
DDR2_B7_BA0
DDR2_B7_BA1
DDR2_B7_BA2
L2
L3
L1
DDR2_DM0
DDR2_DM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_B8_A0
DDR2_B8_A1
DDR2_B8_A2
DDR2_B8_A3
DDR2_B8_A4
DDR2_B8_A5
DDR2_B8_A6
DDR2_B8_A7
DDR2_B8_A8
DDR2_B8_A9
DDR2_B8_A10
DDR2_B8_A11
DDR2_B8_A12
DDR2_B8_A13
DDR2_B8_A14
DDR2_B8_A15
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU/A13
RFU/A14
RFU/A15
BA0
BA1
RFU/BA2
UDQS_P
UDQS_N
B7
A8
DDR2_DQS1
DDR2_B8_BA0
DDR2_B8_BA1
DDR2_B8_BA2
L2
L3
L1
F3
B3
LDM
UDM
LDQS_P
LDQS_N
F7
E8
DDR2_DQS0
DDR2_DM2
DDR2_DM3
DDR2_B7_RASn
DDR2_B7_CASn
DDR2_B7_WEn
DDR2_B7_CSn
K7
L7
K3
L8
RAS_N
CAS_N
WE_N
CS_N
CKE
CK_P
CK_N
K2
J8
K8
DDR2_B7_CKE
DDR2_B7_CLK_P
DDR2_B7_CLK_N
DDR2_B7_ODT
K9
ODT
VREF
0.9VREF
MT47H32M16HR
J2
C158
DDR2_DQS[3:0]
U5A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
BA0
BA1
RFU/BA2
UDQS_P
UDQS_N
B7
A8
DDR2_DQS3
F3
B3
LDM
UDM
LDQS_P
LDQS_N
F7
E8
DDR2_DQS2
DDR2_B8_RASn
DDR2_B8_CASn
DDR2_B8_WEn
DDR2_B8_CSn
K7
L7
K3
L8
RAS_N
CAS_N
WE_N
CS_N
CKE
CK_P
CK_N
K2
J8
K8
DDR2_B8_CKE
DDR2_B8_CLK_P
DDR2_B8_CLK_N
DDR2_B8_ODT
K9
ODT
VREF
MT47H32M16HR
0.1uF
DDR2_DM[3:0]
DDR2_B7_BA[2:0]
DDR2_B7_CLK_N
R151
100, 1%
100, 1%
DDR2_B8_CLK_N
DDR2_DQS[3:0]
6,16
6,7,16
DDR2_B7_A[15:0]
6,16,24
DDR2_B7_BA[2:0]
6,16
DDR2_B7_RASn
DDR2_B7_CASn
DDR2_B7_WEn
DDR2_B7_CSn
DDR2_B7_ODT
DDR2_B7_CKE
DDR2_B7_RASn
DDR2_B7_CASn
DDR2_B7_WEn
DDR2_B7_CSn
DDR2_B7_ODT
DDR2_B7_CKE
DDR2_B7_CLK_P
DDR2_B7_CLK_N
DDR2_B7_CLK_P 6
DDR2_B7_CLK_N 6
D
6,16
6,16
6,16
6,16
6,16
6,16
DDR2 SDRAM BANK 8 SIGNALS
DDR2_B8_A[15:0]
DDR2_B8_A[15:0]
6,7,8,16,24
DDR2_B8_BA[2:0]
6,16
C161
DDR2_B8_BA[2:0]
0.1uF
DDR2_B8_RASn
DDR2_B8_CASn
DDR2_B8_WEn
DDR2_B8_CSn
DDR2_B8_ODT
DDR2_B8_CKE
DDR2_B8_RASn
DDR2_B8_CASn
DDR2_B8_WEn
DDR2_B8_CSn
DDR2_B8_ODT
DDR2_B8_CKE
DDR2_B8_CLK_P
DDR2_B8_CLK_N
DDR2_B8_CLK_P 7
DDR2_B8_CLK_N 6
DDR2_B8_CLK_P
R149
6,7,16
DDR2_DM[3:0]
DDR2_B7_A[15:0]
C
DDR2_B7_CLK_P
DDR2_DQ[31:0]
DDR2 SDRAM BANK 7 SIGNALS
0.9VREF
J2
E
6,16
8,16
6,16
6,16
6,16
6,16
C
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
15
B-1
of
1
25
8
7
6
5
4
3
DDR2 SDRAM POWER & TERM
2
1
DDR2 SDRAM SIGNALS
DDR2_DQ[31:0]
DDR2_DQS[3:0]
E
U5B
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
MT47H32M16HR
VDD
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
0.9VTT
E2
A2
1.8V
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS
VSS
VSS
VSS
VSS
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC2
NC1
VDD
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC2
NC1
U6B
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
E2
A2
PLACE NEAR CYCLONE III LS
1.8V
D
DDR2_DM[3:0]
VSS
VSS
VSS
VSS
VSS
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
MT47H32M16HR
C
B
0.9VTT
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
RN11H
RN11F
RN12H
RN12B
RN12F
RN12D
RN12C
RN12E
8
6
8
2
6
4
3
5
9
11
9
15
11
13
14
12
56
56
56
56
56
56
56
56
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
RN10C
RN9H
RN9D
RN10D
RN9G
RN9E
RN10B
RN9B
3
8
4
4
7
5
2
2
14 56
9 56
13 56
13 56
10 56
12 56
15 56
15 56
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
RN10G
RN11D
RN10E
RN11G
RN11C
RN10F
RN10H
RN11A
7
4
5
7
3
6
8
1
10
13
12
10
14
11
9
16
56
56
56
56
56
56
56
56
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
RN8C
RN8A
RN8G
RN8H
RN9F
RN8F
RN9C
RN8B
3
1
7
8
6
6
3
2
14 56
16 56
10 56
9 56
11 56
11 56
14 56
15 56
DDR2_DQS2
DDR2_DQS3
RN11B
RN11E
2
5
15 56
12 56
DDR2_DQS0
DDR2_DQS1
RN10A
RN8D
1
4
16 56
13 56
DDR2_DM2
DDR2_DM3
RN12G 7
RN12A 1
10 56
16 56
DDR2_DM0
DDR2_DM1
RN9A
RN8E
1
5
16 56
12 56
0.9VTT
6,7,15
DDR2_DQS[3:0]
6,15
DDR2_DM[3:0]
E
6,7,15
0.9VTT
DDR2 SDRAM BANK 7 SIGNALS
DDR2_B7_A[15:0]
DDR2_B7_BA[2:0]
DDR2_B7_RASn
DDR2_B7_CASn
DDR2_B7_WEn
DDR2_B7_CSn
DDR2_B7_ODT
DDR2_B7_CKE
DDR2_B7_A[15:0]
6,15,24
DDR2_B7_BA[2:0]
6,15
DDR2_B7_RASn
DDR2_B7_CASn
DDR2_B7_WEn
DDR2_B7_CSn
DDR2_B7_ODT
DDR2_B7_CKE
6,15
6,15
6,15
6,15
6,15
6,15
D
DDR2 SDRAM BANK 8 SIGNALS
DDR2_B8_A[15:0]
DDR2_B8_BA[2:0]
DDR2_B8_RASn
DDR2_B8_CASn
DDR2_B8_WEn
DDR2_B8_CSn
DDR2_B8_ODT
DDR2_B8_CKE
PLACE CAPS NEAR RESISTOR PACKS
0.9VTT
DDR2_DQ[31:0]
DDR2_B8_A[15:0]
6,7,8,15,24
DDR2_B8_BA[2:0]
6,15
DDR2_B8_RASn
DDR2_B8_CASn
DDR2_B8_WEn
DDR2_B8_CSn
DDR2_B8_ODT
DDR2_B8_CKE
6,15
8,15
6,15
6,15
6,15
6,15
PLACE NEAR DDR2 DEVICES
CN8
1
2
3
4
0.1uf x 4
8
7
6
5
CN5
1
2
3
4
0.1uf x 4
8
7
6
5
CN11 0.1uf x 4
1
8
2
7
3
6
4
5
CN2
1
2
3
4
0.1uf x 4
8
7
6
5
CN3
1
2
3
4
0.1uf x 4
8
7
6
5
CN9
1
2
3
4
CN6
1
2
3
4
0.1uf x 4
8
7
6
5
CN1
1
2
3
4
0.1uf x 4
8
7
6
5
CN10 0.1uf x 4
1
8
2
7
3
6
4
5
CN4
1
2
3
4
0.1uf x 4
8
7
6
5
CN7
1
2
3
4
0.1uf x 4
8
7
6
5
0.9VTT
0.9VTT
C
0.1uf x 4
8
7
6
5
DDR2_B8_A0
DDR2_B8_A1
DDR2_B8_A2
DDR2_B8_A3
DDR2_B8_A4
DDR2_B8_A5
DDR2_B8_A6
DDR2_B8_A7
RN7D
RN5D
RN5E
RN3D
RN7E
RN5A
RN5H
RN3H
4
4
5
4
5
1
8
8
13 56
13 56
12 56
13 56
12 56
16 56
9 56
9 56
DDR2_B7_A0
DDR2_B7_A1
DDR2_B7_A2
DDR2_B7_A3
DDR2_B7_A4
DDR2_B7_A5
DDR2_B7_A6
DDR2_B7_A7
RN6D
RN4D
RN4E
RN2D
RN6E
RN4A
RN4H
RN2H
4
4
5
4
5
1
8
8
13 56
13 56
12 56
13 56
12 56
16 56
9 56
9 56
DDR2_B8_A8
DDR2_B8_A9
DDR2_B8_A10
DDR2_B8_A11
DDR2_B8_A12
DDR2_B8_A13
DDR2_B8_A14
DDR2_B8_A15
RN7B
RN5C
RN3E
RN5F
RN3F
RN7C
RN5B
RN5G
2
3
5
6
6
3
2
7
15 56
14 56
12 56
11 56
11 56
14 56
15 56
10 56
DDR2_B7_A8
DDR2_B7_A9
DDR2_B7_A10
DDR2_B7_A11
DDR2_B7_A12
DDR2_B7_A13
DDR2_B7_A14
DDR2_B7_A15
RN6B
RN4C
RN2E
RN4F
RN2F
RN6C
RN4B
RN4G
2
3
5
6
6
3
2
7
15 56
14 56
12 56
11 56
11 56
14 56
15 56
10 56
DDR2_B8_BA0
DDR2_B8_BA1
DDR2_B8_BA2
DDR2_B8_RASn
DDR2_B8_CASn
DDR2_B8_WEn
DDR2_B8_CSn
DDR2_B8_ODT
RN3B
RN3C
RN3A
RN7F
RN7A
RN3G
RN7G
RN7H
2
3
1
6
1
7
7
8
15 56
14 56
16 56
11 56
16 56
10 56
10 56
9 56
DDR2_B7_BA0
DDR2_B7_BA1
DDR2_B7_BA2
DDR2_B7_RASn
DDR2_B7_CASn
DDR2_B7_WEn
DDR2_B7_CSn
DDR2_B7_ODT
RN2B
RN2C
RN2A
RN6F
RN6A
RN2G
RN6G
RN6H
2
3
1
6
1
7
7
8
15 56
14 56
16 56
11 56
16 56
10 56
10 56
9 56
DDR2_B8_CKE
R140
56.0
DDR2_B7_CKE
R139
B
56.0
1.8V
PLACE CAPS NEAR U17
A
C176
C165
C168
C171
C172
C173
C174
C175
C157
C156
C139
C140
C142
C141
C143
C144
0.1uF
0.1uF
0.01uF
0.1uF
4.7nF
0.1uF
0.1uF
0.01uF
0.1uF
0.1uF
0.01uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
1.8V
C160
C159
C177
C178
C147
C180
C149
C150
C183
C167
C145
C146
C179
C148
C181
C182
0.1uF
0.1uF
0.01uF
0.1uF
4.7nF
0.1uF
0.1uF
0.01uF
0.1uF
0.1uF
0.01uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size
B
Date:
8
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
PLACE CAPS NEAR U18
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
16
B-1
of
1
25
7
6
HSMA_D0
HSMA_D2
3.3V
HSMA_TX_P0
HSMA_TX_N0
3.3V
HSMA_TX_P1
HSMA_TX_N1
3.3V
HSMA_TX_P2
HSMA_TX_N2
3.3V
HSMA_TX_P3
HSMA_TX_N3
3.3V
HSMA_TX_P4
HSMA_TX_N4
3.3V
HSMA_TX_P5
HSMA_TX_N5
3.3V
HSMA_TX_P6
HSMA_TX_N6
3.3V
HSMA_TX_P7
HSMA_TX_N7
3.3V
HSMA_CLKOUT_P1
HSMA_CLKOUT_N1
3.3V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
HSMA_TX_P8
HSMA_TX_N8
3.3V
HSMA_TX_P9
HSMA_TX_N9
3.3V
HSMA_TX_P10
HSMA_TX_N10
3.3V
HSMA_TX_P11
HSMA_TX_N11
3.3V
HSMA_TX_P12
HSMA_TX_N12
3.3V
HSMA_TX_P13
HSMA_TX_N13
3.3V
HSMA_TX_P14
HSMA_TX_N14
3.3V
HSMA_TX_P15
HSMA_TX_N15
3.3V
HSMA_TX_P16
HSMA_TX_N16
3.3V
HSMA_CLKOUT_P2
HSMA_CLKOUT_N2
3.3V
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
E
12V
D
C
B
A
3.3V
3.3V
C132
C135
10uF
10uF
ASP-122953-01
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
BANK 1
High Speed Mezzanine (HSM) Interface
HSMB_SDA
JTAG_TCK
HSMB_JTAG_TDO
HSMB_CLKOUT0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
HSMB_D0
HSMB_D2
3.3V
HSMB_D4
HSMB_D6
3.3V
HSMB_D8
HSMB_D10
3.3V
HSMB_D12
HSMB_D14
3.3V
HSMB_D16
HSMB_D18
3.3V
HSMB_D20
HSMB_D22
3.3V
HSMB_D24
HSMB_D26
3.3V
HSMB_D28
HSMB_D30
3.3V
HSMB_D32
HSMB_D34
3.3V
HSMB_D36
HSMB_D38
3.3V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
12V
HSMA_SCL
JTAG_TMS
HSMA_JTAG_TDI
HSMA_CLKIN0
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
BANK 2
BANK 3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
3
2
J1
161
162
163
164
165
166
167
168
169
170
171
172
HSMA_SDA
JTAG_TCK
HSMA_JTAG_TDO
HSMA_CLKOUT0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
4
HSMA_D1
HSMA_D3
HSMA_RX_P0
HSMA_RX_N0
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P3
HSMA_RX_N3
HSMA_RX_P4
HSMA_RX_N4
HSMA_RX_P5
HSMA_RX_N5
HSMA_RX_P6
HSMA_RX_N6
HSMA_RX_P7
HSMA_RX_N7
HSMA_CLKIN_P1
HSMA_CLKIN_N1
HSMA_RX_P8
HSMA_RX_N8
HSMA_RX_P9
HSMA_RX_N9
12V
12V
12V
12V
12V
12V
12V
12V
12V
12V
12V
12V
HSMA_RX_P10
HSMA_RX_N10
12V
HSMA_RX_P11
HSMA_RX_N11
12V
HSMA_RX_P12
HSMA_RX_N12
12V
HSMA_RX_P13
HSMA_RX_N13
12V
HSMA_RX_P14
HSMA_RX_N14
12V
HSMA_RX_P15
HSMA_RX_N15
12V
HSMA_RX_P16
HSMA_RX_N16
12V
HSMA_CLKIN_P2
HSMA_CLKIN_N2
HSMA_PRSNTn
HSMA_PRSNTn R3
12V
3.3V
56.2
3.3V
C133
C134
10uF
10uF
HSMB_D40
HSMB_D42
3.3V
HSMB_D44
HSMB_D46
3.3V
HSMB_D48
HSMB_D50
3.3V
HSMB_D52
HSMB_D54
3.3V
HSMB_D56
HSMB_D58
3.3V
HSMB_D60
HSMB_D62
3.3V
HSMB_D64
HSMB_D66
3.3V
HSMB_D68
HSMB_D70
3.3V
HSMB_D72
HSMB_D74
3.3V
HSMB_CLKOUT_P2
HSMB_CLKOUT_N2
3.3V
D2
Green_LED
3.3V
ASP-122953-01
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
BANK 1
6
5
4
HSMA_JTAG_TDO
HSMA_JTAG_TDI
HSMB_JTAG_TDO
HSMB_JTAG_TDI
7
7
7
7
E
HSMC PORT A
HSMB_D1
HSMB_D3
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMB_D41
HSMB_D43
HSMB_D5
HSMB_D7
HSMB_D9
HSMB_D11
HSMB_D13
HSMB_D15
HSMB_D17
HSMB_D19
HSMB_D21
HSMB_D23
HSMB_D25
HSMB_D27
HSMB_D29
HSMB_D31
HSMB_D33
HSMB_D35
HSMB_D37
HSMB_D39
HSMB_D45
HSMB_D47
HSMB_D49
HSMB_D51
HSMB_D53
HSMB_D55
HSMB_D57
HSMB_D59
HSMB_D61
HSMB_D63
HSMB_D65
HSMB_D67
HSMB_D69
HSMB_D71
HSMB_D73
HSMB_D75
HSMA_SDA 5
HSMA_SCL 5
HSMA_CLKIN0
HSMA_CLKOUT0
HSMB_SCL
JTAG_TMS
HSMB_JTAG_TDI
HSMB_CLKIN0
HSMA_CLKIN0 8
HSMA_CLKOUT0 5
HSMA_CLKIN_P[2:1]
HSMA_CLKIN_N[2:1]
HSMA_CLKOUT_P[2:1]
12V
HSMA_CLKOUT_N[2:1]
HSMA_D[3:0]
12V
12V
HSMA_CLKIN_N[2:1]
8
HSMA_CLKOUT_P[2:1]
5
HSMA_CLKOUT_N[2:1]
5
D
4,7,8
HSMA_TX_N[16:0] 5
HSMA_RX_P[16:0]
HSMA_RX_P[16:0] 5,18
HSMA_RX_N[16:0]
HSMA_RX_N[16:0] 5,18
12V
HSMA_PRSNTn
12V
8
HSMA_TX_P[16:0] 5
HSMA_TX_N[16:0]
12V
HSMA_CLKIN_P[2:1]
HSMA_D[3:0]
HSMA_TX_P[16:0]
HSMA_PRSNTn 10
HSMC PORT B
12V
HSMB_SDA
HSMB_SCL
12V
12V
HSMB_CLKIN0 8
HSMB_CLKOUT0 3
HSMB_CLKIN_P2
HSMB_CLKIN_N2
12V
HSMB_CLKIN_P2 8
HSMB_CLKIN_N2 8
HSMB_CLKOUT_P2
HSMB_CLKOUT_N2
12V
HSMB_CLKOUT_P2 3
HSMB_CLKOUT_N2 3
HSMB_D[75:0]
12V
C
HSMB_SDA 3
HSMB_SCL 24
HSMB_CLKIN0
HSMB_CLKOUT0
HSMB_D[75:0]
HSMB_PRSNTn
3,19,24
HSMB_PRSNTn 10
12V
B
12V
12V
12V
12V
12V
12V
HSMB_CLKIN_P2
HSMB_CLKIN_N2
HSMB_PRSNTn
12V
HSMB_PRSNTn R2
Title
Size
3
D1
Green_LED
56.2
3.3V
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Date:
7
JTAG_TCK 7,10,12
JTAG_TMS 7,10,12
HSMA_SDA
HSMA_SCL
B
8
JTAG INTERFACE
HSMA_JTAG_TDO
HSMA_JTAG_TDI
HSMB_JTAG_TDO
HSMB_JTAG_TDI
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
BANK 2
BANK 3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
JTAG_TCK
JTAG_TMS
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
J2
5
161
162
163
164
165
166
167
168
169
170
171
172
8
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
17
B-1
of
1
25
8
7
6
5
4
High Speed Mezzanine (HSM) Termination
3
2
1
E
E
By default all of the data signal on the HSMC's are single ended. 100 Ohm resistors should be installed between the P/N pairs in order to use differential signals.
Place near C3LS.
D
C
R165
DNI
HSMA_RX_P0
HSMA_RX_N0
R164
DNI
HSMA_RX_P1
HSMA_RX_N1
R163
DNI
HSMA_RX_P2
HSMA_RX_N2
R167
DNI
HSMA_RX_P3
HSMA_RX_N3
R166
DNI
HSMA_RX_P4
HSMA_RX_N4
R168
DNI
HSMA_RX_P5
HSMA_RX_N5
R170
DNI
HSMA_RX_P6
HSMA_RX_N6
R169
DNI
HSMA_RX_P7
HSMA_RX_N7
R173
DNI
HSMA_RX_P8
HSMA_RX_N8
R171
DNI
HSMA_RX_P9
HSMA_RX_N9
R172
DNI
HSMA_RX_P10
HSMA_RX_N10
R175
DNI
HSMA_RX_P11
HSMA_RX_N11
R174
DNI
HSMA_RX_P12
HSMA_RX_N12
R177
DNI
HSMA_RX_P13
HSMA_RX_N13
R178
DNI
HSMA_RX_P14
HSMA_RX_N14
R185
DNI
HSMA_RX_P15
HSMA_RX_N15
R186
DNI
HSMA_RX_P16
HSMA_RX_N16
B
HSMC PORT A
HSMA_RX_P[16:0]
HSMA_RX_P[16:0] 5,17
HSMA_RX_N[16:0]
HSMA_RX_N[16:0] 5,17
C
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
D
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
18
B-1
of
1
25
8
7
6
5
4
User IO Cyclone III LS
SPACER1
E
2.5V
D28
USER_LED0
Green_LED
D27
USER_LED1
Green_LED
D26
USER_LED2
Green_LED
D25
USER_LED3
RESn_LED0
R131
56.2
RESn_LED1
R130
56.2
RESn_LED2
R129
56.2
RESn_LED3
R128
56.2
3
B1
2
1
B2
E
SPACER2
2x16 LCD
2 x 16 Display Connector
5.0V
J19
1
3
5
7
9
11
13
LCD_WEn
LCD_DATA0
LCD_DATA2
LCD_DATA4
LCD_DATA6
Green_LED
2x7 HDR
1
3
5
7
9
11
13
2
4
6
8
10
12
14
2
4
6
8
10
12
14
LCD_D_Cn
LCD_CSn
LCD_DATA1
LCD_DATA3
LCD_DATA5
LCD_DATA7
SCREW1
STANDOFF1
SCREW2
STANDOFF2
SCREW3
STANDOFF3
SCREW4
STANDOFF4
HDR2X7
D
D
2.5V
C137
0.1uF
2.5V
S2
1
CPU_RESETn
2
R119
10.0K
2.5V
XJ4
C
881545-2
J18
2.5V
PBSwitch
S6
1
2
1
1
1
S5
S4
S3
USER_PB0
R123
10.0K
2
USER_PB1
R122
10.0K
2
USER_PB2
R121
10.0K
4
LCD_HSMB_D73
7
LCD_HSMB_D74
LCD_HSMB_SEL
1
2
16
LCD_HSMB_D72
LCD_HSMB_D75
R148
10.0K
U27
ANALOG SWITCH
CON2
9
USER_PB3
R120
NC1
NO1
2
3
LCD_DATA0
HSMB_D72
COM2
NC2
NO2
5
6
LCD_DATA1
HSMB_D73
NC3
NO3
11
10
LCD_DATA2
HSMB_D75
NC4
NO4
14
13
LCD_DATA3
HSMB_D74
COM3
COM4
1
15
L:COMx=NCx
SEL H:COMx=NOx
EN
8
10.0K
0.1uF
OPEN
R234
R235
R236
R237
USER_LED[3:0]
8
7
6
5
USER_DIPSW[3:0]
EEPROM_SCL
EEPROM_SDA
USER_PB[3:0]
LCD_HSMB_D[75:65]
HSMB_D[75:0]
LCD_HSMB_SEL
VDD
10.0K
10.0K
10.0K
10.0K
TDA04H0SB1
6,8
USER_DIPSW[3:0]
USER_PB[3:0]
6,8
6,8
LCD_HSMB_D[75:65]
HSMB_D[75:0]
3,24
C
3,17,24
LCD_HSMB_SEL 6
FPGA_CONF_DONE
CPU_RESETn 7,10
7,10
EEPROM SIGNALS
2.5V
2
3
LCD_DATA4
HSMB_D66
LCD_HSMB_D66
4
COM1
NC1
NO1
LCD_HSMB_D69
7
COM2
NC2
NO2
5
6
LCD_DATA5
HSMB_D69
LCD_HSMB_D70
9
COM3
NC3
NO3
11
10
LCD_DATA6
HSMB_D70
LCD_HSMB_D68
12
COM4
NC4
NO4
14
13
LCD_DATA7
HSMB_D68
LCD_HSMB_SEL
1
15
L:COMx=NCx
SEL H:COMx=NOx
EN
8
USER_LED[3:0]
USER IO
FPGA_CONF_DONE
CPU_RESETn
GND
2.5V
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
VCC
WP
SCL
SDA
24LC32A
U28
ANALOG SWITCH
16
1
2
3
4
A0
A1
A2
GND
LCD_HSMB_SEL = '1' Jumper Off -> Select HSMB Data Signals.
LCD_HSMB_SEL = '0' Jumper On -> Select LCD Signals.
C152
8
7
6
5
1
2
3
4
U21
TS3A5018
B
S7
2.5V
COM1
12
2.5V
2
VDD
U29
ANALOG SWITCH
16
C153
0.1uF
4
COM1
NC1
NO1
2
3
LCD_D_Cn
HSMB_D71
LCD_HSMB_D65
7
COM2
NC2
NO2
5
6
LCD_CSn
HSMB_D65
LCD_HSMB_D67
9
COM3
NC3
NO3
11
10
LCD_WEn
HSMB_D67
12
COM4
NC4
NO4
14
13
1
15
L:COMx=NCx
SEL H:COMx=NOx
EN
8
TS3A5018
VDD
LCD_HSMB_D71
LCD_HSMB_SEL
GND
EEPROM_SDA
EEPROM_SCL
EEPROM_SDA 4
EEPROM_SCL 3
B
GND
TS3A5018
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
19
B-1
of
1
25
8
E
7
D10
Red_LED
MAX_ERROR
D11
MAX_LOAD
MAX_FACTORY
MAX_CONF_DONE
Green_LED
D12
Green_LED
D13
Green_LED
D4
USB_LED
6
5
RES_MAX_LOAD
RES_MAX_FACTORY
R51
100, 1%
R60
SECURITY_LED0
56.2
R61
CRC_ERROR_MAX
56.2
RES_MAX_CONF_DONE R62
56.2
RES_USB_LED
56.2
R8
SECURITY_LED1
D8
Red_LED
D7
Red_LED
D9
Red_LED
2
1
2.5V
RES_SECURITY_LED0
R31
100, 1%
RES_CRC_ERROR
R26
100, 1%
RES_SECURITY_LED1
R32
100, 1%
Green_LED
D
3
USER IO EPM2210
2.5V
RES_MAX_ERROR
4
E
D
PUSH BUTTON INTERFACE
PGM_SEL
PGM_CONFIG
MAX_RESETn
VCCA_SHDNn_PB
CRC_ERROR_PB
PGM_SEL 10
PGM_CONFIG 10
MAX_RESETn 10
VCCA_SHDNn_PB 10
CRC_ERROR_PB
2.5V
D31
PGM_LED0
Green_LED
D30
PGM_LED1
C
Green_LED
D29
PGM_LED2
RESn_PGM_LED0
R134
56.2
2.5V
2.5V
R184
RESn_PGM_LED1
R133
56.2
R187
1.00K FPGA_TCK
FPGA_TDO
1.00K FPGA_TMS
FPGA_TDI
RESn_PGM_LED2
R132
56.2
J10
1
3
5
7
9
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
2x5
Green_LED
2.5V
1
1
1
S9
S8
S10
2
PGM_SEL
2
PGM_CONFIG
2
MAX_RESETn
R125
MAX_ERROR 10
MAX_LOAD 10
MAX_FACTORY 10
MAX_CONF_DONE 10
USB_LED 10,12
SECURITY_LED0
CRC_ERROR_MAX
SECURITY_LED1
SECURITY_LED0 10
CRC_ERROR_MAX 10
SECURITY_LED1 10
MAX_DIP[1:0]
C
MAX_DIP[1:0] 10
CLK_SEL
CLK_ENABLE
USER_PGM
USB_DISABLEn
JTAG_SECURE
AT_ACTIVE
10.0K
R126
PGM_LED[2:0] 10
MAX_ERROR
MAX_LOAD
MAX_FACTORY
MAX_CONF_DONE
USB_LED
DIP SWITCH INTERFACE
10.0K
R124
LED INTERFACE
PGM_LED[2:0]
10.0K
CLK_SEL 9,10
CLK_ENABLE 10
USER_PGM 10
USB_DISABLEn 7,10,12
JTAG_SECURE
10
AT_ACTIVE
10
JTAG SIGNALS
1
B
1
S11
S1
2
VCCA_SHDNn_PB
R127
10.0K
2
CRC_ERROR_PB
R28
10.0K
MAX II CONTROL
SW2
MAX_DIP0
1
MAX_DIP1
2
AT_ACTIVE
3
JTAG_SECURE
4
USB_DISABLEn
5
USER_PGM
6
CLK_ENABLE
7
CLK_SEL
8
16
15
14
13
12
11
10
9
2.5V
RN1A
RN1B
RN1C
RN1D
RN1E
RN1F
RN1G
RN1H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
10K
10K
10K
10K
10K
10K
10K
10K
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDO
JTAG_FPGA_TDO
JTAG_TCK 7,10,12,17
JTAG_TMS 7,10,12,17
JTAG_BLASTER_TDO 7,12
JTAG_FPGA_TDO 7,10
FPGA_TCK
FPGA_TMS
FPGA_TDI
FPGA_TDO
FPGA_TCK
FPGA_TMS
FPGA_TDI
FPGA_TDO
B
10
10
10
10
DIP_SW_8
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
20
B-1
of
1
25
7
6
5
Power1
2.5V
DC_INPUT
R1
4
SW1
EG2201A
100K
C270
1
TBD
150uF
C109
4.7uF
47uf
0.1uF
RUN
C275
R229
TBD
TBD
RSNS SNS
V14 SENSE_PAD
1 RSNS SNS 2
INTVCC
TK/SS1
D34
3 2 1
C276
SW1
CMDSH2_3
5
S1_P 10.0
S1_P
Q2
RJK0301DPB
S1_N
2
BG1
4
R215
S1_N 10.0
INTVCC
3 2 1
C263
CMDSH2_3
TBD
C264
DNI
R212
INTVCC Forced Continuous
DC_INPUT
C110
C119
4.7uF
47uf
0.1uF
Q4A
SI4816BDY-T1
0.009 L8 1
2 2.2uH
V21
V22
RSNS SNS
SENSE_PAD
2
SW2
S2_P
Q4B
SENSE_PAD SI4816BDY-T1
RSNS SNS
TG1
SW1
BG1
32
31
30
TG1
SW1
BG1
RUN
TK/SS2
35
1
RUN2
TK/SS2
25
BOOST2
BOOST2
C268
1000pF
0
26
27
28
Switching Freq = 400kHz
R220
0
SENSE1+
SENSE1VFB1
TG2
SW2
BG2
5
6
12
SENSE2+
SENSE2VFB2
MODE
FREQ
37
38
39
MODE/PLLIN
FREQ/PLLFLTR
ILIM
INTVCC
R221
10.0K
LTC3853
29
INTVCC
22
RUN3
TK/SS3
34
2
BOOST3
18
BOOST3
TG3
SW3
BG3
19
20
21
TG3
SW3
BG3
SENSE3+
SENSE3VFB3
7
8
14
SENSE3+
SENSE3VFB3
ITH1
ITH2
ITH3
10
13
15
ITH1
ITH2
ITH3
C279
C280
2.2uF
2.2uF
0.1uF
D
12V
2 6.8uH
R87
0.009
100K
BG3
Q3B
SI4816BDY-T1
4
D35
R228
0
INTVCC
C122
C126
1uF
22uF
220uF
V19
SENSE_PAD
V20
SENSE_PAD
C
C277
0.1uF
CMDSH2_3
R211
10.0
S3_P
R210
10.0
S3_N
C267
1000pF
C121
330pF
43K
R219
C266
18.0K
220pF
R209
C261
330pF
B
13.0K
C273
C265
C259
470pF
1500pF
1500pF
2
S2_N
4
BG2
2.55K
3.3V
A
VCCIO_B1B2
2.5V
C124
C131
C125
R56
0.003
1uF
22uF
220uF
R66
0.003
R27
0.003
7
6
VCCIO_B3B4
Title
VCCIO_B5B6
Size
B
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Date:
8
47uf
L7 1
RUN
TK/SS3
C274
R227
TBD
R216
100K
R224
ILM
1000pF
PGOOD_2.5V_3.3V
PGOOD_12V
DRVCC12
R225
10.0K
C271
R231
INTVCC
SENSE2+
SENSE2VFB2
R226
17
16
4.7uF
Q3A
SI4816BDY-T1
1
SW3
PGOOD12
PGOOD3
C91
3
2
1
TG2
7
R113
1
6
5
3.3V
BOOST1
TG2
SW2
BG2
8
C120
33
3
4
9
0
R213
S2_N 10.0
B
R230
BOOST1
SENSE1+
SENSE1VFB1
0.1uF
S2_P 10.0
R218
10.0K
1000pF
R214
C278
VFB2
C269
D36
TK/SS2
3.3V
0.1uF
RUN1
TK/SS1
TG3
C71
2
U30
36
40
VIN
TG1
4
24
R232
SENSE_PAD
C
3.3V
C84
RSNS SNS
1
3.3V
0.1uF
11
V13
C281
2
C130
Q1
RJK0301DPB
2 1.0uH
R223
10.0K
RSNS SNS
C118
2.5V
1
R233
2.20
5
0.003 L4 1
D3
Blue_Led
140.0K
VFB3
1
VFB1
R207
10.0K
31.6K
C15
8
10pf
C272
DC_INPUT
C260
21.5K
R217
14V - 20V
DC Input
2 3
R222
10pf
FM540
100, 1%
E
TBD
D5
R7
12V
C262
DC_INPUT
DC_INPUT
D
R73
J5
CONN JACK PWR
2
1
3
5 6
TK/SS1
R208
PGOOD_2.5V_3.3V 22
TK/SS3
E
2.5V
PGOOD_2.5V_3.3V
5
6
220uF
POWER LED
12V
7
22uF
1
2
3
47uF
2
23
1uF
EXTVCC
C106
EPAD
C83
3
41
C94
SGND
C78
4
1
8
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
21
B-1
of
1
25
8
7
6
5
4
3
2
Power 2
1
VCCA_SHDNn
PGOOD_2.5V_3.3V
VCCA_SHDNn 10
PGOOD_2.5V_3.3V 21
3.3V
E
1.2V_VCCD_PLL
VCCD_PLL
1
L5
R74
0.003
R57
BLM15AG221SN1
U26
7
3
4
9
10
22
23
28
29
24
C284 C285 C282 C283
10uF
10uF
10uF
10uF
D
R109
30.1K
C107
2.2nF
L6
SW
SW
SW
SW
SW
SW
SW
SW
1
2
11
12
20
21
30
31
1
VFB
25
1.2V_VFB
VREF
16
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
SVIN
35
27
R88
5.1K
1.2V
RUN/SS
TRACK
SYNC/MODE
26
6
ITH
RT
8
13
14
15
17
18
19
SGND
PGND
PGND
PGND
PGND
PGND
PGND
PGOOD
PGND
PGND
PGND
PGND
PGND
PGND
GND
0.2uH
C108
R89
5.1K
C92
100uF
1000pF
C62
25V_CSENSE
R53
C95
100uF
0.003
C59
4.7uF
12V
1
3
4.7uF
R90
10.0K
5.0V
VIN
VOUT
ADJ/BYPASS
SHDN
GND
5
4
2
5.0V_CSENSE
R112
D
10.0K
R116
LT1761
C117
4.7uF
3.24K
2.2uF
32
33
34
36
37
38
39
1.8V
C9
3.3V
C
10uF
U4
R6
10.0K
10
7
9
VIN
EN
PGOOD
0.9VREF
C2
1uF
6
C4
REFOUT
TPS51200
0.1uF
VLDOIN
REFIN
2
1
VO
VOSNS
3
5
C
10.0K
R150
0.9VTT
R147
10.0K
C166
10uF
C185
C136
C138
C189
C10
10uF
10uF
10uF
10uF
10uF
C151
1000pF
U10
C26
R158
10uF
2.2M
1.8V_RUN
PGOOD
17
16
SVIN
SW1
SW2
SW3
SW4
8
9
12
13
VFB
19
1.8V_VFB
ITH
18
1.8V_ITH
RT
2
3
SYNC/MODE
4
RUN/SS
C20
6
15
NC1
NC2
LTC3414
21
5
1000pF
PGND
PGND
PGND
PGND
C22
100uF
PVIN
PVIN
1
10
11
20
C23
100uF
B
7
14
EPAD_SGND
SGND
B
1.8V
L2
1.8V_SW
1
0.47uH
2
C14
22pF
R16
R15
A
294K
R10
100K
C30
100uF
C28
100uF
C25
100uF
VCCIO_B7 VCCIO_B8
R20
0.003
R25
0.003
R9
12.4K
C17
C21
470pF
DNI
80.6K
Title
B
Date:
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Size
8
E
R58
9.31K
C129
C123
R54
10.0K
X8
5
C3LS_VCCA
0.003
LTC3418
2.5V
VOUT
ADJ/BYPASS
SHDN
GND
4.7uF
C3LS_VCCINT
R84
2
3
5
4
2
VIN
LT1761
GND_PAD
PGND
GND
PGOOD_2.5V_3.3V
10.0KVCCA_SHDNn
11
4
8
2.5V
2.5V_VCCA
X4
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
22
B-1
of
1
25
8
7
6
5
4
3
2
1
Power Monitor
12V
E
Low Side
2.5V
RSNS SNS
V9
SENSE_PAD
2
1
4.7uF
V10
1
2
1
D
2
V11 SENSE_PAD
RSNS SNS 2
V6
1
2
SENSE_PAD
2
2
SENSE_PAD
RSNS SNS 2
V2
1
1.8V
V3
1
2
SENSE_PAD
2
RSNS SNS
SENSE_PAD
C3LS_VCCINT V17
1 RSNS SNS
2
V18 SENSE_PAD
1 RSNS SNS 2
1.2V
SENSE_PAD
VCCD_PLL
V15
1 RSNS SNS
2
1.2V_VCCD_PLL V16 SENSE_PAD
1 RSNS SNS 2
B
SENSE_PAD
C3LS_VCCA
V8
1 RSNS SNS
2.5V_VCCA
SENSE_PAD
RSNS SNS 2
V7
1
R4
10.0K
= 5.37V
R5
2.94K
C1
4.7uF
5V_MONITOR
C154
0.1uF
U1
VCCIO_B1B2_P
VCCIO_B1B2_N
21
22
CH0
CH1
VCCIO_B3B4_P
VCCIO_B3B4_N
23
24
CH2
CH3
VCCIO_B5B6_P
VCCIO_B5B6_N
25
26
CH4
CH5
VCCIO_B7_P
VCCIO_B7_N
27
28
CH6
CH7
VCCIO_B8_P
VCCIO_B8_P
VCCIO_B8_N
1
2
CH8
CH9
VCCIO_B8_N
C3LS_VCCINT_P
C3LS_VCCINT_N
3
4
CH10
CH11
C3LS_VCCINT_P
VCCD_PLL_P
VCCD_PLL_N
5
6
CH12
CH13
C3LS_VCCINT_N
C3LS_VCCA_P
C3LS_VCCA_N
7
8
CH14
CH15
NC1
NC2
13
14
10
COM
GND
15
VCCIO_B7_P
VCC
9
REF+
11
REF-
12
F0
19
SDO
SDI
SCK
CSn
17
20
18
16
C3
10uF
R145
0
REF=5.37V
R144
DNI
SENSE5_ADC_F0
R143
0
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
SENSE5_CS0n
C
R146
DNI
LTC2418
VCCD_PLL_P
VCCD_PLL_N
2
D
5V_MONITOR
A/D #0
VCCIO_B5B6_P
VCCIO_B7_N
SENSE_PAD
VCCIO_B8
V4
1 RSNS SNS
C
5V_CSENSE
VCCIO_B3B4_P
VCCIO_B5B6_N
RSNS SNS
SENSE_PAD
VCCIO_B7
V1
1 RSNS SNS
1.8V
5
4
2
LT1761
VCCIO_B1B2_P
VCCIO_B3B4_N
SENSE_PAD
VCCIO_B5B6
V5
1 RSNS SNS
2.5V
VOUT
ADJ/BYPASS
SHDN
GND
VCCIO_B1B2_N
RSNS SNS
SENSE_PAD
VCCIO_B3B4
V12
1 RSNS SNS
2.5V
3
VIN
R136
R138
R137
R135
VCCIO_B1B2
1
C5
10K
10K
10K
10K
High Side
E
5V_MONITOR
X1
2.5V
C3LS_VCCA_P
5V_MONITOR
U3
14 VCC
SENSE5_ADC_F0
13 IO VCC1
SENSE5_SDO
12 IO VCC2
SENSE5_SDI
11 IO VCC3
SENSE5_SCK
10 IO VCC4
9 NC2
R141
10.0K
8 /TS
2.5V
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
SENSE_ADC_F0
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_ADC_F0 10
SENSE_SDO 10
SENSE_SDI 10
SENSE_SCK 10
B
MAX3378
C3LS_VCCA_N
SENSE_PAD
2.5V
5V_MONITOR
U2
14 VCC
SENSE5_CS0n
13 IO VCC1
12 IO VCC2
11 IO VCC3
10 IO VCC4
9 NC2
R142
10.0K
8 /TS
2.5V
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
SENSE_CS0n
SENSE_CS0n 10
MAX3378
12V
J3
1
2
A
DNI
Title
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Tuesday, September 15, 2009
2
Sheet
23
B-1
of
1
25
C
B
NC0
NC1
NC2
A
EP3CLS200
EP3CLS200F780
GNDA1
GNDA2
GNDA3
GNDA4
D
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Cyclone III LS
R1
R4
G15
E
AA11
AA13
AA15
AA19
AA21
AB15
AB21
G21
H10
H12
H14
H16
H18
H20
H8
J11
J13
J15
J17
J19
J21
J9
K10
K12
K14
K16
K18
K20
K8
L11
L13
L15
L17
L19
L21
L7
L9
M10
M12
M14
M16
M18
M20
M22
M8
N11
N13
N15
N17
N19
N21
N7
N9
P10
P12
P14
P16
P18
P20
P8
R11
R13
R15
R17
R19
R21
R5
R6
R7
R9
T10
T12
T14
T16
T18
T20
T22
T8
U11
U13
U15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5
4
3
Cyclone III LS Power
U19
U21
U7
U9
V10
V12
V14
V16
V18
V20
V22
V8
W11
W13
W15
W17
W19
W21
W9
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y8
R2
B1
F2
H4
L2
N4
V2
Y4
AC2
AG1
AG3
AD5
AG7
AD8
AG10
AD11
AD13
AG14
AE15
AG17
AG19
AD18
AD20
AD23
AG23
AG26
AG28
AC27
Y25
V27
T25
N25
L27
H25
F27
B28
B17
B20
B23
B26
E15
E18
E20
E23
B3
B6
B10
B14
E6
E9
E11
E13
U17
2
SRAM_DQP[3:0]
SRAM_DQP[3:0]
FSM_A[25:0]
MAX2_CLK
AA10
AA12
AA14
AA16
AA18
AA20
H11
H13
H15
H17
H19
H21
H9
J10
J12
J14
J16
J18
J20
J22
J8
K11
K13
K15
K17
K19
K21
K7
K9
L10
L12
L14
L16
L18
L20
L22
L8
M11
M13
M15
M17
M19
M21
M7
M9
N10
N12
N14
N16
N18
N20
N8
P11
P13
P15
Cyclone III LS, Power
C3LS_VCCINT
EP3CLS200
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
P17
P19
P21
P7
P9
R10
R12
R14
R16
R18
R20
R22
R8
T11
T13
T15
T17
T19
T21
T7
T9
U10
U12
U14
U16
U18
U20
U22
U6
U8
V11
V13
V15
V17
V19
V21
V7
V9
W10
W12
W14
W16
W18
W20
W22
W8
Y11
Y13
Y15
Y17
Y19
Y21
Y7
Y9
U15J
VCCIO_B1B2
HSMB_SCL
HSMB_D23
HSMB_D10
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VREFB5N0
VREFB5N1
VREFB5N2
AC26
AG27
T24
V26
Y24
T23
U27
AC25
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VREFB2N0
VREFB2N1
VREFB2N2
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VREFB6N0
VREFB6N1
VREFB6N2
AC11
AC13
AC5
AC8
AF10
AF14
AF3
AF7
AF12
AE11
AF8
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VREFB3N0
VREFB3N1
VREFB3N2
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VREFB7N0
VREFB7N1
VREFB7N2
C17
C20
C23
C26
F15
F18
F20
F23
D24
A24
C16
AC18
AC20
AC23
AD15
AF17
AF19
AF23
AF26
AE24
AD19
AD16
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VREFB4N0
VREFB4N1
VREFB4N2
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VREFB8N0
VREFB8N1
VREFB8N2
C10
C14
C3
C6
F11
F13
F6
F9
A14
G11
E10
D33
1N6263-W
BT1
6,7,8,15,16
ETHERNET INTERFACE
ENET_INTn
ENET_INTn 13
D
AA7
H23
H7
AA22
VCCA1
VCCA2
VCCA3
VCCA4
VCCD_PLL1
VCCD_PLL2
VCCD_PLL3
VCCD_PLL4
AB8
G22
G8
AB23
ENET_INTn
0.9VREF
C
DDR2_B7_A10
VCCIO_B8
0.9VREF
DDR2_B8_A10
VCCD_PLL
AC7
B
VCCBAT
EP3CLS200F780
VCCBAT
EP3CLS200F780
DDR2_B8_A[15:0]
VCCIO_B7
VCCIO_B3B4
D32
1N6263-W
6,15,16
VCCIO_B5B6
C27
F26
H24
L26
N24
J23
M24
N23
VCCIO_B3B4
2.5V
DDR2_B7_A[15:0]
VCCIO_B5B6
AC3
AF2
R3
V3
Y5
U5
V5
AB5
HSMB_D9
LCD_HSMB_D72
HSMB_D53
MAX2_CLK
SRAM_DQP0
FSM_D31
C3LS_VCCA
E
HSMB_SCL 17
DDR2_B8_A[15:0]
VCCIO_B1B2
FSM_A16
FSM_A21
FSM_D18
3,19
DDR2 SDRAM BANK 8 SIGNALS
Cyclone III LS, IO Power
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VREFB1N0
VREFB1N1
VREFB1N2
LCD_HSMB_D[75:65]
DDR2_B7_A[15:0]
MAX2_CLK 10
EP3CLS200
C2
F3
H5
L3
N5
J5
J3
K4
3,17,19
DDR2 SDRAM BANK 7 SIGNALS
MAXII CONTROL INTERFACE
U15I
HSMB_D[75:0]
HSMA_SCL
FSM_A[25:0] 4,8,10,11
C155
0.1uF
20mm Coin Cell
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Battery
Title
Size
Date:
7
HSMB_D[75:0]
FSM_D[31:0] 4,8,10,11
B
8
HSMB SIGNALS
4,11
LCD_HSMB_D[75:65]
FSM_D[31:0]
C3LS_VCCINT
1
SSRAM INTERFACE
SHARED BUS
AB7
H22
G7
AB22
U15K
6
1
POS
7
2
NEG
8
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
24
B-1
of
1
25
8
7
6
5
4
3
2
1
Decoupling
Cyclone III LS VCCINT
C3LS_VCCINT
C3LS_VCCA
Cyclone III LS VCCA
E
C219
C3LS_VCCINT
4.7nF
C211
10nF
10nF
C204
4.7nF
C239
4.7nF
C186
C230
10nF
4.7nF
C231
10nF
10nF
C241
C243
4.7nF
4.7nF
C240
C242
22nF
22nF
C192
C187
4.7nF
4.7nF
C188
C201
22nF
47nF
C193
+
4.7nF
C49
470uF
10V
Tantalum
C3LS_VCCINT
47nF
220nF
1uF
1uF
Cyclone III LS VCCD PLL
+
4.7uF
C43
470uF
10V
Tantalum
1
C218
+
100nF
+
C70
470uF
10V
Tantalum VCCIO_B3B4
C251
+
100nF
C35
470uF
10V
Tantalum VCCIO_B5B6
VCCIO_B7
C29
470uF
10V
Tantalum
C216
+
100nF
C199
VCCD_PLL
Cyclone III LS VCCIO Bank 7
1
Cyclone III LS VCCIO Bank 5 & 6
1
1
C225
VCCIO_B5B6
2
C53
470uF
10V
Tantalum VCCIO_B1B2
Cyclone III LS VCCIO Bank 3 & 4
2
C
2
+
VCCIO_B3B4
2
Cyclone III LS VCCIO Bank 1 & 2
1
VCCIO_B1B2
100nF
1
C255
2
100nF
C198
2
D
C220
C3LS_VCCA
C229
VCCD_PLL
C232
C238
C27
470uF
10V
Tantalum VCCIO_B7
C200
100nF
D
100nF
VCCIO_B8
Cyclone III LS VCCIO Bank 8
1
4.7nF
C223
+
2
C3LS_VCCINT
C205
2
C224
1
E
C34
470uF
10V
Tantalum VCCIO_B8
C208
100nF
C
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Cyclone III LS FPGA Development Board
Copyright (c) 2009, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320911-B1
Thursday, September 10, 2009
2
Sheet
25
B-1
of
1
25
Similar pages