DK-START-5AGXB3N Starter Kit Schematic

8
7
6
5
4
NOTES:
E
1. Project Drawing Numbers:
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic Drawing
PCB Film
Bill of Materials
Schematic Design Files
Functional Specification
PCB Layout Guidelines
Assembly Rework
2.
Known Issue List:
(1) Full duplex x8 transceivers @ 6G interface at HSMC connector can not be compiled in the same
Quartus II project. Up to x7 transceivers @ 6G can be compiled at in one Quartus II project.
(2) LVDS channels in bank 2 and bank 3 of HSMC connector with total of 17 channels can not be
compiled in the same Quartus II project. LVDS channels in HSMC bank 2 needs clock source from
bottom banks while bank 3 needs clock source from top banks of FPGA.
100-0320806-C1
110-0320806-C1
120-0320806-C1
130-0320806-C1
140-0320806-C1
150-0320806-C1
160-0320806-C1
170-0320806-C1
180-0320806-C1
210-0320806-C1
220-0320806-C1
320-0320806-C1
3
REV
DATE
A
B
C
C1.1
13 Dec 2011
4 April 2012
6 July 2012
21 Sept 2012
2
PAGES
1
DESCRIPTION
All
All
All
1 - 3, 23
INITIAL REVISION A RELEASE
INITIAL REVISION B RELEASE
INITIAL REVISION C RELEASE
Update know issues list and block diagram. Edited MDIO bus CAD note
E
1011 Parts, 187 Library Parts, 982 Nets, 4837 Pins
Arria V GX Starter Kit Board
D
C
DESCRIPTION
DESCRIPTION
1
Title, Notes, Block Diagram, Rev. History
30
Power 5 - Linear Regulator
2
FPGA Package Top
31
Power 6 - Power Monitor
3
System Block Diagram
32
Power 7 - Arria V GX Power
4
Power Tree
33
Power 8 - Arria V GX GND
5
Clock Tree
PCI Express Edge Connector
34
Arria V GX Decoupling
6
35
Arria V GX Decoupling
7
Arria V GX Bank 3
8
Arria V GX Bank 4
9
Arria V GX Bank 7
10
Arria V GX Bank 8
11
Arria V GX Transceiver Banks
12
Arria V GX Configuration
13
Arria V GX Clocks
PLL
14
B
PAGE
PAGE
C
15
JTAG
16
17
DDR3 SDRAM
Flash
18
SRAM
19
20
5M2210 System Controller
HDMI
21
SDI TX/RX Cable Driver & SMB
22
HSMC Port
23
Ethernet PHY & RJ-45
24
26
On-Board USB Blaster II
User I/O (LEDs, Buttons, Switches, LCD)
Power 1 - DC Input, 12V, 3.3V
25
D
B
27
Power 2 - 1.1V & 2.5V FPGA
28
Power 3 - 1.15V & 1.5V FPGA
29
Power 4 - 2.5V
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
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Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
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C1.1
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FPGA Package Top View
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Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
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Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
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C1.1
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Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
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of
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Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
C1.1
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
4
of
1
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5
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Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
5
4
3
2
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
C1.1
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
Sheet
1
5
of
35
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1
PCI Express x8 Edge Connector
Link Width DIP Switch
E
12V_PCIE
12V_PCIE
SW1
J1
PCIE_SMBCLK
PCIE_SMBDAT
PCIE_WAKEn
R2
R3
D
3.3V_PCIE_AUX
DNI
DNI PCIE_WAKEn_R
B12
B13
B14
B15
B16
B17
B18
PCIE_RX_P0
PCIE_RX_N0
PCIE_PRSNT2n_x1
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
PCIE_RX_P1
PCIE_RX_N1
PCIE_RX_P2
PCIE_RX_N2
PCIE_RX_P3
PCIE_RX_N3
PCIE_PRSNT2n_x4
C
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
PCIE_RX_P4
PCIE_RX_N4
PCIE_RX_P5
PCIE_RX_N5
PCIE_RX_P6
PCIE_RX_N6
PCIE_RX_P7
PCIE_RX_N7
PCIE_PRSNT2n_x8
B
B3
E
3.3V_PCIE
+12V
+12V
+12V
GND
SMCLK
SMDAT
GND
+3_3V
JTAG_TRSTN
+3_3VAUX
WAKE_N
KEY
PRSNT1_N
+12V
+12V
GND
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
+3_3V
+3_3V
PERST_N
RSVD1
GND
X1
GND
REFCLK+
PET0P
REFCLKPET0N
GND
GND
PER0P
PRSNT2_N_X1
PER0N
GND
GND
PET1P
X4
PET1N
GND
GND
PET2P
PET2N
GND
GND
PET3P
PET3N
GND
RSVD3
PRSNT2_N_X4
GND
RSVD2
GND
PER1P
PER1N
GND
GND
PER2P
PER2N
GND
GND
PER3P
PER3N
GND
RSVD4
PET4P
X8
PET4N
GND
GND
PET5P
PET5N
GND
GND
PET6P
PET6N
GND
GND
PET7P
PET7N
GND
PRSNT2_N_X8
GND
RSVD5
GND
PER4P
PER4N
GND
GND
PER5P
PER5N
GND
GND
PER6P
PER6N
GND
GND
PER7P
PER7N
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
1
2
3
4
PCIE_PRSNT1n
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
8
7
6
5
OPEN
3.3V_PCIE
PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x4
PCIE_PRSNT2n_x8
FAN_FORCE_ON
2.5V
R1
10K
Switch, DIP x4, TDA04H0SB1
PCIE_PERSTn
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_TX_CP0
PCIE_TX_CN0
0.1uF
0.1uF
C1
C2
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_CP1
PCIE_TX_CN1
0.1uF
0.1uF
C3
C4
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_CP2
PCIE_TX_CN2
0.1uF
0.1uF
C5
C6
PCIE_TX_P2
PCIE_TX_N2
D
MAX V Interface
FAN_FORCE_ON
19
FPGA Interface
PCIE_TX_P[7:0]
11
PCIE_TX_N[7:0]
11
PCIE_RX_P[7:0]
11
PCIE_RX_N[7:0]
PCIE_TX_CP3
PCIE_TX_CN3
0.1uF
0.1uF
C7
C8
PCIE_TX_P3
PCIE_TX_N3
11
PCIE_REFCLK_P
11
C
PCIE_REFCLK_N
11
PCIE_PERSTn
12
PCIE_TX_CP4
PCIE_TX_CN4
0.1uF
0.1uF
C9
C10
PCIE_TX_P4
PCIE_TX_N4
PCIE_JTAG_TCK
PCIE_TX_CP5
PCIE_TX_CN5
0.1uF
0.1uF
C11
C12
PCIE_TX_P5
PCIE_TX_N5
PCIE_JTAG_TDO
15
PCIE_JTAG_TMS
15
PCIE_TX_CP6
PCIE_TX_CN6
0.1uF
0.1uF
C13
C14
PCIE_TX_P6
PCIE_TX_N6
15
PCIE_JTAG_TDI
15
PCIE_SMBCLK
9
PCIE_SMBDAT
PCIE_TX_CP7
PCIE_TX_CN7
0.1uF
0.1uF
C15
C16
9
PCIE_WAKEn
PCIE_TX_P7
PCIE_TX_N7
9
B
PCIe x8 Edge Finger
PCI BRACKET
Design Note:
Custom PCI bracket
12V_PCIE
C17
0.1uF
3.3V_PCIE
C18
0.1uF
C19
0.1uF
C20
0.1uF
C21
0.1uF
C22
0.1uF
C23
0.1uF
C24
0.1uF
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
6
of
1
35
8
7
6
5
4
3
2
1
Arria V GX Bank 3
U1C
SRAM, Flash, MAX V Interface
Arria V GX Bottom IO Bank 3
E
Bank 3A
FSM_D11
FSM_D10
FSM_D28
FSM_D29
FSM_D16
FSM_D14
FSM_D15
FSM_D13
FSM_D25
FSM_D23
FSM_D30
FSM_D31
FSM_D26
FSM_D24
FSM_D5
AH27
AG27
AP28
AP27
AL27
AK27
AK26
AJ26
AM26
AL26
AP26
AP25
AM25
AL25
AF28
FSM_D[31:0]
2.5V
DIFFIO_RX_B11P/DQS2B/CQ2B/CAS#_3A
DIFFIO_RX_B11n/DQSN2B/CQN2B/WE#_3A
DIFFIO_RX_B13P/DQ2B/BA_3A_0
DIFFIO_RX_B13N/DQ2B/BA_3A_1
DIFFIO_RX_B15P/DQ2B/A_3A_12
DIFFIO_RX_B15N/DQ2B/A_3A_13
DIFFIO_RX_B17P/DQ3B/A_3A_8
DIFFIO_RX_B17N/DQ3B/A_3A_9
DIFFIO_RX_B19P/DQS3B/CQ3B/A_3A_4
DIFFIO_RX_B19N/DQSN3B/CQN3B/A_3A_5
DIFFIO_RX_B21P/DQ3B/A_3A_0
DIFFIO_RX_B21N/DQ3B/A_3A_1
DIFFIO_RX_B23P/DQ3B/CK_3A
DIFFIO_RX_B23N/DQ3B/CK#_3A
DQ1B
D
DIFFIO_TX_B1P/DQ1B
DIFFIO_TX_B1N/RZQ_0
DIFFIO_TX_B3P/DQ1B
DIFFIO_TX_B3N
DIFFIO_TX_B8P/DQ2B/CS#_3A_0
DIFFIO_TX_B8N/CS#_3A_1
DIFFIO_TX_B10P/DQ2B/ODT_3A_0
DIFFIO_TX_B10N/ODT_3A_1
DIFFIO_TX_B12P/DQ2B/BA_3A_2
DIFFIO_TX_B12N/RAS#_3A
DIFFIO_TX_B14P/DQ2B/A_3A_14
DIFFIO_TX_B14N/A_3A_15
DIFFIO_TX_B16P/DQ3B/A_3A_10
DIFFIO_TX_B16N/A_3A_11
DIFFIO_TX_B18P/DQ3B/A_3A_6
DIFFIO_TX_B18N/A_3A_7
DIFFIO_TX_B20P/DQ3B/A_3A_2
DIFFIO_TX_B20N/A_3A_3
DIFFIO_TX_B22P/DQ3B/CKE_3A_0
DIFFIO_TX_B22N/CKE_3A_1
AM31
AL31
AD26
AD27
AM29
AL29
AF29
AE29
AM28
AL28
AH29
AG29
AH26
AG26
AE28
AD29
AN26
AN27
AF26
AE26
FSM_D20
2.5V_OCT_RZQ
FSM_D1
FSM_D0
FSM_D21
FSM_D18
FSM_D4
FSM_D19
FSM_D22
FSM_D17
FSM_D9
FSM_D7
FSM_D12
FSM_D8
FSM_D3
R316
1%
C
AC25
AC24
AE25
AD24
AH25
AH24
AK24
AJ25
AG23
AF23
AJ23
AH23
AN24
AN23
AP23
AP22
AB24
DIFFIO_RX_B25P/DQ4B/DQ1_3B_6 2.5V
DIFFIO_RX_B25N/DQ4B/DQ1_3B_7
DIFFIO_RX_B27P/DQS4B/CQ4B/DQS1_3B
DIFFIO_RX_B27N/DQSN4B/CQN4B/DQS#1_3B
DIFFIO_RX_B29P/DQ4B/DQ1_3B_3
DIFFIO_RX_B29N/DQ4B/DQ1_3B_4
DIFFIO_RX_B30P/DQ4B/DQ1_3B_0
DIFFIO_RX_B30N/DQ4B/DQ1_3B_1
DIFFIO_RX_B32P/DQ5B/DQ2_3B_6
DIFFIO_RX_B32N/DQ5B/DQ2_3B_7
DIFFIO_RX_B34P/DQS5B/CQ5B/DQS2_3B
DIFFIO_RX_B34N/DQSN5B/CQN5B/DQS#2_3B
DIFFIO_RX_B36P/DQ5B/DQ2_3B_3
DIFFIO_RX_B36N/DQ5B/DQ2_3B_4
DIFFIO_RX_B38P/DQ5B/DQ2_3B_0
DIFFIO_RX_B38N/DQ5B/DQ2_3B_1
17,19
FLASH_CEn[1:0]
17,19
FLASH_OEn
17,19
FLASH_RESETn
17,19
FLASH_WEn
17,19
FLASH_CLK
17,19
FLASH_ADVn
17,19
FSM_D27
SRAM_BWn[3:0]
FSM_D6
FSM_D2
18
SRAM_CEn
AE24
AE23
AB25
AA25
AG24
AF25
AL24
AK23
AD23
AC23
AM23
AL23
AB23
AA23
FSM_A19
FSM_A20
18
SRAM_OEn
18
SRAM_ADSCn
FSM_A15
FSM_A17
FSM_A6
FSM_A8
SDI_RX_EN
SDI_CLK148_UP
FSM_A4
FSM_A5
SDI_CLK148_DN
18
SRAM_CLK
18
SRAM_MODE
18
SRAM_GWn
18
SRAM_ADSPn
18
SRAM_ADVn
18
C
SRAM_ZZ
18
SRAM_DQP[3:0]
DQ4B/DQ1_3B_2
D
18
SRAM_BWEn
DIFFIO_TX_B24P/DQ4B/DQ1_3B_8
DIFFIO_TX_B24N/RESET#_3A
DIFFIO_TX_B26P/DQ4B/DM1_3B
DIFFIO_TX_B26N
DIFFIO_TX_B28P/DQ4B/DQ1_3B_5
DIFFIO_TX_B28N
DIFFIO_TX_B31P/DQ5B/DQ2_3B_8
DIFFIO_TX_B31N
DIFFIO_TX_B33P/DQ5B/DM2_3B
DIFFIO_TX_B33N
DIFFIO_TX_B35P/DQ5B/DQ2_3B_5
DIFFIO_TX_B35N
DIFFIO_TX_B37P/DQ5B/DQ2_3B_2
DIFFIO_TX_B37N
E
17,18,19
FLASH_RDYBSYn[1:0]
Bank 3B
SDI_TX_SD_HDn
SDI_TX_EN
FSM_A18
SDI_RX_BYPASS
FSM_A13
FSM_A12
FSM_A7
FSM_A10
FSM_A14
FSM_A16
FSM_A9
FSM_A11
FSM_A3
FSM_A2
FSM_A1
FSM_A0
17,18,19
FSM_A[26:0]
100
18
Bank 3C
FLASH_OEn
B
FLASH_RESETn
FLASH_WEn
FLASH_CEn0
FLASH_CLK
FSM_A22
FSM_A25
FSM_A21
FSM_A23
FSM_A24
FSM_A26
FLASH_RDYBSYn0
FLASH_RDYBSYn1
SRAM_DQP0
SRAM_DQP1
AL22
AL21
AH22
AH21
AK21
AJ22
AN21
AM22
AP20
AN20
AM20
AL20
AH20
AG20
AF20
AE20
AD20
DIFFIO_RX_B40P/DQ6B/DQ3_3C_6 2.5V
DIFFIO_RX_B40N/DQ6B/DQ3_3C_7
DIFFIO_RX_B42P/DQS6B/CQ6B/DQS3_3C
DIFFIO_RX_B42N/DQSN6B/CQN6B/DQS#3_3C
DIFFIO_RX_B44P/DQ6B/DQ3_3C_3
DIFFIO_RX_B44N/DQ6B/DQ3_3C_4
DIFFIO_RX_B46P/DQ6B/DQ3_3C_0
DIFFIO_RX_B46N/DQ6B/DQ3_3C_1
DIFFIO_RX_B48P/DQ7B/DQ4_3C_6
DIFFIO_RX_B48N/DQ7B/DQ4_3C_7
DIFFIO_RX_B50P/DQS7B/CQ7B/DQS4_3C
DIFFIO_RX_B50N/DQSN7B/CQN7B/DQS#4_3C
DIFFIO_RX_B52P/DQ7B/DQ4_3C_3
DIFFIO_RX_B52N/DQ7B/DQ4_3C_4
DIFFIO_RX_B53P/DQ7B/DQ4_3C_0
DIFFIO_RX_B53N/DQ7B/DQ4_3C_1
DIFFIO_TX_B39P/DQ6B/DQ3_3C_8
DIFFIO_TX_B39N
DIFFIO_TX_B41P/DQ6B/DM3_3C
DIFFIO_TX_B41N
DIFFIO_TX_B43P/DQ6B/DQ3_3C_5
DIFFIO_TX_B43N
DIFFIO_TX_B45P/DQ6B/DQ3_3C_2
DIFFIO_TX_B45N
DIFFIO_TX_B47P/DQ7B/DQ4_3C_8
DIFFIO_TX_B47N
DIFFIO_TX_B49P/DQ7B/DM4_3C
DIFFIO_TX_B49N
DIFFIO_TX_B51P/DQ7B/DQ4_3C_5
DIFFIO_TX_B51N
AE22
AE21
AC22
AB22
AG21
AF22
AB21
AA21
AD21
AC21
AB20
AA20
AK20
AJ20
SRAM_DQP2
SRAM_DQP3
On-board USB Blaster II Interface
USB_SCL
SRAM_MODE
SRAM_GWn
AM19
AL19
AP19
AN18
AL18
AK18
AA18
24
USB_WRn
24
SRAM_ZZ
SDI Interface
FLASH_CEn1
FLASH_ADVn
19,21
SDI_RX_BYPASS
DQ7B/DQ4_3C_2
DIFFIO_RX_B71P/DQ8B
DIFFIO_RX_B71N/DQ8B
DIFFIO_RX_B73P/DQS8B/CQ8B
DIFFIO_RX_B73N/DQSN8B/CQN8B
DIFFIO_RX_B75P/DQ8B
DIFFIO_RX_B75N/DQ8B
19,21
SDI_TX_SD_HDn
2.5V
DIFFIO_TX_B70P/DQ8B
DIFFIO_TX_B70N
DIFFIO_TX_B72P/DQ8B
DIFFIO_TX_B72N
DIFFIO_TX_B74P/DQ8B
DIFFIO_TX_B74N
DIFFIO_TX_B77P/DQ9B
DIFFIO_TX_B77N
DIFFIO_TX_B81P/DQ9B
DIFFIO_TX_B81N
DIFFIO_TX_B83P/DQ9B
DIFFIO_TX_B83N
DQ8B
AJ19
AH19
AC19
AB19
AF19
AE19
AP17
AN17
AM17
AL17
AC18
AC17
USB_SCL
USB_RDn
14
SDI_CLK148_DN
14
SRAM_ADSPn
SRAM_ADVn
SRAM_BWEn
SRAM_BWn2
SRAM_BWn0
SRAM_OEn
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Version 2.0 Pin Out
Size
B
Date:
6
21
SDI_CLK148_UP
5AGXFB3H4F35
7
19,21
SDI_TX_EN
A
8
B
SDI_RX_EN
Bank 3D
SRAM_BWn1
SRAM_CEn
SRAM_ADSCn
SRAM_BWn3
SRAM_CLK
USB_WRn
24
USB_RDn
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
7
of
1
35
8
7
6
5
4
3
Arria V GX Bank 4
2
HSMC Port Interface
HSMA_TX_D_P[6:0]
22
HSMA_TX_D_N[6:0]
Arria V GX Bottom IO Bank 4
AL6
DQ16B
2.5V
Bank 4B
D
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMA_D0
HSMA_D1
HSMA_RX_D_P1
HSMA_RX_D_N1
HSMA_D2
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMA_SDA
HSMA_SCL
HSMA_D3
FX2_RESETn
AN11
AM11
AP11
AP10
AJ10
AH10
AN8
AN9
AH9
AG9
AM8
AL8
AK8
AJ8
AH8
AG8
DIFFIO_TX_B163P/DQ17B
DIFFIO_TX_B163N
DIFFIO_TX_B165P/DQ17B
DIFFIO_TX_B165N
DIFFIO_TX_B167P/DQ17B/RZQ_1
DIFFIO_TX_B167N
2.5V
DIFFIO_RX_B124P/DQ14B/DQ3_4B_6
DIFFIO_TX_B123P/DQ14B/DQ3_4B_8
DIFFIO_RX_B124N/DQ14B/DQ3_4B_7
DIFFIO_TX_B123N
DIFFIO_RX_B126P/DQS14B/CQ14B/DQS3_4B
DIFFIO_TX_B125P/DQ14B/DM3_4B
DIFFIO_RX_B126N/DQSN14B/CQN14B/DQS#3_4B
DIFFIO_TX_B125N
DIFFIO_RX_B128P/DQ14B/DQ3_4B_3
DIFFIO_TX_B127P/DQ14B/DQ3_4B_5
DIFFIO_RX_B128N/DQ14B/DQ3_4B_4
DIFFIO_TX_B127N
DIFFIO_RX_B130P/DQ14B/DQ3_4B_0
DIFFIO_TX_B129P/DQ14B/DQ3_4B_2
DIFFIO_RX_B130N/DQ14B/DQ3_4B_1
DIFFIO_TX_B129N
DIFFIO_RX_B132P/DQ15B/DQ4_4B_6
DIFFIO_TX_B131P/DQ15B/DQ4_4B_8
DIFFIO_RX_B132N/DQ15B/DQ4_4B_7
DIFFIO_TX_B131N
DIFFIO_RX_B134P/DQS15B/CQ15B/DQS4_4B
DIFFIO_TX_B133P/DQ15B/DM4_4B
DIFFIO_RX_B134N/DQSN15B/CQN15B/DQS#4_4B
DIFFIO_TX_B133N
DIFFIO_RX_B136P/DQ15B/DQ4_4B_3
DIFFIO_TX_B135P/DQ15B/DQ4_4B_5
DIFFIO_RX_B136N/DQ15B/DQ4_4B_4
DIFFIO_TX_B135N
DIFFIO_RX_B137P/DQ15B/DQ4_4B_0
DIFFIO_RX_B137N/DQ15B/DQ4_4B_1
DQ15B/DQ4_4B_2
22
HSMA_RX_D_N[7:0]
Bank 4A
HSMA_CLK_OUT0
22
HSMA_RX_D_P[7:0]
U1D
E
AJ6
AH6
AC6
AC7
AM4
AM3
AE9
AD9
AM10
AL10
AB10
AA10
AL9
AK9
AC10
AC9
AF10
AE10
AD8
AC8
AF8
HSMA_D[3:0]
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_TX_D_P6
HSMA_TX_D_N6
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P0
HSMA_TX_D_N0
C
ENET_RX_P
ENET_RX_N
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMA_RX_D_P6
HSMA_RX_D_N6
ENET_RX_D1
ENET_RX_D3
ENET_RX_D2
ENET_GTX_CLK
ENET_INTn
ENET_RX_D0
AP14
AN14
AM13
AL13
AL12
AK12
AJ13
AH13
AH12
AG12
AF13
AE13
AE12
AD12
AG11
AF11
2.5V
DIFFIO_RX_B109P/DQ12B/DQ1_4C_6
DIFFIO_TX_B108P/DQ12B/DQ1_4C_8
DIFFIO_RX_B109N/DQ12B/DQ1_4C_7
DIFFIO_TX_B108N/RESET#_4D
DIFFIO_RX_B111P/DQS12B/CQ12B/DQS1_4C
DIFFIO_TX_B110P/DQ12B/DM1_4C
DIFFIO_RX_B111N/DQSN12B/CQN12B/DQS#1_4C
DIFFIO_TX_B110N
DIFFIO_RX_B113P/DQ12B/DQ1_4C_3
DIFFIO_TX_B112P/DQ12B/DQ1_4C_5
DIFFIO_RX_B113N/DQ12B/DQ1_4C_4
DIFFIO_TX_B112N
DIFFIO_RX_B114P/DQ12B/DQ1_4C_0
DIFFIO_TX_B115P/DQ13B/DQ2_4C_8
DIFFIO_RX_B114N/DQ12B/DQ1_4C_1
DIFFIO_TX_B115N
DIFFIO_RX_B116P/DQ13B/DQ2_4C_6
DIFFIO_TX_B117P/DQ13B/DM2_4C
DIFFIO_RX_B116N/DQ13B/DQ2_4C_7
DIFFIO_TX_B117N
DIFFIO_RX_B118P/DQS13B/CQ13B/DQS2_4C DIFFIO_TX_B119P/DQ13B/DQ2_4C_5
DIFFIO_RX_B118N/DQSN13B/CQN13B/DQS#2_4C
DIFFIO_TX_B119N
DIFFIO_RX_B120P/DQ13B/DQ2_4C_3
DIFFIO_TX_B121P/DQ13B/DQ2_4C_2
DIFFIO_RX_B120N/DQ13B/DQ2_4C_4
DIFFIO_TX_B121N
DIFFIO_RX_B122P/DQ13B/DQ2_4C_0
DIFFIO_RX_B122N/DQ13B/DQ2_4C_1
DQ12B/DQ1_4C_2
E
22
22
HSMA_CLK_OUT_P1
22
HSMA_CLK_OUT_N1
22
HSMA_SCL
22
HSMA_SDA
22
HSMA_CLK_OUT0
22
Ethernet PHY Interface
HSMA_TX_D_P1
HSMA_TX_D_N1
ENET_TX_P
23
ENET_TX_N
HDMI_FPGA_OE_N
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
D
23
ENET_RX_P
23
ENET_RX_N
23
ENET_RESETn
23
HDMI_FPGA_HPD
ENET_MDC
23
ENET_MDIO
Bank 4C
1
23
AC13
AB13
AP13
AN12
AA12
Y11
AB12
AB11
AJ11
AH11
AC12
AC11
AE11
AD11
ENET_TX_D2
ENET_RX_DV
ENET_TX_P
ENET_TX_N
ENET_INTn
ENET_TX_EN
ENET_TX_D3
ENET_MDC
ENET_MDIO
ENET_TX_D1
ENET_TX_D0
HDMI_FPGA_SCL_DDC
HDMI_FPGA_SDA_DDC
ENET_GTX_CLK
23
ENET_TX_EN
23
ENET_RX_DV
23
AL11
ENET_RESETn
23
ENET_TX_D[3:0]
23
ENET_RX_D[3:0]
23
C
On-board USB Blaster II Interface
USB_ADDR[1:0]
24
USB_DATA[7:0]
24
Bank 4D
USB_FULL
USB_EMPTY
B
USB_DATA2
USB_DATA4
USB_DATA3
USB_DATA6
USB_DATA5
USB_OEn
USB_ADDR0
USB_CLK
AJ16
AH16
AA15
Y15
AM16
AL16
AM14
AL14
AL15
AK15
AH15
AG15
AF14
AE14
AD14
AC14
2.5V
DIFFIO_RX_B94P/DQ10B
DIFFIO_TX_B93P/DQ10B/CS#_4D_0
DIFFIO_RX_B94N/DQ10B
DIFFIO_TX_B93N/CS#_4D_1
DIFFIO_RX_B96P/DQS10B/CQ10B/CAS#_4D
DIFFIO_TX_B95P/DQ10B/ODT_4D_0
DIFFIO_RX_B96N/DQSN10B/CQN10B/WE#_4D
DIFFIO_TX_B95N/ODT_4D_1
DIFFIO_RX_B98P/DQ10B/BA_4D_0
DIFFIO_TX_B97P/DQ10B/BA_4D_2
DIFFIO_RX_B98N/DQ10B/BA_4D_1
DIFFIO_TX_B97N/RAS#_4D
DIFFIO_RX_B99P/DQ10B/A_4D_12
DIFFIO_TX_B100P/DQ11B/A_4D_10
DIFFIO_RX_B99N/DQ10B/A_4D_13
DIFFIO_TX_B100N/A_4D_11
DIFFIO_RX_B101P/DQ11B/A_4D_8
DIFFIO_TX_B102P/DQ11B/A_4D_6
DIFFIO_RX_B101N/DQ11B/A_4D_9
DIFFIO_TX_B102N/A_4D_7
DIFFIO_RX_B103P/DQS11B/CQ11B/A_4D_4
DIFFIO_TX_B104P/DQ11B/A_4D_2
DIFFIO_RX_B103N/DQSN11B/CQN11B/A_4D_5
DIFFIO_TX_B104N/A_4D_3
DIFFIO_RX_B105P/DQ11B/A_4D_0
DIFFIO_TX_B106P/DQ11B/CKE_4D_0
DIFFIO_RX_B105N/DQ11B/A_4D_1
DIFFIO_TX_B106N/CKE_4D_1
DIFFIO_RX_B107P/DQ11B/CK_4D
DIFFIO_RX_B107N/DQ11B/CK#_4D
DQ10B/A_4D_14
AN15
AP16
AF16
AE16
AC16
AB16
AB15
AA14
AH14
AG14
AE15
AD15
AC15
AB14
USB_DATA1
USB_DATA0
AK14
USB_DATA7
USB_CLK
19,24
USB_OEn
24
USB_FULL
24
USB_EMPTY
FX2_RESETn
USB_ADDR1
B
24
24
HDMI Interface
HDMI_FPGA_HPD
20
HDMI_FPGA_SCL_DDC
20
HDMI_FPGA_SDA_DDC
20
HDMI_FPGA_OE_N
Version 2.0 Pin Out
20
5AGXFB3H4F35
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
8
of
1
35
8
7
6
5
4
Arria V GX Bank 7
3
2
HSMC PORT Interface
HSMA_TX_D_P[16:8]
U1E
2.5V
DQ2T
DIFFIO_TX_T2P/DQ1T/RZQ_5
DIFFIO_TX_T2N
DIFFIO_TX_T4P/DQ1T
DIFFIO_TX_T4N
DIFFIO_TX_T6P/DQ1T
DIFFIO_TX_T6N
E1
F1
G6
H6
E5
F6
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P11
HSMA_TX_D_N11
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_RX_D_P14
HSMA_RX_D_N14
OVERTEMP_FPGA
HSMA_PRSNTn
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_RX_LED
HSMA_TX_LED
HSMA_RX_D_P13
HSMA_RX_D_N13
K9
K8
C8
D7
N10
N11
H8
J8
B6
C7
A7
A6
D8
D9
A10
B9
DIFFIO_RX_T32P/DQ3T/DQ4_7B_0 2.5V
DIFFIO_RX_T32N/DQ3T/DQ4_7B_1
DIFFIO_RX_T33P/DQ3T/DQ4_7B_3
DIFFIO_RX_T33N/DQ3T/DQ4_7B_4
DIFFIO_RX_T35P/DQS3T/CQ3T/DQS4_7B
DIFFIO_RX_T35N/DQSN3T/CQN3T/DQS#4_7B
DIFFIO_RX_T37P/DQ3T/DQ4_7B_6
DIFFIO_RX_T37N/DQ3T/DQ4_7B_7
DIFFIO_RX_T39P/DQ4T/DQ3_7B_0
DIFFIO_RX_T39N/DQ4T/DQ3_7B_1
DIFFIO_RX_T41P/DQ4T/DQ3_7B_3
DIFFIO_RX_T41N/DQ4T/DQ3_7B_4
DIFFIO_RX_T43P/DQS4T/CQ4T/DQS3_7B
DIFFIO_RX_T43N/DQSN4T/CQN4T/DQS#3_7B
DIFFIO_RX_T45P/DQ4T/DQ3_7B_6
DIFFIO_RX_T45N/DQ4T/DQ3_7B_7
DIFFIO_TX_T34P/DQ3T/DQ4_7B_5
DIFFIO_TX_T34N
DIFFIO_TX_T36P/DQ3T/DM4_7B
DIFFIO_TX_T36N
DIFFIO_TX_T38P/DQ3T/DQ4_7B_8
DIFFIO_TX_T38N
DIFFIO_TX_T40P/DQ4T/DQ3_7B_2
DIFFIO_TX_T40N
DIFFIO_TX_T42P/DQ4T/DQ3_7B_5
DIFFIO_TX_T42N
DIFFIO_TX_T44P/DQ4T/DM3_7B
DIFFIO_TX_T44N
DIFFIO_TX_T46P/DQ4T/DQ3_7B_8
DIFFIO_TX_T46N
E8
F7
G8
G7
L9
M8
E9
F8
G9
H9
A8
B8
J10
K10
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P16
HSMA_TX_D_N16
DQ3T/DQ4_7B_2
22
HSMA_CLK_OUT_P2
22
HSMA_CLK_OUT_N2
22
HSMA_PRSNTn
Bank 7B
E
22
HSMA_RX_D_N[16:8]
Bank 7A
L6
13,22
HSMA_RX_D_P[16:8]
Arria V GX Top IO Bank 7
D
13,22
HSMA_TX_D_N[16:8]
E
1
19,22,25
MAX V System Controller Interface
MAX5_BEn[3:0]
19
MAX5_CLK
19
MAX5_CSn
19
MAX5_OEn
D
19
MAX5_WEn
19
INT_TSD_SDA
19
INT_TSD_SCL
19
M10
LED Interface
PCIE_LED_X4
Bank 7C
C
HSMA_RX_D_P11
HSMA_RX_D_N11
MAX5_CSn
INT_TSD_SDA
HSMA_RX_D_P10
HSMA_RX_D_N10
MAX5_CLK
INT_TSD_SCL
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMA_RX_D_P8
HSMA_RX_D_N8
MAX5_BEn1
MAX5_BEn0
F10
G10
G11
H11
E11
F11
G12
H12
A11
B11
C11
D11
A13
B12
F13
G13
DIFFIO_RX_T47P/DQ5T/DQ2_7C_0 2.5V
DIFFIO_RX_T47N/DQ5T/DQ2_7C_1
DIFFIO_RX_T49P/DQ5T/DQ2_7C_3
DIFFIO_RX_T49N/DQ5T/DQ2_7C_4
DIFFIO_RX_T51P/DQS5T/CQ5T/DQS2_7C
DIFFIO_RX_T51N/DQSN5T/CQN5T/DQS#2_7C
DIFFIO_RX_T53P/DQ5T/DQ2_7C_6
DIFFIO_RX_T53N/DQ5T/DQ2_7C_7
DIFFIO_RX_T55P/DQ6T/DQ1_7C_0
DIFFIO_RX_T55N/DQ6T/DQ1_7C_1
DIFFIO_RX_T56P/DQ6T/DQ1_7C_3
DIFFIO_RX_T56N/DQ6T/DQ1_7C_4
DIFFIO_RX_T58P/DQS6T/CQ6T/DQS1_7C
DIFFIO_RX_T58N/DQSN6T/CQN6T/DQS#1_7C
DIFFIO_RX_T60P/DQ6T/DQ1_7C_6
DIFFIO_RX_T60N/DQ6T/DQ1_7C_7
DIFFIO_TX_T48P/DQ5T/DQ2_7C_2
DIFFIO_TX_T48N
DIFFIO_TX_T50P/DQ5T/DQ2_7C_5
DIFFIO_TX_T50N
DIFFIO_TX_T52P/DQ5T/DM2_7C
DIFFIO_TX_T52N
DIFFIO_TX_T54P/DQ5T/DQ2_7C_8
DIFFIO_TX_T54N
DIFFIO_TX_T57P/DQ6T/DQ1_7C_5
DIFFIO_TX_T57N
DIFFIO_TX_T59P/DQ6T/DM1_7C
DIFFIO_TX_T59N
DIFFIO_TX_T61P/DQ6T/DQ1_7C_8
DIFFIO_TX_T61N/RESET#_7D
DQ6T/DQ1_7C_2
J11
K11
K12
L11
C10
D10
L12
M12
J13
K13
D12
E12
M11
N12
25
PCIE_LED_X8
25
USER_LED[3:0]
MAX5_OEn
MAX5_WEn
25
C
HSMA_RX_LED
25
HSMA_TX_LED
25
Push Button Switch Interface
MAX5_BEn3
MAX5_BEn2
USER_PB[2:0]
25
DIP Switch Interface
N13
USER_DIPSW[3:0]
25
Bank 7D
PCIE_SMBDAT
B
PCIE_LED_X8
USER_DIPSW1
PCIE_WAKEn
USER_PB2
USER_LED1
USER_PB0
USER_PB1
PCIE_SMBCLK
PCIE_LED_X4
USER_LED0
USER_LED3
H14
J14
F14
G14
G15
H15
D14
E14
B14
C14
A14
B15
F16
G16
C16
D16
2.5V
DIFFIO_RX_T62P/DQ7T/CK_7D
DIFFIO_RX_T62N/DQ7T/CK#_7D
DIFFIO_RX_T64P/DQ7T/A_7D_0
DIFFIO_RX_T64N/DQ7T/A_7D_1
DIFFIO_RX_T66P/DQS7T/CQ7T/A_7D_4
DIFFIO_RX_T66N/DQSN7T/CQN7T/A_7D_5
DIFFIO_RX_T68P/DQ7T/A_7D_8
DIFFIO_RX_T68N/DQ7T/A_7D_9
DIFFIO_RX_T70P/DQ8T/A_7D_12
DIFFIO_RX_T70N/DQ8T/A_7D_13
DIFFIO_RX_T71P/DQ8T/BA_7D_0
DIFFIO_RX_T71N/DQ8T/BA_7D_1
DIFFIO_RX_T73p/DQS8T/CQ8T/CAS#_7D
DIFFIO_RX_T73N/DQ8T/WE#_7D
DIFFIO_RX_T75P/DQ8T
DIFFIO_RX_T75N/DQ8T
DIFFIO_TX_T63P/DQ7T/CKE_7D_0
DIFFIO_TX_T63N/CKE_7D_1
DIFFIO_TX_T65P/DQ7T/A_7D_2
DIFFIO_TX_T65N/A_7D_3
DIFFIO_TX_T67P/DQ7T/A_7D_6
DIFFIO_TX_T67N/A_7D_7
DIFFIO_TX_T69P/DQ7T/A_7D_10
DIFFIO_TX_T69N/A_7D_11
DIFFIO_TX_T72P/DQ8T/BA_7D_2
DIFFIO_TX_T72N/RAS#_7D
DIFFIO_TX_T74P/DQ8T/ODT_7D_0
DIFFIO_TX_T74N/ODT_7D_1
DIFFIO_TX_T76P/DQ8T/CS#_7D_0
DIFFIO_TX_T76N/CS#_7D_1
DQ8T/A_7D_14
K14
L14
M14
M15
C13
D13
K15
L15
D15
E15
J16
K16
M16
N16
PCIe Edge Connector Interface
PCIE_SMBCLK
6
B
PCIE_SMBDAT
USER_LED2
USER_DIPSW2
6
PCIE_WAKEn
USER_DIPSW0
USER_DIPSW3
6
Fan Interface
OVERTEMP_FPGA
31
N15
Version 2.0 Pin Out
5AGXFB3H4F35
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
9
of
1
35
8
7
6
5
4
3
2
1
Arria V GX Bank 8
U1F
Arria V GX Top IO Bank 8
E
DDR3 X32 SDRAM INTERFACE
E
Bank 8A
E26
F26
D26
E27
G26
H26
D27
C28
G27
G28
A29
A28
F28
F29
DDR3_CLK_P
DDR3_CLK_N
DDR3_A0
DDR3_A1
DDR3_A4
DDR3_A5
DDR3_A8
DDR3_A9
DDR3_A12
DDR3_A13
DDR3_BA0
DDR3_BA1
DDR3_CASn
DDR3_WEn
L26
D
DIFFIO_RX_T146P/DQ15T/CK_8A 1.5V
DIFFIO_TX_T147P/DQ15T/CKE_8A_0
DIFFIO_RX_T146N/DQ15T/CK#_8A
DIFFIO_TX_T147N/CKE_8A_1
DIFFIO_RX_T148P/DQ15T/A_8A_0
DIFFIO_TX_T149P/DQ15T/A_8A_2
DIFFIO_RX_T148N/DQ15T/A_8A_1
DIFFIO_TX_T149N/A_8A_3
DIFFIO_RX_T150P/DQS15T/CQ15T/A_8A_4
DIFFIO_TX_T151P/DQ15T/A_8A_6
DIFFIO_RX_T150N/DQSN15T/CQN15T/A_8A_5
DIFFIO_TX_T151N/A_8A_7
DIFFIO_RX_T152P/DQ15T/A_8A_8
DIFFIO_TX_T153P/DQ15T/A_8A_10
DIFFIO_RX_T152N/DQ15T/A_8A_9
DIFFIO_TX_T153N/A_8A_11
DIFFIO_RX_T154P/DQ16T/A_8A_12
DIFFIO_TX_T155P/DQ16T/A_8A_14
DIFFIO_RX_T154N/DQ16T/A_8A_13
DIFFIO_TX_T155N/A_8A_15
DIFFIO_RX_T156P/DQ16T/BA_8A_0
DIFFIO_TX_T157P/DQ16T/BA_8A_2
DIFFIO_RX_T156N/DQ16T/BA_8A_1
DIFFIO_TX_T157N/RAS#_8A
DIFFIO_RX_T158P/DQS16T/CQ16T/CAS#_8A DIFFIO_TX_T159P/DQ16T/ODT_8A_0
DIFFIO_RX_T158N/DQSN16T/CQN16T/WE#_8A
DIFFIO_TX_T159N/ODT_8A_1
DIFFIO_TX_T161P/DQ16T/CS#_8A_0
DIFFIO_TX_T161N/CS#_8A_1
DQ17T
DIFFIO_TX_T166P/DQ17T
DIFFIO_TX_T166N
DIFFIO_TX_T168P/DQ17T
DIFFIO_TX_T168N/RZQ_6
K29
L29
A27
B27
K27
L27
C29
D28
J26
K26
B29
B30
H27
J27
D30
E30
J28
K28
D32
E32
DDR3_CKE
DDR3_DQ[31:0]
DDR3_A2
DDR3_A3
DDR3_A6
DDR3_A7
DDR3_A10
DDR3_A11
DDR3_DQS_P[3:0]
C
H23
J23
B24
C23
F23
G23
D24
E24
G24
H24
A26
A25
F25
G25
B26
C26
DDR3_DQ2
M24
DDR3_DQ24
DDR3_DQ25
DDR3_DQ27
DDR3_DQ28
DDR3_DQS_P3
DDR3_DQS_N3
DDR3_DQ30
DDR3_DQ31
DDR3_DQ16
DDR3_DQ17
DDR3_DQ19
DDR3_DQ20
DDR3_DQS_P2
DDR3_DQS_N2
DDR3_DQ22
DDR3_DQ23
K20
L20
A22
B21
D20
E20
F20
G20
D21
E21
C22
D22
F22
G22
A23
B23
DDR3_DQ26
M20
LCD_DATA0
LCD_D_Cn
C19
B18
H18
J19
D19
D18
16
DDR3_A[13:0]
16
DDR3_BA[2:0]
16
DDR3_DM[3:0]
16
DDR3_CLK_P
16
DDR3_CLK_N
DDR3_CSn
100
R4
16
DDR3_CKE
16
DDR3_CSn
16
D
DDR3_RASn
1%
16
DDR3_CASn
Bank 8B
DDR3_DQ8
DDR3_DQ9
DDR3_DQ11
DDR3_DQ12
DDR3_DQS_P1
DDR3_DQS_N1
DDR3_DQ14
DDR3_DQ15
DDR3_DQ0
DDR3_DQ1
DDR3_DQ3
DDR3_DQ4
DDR3_DQS_P0
DDR3_DQS_N0
DDR3_DQ6
DDR3_DQ7
16
DDR3_DQS_N[3:0]
DDR3_BA2
DDR3_RASn
DDR3_ODT
DDR3_OCT_RZQ
16
DIFFIO_RX_T131P/DQ13T/DQ2_8B_0 1.5V DIFFIO_TX_T132P/DQ13T/DQ2_8B_2
DIFFIO_RX_T131N/DQ13T/DQ2_8B_1
DIFFIO_TX_T132N
DIFFIO_RX_T133P/DQ13T/DQ2_8B_3
DIFFIO_TX_T134P/DQ13T/DQ2_8B_5
DIFFIO_RX_T133N/DQ13T/DQ2_8B_4
DIFFIO_TX_T134N
DIFFIO_RX_T135P/DQS13T/CQ13T/DQS2_8B DIFFIO_TX_T136P/DQ13T/DM2_8B
DIFFIO_RX_T135N/DQSN13T/CQN13T/DQS#2_8B
DIFFIO_TX_T136N
DIFFIO_RX_T137P/DQ13T/DQ2_8B_6
DIFFIO_TX_T138P/DQ13T/DQ2_8B_8
DIFFIO_RX_T137N/DQ13T/DQ2_8B_7
DIFFIO_TX_T138N
DIFFIO_RX_T139P/DQ14T/DQ1_8B_0
DIFFIO_TX_T141P/DQ14T/DQ1_8B_5
DIFFIO_RX_T139N/DQ14T/DQ1_8B_1
DIFFIO_TX_T141N
DIFFIO_RX_T140P/DQ14T/DQ1_8B_3
DIFFIO_TX_T143P/DQ14T/DM1_8B
DIFFIO_RX_T140N/DQ14T/DQ1_8B_4
DIFFIO_TX_T143N
DIFFIO_RX_T142P/DQS14T/CQ14T/DQS1_8B DIFFIO_TX_T145P/DQ14T/DQ1_8B_8
DIFFIO_RX_T142N/DQSN14T/CQN14T/DQS#1_8B DIFFIO_TX_T145N/RESET#_8A
DIFFIO_RX_T144P/DQ14T/DQ1_8B_6
DIFFIO_RX_T144N/DQ14T/DQ1_8B_7
K24
L24
D23
E23
M23
N23
K23
L23
C25
D25
M25
N25
J25
K25
DDR3_DQ10
16
DDR3_WEn
DDR3_DQ13
16
DDR3_RESETn
DDR3_DM1
16
DDR3_ODT
16
DDR3_DQ5
2x16 LCD DISPLAY INTERFACE
DDR3_DM0
LCD_DATA[7:0]
DDR3_RESETn
25
C
LCD_CSn
25
LCD_D_Cn
DQ14T/DQ1_8B_2
25
LCD_WEn
25
Bank 8C
B
DIFFIO_RX_T116P/DQ11T/DQ4_8C_01.5V DIFFIO_TX_T118P/DQ11T/DQ4_8C_5
DIFFIO_RX_T116N/DQ11T/DQ4_8C_1
DIFFIO_TX_T118N
DIFFIO_RX_T117P/DQ11T/DQ4_8C_3
DIFFIO_TX_T120P/DQ11T/DM4_8C
DIFFIO_RX_T117N/DQ11T/DQ4_8C_4
DIFFIO_TX_T120N
DIFFIO_RX_T119P/DQS11T/CQ11T/DQS4_8C DIFFIO_TX_T122P/DQ11T/DQ4_8C_8
DIFFIO_RX_T119N/DQSN11T/CQN11T/DQS#4_8C
DIFFIO_TX_T122N
DIFFIO_RX_T121P/DQ11T/DQ4_8C_6
DIFFIO_TX_T124P/DQ12T/DQ3_8C_2
DIFFIO_RX_T121N/DQ11T/DQ4_8C_7
DIFFIO_TX_T124N
DIFFIO_RX_T123P/DQ12T/DQ3_8C_0
DIFFIO_TX_T126P/DQ12T/DQ3_8C_5
DIFFIO_RX_T123N/DQ12T/DQ3_8C_1
DIFFIO_TX_T126N
DIFFIO_RX_T125P/DQ12T/DQ3_8C_3
DIFFIO_TX_T128P/DQ12T/DM3_8C
DIFFIO_RX_T125N/DQ12T/DQ3_8C_4
DIFFIO_TX_T128N
DIFFIO_RX_T127P/DQS12T/CQ12T/DQS3_8C DIFFIO_TX_T130P/DQ12T/DQ3_8C_8
DIFFIO_RX_T127N/DQSN12T/CQN12T/DQS#3_8C
DIFFIO_TX_T130N
DIFFIO_RX_T129P/DQ12T/DQ3_8C_6
DIFFIO_RX_T129N/DQ12T/DQ3_8C_7
B20
C20
K21
L21
H20
J20
M21
N21
G21
H21
M22
N22
J22
K22
DDR3_DQ29
DDR3_DM3
DDR3_DQ18
DDR3_DQ21
DDR3_DM2
B
DQ11T/DQ4_8C_2
Bank 8D
LCD_DATA1
LCD_DATA2
M18
DIFFIO_RX_T94P/DQ10T
2.5V
DIFFIO_RX_T94N/DQ10T
DIFFIO_RX_T96P/DQS10T/CQ10T
DIFFIO_RX_T96N/DQSN10T/CQN10T
DIFFIO_RX_T98P/DQ10T
DIFFIO_RX_T98N/DQ10T
DQ10T
A
DIFFIO_TX_T86P/DQ9T
DIFFIO_TX_T86N
DIFFIO_TX_T88P/DQ9T
DIFFIO_TX_T88N
DIFFIO_TX_T92P/DQ9T
DIFFIO_TX_T92N
DIFFIO_TX_T95P/DQ10T
DIFFIO_TX_T95N
DIFFIO_TX_T97P/DQ10T
DIFFIO_TX_T97N
DIFFIO_TX_T99P/DQ10T
DIFFIO_TX_T99N
K17
L17
D17
E17
B17
C17
G18
G19
M19
N19
E18
F19
LCD_DATA3
LCD_DATA4
LCD_CSn
LCD_WEn
LCD_DATA5
A
LCD_DATA6
LCD_DATA7
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Version 2.0 Pin-out
Size
5AGXFB3H4F35
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
10
of
1
35
8
7
6
5
4
3
2
1
Arria V GX Transceivers Banks
U1G
U1H
Arria V GX Transceiver Left Bank
Bank L0
D
PCIE_RX_P5
PCIE_RX_N5
PCIE_RX_P6
PCIE_RX_N6
PCIE_RX_P7
PCIE_RX_N7
SDI_RX_P
SDI_RX_N
UNUSED_XCVR_RX_L1
CAD Note:
Place resistor near
GXB_RX pins
SMA_XCVR_RX_CP
SMA_XCVR_RX_CN
From CH0 Si5338A
REFCLK2_QL1_P
REFCLK2_QL1_N
CLK_148_P
CLK_148_N
R7
0
C
2.0K XCVR_RREF_TL
R9
1%
AA27
AA28
W26
W27
AJ32
AJ31
AG32
AG31
AE32
AE31
AC32
AC31
AA32
AA31
W32
W31
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_P3
PCIE_TX_N3
R5
HSMA_RX_P7
HSMA_RX_N7
HSMA_RX_P6
HSMA_RX_N6
PCIE_TX_P4
PCIE_TX_N4
0
GXB_TX_L6P
GXB_TX_L6N
GXB_TX_L7P
GXB_TX_L7N
GXB_TX_L8P
GXB_TX_L8N
GXB_TX_L9P
GXB_TX_L9N
GXB_TX_L10P
GXB_TX_L10N
GXB_TX_L11P
GXB_TX_L11N
U32
U31
R32
R31
N32
N31
L32
L31
J32
J31
G32
G31
PCIE_TX_P5
PCIE_TX_N5
PCIE_TX_P6
PCIE_TX_N6
PCIE_TX_P7
PCIE_TX_N7
SDI_TX_P
SDI_TX_N
SMA_XCVR_TX_RP
SMA_XCVR_TX_RN
REFCLK2LP
REFCLK2LN
REFCLK3LP
REFCLK3LN
From CH0 Si5338A
From HSMA connector
100MHz
Reference Resistor
F34
CAD Note:
Place resistor near
RREF_TL pins
REFCLK1_QR0_P
REFCLK1_QR0_N
From CH2 Si5338A
R293
GXB_RX_L6P,GXB_REFCLK_L6P
GXB_RX_L6N,GXB_REFCLK_L6N
GXB_RX_L7P,GXB_REFCLK_L7P
GXB_RX_L7N,GXB_REFCLK_L7N
GXB_RX_L8P,GXB_REFCLK_L8P
GXB_RX_L8N,GXB_REFCLK_L8N
GXB_RX_L9P,GXB_REFCLK_L9P
GXB_RX_L9N,GXB_REFCLK_L9N
GXB_RX_L10P,GXB_REFCLK_L10P
GXB_RX_L10N,GXB_REFCLK_L10N
GXB_RX_L11P,GXB_REFCLK_L11P
GXB_RX_L11N,GXB_REFCLK_L11N
U26
U27
R26
R27
V1
V2
T1
T2
P1
P2
M1
M2
K1
K2
H1
H2
REFCLK2_QR1_P
REFCLK2_QR1_N
REFCLK3_QR1_P
REFCLK3_QR1_N
U9
U8
R9
R8
2.0K XCVR_RREF_BR
1%
Version 2.0 Pin Out
5AGXFB3H4F35
PCIE_TX_P[7:0]
6
REFCLK1_QL0_P
6
REFCLK1_QL0_N
6
PCIE_REFCLK_P
6
PCIE_REFCLK_N
6
REFCLK1_QR0_N
REFCLK2_QL1_P
SDI Cable Driver/Equalizer Interface
21
SDI_TX_N
21
SDI_RX_P
SDI_RX_N
AJ3
AJ4
AG3
AG4
AE3
AE4
AC3
AC4
AA3
AA4
W3
W4
HDMI_TX_P0
HDMI_TX_N0
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_CLK_P
HDMI_TX_CLK_N
HSMA_TX_P7
HSMA_TX_N7
HSMA_TX_P6
HSMA_TX_N6
U3
U4
R3
R4
N3
N4
L3
L4
J3
J4
G3
G4
HSMA_TX_P5
HSMA_TX_N5
HSMA_TX_P4
HSMA_TX_N4
HSMA_TX_P3
HSMA_TX_N3
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P0
HSMA_TX_N0
E
REFCLK0RP
REFCLK0RN
REFCLK1RP
REFCLK1RN
GXB_RX_R6P,GXB_REFCLK_R6P
GXB_RX_R6N,GXB_REFCLK_R6N
GXB_RX_R7P,GXB_REFCLK_R7P
GXB_RX_R7N,GXB_REFCLK_R7N
GXB_RX_R8P,GXB_REFCLK_R8P
GXB_RX_R8N,GXB_REFCLK_R8N
GXB_RX_R9P,GXB_REFCLK_R9P
GXB_RX_R9N,GXB_REFCLK_R9N
GXB_RX_R10P,GXB_REFCLK_R10P
GXB_RX_R10N,GXB_REFCLK_R10N
GXB_RX_R11P,GXB_REFCLK_R11P
GXB_RX_R11N,GXB_REFCLK_R11N
GXB_TX_R6P
GXB_TX_R6N
GXB_TX_R7P
GXB_TX_R7N
GXB_TX_R8P
GXB_TX_R8N
GXB_TX_R9P
GXB_TX_R9N
GXB_TX_R10P
GXB_TX_R10N
GXB_TX_R11P
GXB_TX_R11N
D
REFCLK2RP
REFCLK2RN
REFCLK3RP
REFCLK3RN
Reference Resistor
AM1
C
RREF_BR
Version 2.0 Pin Out
SMA Connector Interface
5AGXFB3H4F35
SMA_XCVR_RX_CP
C421
0.1uF
SMA_XCVR_RX_P
1
SMA_XCVR_RX_CN
C422
0.1uF
SMA_XCVR_RX_N
1
14
22
14
HSMA_TX_N[7:0]
14
22
B
REFCLK3_QR1_P
22
REFCLK3_QR1_N
14
REFCLK2_QR1_N
22
SMA_XCVR_TX_RP
R282
20
SMA_XCVR_TX_RN
R283
0
0
SMA_XCVR_TX_P
1
SMA_XCVR_TX_N
1
CLK_148_P
21
CLK_148_N
J4
14
14
HDMI_TX_P[2:0]
14
HDMI_TX_N[2:0]
21
J3
22
HDMI Level Shifter Interface
REFCLK2_QR1_P
J2
22
HSMA_RX_N[7:0]
HSMA_TX_P[7:0]
REFCLK1_QR0_P
REFCLK2_QL1_N
SDI_TX_P
CAD Note:
Place resistor near
RREF_BR pins
HSMA_RX_P[7:0]
14
6
PCIE_TX_N[7:0]
GXB_TX_R0P
GXB_TX_R0N
GXB_TX_R1P
GXB_TX_R1N
GXB_TX_R2P
GXB_TX_R2N
GXB_TX_R3P
GXB_TX_R3N
GXB_TX_R4P
GXB_TX_R4N
GXB_TX_R5P
GXB_TX_R5N
HSMA Connector Interface
PLL Interface
PCIE_RX_N[7:0]
GXB_RX_R0P,GXB_REFCLK_R0P
GXB_RX_R0N,GXB_REFCLK_R0N
GXB_RX_R1P,GXB_REFCLK_R1P
GXB_RX_R1N,GXB_REFCLK_R1N
GXB_RX_R2P,GXB_REFCLK_R2P
GXB_RX_R2N,GXB_REFCLK_R2N
GXB_RX_R3P,GXB_REFCLK_R3P
GXB_RX_R3N,GXB_REFCLK_R3N
GXB_RX_R4P,GXB_REFCLK_R4P
GXB_RX_R4N,GXB_REFCLK_R4N
GXB_RX_R5P,GXB_REFCLK_R5P
GXB_RX_R5N,GXB_REFCLK_R5N
Bank R1
HSMA_RX_P5
HSMA_RX_N5
HSMA_RX_P4
HSMA_RX_N4
HSMA_RX_P3
HSMA_RX_N3
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P0
HSMA_RX_N0
R10
RREF_TL
PCIE_RX_P[7:0]
AA8
AA7
W9
W8
UNUSED_XCVR_REFCLK_R0
Bank L1
V34
V33
T34
T33
P34
P33
M34
M33
K34
K33
H34
H33
Bank R0
AK1
AK2
AH1
AH2
AF1
AF2
AD1
AD2
AB1
AB2
Y1
Y2
Design Note:
Tie unused refclk/rx pin to
GND through 10K resistor
0
REFCLK0LP
REFCLK0LN
REFCLK1LP
REFCLK1LN
PCIe Connector Interface
B
GXB_TX_L0P
GXB_TX_L0N
GXB_TX_L1P
GXB_TX_L1N
GXB_TX_L2P
GXB_TX_L2N
GXB_TX_L3P
GXB_TX_L3N
GXB_TX_L4P
GXB_TX_L4N
GXB_TX_L5P
GXB_TX_L5N
2
3
4
5
PCIE_REFCLK_P
PCIE_REFCLK_N
REFCLK1_QL0_P
REFCLK1_QL0_N
From CH1 Si5338A
GXB_RX_L0P,GXB_REFCLK_L0P
GXB_RX_L0N,GXB_REFCLK_L0N
GXB_RX_L1P,GXB_REFCLK_L1P
GXB_RX_L1N,GXB_REFCLK_L1N
GXB_RX_L2P,GXB_REFCLK_L2P
GXB_RX_L2N,GXB_REFCLK_L2N
GXB_RX_L3P,GXB_REFCLK_L3P
GXB_RX_L3N,GXB_REFCLK_L3N
GXB_RX_L4P,GXB_REFCLK_L4P
GXB_RX_L4N,GXB_REFCLK_L4N
GXB_RX_L5P,GXB_REFCLK_L5P
GXB_RX_L5N,GXB_REFCLK_L5N
2
3
4
5
0
AK34
AK33
AH34
AH33
AF34
AF33
AD34
AD33
AB34
AB33
Y34
Y33
2
3
4
5
PCIE_RX_P0
PCIE_RX_N0
PCIE_RX_P1
PCIE_RX_N1
PCIE_RX_P2
CAD Note:
PCIE_RX_N2
Place resistor near
PCIE_RX_P3
GXB_RX pins
PCIE_RX_N3
UNUSED_XCVR_RX_L0
CMU PLL (PCIe Gen2)
PCIE_RX_P4
PCIE_RX_N4
R6
Arria V GX Transceiver Right Bank
14
HDMI_TX_CLK_P
14
HDMI_TX_CLK_N
J5
20
CAD Note:
Place resistors & capacitors
near SMA connectors
20
2
3
4
5
E
CAD Note:
Place resistor near
GXB_RX pins
UNUSED_XCVR_RX_R0
20
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
11
of
1
35
8
7
6
5
4
3
2
1
Arria V GX Configuration
E
E
U1A
Arria V GX Configuration
MAX V System Controller Interface
On-board USB Blaster II Interface
Bank 3A
FPGA_DCLK
AM32
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
AN34
AN33
AP33
AM33
AM34
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
FPGA_CONFIG_D8
FPGA_CONFIG_D9
FPGA_CONFIG_D10
FPGA_CONFIG_D11
FPGA_CONFIG_D12
FPGA_CONFIG_D13
FPGA_CONFIG_D14
FPGA_CONFIG_D15
AL7
AM7
AP6
AP5
AM5
AP8
AP7
AM6
AN6
AE7
AF7
DCLK
TCK
TMS
TDO
TDI
AS_DATA0,ASDO/DATA0
AS_DATA1/DATA1
AS_DATA2/DATA2
AS_DATA3/DATA3
NCSO/DATA4
AN32
AF30
AC28
AC29
FPGA_CONFIG_D[15:0]
JTAG_TCK
JTAG_TMS
JTAG_FPGA_TDO
JTAG_BLASTER_TDO
15,19,22,24
15,24
24
15,24
19
FPGA_DCLK
MSEL[4:0]
19
FPGA_CONF_DONE
19
FPGA_nSTATUS
Bank 4A
D
19
DATA5/DIFFIO_RX_B155N/DQ16B
CLKUSR/DIFFIO_RX_B159P/DQ16B
DATA6/DIFFIO_RX_B155P/DQ16B
DATA7/DIFFIO_RX_B157N/DQSN16B/CQN16B
DATA8/DIFFIO_RX_B157P/DQS16B/CQ16B
DATA9/DIFFIO_RX_B159N/DQ16B
DATA10/DIFFIO_TX_B154N
DATA11/DIFFIO_TX_B154P/DQ16B
DATA12/DIFFIO_TX_B156N
DATA13/DIFFIO_TX_B156P/DQ16B
DATA14/DIFFIO_TX_B158N
DATA15/DIFFIO_TX_B158P/DQ16B
AN5
19
FPGA_nCONFIG
19
D
FPGA_CvP_CONFDONE
19
FPGA_PR_ERROR
2.5V_VCCIO_VCCPD_VCCPGM
19
FPGA_PR_READY
19
FPGA_PR_DONE
R12
R13
R14
R11
10K
10K
10K
10K
19
FPGA_PR_REQUEST
19
Bank 7A
C6
D5
C4
D6
E6
CPU_RESETn
2.5V_VCCIO_VCCPD_VCCPGM
C
R15
10K
DEV_OE/DIFFIO_RX_T10P/DQ2T
NPERSTL1/DIFFIO_TX_T11P/DQ2T
DEV_CLRN/DIFFIO_RX_T10N/DQ2T
NPERSTL0/DIFFIO_TX_T11N
CRC_ERROR/DIFFIO_RX_T12N/DQSN2T/CQN2T
INIT_DONE/DIFFIO_RX_T14P/DQ2T
PR_DONE/DIFFIO_TX_T13P/DQ1T
NCEO/DIFFIO_RX_T14N/DQ2T
PR_REQUEST/DIFFIO_TX_T13N
PR_ERROR/DIFFIO_TX_T15P/DQ1T
PR_READY/DIFFIO_TX_T15N
FPGA_CONF_DONE
R16
10K FPGA_nSTATUS
R17
10K FPGA_nCONFIG
CVP_CONFDONE/DIFFIO_RX_T12P/DQS2T/CQ2T
A2
B2
PCIE_PERSTn
A5
A4
J7
K7
FPGA_PR_DONE
FPGA_PR_REQUEST
FPGA_PR_ERROR
FPGA_PR_READY
B5
FPGA_CvP_CONFDONE
Push Button Interface
CPU_RESETn
CONF_DONE
NSTATUS
NCONFIG
NCE
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
D34
H30
K30
M29
M30
MSEL0_R
MSEL1_R
MSEL2_R
MSEL3_R
MSEL4_R
DNI
DNI
DNI
DNI
DNI
R18
R19
R20
R21
R22
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
2.5V_VCCIO_VCCPD_VCCPGM
DNU_1
DNU_2
DNU_3
DNU_4
DNU_5
DNU_6
DNU_7
DNU_8
Version 2.0 Pin Out
B
5AGXFB3H4F35
AM2
AN2
K5
L18
R294
0
R295
DNI
R296
0
R297
DNI
R298
0
R299
DNI
R300
0
R301
DNI
R302
0
R303
DNI
Design Note:
Remove pull up/pull down resistors
and populate series resistors before
changing the MSEL setting by
editing MAX V system controller
code
B
Default Configuration Mode:
- MSEL[4:0] = 00000
- FPP x16
- Fast POR Delay
- Decompression feature is disabled
- Design Security feature is disabled
CAD Note:
Overlap resistor pads
Design Note:
Optional termination resistor
for DCLK
Warning!!
Follow MSEL setting in datasheet strictly
to avoid undesirable behavior of FPGA
CAD Note:
Place near FPGA DCLK pin
DNI FPGA_DCLK R24
6
Bank 8A
C34
B34
C33
A33
Do Not Use
R23
C
PCIe Edge Connector Interface
PCIE_PERSTn
E33
F33
AL32
AD18
2.5V_VCCIO_VCCPD_VCCPGM
19,25
DNI
C25
DNI
R25
A
A
DNI
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
12
of
1
35
8
7
6
5
4
3
2
1
Arria V GX Clock
PLL Interface
CLKINTOP_100_P
U1B
Arria V GX Clock
E
AP32
AP31
AK29
AJ29
AJ28
AH28
AP29
AN29
CLKINBOT_125_P
CLKINBOT_125_N
SDI_FAULT
SDI_SDA
SDI_SCL
CLKIN_50_BOT
AH18
AG18
AH17
AG17
AF17
AE17
AE18
AD17
CLKINBOT_100_P
CLKINBOT_100_N
CLK_125_P
CLK_125_N
D
AG6
AF6
AL5
AL4
AN3
AP2
AJ7
AH7
HSMA_CLK_IN0
ENET_RX_CLK
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
E3
E4
D1
E2
C1
C2
A3
B3
C
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
CLKINTOP_125_P
CLKINTOP_125_N
CLK0P/DIFFIO_RX_B2P/DQ1B
CLK0N/DIFFIO_RX_B2N/DQ1B
CLK1P/DIFFIO_RX_B4P/DQS1B/CQ1B
CLK1N/DIFFIO_RX_B4N/DQSN1B/CQN1B
CLK2P/DIFFIO_RX_B7P/DQ1B
CLK2N/DIFFIO_RX_B7N/DQ1B
CLK3P/DIFFIO_RX_B9P/DQ2B
CLK3N/DIFFIO_RX_B9N/DQ2B
FPLL_BL_CLKOUT0/CLKOUTP/FB0/DIFFIO_TX_B5P/DQ1B
FPLL_BL_CLKOUT1/CLKOUTN/DIFFIO_TX_B5N
FPLL_BL_CLKOUT2/FBP/FB1/DIFFIO_RX_B6P/DQ1B
FPLL_BL_CLKOUT3/FBN/DIFFIO_RX_B6N/DQ1B
E
AL30
CLKINBOT_100_N
AP30
CLK_125_P
AN30
CLK_125_N
14
14
14
14
14
CLKIN_50_TOP
FPLL_BC_CLKOUT0/CLKOUTP/FB0/DIFFIO_TX_B79P/DQ9B
FPLL_BC_CLKOUT1/CLKOUTN/DIFFIO_TX_B79N
FPLL_BC_CLKOUT2/FBP/FB1/DIFFIO_RX_B80P/DQS9B/CQ9B
FPLL_BC_CLKOUT3/FBN/DIFFIO_RX_B80N/DQSN9B/CQN9B
Bank 4A (2.5V)
CLK8P/DIFFIO_RX_B168P/DQ17B
FPLL_BR_CLKOUT0/CLKOUTP/FB0/DIFFIO_TX_B161P/DQ17B
CLK8N/DIFFIO_RX_B168N/DQ17B
CLK9P/DIFFIO_RX_B166P/DQ17B
FPLL_BR_CLKOUT1/CLKOUTN/DIFFIO_TX_B161N
CLK9N/DIFFIO_RX_B166N/DQ17B
CLK10P/DIFFIO_RX_B164P/DQS17B/CQ17B
FPLL_BR_CLKOUT2/FBP/FB1/DIFFIO_RX_B162P/DQ17B
CLK10N/DIFFIO_RX_B164N/DQSN17B/CQN17B
CLK11P/DIFFIO_RX_B160P/DQ16B
FPLL_BR_CLKOUT3/FBN/DIFFIO_RX_B162N/DQ17B
CLK11N/DIFFIO_RX_B160N/DQ16B
14
AB17
14
CLKINTOP_125_P
AA17
14
CLKINTOP_125_N
AK17
USB_SDA
AJ17
USB_RESETn
AE6
HSMA_TX_D_P7
AD6
HSMA_TX_D_N7
14
CLKINBOT_125_P
14
CLKINBOT_125_N
FPLL_TR_CLKOUT0/CLKOUTP/FB0/DIFFIO_TX_T8P/DQ1T
HSMC PORT Interface
HSMA_CLK_IN0
AP4
HSMA_CLK_IN_P[2:1]
AP3
HSMA_CLK_IN_N[2:1]
22
22
22
HSMA_TX_D_P7
FPLL_TR_CLKOUT1/CLKOUTN/DIFFIO_TX_T8N
FPLL_TR_CLKOUT2/FBP/FB1/DIFFIO_RX_T7P/DQ1T
FPLL_TR_CLKOUT3/FBN/DIFFIO_RX_T7N/DQ1T
J6
HSMA_TX_D_P9
K6
HSMA_TX_D_N9
C3
CLKOUT_SMA
22
22
HSMA_TX_D_P9
22
C
HSMA_TX_D_N9
22
D3
On-board USB Blaster II Interface
USB_SDA
A19
A20
H17
J17
K18
K19
A16
A17
CLKINTOP_100_P
CLKINTOP_100_N
CLKIN_50_TOP
B
D33
C32
A32
B32
G29
H29
D29
E29
Bank 8D (2.5V)
CLK16P/DIFFIO_RX_T93P/DQ10T
CLK16N/DIFFIO_RX_T93N/DQ10T
CLK17P/DIFFIO_RX_T91P/DQ9T
CLK17N/DIFFIO_RX_T91N/DQ9T
CLK18P/DIFFIO_RX_T87P/DQ9T
CLK18N/DIFFIO_RX_T87N/DQ9T
CLK19P/DIFFIO_RX_T85P/DQ9T
CLK19N/DIFFIO_RX_T85N/DQ9T
FPLL_TC_CLKOUT0/CLKOUTP/FB0/DIFFIO_TX_T90P/DQ9T
FPLL_TC_CLKOUT1/CLKOUTN/DIFFIO_TX_T90N
FPLL_TC_CLKOUT2/FBP/FB1/DIFFIO_RX_T89P/DQS9T/CQ9T
FPLL_TC_CLKOUT3/FBN/DIFFIO_RX_T89N/DQSN9T/CQN9T
24
USB_RESETn
M17
24
N17
F17
PCIE_LED_G2
G17
PCIE_LED_X1
LED INTERFACE
PCIE_LED_G2
25
PCIE_LED_X1
Bank 8A (1.5V)
CLK20P/DIFFIO_RX_T167P
CLK20N/DIFFIO_RX_T167N
CLK21P/DIFFIO_RX_T165P
CLK21N/DIFFIO_RX_T165N
CLK22P/DIFFIO_RX_T162P
CLK22N/DIFFIO_RX_T162N
CLK23P/DIFFIO_RX_T160P/DQ8T
CLK23N/DIFFIO_RX_T160N/DQ8T
FPLL_TL_CLKOUT0/CLKOUTP/FB0/DIFFIO_TX_T164P/DQ17T
FPLL_TL_CLKOUT1/CLKOUTN/DIFFIO_TX_T164N
FPLL_TL_CLKOUT2/FBP/FB1/DIFFIO_RX_T163P/DQ17T
FPLL_TL_CLKOUT3/FBN/DIFFIO_RX_T163N/DQ17T
25
B
C31
Ethernet PHY INTERFACE
D31
ENET_RX_CLK
23
A31
A30
SDI Interface
SDI_SDA
HSMA_CLK_IN_P1
HSMA_CLK_IN_P2
A
R26
R27
100 1%
100 1%
CAD Note:
Place near FPGA pins
Version 2.0 Pin Out
HSMA_CLK_IN_N1
HSMA_CLK_IN_N2
CLKINTOP_100_P
CLKINBOT_100_P
R28
R29
100 1%
100 1%
CLKINTOP_100_N
CLKINBOT_100_N
CLKINTOP_125_P
CLKINBOT_125_P
R30
R31
100 1%
100 1%
CLKINTOP_125_N
CLKINBOT_125_N
CLK_125_P
R284
100 1%
CLK_125_N
SDI_FAULT
CLKOUT_SMA
R313
0 CLKOUT_SMA_CONN 1
0 CLKOUT_SMA_R R315
CAD Note:
Place near FPGA pins
and near to each other
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
B
Date:
6
21
A
R314
Size
7
21
J6
DNI
8
21
SDI_SCL
5AGXFB3H4F35
2
3
4
5
LVDS Clock Input Termination
D
14
HSMA_TX_D_N7
Bank 7A (2.5V)
CLK12P/DIFFIO_RX_T1P/DQ1T
CLK12N/DIFFIO_RX_T1N/DQ1T
CLK13P/DIFFIO_RX_T3P/DQ1T
CLK13N/DIFFIO_RX_T3N/DQ1T
CLK14P/DIFFIO_RX_T5P/DQS1T/CQ1T
CLK14N/DIFFIO_RX_T5N/DQSN1T/CQN1T
CLK15P/DIFFIO_RX_T9P/DQ2T
CLK15N/DIFFIO_RX_T9N/DQ2T
AM30
CLKINBOT_100_P
CLKIN_50_BOT
Bank 3D (2.5V)
CLK4PDIFFIO_RX_B76P/DQ8B
CLK4NDIFFIO_RX_B76N/DQ8B
CLK5PDIFFIO_RX_B78P/DQ9B
CLK5NDIFFIO_RX_B78N/DQ9B
CLK6P/DIFFIO_RX_B82P/DQ9B
CLK6N/DIFFIO_RX_B82N/DQ9B
CLK7P/DIFFIO_RX_B84P/DQ9B
CLK7N/DIFFIO_RX_B84N/DQ9B
14
CLKINTOP_100_N
Bank 3A (2.5V)
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
13
of
1
35
8
7
6
5
4
3
2
1
PLL
C29
Programmable Clock
DNI
Y1
4
C33
1
2
3
2.5V
4
5
6
DNI
2.5V
U4
25.00MHz
2
1
3
E
XTAL_25M_Si5338A_P
XTAL_25M_Si5338A_N
R33
4.7k
CLOCK_SCL
12
R34
4.7k
CLOCK_SDA
19
7
24
11
15
16
20
VDD1
VDD2
VDDO3
VDDO2
VDDO1
VDDO0
CLKIN_P
CLKIN_N
CLKIN
I2C_LSB
FDBK_P
FDBK_N
INTR
SCL
CLK3B
CLK3A
SDA
CLK2B
CLK2A
Design Note:
I2C bus pull up for clock generators
CLK1B
CLK1A
D
CLK0B
CLK0A
C30
2.5V_PLL
C36
C31
C37
C32
C38
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
U3
Si5338A_INTR
9
10
Si5338A_CLK3_100_N
Si5338A_CLK3_100_P
13
14
REFCLK1_QR0_CN
REFCLK1_QR0_CP
C39
C40
0.1uF
0.1uF
REFCLK1_QR0_N
REFCLK1_QR0_P
11
11
17
18
REFCLK1_QL0_CN
REFCLK1_QL0_CP
C41
C42
0.1uF
0.1uF
REFCLK1_QL0_N
REFCLK1_QL0_P
11
11
21
22
Si5338A_CLK0_125_N
Si5338A_CLK0_125_P
4.7k
R32
TERM_MUX_CLKIN
PDn
5
4
3
2
Si5338A_CLK0_125_P
Si5338A_CLK0_125_N
R48
100
1%
6
7
CLKIN_SMA_CP
CLKIN_SMA_CN
16
15
CLK_SEL
28
19,25
Q3p
Q3n
PDn
Q4p
Q4n
CLK1p
CLK1n
Q5p
Q5n
CLK2p
CLK2n
CLK_SEL
22
B
21
Q1p
Q1n
Q2p
Q2n
Gn
GL
GND
4.7k
1
8
VDD
VDD
VDD
29
BUFFER_EN
4.7k GL
R47
U5
9
5
2
4.7k
2.5V
R46
CAD Note:
Place 100 ohm resistor
near IDT5T9306 pins
R41
R42
Clock Distribution to Top & Bottom
Left & Right Tranceiver Banks
Q6p
Q6n
C50
C51
C52
0.1uF
0.1uF
2.2uF
13
13
10
11
13
13
19
18
REFCLK2_QR1_CP C56
REFCLK2_QR1_CN
0.1uF
C57
0.1uF
13
13
REFCLK2_QL1_P
REFCLK2_QL1_N
11
11
REFCLK2_QR1_P
REFCLK2_QR1_N
C34
C26
C27
C28
C35
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2
CLOCK_SDA
7
CLOCK_SCL
8
OE
SDI Reference Clocks
2.5V
VDD
SDA
CLK+
SCL
CLK-
GND
VC
LVDS
11
5
CLK_148_CN C46
0.1uF CLK_148_N
11
1
SI571_VCONTROL
SDI_CLK148_UP
R40
4.99K
From FPGA
SDI_CLK148_DN
R43
4.99K
GND
VCC
OUT
C63
11
11
C64
C65
2.2uF
0.1uF
2
6
C58
C59
0.1uF
10uF
NC
OUTn
VCC
GND
4
CLK_125_P
13
5
CLK_125_N
13
3
To bottom CLKIN
Si511 - 125.0MHz
100MHz Configuration Clock
0.1uF
Design Note:
Clock output goes to top/bottom
FPGA and MAXV
2.5V
10uF
VDD_SL18860DC 2
From MAXV
19
CLK50_EN
6
7
2.5V
10K
5
VDD
CLKOUT1
CLKIN
CLKOUT2
OE1
CLKOUT3
OE2
OE_OSC
OE3
GND
8
CLKIN_50_TOP
9
CLKIN_50_BOT
10
CLKIN_50_MAXV
4
OSC_50M_EN
EN
VCC
GND
OUT
C60
C62
2.2uF
0.1uF
19
13
13
19
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
1
Size
B
5
LVCMOS
CLK_CONFIG
3
LVCMOS
Date:
6
4
Si510 - 100MHz
SL18860DC
7
OUT
B
3
R285
8
LVDS
EN
26
25
U6
49.9
CLKOUT_50
Si510 - 50MHz
A
C
0.1uF
180K C53
X3
R49
3
R44
X2
1
2.5V
24
23
2.5V
4
1000pF
C48
125MHz Clocks for ENET
2.5V
50MHz LVMOS Clocks for FPGA and MAXV
EN
10uF
0.1uF CLK_148_P
IDT5T9306
(Alternate: IDT8R9306I)
C61
2
0.1uF
CLK_148_CP C45
2
1
C43
4
1
2.5V
D
C44
6
From MAXV
CLK125_EN
19
CLK_SEL = HIGH selects (CLK1p/n) Si5338A input
CLK_SEL = LOW selects (CLK2p/n) SMA input
X4
CAD Note:
Place near NB6L11SMNG
clock buffer
X1
SI571_EN
7
CLKINBOT_125_P
CLKINBOT_125_N
0.1uF
CLKINBOT_100_P
CLKINBOT_100_N
7
3
4
0.1uF
C55
3
4
10K
LVDS
REFCLK2_QL1_CP C54
REFCLK2_QL1_CN
13
13
Si571
CLKINTOP_125_P
CLKINTOP_125_N
12
13
CLKINTOP_100_P
CLKINTOP_100_N
6
7
8
17
NC
GND
GND
EP_GND
3
2.5V
2.5V
R45
CAD Note:
Place 84.5 & 124 ohm resistor
near IDT5T9306 pins
14
17
20
27
CAD Note:
Place 100 ohm resistors &
cap near IDT5T9306
R36
R37
VDD
VDD
VDD
VDD
1
C49
19
NC
5
4
3
2
100 1%
R39
CLKIN_SMA_N
J8
0.1uF
CLKIN_SMA_CP
CLKIN_SMA_CN
124
124
R38
100 1%
C
84.5
84.5
E
1
2
2.5V
R35
19
3.3V
0.1uF
Q1
Q1
From MAXV
19
C47
D
VTD
VTD
D
Q0
Q0
Si571 Programmable Oscillator
Use Clock Control GUI
(Default 148.5MHz)
I2C Address 55 HEX
2.5V
Si5338 Programmable Oscillator Use Clock Control GUI (Defaults
125MHz, 409.6MHz, 156.25MHz, 100MHz)
I2C Address 70 HEX
Si5338A-CUSTOM
CLKIN_SMA_P
11
12
9
10
LVDS
VCC
VCC
VCC
VCC
VCC
NB6L11SMNG
LVDS
User Clock Input
1
5
13
14
15
16
BLM15AG221SN1
300mA
8
23
25
RSVD_GND
EPAD
J7
100MHz Clock Distribution to Top & Bottom Banks
2.5V
L1
4
3
Arria V GX Starter Kit Board
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
14
of
1
35
8
7
6
2.5V
0.1uF
5
4
0.1uF
C4
C3
C2
C1
JTAG_TCK
JTAG_BLASTER_TDO
JTAG_BLASTER_TDI
JTAG_TMS
PCIE_JTAG_EN
19
B3
VL
VCC
IO_VL1
IO_VL2
IO_VL3
IO_VL4
IO_VCC1
IO_VCC2
IO_VCC3
IO_VCC4
EN
GND
B1
SW2
A4
A3
A2
A1
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
1
2
3
4
6
6
6
6
B4
5M2210_JTAG_EN
HSMA_JTAG_EN
PCIE_JTAG_EN
E
2.5V
JTAG Chain Control
8
7
6
5
OPEN
B2
1
C67
U7
E
2
JTAG
3.3V
C66
3
R50
R51
R52
1k
1k
1k
Switch, DIP x4, TDA04H0SB1
Level Shifter, MAX13042
JTAG_TCK
R53
DNI
C68
DNI
ON = not-in-chain
OFF = in-chain
R54
1k
USB Blaster Programming Header
(uses JTAG mode only)
2.5V
2.5V
D
D
J9
2
4
6
8
10
USB_DISABLEn
24
2.5V
R57
1k
1
3
5
7
9
JTAG_TCK
JTAG_BLASTER_TDI
JTAG_TMS
12,19,22,24
12,24
JTAG_BLASTER_TDO
2x5-PIN JTAG HEADER
12,24
R56
1k
R58
JTAG_BLASTER_TDO
1k
R59
DNI
JTAG_BLASTER_TDI
Design Note:
Populate R59 if you would like to
Master the JTAG chain through
HSMC Port .
TS5A23157 Switch Functions
When Pins 1 & 5 are:
LOW --> NC to/from COM = ON and NO to/from COM = OFF
HIGH --> NC to/from COM = OFF and NO to/from COM = ON
C
Logic 0 = pin 10 <--> pin 9 (HSMA Bypass)
Logic 1 = pin 10 <--> pin 2 (HSMA Enable)
22
U8
HSMA_JTAG_EN
1
HSMA_JTAG_TDO
2
Logic 0 = pin 6 <--> pin 7 (HSMA Bypass)
Logic 1 = pin 6 <--> pin 4 (HSMA Enable)
C
3
JTAG_TMS
4
HSMA_JTAG_EN
5
B
IN1
COM1
NO1
NC1
GND
V+
NO2
NC2
IN2
COM2
10
9
8
7
6
JTAG_5M2210_TDI
19
JTAG_FPGA_TDO_RETIMER
22,24
2.5V
HSMC TDI = JTAG_FPGA_TDO_RETIMER
C69
0.1uF
2.5V
R55
1k
HSMA_JTAG_TMS
22
B
TS5A23157
Logic 0 = pin 10 <--> pin 9 (5M2210 Bypass)
Logic 1 = pin 10 <--> pin 2 (5M2210 Enable)
5M2210_JTAG_EN
19
JTAG_5M2210_TDO
Logic 0 = pin 6 <--> pin 7 (5M2210 Bypass)
Logic 1 = pin 6 <--> pin 4 (5M2210 Enable)
JTAG_TMS
5M2210_JTAG_EN
A
U9
1
2
3
4
5
IN1
COM1
NO1
NC1
GND
V+
NO2
NC2
IN2
COM2
10
JTAG_BLASTER_TDI
9
JTAG_5M2210_TDI
2.5V
8
C70
24
0.1uF
2.5V
7
6
R60
1k
5M2210_JTAG_TMS
19
A
TS5A23157
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
15
of
1
35
8
7
6
5
4
3
2
1
256MB DDR3 x32 SDRAM
Arria V Interface
DDR3_DQ[31:0]
E
10
E
DDR3_A[13:0]
10
DDR3_DQS_P[3:0]
10
DDR3_DQS_N[3:0]
U10
U11
DDR3 Device
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
D
K9
J7
K7
DDR3_CKE
DDR3_CLK_P
DDR3_CLK_N
C
DDR3_DM2
DDR3_DM3
E7
D3
DDR3_CSn
DDR3_WEn
DDR3_RASn
DDR3_CASn
L2
L3
J3
K3
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_RESETn
DDR3_ODT
DDR3_ZQ02
VREF_DDR3
M2
N8
M3
T2
K1
L8
H1
M8
R61
C71
B2
D9
G7
K2
K8
N1
N9
R1
R9
0.1uF
240
A1
A8
C1
C9
D2
E9
F1
H2
H9
1.5V
B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CKE
CK_P
CK_N
DQS0p
DQS0n
DQS1p
DQS1n
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
NC_J1
NC_J9
NC_L1
NC_L9
NC/A13
NC/A14
NC/A15
VREFDQ
VREFCA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
F3
G3
C7
B7
DDR3_DQS_P2
DDR3_DQS_N2
DDR3_DQS_P3
DDR3_DQS_N3
DDR3_A13
B1
B9
D1
D8
E2
E8
F9
G1
G9
E7
D3
DDR3_CSn
DDR3_WEn
DDR3_RASn
DDR3_CASn
L2
L3
J3
K3
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_RESETn
DDR3_ODT
DDR3_ZQ01
VREF_DDR3
M2
N8
M3
T2
K1
L8
H1
M8
0.1uF
DDR3_CLK_P
240
R63
100
1%
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
DDR3_CLK_N
C93
0.47uF
C80
4.7nF
3300pF
2200pF
C94
0.47uF
C95
0.1uF
C96
0.1uF
C81
C82
2200pF
C97
0.1uF
C98
0.01uF
2200pF
C99
0.01uF
A1
A8
C1
C9
D2
E9
F1
H2
H9
1.5V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CKE
CK_P
CK_N
DQS0p
DQS0n
DQS1p
DQS1n
DM0
DM1
CS
WE
RAS
CAS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8
DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
F3
G3
C7
B7
DDR3_DQS_P0
DDR3_DQS_N0
DDR3_DQS_P1
DDR3_DQS_N1
C83
BA0
BA1
BA2
RESETn
ODT
ZQ
NC/A13
NC/A14
NC/A15
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J1
J9
L1
L9
T3
T7
M7
10
DDR3_CKE
10
DDR3_CLK_P
10
DDR3_CLK_N
10
DDR3_CSn
10
DDR3_WEn
10
DDR3_RASn
D
10
DDR3_CASn
10
DDR3_RESETn
10
DDR3_ODT
10
4.7k DDR3_CKE R425
0.75V_VTT
DDR3_A0
DDR3_BA2
DDR3_A6
DDR3_A8
DDR3_A1
DDR3_A10
RN1A
RN1B
RN1C
RN1D
RN1E
RN1F
RN1G
RN1H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
56
56
56
56
56
56
56
56
DDR3_RESETn
DDR3_RASn
DDR3_BA1
DDR3_A9
DDR3_A12
DDR3_A11
DDR3_A13
DDR3_A2
RN2A
RN2B
RN2C
RN2D
RN2E
RN2F
RN2G
RN2H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
56
56
56
56
56
56
56
56
DDR3_A4
B1
B9
D1
D8
E2
E8
F9
G1
G9
CAD Note:
Overlap resistor pads
DNI
DDR3_A13
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
C74
C75
C76
C77
C84
4.7nF
3300pF
2200pF
2200pF
2200pF
2200pF
C85
C86
C87
C88
C89
C90
C91
C92
0.47uF
0.47uF
0.1uF
0.1uF
0.1uF
0.01uF
0.01uF
0.01uF
RN3A
RN3B
RN3C
RN3D
RN3E
RN3F
RN3G
RN3H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
1
2
3
4
CN2
8
7
6
5
B
CN3
8
7
6
5
0.1uF
CAD Note:
Use tree-topology for termination signals
Use star via to branch out address/
command/control signals from FPGA
to memory devices and termination resistors
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Date:
5
C
0.75V_VTT
56
56
56
56
56
56
56
56
Title
6
8
7
6
5
0.1uF
B
7
CN1
0.75V_VTT
0.75V_VTT
DDR3_ODT
DDR3_A5
DDR3_A7
DDR3_WEn
DDR3_A3
DDR3_CASn
DDR3_CSn
DDR3_BA0
1
2
3
4
0.1uF
Size
8
0.75V_VTT
CAD Note:
Place cap arrays near
resistor packs and on
the same side of PCB
0.75V_VTT
2200pF
0.01uF
DDR3_DM[3:0]
R423
C73
C100
10
0.75V_VTT
NC_J1
NC_J9
NC_L1
NC_L9
DDR3 SDRAM, MT41J64M16LA-15E
1.5V
CAD Note:
Place decoupling caps
near SDRAM power pins
C79
B2
D9
G7
K2
K8
N1
N9
R1
R9
C72
DDR3 SDRAM, MT41J64M16LA-15E
A
DDR3_DM0
DDR3_DM1
R62
1.5V
C78
K9
J7
K7
DDR3_CKE
DDR3_CLK_P
DDR3_CLK_N
J1
J9
L1
L9
T3
T7
M7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
10
DDR3_BA[2:0]
DDR3 Device
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
16
of
1
35
8
7
6
5
4
3
2
1
Flash
SRAM, FPGA, MAX V Interface
E
FSM_A[26:0]
7,18,19
FSM_D[31:0]
Flash A
FLASH 1Gb (64M X 16)
U12
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_A26
D
C
FLASH_CLK
E6
FLASH_RESETn D4
FLASH_CEn0 B4
F8
FLASH_OEn
G8
FLASH_WEn
FLASH_ADVn F6
C6
FLASH_WPn
7,18,19
Flash B
FLASH 1Gb (64M X 16)
U13
PC28FxxxP30B85
FLASH
E
1.8V
VPP
A1
A2
VCC
A3
VCC
A4
A5
VCCQ
A6
VCCQ
A7
VCCQ
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
NC(64M)/A23
D13
NC(64M,128M)/A24 D14
NC/A25(512M)
D15
NC/A26(1G)
WAIT
CLK
GND
RESET#
GND
CE#
GND
OE#
GND
WE#
ADV#
RFU0
WP#
RFU1
RFU2
RFU3
A4
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_A26
A6
H3
2.5V
D5
D6
G4
F2
E2
G3
E4
E5
G5
G6
H7
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
E1
E3
F3
F4
F5
H5
G7
E7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
F7
FLASH_RDYBSYn0
FLASH_CLK
B2
H2
H4
H6
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
E6
FLASH_RESETn D4
FLASH_CEn1 B4
F8
FLASH_OEn
G8
FLASH_WEn
FLASH_ADVn F6
C6
FLASH_WPn
H1
G2
F1
E8
PC28F00AP30BF
PC28FxxxP30B85
FLASH
VPP
A1
A2
VCC
A3
VCC
A4
A5
VCCQ
A6
VCCQ
A7
VCCQ
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
NC(64M)/A23
D13
NC(64M,128M)/A24 D14
NC/A25(512M)
D15
NC/A26(1G)
WAIT
CLK
GND
RESET#
GND
CE#
GND
OE#
GND
WE#
ADV#
RFU0
WP#
RFU1
RFU2
RFU3
FLASH_CLK
FLASH_RESETn
FLASH_OEn
FLASH_WEn
FLASH_ADVn
1.8V
A4
A6
H3
2.5V
7,19
7,19
7,19
7,19
7,19
FLASH_CEn[1:0]
D5
D6
G4
7,19
D
FLASH_RDYBSYn[1:0]
F2
E2
G3
E4
E5
G5
G6
H7
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
E1
E3
F3
F4
F5
H5
G7
E7
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
F7
FLASH_RDYBSYn1
7,19
Design Note:
- When using a single x16 flash device a word consists of 16 data bits
so addressing starts with FSM_A2 mapped to address bit 1 in software.
- When using dual x16 flash devices for an equivalent x32 (x16||x16)
flash device a word consists of 32 data bits so addressing starts with
FSM_A2 mapped to address bit 2 in software.
B2
H2
H4
H6
C
H1
G2
F1
E8
PC28F00AP30BF
B
B
2.5V
Place capacitors near Flash A
Place capacitors near Flash B
1.8V
1.8V
C101
C102
C103
C104
C105
C106
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2.5V
A
10K
10K
10K
10K
R68
10K FLASH_RESETn
2.5V
C107
C108
C109
C110
C111
C112
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
FLASH_WEn
FLASH_WPn
FLASH_RDYBSYn0
FLASH_RDYBSYn1
R64
R65
R66
R67
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
17
of
1
35
8
7
6
5
4
3
2
1
SRAM
FSM BUS
FSM_D[31:0]
7,17,19
E
E
2.5V
J3
J9
K3
K9
L3
L9
M3
M9
N3
N9
C3
C9
D3
D9
E3
E9
F3
F9
G3
G9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U14
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
D
C
7
SRAM_CLK
B6
7
7
7
SRAM_OEn
SRAM_CEn
SRAM_CE2
SRAM_CE3n
SRAM_MODE
B8
A3
B3
A6
R1
7
SRAM_BWn0
SRAM_BWn1
SRAM_BWn2
SRAM_BWn3
SRAM_BWEn
B5
A5
A4
B4
A7
7
SRAM_GWn
B7
7
7
7
7
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_ZZ
SRAM_BWn[3:0]
7
B
R6
P6
A2
A10
B2
B10
N6
P3
P4
P8
P9
P10
P11
R3
R4
R8
R9
R10
R11
B1
A1
B11
C10
P2
R2
A8
B9
A9
H11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
2.5V
D4
D8
E4
E8
F4
F8
G4
G8
H4
H8
J4
J8
K4
K8
L4
L8
M4
M8
FSM_A[26:0]
7,17,19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC_144M
NC_288M
NC_576M
NC_1G
NC_A
NC_B
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CLK
OE_n
CE1_n
CE2
CE3_n
MODE
BWA_n
BWB_n
BWC_n
BWD_n
BWE_n
DQPA
DQPB
DQPC
DQPD
GW_n
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
ADSC_n
ADSP_n
ADV_n
ZZ
2.5V
TCK
TDI
TDO
TMS
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
N11
C11
C1
N1
SRAM_DQP0
SRAM_DQP1
SRAM_DQP2
SRAM_DQP3
D
C
7
7
7
7
A11
C2
H1
P1
H3
H9
H10
N2
N5
N10
B
H2
N7
L5
K7
K6
K5
J7
J6
J5
H7
H6
H5
G7
G6
G5
F7
C8
F6
L6
F5
E7
E6
E5
D7
D6
D5
C7
C6
C5
C4
M5
L7
N8
N4
M7
M6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R7
P5
P7
R5
J10
J11
K10
K11
L10
L11
M10
M11
D10
D11
E10
E11
F10
F11
G10
G11
D1
D2
E1
E2
F1
F2
G1
G2
J1
J2
K1
K2
L1
L2
M1
M2
SRAM, IS61VPS51236A
2.5V
2.5V
A
A
R70
R69
10K SRAM_CE2
10K SRAM_CE3n
C113
C114
C115
C116
C117
C118
C119
C120
C121
C122
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
18
of
1
35
8
7
6
5
4
3
5M2210 System Controller
U15A
E
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
D3
C2
C3
E3
D2
E4
D1
E5
FPGA_CONFIG_D8
FPGA_CONFIG_D9
FPGA_CONFIG_D10
FPGA_CONFIG_D11
FPGA_CONFIG_D12
FPGA_CONFIG_D13
FPGA_CONFIG_D14
FPGA_CONFIG_D15
F3
E1
F4
F2
F1
F6
G2
G3
G1
G4
H2
G5
H3
J1
H4
J2
D
H5
J5
USB_CLK
CLK_CONFIG
2
FPGA Interface
FPGA_CONFIG_D[15:0]
DIFFIO_L1P
DIFFIO_L1N
DIFFIO_L2P
DIFFIO_L2N
DIFFIO_L3P
DIFFIO_L3N
DIFFIO_L4P
DIFFIO_L4N
DIFFIO_L5P
DIFFIO_L5N
DIFFIO_L6P
DIFFIO_L6N
DIFFIO_L7P
DIFFIO_L7N
DIFFIO_L8P
DIFFIO_L8N
J4
K1
J3
K2
K5
L1
L2
K3
DIFFIO_L13P
DIFFIO_L13N
DIFFIO_L14P
DIFFIO_L14N
DIFFIO_L15P
DIFFIO_L15N
DIFFIO_L16P
DIFFIO_L16N
M1
M2
L4
L3
N1
M4
N2
M3
DIFFIO_L17P
DIFFIO_L17N
DIFFIO_L18P
DIFFIO_L18N
DIFFIO_L19P
DIFFIO_L19N
DIFFIO_L20P
DIFFIO_L20N
DIFFIO_L9P
DIFFIO_L21P
DIFFIO_L9N
DIFFIO_L21N
DIFFIO_L10P
DIFFIO_L10N
IOB1_1
DIFFIO_L11P
IOB1_2
DIFFIO_L11N
IOB1_3
DIFFIO_L12P
IOB1_4
DIFFIO_L12N
IOB1_5
IOB1/CLK0
IOB1/CLK1
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_DCLK
EXTRA_SIG0
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_CS0n
FAN_FORCE_ON
OVERTEMP
FPGA_nCONFIG
N3
P2
FPGA_CvP_CONFDONE
FPGA_PR_ERROR
HSMA_PRSNTn
E2
F5
H1
K4
L5
FPGA_PR_READY
FPGA_PR_REQUEST
FPGA_PR_DONE
CLK50_EN
CLK125_EN
CLOCK_SDA
CLOCK_SCL
P3
L6
M5
N4
TCK
TDI
TDO
TMS
SI571_EN
LTC3880_ALERT_N_2.5V
LTC3880_GPIO0_N_2.5V
LTC3880_SDA_2.5V
LTC3880_SCL_2.5V
INT_TSD_SDA
INT_TSD_SCL
JTAG_TCK
JTAG_5M2210_TDI
JTAG_5M2210_TDO
5M2210_JTAG_TMS
D4
B1
C5
C4
B4
D6
E6
B5
A5
D7
B6
E7
C8
B7
D8
A7
B8
A8
A9
E9
B9
D9
A10
C9
MAX V
BANK2
DIFFIO_T1P
DIFFIO_T1N
DIFFIO_T2P
DIFFIO_T2N
DIFFIO_T3P
DIFFIO_T3N
DIFFIO_T4P
DIFFIO_T4N
DIFFIO_T5P
DIFFIO_T5N
DIFFIO_T6P
DIFFIO_T6N
DIFFIO_T7P
DIFFIO_T7N
DIFFIO_T8P
DIFFIO_T8N
DIFFIO_T13P
DIFFIO_T13N
DIFFIO_T14P
DIFFIO_T14N
DIFFIO_T15P
DIFFIO_T15N
DIFFIO_T16P
DIFFIO_T16N
DIFFIO_T17P
DIFFIO_T17N
DIFFIO_T18P
DIFFIO_T18N
IOB2_6
IOB2_7
DIFFIO_T9P
DIFFIO_T9N
DIFFIO_T10P
DIFFIO_T10N
DIFFIO_T11P
DIFFIO_T11N
DIFFIO_T12P
DIFFIO_T12N
IOB2_8
IOB2_9
IOB2_10
IOB2_11
IOB2_12
IOB2_13
IOB2_14
IOB2_15
IOB2_16
IOB2_17
IOB2_18
IOB2_19
IOB2_20
12,15,22,24
15
15
15
E10
A11
B11
A12
E11
B12
C11
B13
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_DCLK
FPGA_nCONFIG
MSEL[4:0]
D12
B14
C13
B16
PGM_CONFIG
PGM_LED0
PGM_LED1
PGM_LED2
A13
A15
CLK_SEL
CLK_ENABLE
A2
A4
A6
B10
B3
C10
C12
C6
FACTORY_LOAD
MAX_ERROR
MAX_LOAD
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
C7
D10
D11
D5
E8
12
12
12
12
12
MAX5_BEn[3:0]
MAX5_OEn
MAX5_CSn
MAX5_WEn
MAX5_CLK
14
14
14
14
14
14
14
6
D
INT_TSD_SDA
INT_TSD_SCL
9
9
Power Monitor Interface
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_CS0n
OVERTEMP
PMBus Interface
PCIE_JTAG_EN
CPU_RESETn
SDI_TX_EN
SDI_RX_BYPASS
SDI_RX_EN
LTC3880_SCL_2.5V
LTC3880_SDA_2.5V
LTC3880_ALERT_N_2.5V
LTC3880_GPIO0_N_2.5V
25,27
25,27
27
27
31
31
31
31
31
SDI Interface
SDI_TX_EN
SDI_RX_BYPASS
SDI_RX_EN
MAX V, 5M2210ZF256
7,21
7,21
7,21
MAX V, 5M2210ZF256
U15C
U15D
MAX V
BANK3
C
B
FSM_A0
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
E14
C14
C15
E13
E12
D15
F14
D16
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
F13
E15
E16
F15
G14
F16
G13
G15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_D23
G12
G16
H14
H15
H13
H16
J13
J16
CLKIN_50_MAXV
J12
H12
DIFFIO_R1P
DIFFIO_R1N
DIFFIO_R2P
DIFFIO_R2N
DIFFIO_R3P
DIFFIO_R3N
DIFFIO_R4P
DIFFIO_R4N
DIFFIO_R13P
DIFFIO_R13N
DIFFIO_R14P
DIFFIO_R14N
DIFFIO_R15P
DIFFIO_R15N
DIFFIO_R16P
DIFFIO_R16N
DIFFIO_R5P
DIFFIO_R5N
DIFFIO_R6P
DIFFIO_R6N
DIFFIO_R7P
DIFFIO_R7N
DIFFIO_R8P
DIFFIO_R8N
DIFFIO_R17P
DIFFIO_R17N
DIFFIO_R18P
DIFFIO_R18N
DIFFIO_R19P
DIFFIO_R19N
DIFFIO_R20P
DIFFIO_R20N
DIFFIO_R9P
DIFFIO_R9N
DIFFIO_R10P
DIFFIO_R10N
DIFFIO_R11P
DIFFIO_R11N
DIFFIO_R12P
DIFFIO_R12N
DIFFIO_R21P
DIFFIO_R21N
DIFFIO_R22P
DIFFIO_R22N
IOB3_21
IOB3_22
IOB3_23
IOB3_24
IOB3_25
IOB3_26
IOB3_27
IOB3/CLK2
IOB3/CLK3
J14
J15
K16
K13
K15
K14
L16
L11
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
L15
L12
M16
L13
M15
L14
N16
M13
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
N15
N14
P15
P14
FSM_D16
FSM_D17
FSM_D18
FSM_D19
D13
D14
F11
FSM_D20
FSM_D21
FSM_D22
F12
K12
M14
N13
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_A25
FSM_A24
FSM_A23
FSM_D30
FSM_D31
FLASH_WEn
FLASH_CEn0
FLASH_OEn
FLASH_RDYBSYn0
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
FLASH_CEn1
FLASH_RDYBSYn1
R1
P4
T2
P5
R3
N5
P6
N6
R5
M6
T5
P7
R6
N7
M7
R7
USB_CFG2
USB_CFG3
USB_CFG4
USB_CFG5
USB_CFG6
USB_CFG7
USB_CFG8
USB_CFG9
P8
T7
N8
R8
T8
T9
R9
P9
MAX_RESETn
USB_CFG10
M9
M8
ON-BOARD USB BLASTER II
U15E
MAX V
BANK4
DIFFIO_B1P
DIFFIO_B1N
DIFFIO_B2P
DIFFIO_B2N
DIFFIO_B3P
DIFFIO_B3N
DIFFIO_B4P
DIFFIO_B4N
DIFFIO_B14P
DIFFIO_B14N
DIFFIO_B15P
DIFFIO_B15N
DIFFIO_B16P
DIFFIO_B16N
DIFFIO_B17P
DIFFIO_B17N
DIFFIO_B5P
DIFFIO_B5N
DIFFIO_B6P
DIFFIO_B6N
DIFFIO_B7P
DIFFIO_B7N
DIFFIO_B8P
DIFFIO_B8N
DIFFIO_B19P
DIFFIO_B19N
DIFFIO_B18P
DIFFIO_B18N
DIFFIO_B20P
DIFFIO_B20N
DIFFIO_B21P
DIFFIO_B21N
DIFFIO_B9P DIFFIO_B22P
DIFFIO_B9N DIFFIO_B22N
DIFFIO_B10P
IOB4_28
DIFFIO_B10N
IOB4_29
DIFFIO_B11P
IOB4_30
DIFFIO_B11N
IOB4_31
DIFFIO_B12P
IOB4_32
DIFFIO_B12N
IOB4_33
F7
G6
H7
H9
J10
J8
K11
L10
M10
R10
N10
T11
P10
R11
T12
N11
MAX5_OEn
MAX5_CSn
MAX5_WEn
MAX5_CLK
MAX5_BEn0
MAX5_BEn1
MAX5_BEn2
MAX5_BEn3
T13
R13
R12
P11
N12
R14
P12
T15
EXTRA_SIG1
FSM_A26
SECURITY_MODE
M570_CLOCK
FACTORY_STATUS
FACTORY_REQUEST
M570_PCIE_JTAG_EN
EXTRA_SIG2
R16
P13
M11
M12
N9
R4
T10
T4
USB_CFG0
USB_CFG11
USB_CFG1
DIFFIO_B13N/DEV_CLRn
DIFFIO_B13P/DEV_OE
A1
A16
B15
B2
G10
G7
G8
G9
K10
K7
K8
K9
R15
R2
T1
T16
T6
E
Clock Interface
9,22,25
FAN_FORCE_ON
7,17
7,17
7,17
7,17
7,17
7,17
7,17
7,17
7,17
CLK125_EN
CLK50_EN
SI571_EN
CLOCK_SDA
CLOCK_SCL
CLKIN_50_MAXV
CLK_CONFIG
9
9
9
9
9
HSMA_PRSNTn
7,17,18
FLASH_WEn
FLASH_CEn0
FLASH_CEn1
FLASH_OEn
FLASH_RDYBSYn0
FLASH_RDYBSYn1
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
12
FPGA_PR_DONE
FPGA_PR_REQUEST
FPGA_PR_READY
FPGA_PR_ERROR
FPGA_CvP_CONFDONE
7,17,18
FSM_A[26:0]
12
12
12
12
MAX_CONF_DONEn
PGM_SEL
FSM_D[31:0]
12
U15B
MAX V
BANK1
1
Flash & SRAM Interface
USB_CFG[11:0]
1.8V
MAX V
Power
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
F10
G11
H10
H8
J7
J9
K6
L7
C
24
USB_CLK
PCIE_JTAG_EN
M570_PCIE_JTAG_EN
M570_CLOCK
FACTORY_STATUS
FACTORY_REQUEST
2.5V
C1
H6
J6
P1
A14
A3
F8
F9
24
EXTRA_SIG[2:0]
8,24
15
24
24
24
24
MAXV DIPSWITCH
CLK_SEL
CLK_ENABLE
FACTORY_LOAD
SECURITY_MODE
14,25
25
25
25
PUSH BUTTON INTERFACE
2.5V
C16
H11
J11
P16
CPU_RESETn
PGM_SEL
PGM_CONFIG
MAX_RESETn
L8
L9
T14
T3
LED INTERFACE
B
12,25
25
25
25
PGM_LED[2:0]
25
MAX_ERROR
25
MAX V, 5M2210ZF256
MAX_LOAD
25
MAX_CONF_DONEn
MAX V, 5M2210ZF256
25
MAX V, 5M2210ZF256
VCCINT
1.8V
2.5V
2.5V VCCIO Bank 1 & 2
2.5V
2.5V VCCIO Bank 3 & 4
A
A
C123
C124
C125
C126
C127
C128
C129
C130
C131
C132
C133
C134
C135
C136
C137
C138
C139
C140
C141
C142
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
19
of
1
35
8
7
6
5
4
3
2
1
HDMI Video Output
E
E
U16A
7
HDMI_HPD
HPD_SRC
HPD_SINK
3.3V
REXT
D
HDMI_TX_P0
HDMI_TX_N0
C143
HDMI_TX_P1
HDMI_TX_N1
C147
0.1uF
C149
HDMI_TX_P2
HDMI_TX_N2
C151
0.1uF
C153
HDMI_TX_CLK_P C155
HDMI_TX_CLK_N
3.3V
0.1uF
C145
0.1uF
C157
HDMI_DDC_EN
HDMI_OE_N
32
25
0.1uF
HDMI_TX_C_P0
HDMI_TX_C_N0
39
38
0.1uF
HDMI_TX_C_P1
HDMI_TX_C_N1
42
41
0.1uF
HDMI_TX_C_P2
HDMI_TX_C_N2
45
44
HDMI_TX_CLK_C_P 48
HDMI_TX_CLK_C_N 47
0.1uF
HDMI_FUNCTION3
4.7k
R77
34
9
8
HDMI_SCL_DDC
HDMI_SDA_DDC
HDMI_CONN_HPD
6
HDMI_REXT
5.0V
4.7k
R73
J10
HDMI-19-01-F-SM
DDC_EN
OE_N
18
IN_D1p
IN_D1n
OUT_D1p
OUT_D1n
IN_D2p
IN_D2n
OUT_D2p
OUT_D2n
IN_D3p
IN_D3n
OUT_D3p
OUT_D3n
IN_D4p
IN_D4n
OUT_D4p
OUT_D4n
22
23
TMDS_DATA_P0
TMDS_DATA_N0
19
20
TMDS_DATA_P1
TMDS_DATA_N1
16
17
TMDS_DATA_P2
TMDS_DATA_N2
13
14
FUNCTION3
28
29
SCL_SINK
SDA_SINK
7
9
8
4
6
5
1
3
2
TMDS_CLKp
TMDS_CLKn
10
12
11
DDCSCL
DDCSDA
17
5.0V
16
15
13
DDCSDA
DDCSCL
19
HDMI_CONN_HPD
2.0K
2.0K
R71
R72
DNI
D
R78
Design Note:
Level shifter has 160k
internal pull down
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA_SHLD_CLK
3.3V
C
C
U16B
C159
C160
C162
C163
C164
C165
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C166
C167
C168
C169
C170
C171
0.1uF
0.1uF
1000pF
1000pF
1000pF
1000pF
2
11
15
21
26
33
40
46
R87
4.7k
HDMI_ANALOG2 10
B
14
G1
G2
G3
G4
STHDLS101T
Design Note:
Place near TMDS level shifter VCC pins
RESERVED_NC
TMDS_DATA_P0
DDC_CEC_GND
TMDS_DATA_N0
TMDS_DATA_SHLD0
SDA
TMDS_DATA_P1
SCL
TMDS_DATA_N1
CEC
TMDS_DATA_SHLD1
HOT_PLUG_DETECT
TMDS_DATA_P2
TMDS_DATA_N2
TMDS_DATA_SHLD2
SCL_SRC
SDA_SRC
TMDS Level Shifter
3.3V
HDMI 19-Pin Connector
5V_VCC
MTG1
MTG2
MTG3
MTG4
4.7k
R74
30
C172
C173
C161
C144
C146
C148
1000pF
1000pF
1000pF
1000pF
1000pF
1000pF
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND_EPAD
ANALOG2
FUNCTION1
FUNCTION2
FUNCTION4
1
5
12
18
24
27
31
36
37
43
49
FPGA Interface
HDMI_FPGA_SCL_DDC
8
HDMI_FPGA_SDA_DDC
8
HDMI_FPGA_OE_N
3
4
35
8
HDMI_FPGA_HPD
8
STHDLS101T
B
HDMI_TX_P[2:0]
11
HDMI_TX_N[2:0]
11
HDMI_TX_CLK_P
2.5V_VCCIO_VCCPD_VCCPGM
R82
R83
0.1uF
3.3V
C175
U17
B2
2.0K
A
DNI
11
3.3V
2.5V
R84
11
HDMI_TX_CLK_N
Design Note:
Use weak pull-up in
FPGA on DDC signals
DNI
HDMI_FPGA_SCL_DDC
HDMI_FPGA_SDA_DDC
HDMI_FPGA_HPD
HDMI_FPGA_OE_N
C4
C3
C2
C1
HDMI_5V_LVL_SHIFTER_EN
B3
VL
IO_VL1
IO_VL2
IO_VL3
IO_VL4
EN
0.1uF
VCC
IO_VCC1
IO_VCC2
IO_VCC3
IO_VCC4
GND
R85
R86
2.0K
2.0K
C174
B1
A4
A3
A2
A1
B4
Level Shifter, MAX13042
HDMI_SCL_DDC
HDMI_SDA_DDC
HDMI_HPD
HDMI_OE_N
R81
A
DNI
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Design Note:
Level shifter internal
pull down
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
20
of
1
35
8
7
6
5
4
3
2
1
SDI Cable Driver, Equalizer, and SMB
E
75 Ohm Impedance
3.3V_SDI
R89
750
L2
1
E
5.6nH
2
SDI_TXDRV_FILTER_P
75
R90
3.3V_SDI
SDI_TX_P
C177
11
SDI_TX_N
7
SDI_TX_SD_HDn
4.7uF
C178
4.7uF
SDI_TXCAP_P
SDI_TXCAP_N
1
2
SDI_TX_RSET
10
4
SDI_TX_EN
R92
R94
From FPGA
R95
SDI_SDA
SDI_SCL
10K
10K
SDI
SDI
5
6
7
8
SDO
SDO
RSTO
FAULT
RSTI
ENABLE
SDA
SCL
14
15
49.9
VCC
SD/HD
RREF
R96
49.9
Cable
Driver
Mini SMB
9
R91
12
11
75
SDI_TXDRV_P
SDI_TXDRV_N
16
13
D
R422
10K
R93
75
3
17
R97
SDI Cable Driver, LMH0303SQx
L3
NC5
NC6
VEE
CENTERPAD
Right
Angle
CAD Note:
Route traces at
secondary side
3.3V_SDI
SDI_FAULT
7,19
J11
1
SDI_TXBNC_P
U18
3.3V_SDI
D
4.7uF
2
3
4
5
11
C176
3.3V_SDI
75
C179
4.7uF
SDI_TXBNC_N
5.6nH
1
R98
2
SDI_TXDRV_FILTER_N
C180
75
3.3V
3.3V_SDI
L4
0.01uF
120 ohm FB
C182
C183
C184
C185
0.1uF
0.1uF
220nF
220nF
FPGA Interface
C181
C
22uF
C
SDI_SCL
75 Ohm Impedance
13
SDI_SDA
13
SDI_FAULT
L5
J12
1
2
SDI_IN_P1
SDI_IN_FILTER_P1
Mini SMB
1.0UF
C186
75
R99
3.3V_SDI
5
4
3
2
Right
Angle
13
5.6nH
1
75
R100
CAD Note:
Route traces at
secondary side
U19
R101
1.0UF
37.4 C187
B
2
3
SDI_EQIN_P1
SDI_EQIN_N1
7
15
4
12
SDI_RX_CDn
3.3V_SDI
From FPGA
R102
3.3V_SDI
10K
5
6
AEC
7,19
SDI_RX_BYPASS
7,19
SDI_RX_EN
1.0UF
C190
R103
Read-Only (Auto-Mute)
14
8
R104
SDI
SDI
BYPASS
CD
SPI_EN
AUTO_SLEEP
VCC1
VCC2
SDO
SDO
AEC+
AECMUTE
MUTEref
VEE1
VEE2
DAP
13
16
11
10
SDO_P
SDO_N
C189
C188
4.7UF
4.7UF
SDI_RX_P
SDI_RX_N
11
11
B
1
9
17
SDI Cable Equalizer, LMH0384SQ
3.3V_SDI
R105
75
0
D1
0
Green_LED
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
21
of
1
35
7
6
Cad Note:
Place resistors near HSMC connector
HSMA_TX_P7
HSMA_TX_N7
HSMA_TX_P6
HSMA_TX_N6
HSMA_TX_P5
HSMA_TX_N5
HSMA_TX_P4
HSMA_TX_N4
HSMA_TX_P3
HSMA_TX_N3
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P0
HSMA_TX_N0
E
R106
R107
R108
R109
R110
R111
R112
R113
R114
R115
R116
R117
R118
R119
R120
R121
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSMA_TX_CP7
HSMA_TX_CN7
HSMA_TX_CP6
HSMA_TX_CN6
HSMA_TX_CP5
HSMA_TX_CN5
HSMA_TX_CP4
HSMA_TX_CN4
HSMA_TX_CP3
HSMA_TX_CN3
HSMA_TX_CP2
HSMA_TX_CN2
HSMA_TX_CP1
HSMA_TX_CN1
HSMA_TX_CP0
HSMA_TX_CN0
HSMA_SDA
JTAG_TCK
HSMA_JTAG_TDO
HSMA_CLK_OUT0
D
HSMA_TX_D_P0
HSMA_TX_D_N0
HSMA_TX_D_P1
HSMA_TX_D_N1
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P5
HSMA_TX_D_N5
C
HSMA_TX_D_P6
HSMA_TX_D_N6
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P10
HSMA_TX_D_N10
B
HSMA_TX_D_P11
HSMA_TX_D_N11
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_TX_D_P14
HSMA_TX_D_N14
CAD Note:
Place near HSMC connector
A
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_TX_D_P16
HSMA_TX_D_N16
3.3V
C191
C192
10uF
10uF
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
3.3V
4
3
J13
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
HSMA_D0
HSMA_D2
12V
5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
2
BANK 1
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
A
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
BANK 3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HSMA_RX_P7
HSMA_RX_N7
HSMA_RX_P6
HSMA_RX_N6
HSMA_RX_P5
HSMA_RX_N5
HSMA_RX_P4
HSMA_RX_N4
HSMA_RX_P3
HSMA_RX_N3
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P0
HSMA_RX_N0
HSMA_SCL
HSMA_JTAG_TMS
JTAG_FPGA_TDO_RETIMER
HSMA_CLK_IN0
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
HSMA_D1
HSMA_D3
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMA_TX_P[7:0]
5
11
HSMA_SCL
8
HSMA_SDA
8
JTAG_TCK
12,15,19,24
HSMA_JTAG_TMS
15
HSMA_JTAG_TDO
15
JTAG_FPGA_TDO_RETIMER
15,24
HSMA_CLK_OUT0
8
D
HSMA_CLK_IN0
HSMA_RX_D_P0
HSMA_RX_D_N0
13
HSMA_D[3:0]
HSMA_RX_D_P1
HSMA_RX_D_N1
8
HSMA_TX_D_P[16:0]
8,9,13
HSMA_TX_D_N[16:0]
HSMA_RX_D_P2
HSMA_RX_D_N2
8,9,13
HSMA_RX_D_P[16:0]
HSMA_RX_D_P3
HSMA_RX_D_N3
8,9
HSMA_RX_D_N[16:0]
8,9
HSMA_CLK_OUT_P[2:1]
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMA_CLK_OUT_N[2:1]
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMA_CLK_IN_P[2:1]
C
9,19,25
REFCLK3_QR1_P
11
REFCLK3_QR1_N
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
8,9
13
HSMA_PRSNTn
HSMA_RX_D_P7
HSMA_RX_D_N7
8,9
13
HSMA_CLK_IN_N[2:1]
HSMA_RX_D_P6
HSMA_RX_D_N6
E
11
HSMA_RX_N[7:0]
11
To FPGA
To HSMA connector
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMA_CLK_IN_P2
R309
0
REFCLK3_QR1_P
R310
DNI
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMA_CLK_IN_N2
R312
0
HSMA_RX_D_P13
HSMA_RX_D_N13
REFCLK3_QR1_N
R311
DNI
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMA_RX_D_P14
HSMA_RX_D_N14
Design Note:
If HSMC-to-PCIe adapter board is used
and FPGA is configured as PCIe root port,
remove R309 & R312 and populate
R310 & R311 with 0 ohm resistors
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_CLK_IN_R_P2
HSMA_CLK_IN_R_N2
HSMA_PRSNTn
B
HSMA_CLK_IN_R_N2
CAD Note:
Overlap pads on
each resistor pair
A
Title
12V
Size
B
4
HSMA_CLK_IN_R_P2
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
161
162
163
164
165
166
167
168
169
170
171
172
6
11
HSMA_RX_P[7:0]
Date:
7
11
HSMA_TX_N[7:0]
CONN, HSMC_Male
8
1
FPGA Interface
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
8
HSMC Port
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
22
of
1
35
8
7
6
5
4
3
2
1
10/100/1000 Ethernet
E
RGMII Mode (default)
2.5V
E
U20A
8
8
8
8
ENET_RESETn
VCC
Design Note:
MDI signals termination
CAD Note:
Place near RJ-45 connector pins
C194
0.01uF
C195
0.01uF
C196
0.01uF
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
TD1_P
TD1_N
TD2_P
TD2_N
GND_TAB
GND_TAB
0.01uF
R126
R127
R128
R129
R130
R131
R132
R133
29
31
33
34
39
41
42
43
TD3_P
TD3_N
ENET_MDIO
ENET_MDC
ENET_INTn
24
25
23
GND
1
2
3
6
4
5
7
8
10
37
38
V24
V25
7499111001A
30
56
ENET_RSET
2.5V
2.5V
10K
R286
X5
1
2
EN
VCC
GND
OUT
3
22
55
54
53
ENET_XTAL_25MHZ
C433
0.01uF
13
51
B
97
NC1
NC2
R134
R135
4.99K
1%
4.7k
47
49
44
50
46
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
HSDAC_P
HSDAC_N
RXCLK
RX_DV
RX_ER
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
COL
RSET
SEL_FREQ
125CLK
XTAL1
XTAL2
VSSC
TRST_N
TCK
TDI
TDO
TMS
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
8
4
9
7
ENET_GTX_CLK
11
12
14
16
17
18
19
20
ENET_TX_D0
ENET_TX_D1
ENET_TX_D2
ENET_TX_D3
2
94
3
ENET_RX_CLK
ENET_RX_DV
95
92
93
91
90
89
87
86
ENET_RX_D0
ENET_RX_D1
ENET_RX_D2
ENET_RX_D3
ENET_TX_EN
ENET_TX_D[3:0]
8
ENET_RX_D[3:0]
8
ENET_GTX_CLK
ENET_TX_EN
ENET_RX_CLK
ENET_RX_DV
D
8
8
13
8
84
83
79
80
82
81
77
75
ENET_TX_P
ENET_TX_N
ENET_RX_P
ENET_RX_N
68
69
70
73
74
76
ENET_LED_TX
ENET_LED_RX
ENET_LED_DUPLEX
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
8
8
8
8
C
Ethernet PHY, 88E1111
72
66
52
VDDOH
VDDOH
VDDOH
26
48
5
21
88
96
VDDO
VDDO
VDDO
VDDO
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VDDOX
VDDOX
32
36
35
40
45
78
MDIO
MDC
INT_N
JTAG
2.5V
U20B
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
4
25.00MHz
C
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
TEST
12
11
D
C193
TD0_P
TD0_N
9
GTX_CLK
TX_CLK
TX_EN
TX_ER
MGMT
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
2.5V
COMA
RESET_N
MDI INTERFACE
ENET_CONFIG4
ENET_CONFIG5
ENET_LED_RX
65
64
63
61
60
59
58
2.5V
J19
27
28
GMII/MII/TBI INTERFACE
ENET_MDIO
ENET_MDC
ENET_INTn
ENET_RESETn
4.7k
4.7k
4.7k
4.7k
SGMII INTERFACE
R122
R123
R124
R125
ENET_DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
1
6
10
15
57
62
67
71
85
D2
Green_LED
ENET_LED_DUPLEX
ENET_LED_LINK1000
R305
0
ENET_LED_TX
R136
220
ENET_LED_RX
R137
220
ENET_LED_LINK1000
R138
220
ENET_LED_LINK100
R139
220
ENET_LED_LINK10
R304
220
ENET_CONFIG4
D3
Green_LED
R306
DNI
R308
0
ENET_CONFIG5
R307
DNI
CAD Note:
Overlap pads on
each resistor pair
D4
Green_LED
2.5V
ENET_LED_LINK10
CAD Note: Place near 88E1111 PHY
2.5V
B
D5
Green_LED
VSS
Ethernet PHY, 88E1111
2.5V
D33
Green_LED
ENET_DVDD
C199
C200
C201
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
23
of
1
35
8
7
R140
VBUS_5V
C212
0.1uF
1M
FX2_WAKEUP
10.0K
R142
6
Design Note:
GND isolation
C213
CAD Note:
Place R141, C214, C438
inside pennisula area
underneath USB connector
20K
0.1uF
C214
C438
FX2_PA2
FX2_FLAGC
FX2_PA7
FX2_FLAGA
FX2_PA3
FX2_PA4
M570_PCIE_JTAG_EN
FX2_PB4
FX2_PA6
FX2_PB2
FX2_FLAGB
FX2_PB0
FX2_PA1
FX2_PB5
USB_DISABLEn
FX2_PB6
U22
1
VBUS_5V
FX2_D_N
FX2_D_P
GND
VCC
4
C215
R143
FX2_RESETn
2
RESET
MR
3
0.1uF
RESET, MAX811
5
100K
3.3V
D1
D2
U24
D+
GND D-
3
D
U23
1
2
G1
A5
B5
C5
E7
E8
TPD2EUSB30
E1
E2
USB_CLK
24M_XTALIN
24M_XTALOUT
4
Y3
3
2
1
24MHz
C216
C217
12pF
12pF
C
FX2_PA1
FX2_PA2
FX2_PA3
FX2_PA4
FX2_PA5
FX2_PA6
FX2_PA7
G2
C1
C2
G8
G6
F8
F7
F6
C8
C7
C6
H2
F1
F2
H1
A4
B4
C4
D7
D8
3.3V
AVCC
AVCC
RESET
SCL
SDA
VCC
VCC
VCC
VCC
VCC
VCC
WAKEUP
CTL0
CTL1
CTL2
DMINUS
DPLUS
RDY0
RDY1
IFCLK
XTALIN
XTALOUT
CLKOUT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RESERVED
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
AGND
AGND
GND
GND
GND
GND
GND
GND
B8
F3
G3
B7
FX2_RESETn
FX2_SCL R144
FX2_SDA R145
B1
C1
C2
D1
D2
D3
E3
F1
F2
F3
G1
G2
G3
H1
H4
H7
2.0K
2.0K
FX2_FLAGA
FX2_FLAGB
FX2_FLAGC
A1
B1
FX2_SLRDn
FX2_SLWRn
FX2_PB0
FX2_PB1
FX2_PB2
FX2_PB3
FX2_PB4
FX2_PB5
FX2_PB6
FX2_PB7
A8
A7
B6
A6
B3
A3
C3
A2
FX2_PD0
FX2_PD1
FX2_PD2
FX2_PD3
FX2_PD4
FX2_PD5
FX2_PD6
FX2_PD7
8
USB_ADDR[1:0]
MAX II
BANK 1
IO_B1_B1
IO_B1_C1
IO_B1_C2
IO_B1_D1
IO_B1_D2
IO_B1_D3
IO_B1_E3
IO_B1_F1
IO_B1_F2
IO_B1_F3
IO_B1_G1
IO_B1_G2
IO_B1_G3
IO_B1_H1
IO_B1_H4
IO_B1_H7
IO_B1_H8
IO_B1_J3
IO_B1_J4
IO_B1_J5
IO_B1_J6
IO_B1_J8
IO_B1_J9
IO_B1_K1
IO_B1_K2
IO_B1_K3
IO_B1_K4
IO_B1_K5
IO_B1_K6
IO_B1_K7
IO_B1_K8
IO_B1_K10
H8
J3
J4
J5
J6
J8
J9
K1
K2
K3
K4
K5
K6
K7
K8
K10
FX2_PB1
FX2_PB3
FX2_SCL
FX2_PD6
FX2_PD4
JTAG_FPGA_TDO
FX2_SLWRn
FX2_SLRDn
FX2_PD7
FX2_PD5
FX2_PA5
C_JTAG_TDO
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TCK
JTAG_FPGA_TDO_RETIMER
8
USB_FULL
USB_EMPTY
USB_SCL
USB_SDA
USB_CLK
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
8
8
7
13
8,19
13
8
7
7
M570_PCIE_JTAG_EN
15,22
FX2_RESETn
R146
8
JTAG_FPGA_TDO
0
12
MAX V USB INTERFACE
USB_CFG[11:0]
19
EXTRA_SIG[2:0]
MAX II
BANK 2
A1
JTAG_TX
A2
JTAG_RX
FACTORY_REQUEST A3
A4
USB_CFG5
A5
USB_RESETn
A6
USB_OEn
A7
USB_RDn
A8
USB_WRn
FACTORY_STATUS A9
A10
SC_RX
B2
SC_TX
B3
USB_CFG4
B4
EXTRA_SIG1
B5
USB_CFG6
B6
USB_DATA0
B7
USB_DATA1
B8
USB_DATA2
B9
USB_DATA3
B10
USB_DATA4
IO_B2_A1
IO_B2_A2
IO_B2_A3
IO_B2_A4
IO_B2_A5
IO_B2_A6
IO_B2_A7
IO_B2_A8
IO_B2_A9
IO_B2_A10
IO_B2_B2
IO_B2_B3
IO_B2_B4
IO_B2_B5
IO_B2_B6
IO_B2_B7
IO_B2_B8
IO_B2_B9
IO_B2_B10
IO_B2_C3
IO_B2_C4
IO_B2_C7
IO_B2_C8
IO_B2_C9
IO_B2_C10
IO_B2_D8
IO_B2_D9
IO_B2_D10
IO_B2_E8
IO_B2_E9
IO_B2_F9
IO_B2_F10
IO_B2_G8
IO_B2_G9
IO_B2_G10
IO_B2_H9
IO_B2_H10
IO_B2_J10
C3
C4
C7
C8
C9
C10
D8
D9
D10
E8
E9
F9
F10
G8
G9
G10
H9
H10
J10
USB_CFG3
EXTRA_SIG0
USB_DATA7
USB_DATA5
USB_DATA6
USB_ADDR1
USB_CFG8
USB_ADDR0
USB_FULL
USB_EMPTY
USB_CFG11
USB_SCL
USB_SDA
EXTRA_SIG2
USB_CFG10
USB_CFG0
USB_CFG1
USB_CFG2
USB_CFG9
D
19
M570_CLOCK
FACTORY_STATUS
FACTORY_REQUEST
19
19
19
JTAG INTERFACE
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
12,15,19,22
12,15
15
12,15
USB_DISABLEn
V1
V2
V3
EPM570GF100
15
C_JTAG_TDI
C_JTAG_TMS
C_JTAG_TDO
C_JTAG_TCK
R147
R148
R149
R150
0
0
0
0
JTAG_BLASTER_TDI
JTAG_TMS
JTAG_BLASTER_TDO
JTAG_TCK
FX2_SDA
R151
0
MAX_SDA
C
2.5V
U21D
MAX II
CONFIGURATION
MAX_SDA
FX2_PD2
FX2_PD0
FX2_PD1
FX2_PD3
USB Microcontroller, CY7C68013A
R156
R158
R159
R160
C_USB_MAX_TDI
C_USB_MAX_TCK
C_USB_MAX_TMS
C_USB_MAX_TDO
0
0
0
0
J7
H2
H3
J1
J2
IO1/DEV_OE
IO1/DEV_CLRn
TDI
TCK
TMS
TDO
IO1/GCLK0p
IO1/GCLK1p
IO2/GCLK2p
IO2/GCLK3p
K9
FX2_RESETn
E2
E1
F8
E10
USB_CLK
FX2_PB7
USB_CFG7
M570_CLOCK
R152
R153
R154
R155
1k
1k
1k
1k
USB_SCL
USB_SDA
USB_FULL
USB_EMPTY
R157
1k
FACTORY_REQUEST
DNI
R161
JTAG_BLASTER_TDI
EPM570GF100
B
B
U21A
MAX II
POWER
PLACE NEAR CY7C68013A
C5
E6
F5
H5
3.3V
PLACE NEAR MAX II EPM570
C218
C219
C220
C221
C222
C223
C224
C225
2.5V
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
J15
R164
1k
R165
1k
C_USB_MAX_TCK 1
C_USB_MAX_TDO 3
C_USB_MAX_TMS 5
7
C_USB_MAX_TDI 9
R162
R163
Green_LED D7
56.2
JTAG_TX
R166
Green_LED D8
56.2
SC_RX
3.3V
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
1.8V
Green_LED D6
56.2
0.1uF
3.3V
A
E
19
JTAG_FPGA_TDO_RETIMER
U21C
B2
H3
F4
H4
G4
H5
G5
F5
H6
1
USB_DATA[7:0]
EPM570GF100
FX2_WAKEUP
H7
G7
H8
2
Arria V USB Interface
0.1uF
3.3V
1
2
3
4
6
3
U21B
E
J14
USB Type B
4
USB Blaster II
3.3V
R141
4.7nF
5
2.5V
D5
D7
E5
F6
G5
G7
3.3V
JTAG_RX
C226
C227
C228
C229
C230
C231
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
C6
E7
F4
H6
3.3V
E4
G4
G6
2.5V
D4
D6
F7
EPM570GF100
R167
Green_LED D9
56.2
A
Title
SC_TX
Size
B
Date:
7
VCCINT
VCCINT
VCCINT
VCCINT
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
DNI
8
1.8V
GNDINT
GNDINT
GNDINT
GNDINT
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
24
of
1
35
8
7
6
5
4
3
2
1
User IO & Connector
Push Button Switches
2.5V
E
D10
MAX_ERROR
D11
MAX_LOAD
D12
MAX_CONF_DONEn
RED_LED
RES_MAX_ERROR
Green_LED
RES_MAX_LOAD
R168
R171
100
1
1
56.2
R173
2.5V
R169
PGM_CONFIG
2
R170
PGM_SEL
B2
S3
LED INTERFACE
MAX_RESETn
R172
10K
HSMA_RX_LED
Green_LED
RESn_HSMA_RX_LED R175
56.2
1
2
HSMA_TX_LED
D14 Green_LED
RESn_HSMA_TX_LED R178
56.2
1
2
S4
2
CPU_RESETn
R174
10K
S5
3
4
USER_PB0
R176
10K
S6
3
4
USER_PB1
R177
10K
9
MAX_ERROR
MAX_LOAD
MAX_CONF_DONEn
10K
2
E
USER_LED[3:0]
2X7 LCD SOCKET STRIP, THM
5.0V
19
19
19
HSMA_RX_LED
HSMA_TX_LED
9
9
HSMA_PRSNTn
9,19,22
PCIE_LED_X1
PCIE_LED_X4
PCIE_LED_X8
PCIE_LED_G2
13
9
9
13
J16
LCD_WEn
LCD_DATA0
LCD_DATA2
LCD_DATA4
LCD_DATA6
1
3
5
7
9
11
13
1
3
5
7
9
11
13
2
4
6
8
10
12
14
2
4
6
8
10
12
14
LCD_D_Cn
LCD_CSn
LCD_DATA1
LCD_DATA3
LCD_DATA5
LCD_DATA7
PGM_LED[2:0]
19
HDR 2X7, VT, THM, TSW-107-07
D
3.3V
HSMA_PRSNTn R180
56.2
D15 Green_LED
1
2
S7
3
4
R179
USER_PB2
2.5V
R181
56.2
R185
56.2
D17 Yellow_LED
PCIE_LED_X4
D18 Yellow_LED
R187
PCIE_LED_X8
D19 Yellow_LED
R188
PCIE_LED_G2
SW3
1
2
3
4
OPEN
D16 Yellow_LED
PCIE_LED_X1
DIP SWITCH INTERFACE
R412
DNI
Design Note:
For debug connection to
LTC DC1613 USB to
I2C/SMBus/PMBus
Controller
USER_DIPSW[3:0]
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
R182
R183
R184
R186
10K
10K
10K
10K
LTC3880_SDA_2.5V
LTC3880_SCL_2.5V
PUSH BUTTON INTERFACE
19,27
USER_PB[2:0]
19,27
ON = 0
OFF = 1
Design Note:
PCIe GEN2 link indication
14,19
19
19
19
PMBus Interface
USER DIPSWITCH
56.2
9
CLK_SEL
CLK_ENABLE
FACTORY_LOAD
SECURITY_MODE
2.5V
8
7
6
5
Switch, DIP x4, TDA04H0SB1
56.2
D
10K
R411
DNI
C
B1
10K
2 x 7 Display Connector
56.2
1
D13
S2
2
2X16 LCD
1
Green_LED
RES_CONF_DONEn
S1
9
CPU_RESETn
MAX_RESETn
12,19
19
PGM_SEL
PGM_CONFIG
19
19
C
2.5V
RESn_LED0
D21 Green_LED
USER_LED1
RESn_LED1
R193
56.2
SW4
1
2
3
4
56.2
2x16 LCD DISPLAY INTERFACE
2.5V
8
7
6
5
CLK_SEL
CLK_ENABLE
FACTORY_LOAD
SECURITY_MODE
R190
R191
R192
R194
10K
10K
10K
10K
LCD_DATA[7:0]
RESn_LED2
R195
56.2
RESn_LED3
R196
56.2
10
LCD_CSn
LCD_D_Cn
LCD_WEn
Switch, DIP x4, TDA04H0SB1
D22 Green_LED
USER_LED2
R189
OPEN
D20 Green_LED
USER_LED0
10
10
10
BOARD SETTINGS DIPSWITCH
B
D23 Green_LED
USER_LED3
B
2.5V
PGM_LED0
D24 Green_LED
RESn_PGM_LED0
R197
56.2
PGM_LED1
D25 Green_LED
RESn_PGM_LED1
R198
56.2
PGM_LED2
D26 Green_LED
RESn_PGM_LED2
R199
56.2
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Wednesday, October 17, 2012
2
Sheet
C1.1
25
of
1
35
7
6
12V
CONN JACK PWR
2
1
3
1
2
3
Q1
FDMC8878
14V - 20V
DC Input
0.1UF
50V
0.1UF
50V
3
2
LTC4357_DUAL_DIODE
Cad Note:
Use copper pour
LTC3855_INTVCC
C234
3.3V_SHDNn
LTC3855_INTVCC R202
U28
5
GATE
IN
NC
OUT
VDD
GND
EP_GND
DNI
LTC3855_ILIM1
LTC3855_ITH1
LTC3855_SS1
CAD Note:
Overlap resistor pad R206
on 1 of the pins
DNI
1
6
4
7
12V_SHDNn
LTC3855_ILIM2
LTC3855_ITH2
LTC3855_SS2
LTC4357
R208
3.3V
CAD Note:
Overlap resistor pad
on 1 of the pins
C
3.3V_MUXVCCP
VIN
INTVCC
EXTVCC
TG1
BOOST1
12
11
8
1 2 3
3
4
LTC4352CDD
2
VCC
SOURCE
GATE
OUT
C240
C241
1000pF
1000pF
R213
DNI
REV
EP
GND
7
13
9
4
41
28
22
18
10pF
C245
C246
C247
0.1UF
39pF
33pF
RUN2
ITEMP2
ILIM2
ITH2
TK/SS2
SENSE1+
SENSE1PGOOD1
29
Cad Note:
Place output caps
near inductor
L6
CH1
31
LTC3855_BOOST1
0.1UF
LTC3855_SW1
27
LTC3855_BG1
3
LTC3855_VFB1
39
40
LTC3855_S1P
LTC3855_S1N
7
6
5
C236
CH2
1
2
1
SNS RSNS
SENSE_PAD
R203
R204
1.62K
C239
0.1uF
16 PGOOD_3.3V
3.32K
V4
1%
SENSE_PAD
1%
R207 11.5K
SGND1
SGND2
PGND1
PGND2
NC
10pF
TG2
BOOST2
SW2
BG2
VFB2
R216
174K
DIFFOUT 12
10
11
124K
1%
3.3V_MUX
SENSE2+
SENSE2-
DIFFOUT
DIFFP
DIFFN
PGOOD2
20
21
RJK0305DPB
4
LTC3855_TG2
C243
LTC3855_BOOST2
0.1UF
19 LTC3855_SW2
drain-tab
C232
C233
47uF
35V
47uF
35V
C440
22uF
25V
1210
5
LTC3855_VFB2
1
Q15
8
9
LTC3855_S2P
LTC3855_S2N
2
SNS RSNS
1
SENSE_PAD
R217 4.64K 1%
R219
C252
0.1uF
17 PGOOD_12V
V7
SENSE_PAD
3.24K
C
Cad Note:
Place output caps
near inductor
2
2.2uH
Isat = 13A
V6
4
RJK0301DPB
R209
2.55K
1%
Cad Note:
Place cap across
MOSFET drain
and source pins
L7
drain-tab
23 LTC3855_BG2
DIFFOUT
1%
D29
Q5
D
C238
330uF
6.3V
C237
100UF
6.3V
DC_IN
CMDSH-3
3.3V_MUX
3.3uH
Isat = 13.5A
V5
4
3
2
2
SI4816BDY
FREQ
MODE/PLLIN
PHSASMD
CLKOUT
1%
C251
R214
215.0K
1%
12V_MUX
C248
C249
C250
100UF
25V
100UF
25V
220uF
16V
R218
11.3K
1%
1%
B
FDMC8878
8 7 6 5
Q7
FDMC8878
3.3V_MUX
R224
DNI
VIN
100K
PGOOD_3.3V R221
LTC4352CDD
GND
EP
REV
9
13
7
R222
1k
CPO
3
4
3.3V_MUX
1
UV
OV
10
OUT
GATE
SOURCE
STATUS
FAULT
U30
8
11
12
5
6
5.0V
4
1 2 3
R220
100K
Cad Note:
Route traces DIFFP/N differentially
from load back to regulator pins 10 & 11
8 7 6 5
A
VFB1
gnd-pad
Q6
B
BG1
C439
22uF
25V
1210
1
169K
5
6
4
RUN1
ITEMP1
ILIM1
ITH1
TK/SS1
R215
CPO
STATUS
FAULT
10
DNI
VIN
8
LTC3855_TG1
C235
22uF
25V
1210
LTC3855_INTVCC
C244
UV
OV
U29
13
36
15
6
7
LTC3855_FREQ 35
34
33
32
R210
1%
1
38
37
14
2
1
SW1
30
DNI
3.3V_PCIE
R211
Q4
CMDSH-3
LTC3855EUH-1
26
25
24
4.7UF
3
2
C242
22uF
25V
1210
D28
U27
MMBD1205
4
Cad Note:
Place cap across MOSFET
drain and source pins
DC_IN
LTC3855_INTVCC
2
12V_MUX
8
7
6
5
C1115
RSNS SNS
D
1
2
3
1
Design Note:
Reverse input
protection
C1114
1
LTC4357
Q3
FDMC8878
NC
LTC4357
D27
Cad Note:
Place caps near regulator
2
5
1
6
4
7
1
NC
DC_IN
OUT
VDD
GND
EP_GND
RSNS SNS
1
6
4
7
OUT
VDD
GND
EP_GND
GATE
IN
5
5
E
4
3
2
U26
GATE
IN
1
8
7
6
5
U25
4
3
2
2
1
2
3
8
7
6
5
3
5
Q2
FDMC8878
1
2
3
12V_PCIE
4
Power 1 - DC Input & 12V, 3.3V Output
DC_INPUT
J17
E
5
1
2
3
8
VCC
DC_IN
100K
POWER LED
2
12V_SHDNn
D30
C253
R226
20K
BLUE LED
0.1UF
Cad Note:
Place Q15 near Q5
SW5
R223
DC_IN
7
1
8
9
2
3
10
4
11
12
5
6
100K
R225
3.3V_SHDNn
R227
20K
Title
SW SLIDE-4P2T
3.3V_MUXVCC
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
26
of
1
35
5
4
3
2
1
Power 2 - 1.1V & 2.5V FPGA
10
5.0V_LTC3880
C443
25V 100UF
0.1uF
0.01uF
10K LTC3880_2.5V_RUN 15
C460
R322
1%
0.01uF
1%
11.5K
C459
C461
82pF
C462
19.1K
560pF
27pF
C464
VDD33_LTC3880
Design Note:
CAD Note:
R327
4.99K LTC3880_SYNC
External termperature Place PNP BJT near
R328
sensing diodes
10K LTC3880_SDA
inductor of individual
R329
10K LTC3880_SCL
pwr rail respectively
R330
10K LTC3880_ALERT_N
R331
10K LTC3880_SHARE_CLK
VDD25_LTC3880
1%
24.9K
R332
4.32K
R333
VDD25_LTC3880 1%
1%
R334
20K
LTC3880_VOUT0_CFG
R335
15K
LTC3880_VOUT1_CFG
VDD25_LTC3880
1%
DNI
R337 1%
LTC3880_VTRIM0_CFG
R338
DNI
LTC3880_VTRIM1_CFG
VDD25_LTC3880
1%
1%
DNI
R339
R341
DNI
VDD25_LTC3880
1%
R343 1% 24.9K
LTC3880_FREQ_CFG
4.32K
R344
VDD25_LTC3880
1%
R345
10.0K LTC3880_ASEL
1%
R346
23.2K
TSNS0
TSNS1
5
ITH0
26
36
RJK0301DPB
4
LTC3880_BG0
VSENSE0+
VSENSE0GPIO0
GPIO1
6
7
TG1
BOOST1
SW1
BG1
1%
R424
LTC3880_IS0P
LTC3880_IS0N
806
18
19
VOUT0_CFG
VOUT1_CFG
20
21
ISENSE1+
ISENSE1-
VTRIM0_CFG
VTRIM1_CFG
1
2
VDD33_LTC3880
30
31
LTC3880_TG1
LTC3880_BOOST1
C466
0.1UF
29
Q13
drain-tab
RJK0305DPB
4
LTC3880_BG1
806
C463
C445
100UF
25V
4
3
4
CAD Note:
Regulator input caps
Place across MOSFET
drain tab & source pins
LTC3880_SW1
Q14
RJK0301DPB
ASEL
PGND
GND_PAD
C474
A4
A3
A2
A1
B4
VCC
IO_VCC1
IO_VCC2
IO_VCC3
IO_VCC4
GND
VL
IO_VL1
IO_VL2
IO_VL3
IO_VL4
EN
B2
330uF
1.1V_VCCP
4A, 33 Ohm FB
Design Note:
L15 DCR = 8m ohms
SENSE_PAD
C456
10UF
C
Isat = 18A
V28
SNS RSNS
1
2.0K LTC3880_R_IS1P
DNI
R342
C470
2.0K
C467
100UF
6.3V
V29
C468
100UF
6.3V
C1211
100UF
6.3V
SENSE_PAD
MAX V Interface
LTC3880_2.5V_RUN
31
LTC3880_R_IS1N
B
LTC3880_1.1V_RUN
1uF
31
LTC3880
CAD Note:
Route Vsense0 & Vsense1
pseudo-differentially and tap
output voltage near FPGA
for remote sensing
2.5V_FPGA
2.5V_VCCIO_VCCPD_VCCPGM
R247
0.1uF
U43
B1
330uF
L15
2.5V_FPGA
R340
34
41
C455
1
SENSE_PAD
0.1uF
C454
LTC3880_R_IS0N
C469
27
V27
C453
100UF
6.3V
L18
2
2
R336
LTC3880_IS1P
LTC3880_IS1N
C452
100UF
6.3V
0.001
1uF
1.2uH
drain-tab
32
1%
R323
12V
R325 10K
10K
12 LTC3880_GPIO0_N
13 LTC3880_GPIO1_N
DNI
0.1uF
FREQ_CFG
16
1
R321
2.5V_FPGA
VSENSE1
17
SNS RSNS
SENSE_PAD
LTC3880_R_IS0P
C458
R326
SYNC
SDA
SCL
ALERT
SHARE_CLK
WP
V26
2
1.1V_VCC
ITH1
8
10
9
11
24
23
0.22uH
Isat = 40A
Q10
1.1V_VCC
R228
1
2.5V
C473
LTC3880_SCL
LTC3880_SDA
LTC3880_ALERT_N
LTC3880_GPIO0_N
ISENSE0+
ISENSE0-
2
drain-tab
CAD Note:
PGND and GND_PAD
should be connected
at 1 point only
3.3V
A
RUN1
1%
Design Note:
To increase the Vout to 1.15V,
stuff R337 with 20K 1% and
stuff R338 with 17.8K 1% parts
0.1uF
BG0
LTC3880_SW0
0.1UF
39
1.1V
L16
C447
LTC3880_BOOST0
RUN0
40
28
560pF
SW0
37
2
10K LTC3880_1.1V_RUN 14
R319
1.1V_TSNS0
2.5V_TSNS1
R324
B
R318
BOOST0
LTC3880_TG0
1
2
3
0.1uF
2
Q12
MMBT3906
1
3
C
Q11
MMBT3906
1
3
C457
2
4.7uF
VDD33
38
1
2
3
1.0UF
TG0
INTVCC
VDD33_LTC3880
C449
4
VDD25
RSNS SNS
33
C448
CAD Note:
Place VCC on power plane furthest away from FPGA in stakcup
Place VCCP on power plane closest to FPGA in stackup
RJK0305DPB
1
5.0V_LTC3880
C450
C1111
100UF
6.3V
2
25
D
1
2
3
22
VDD33_LTC3880
1.0UF
drain-tab
VIN
VDD25_LTC3880
C446
CMDSH-3 CMDSH-3
Q9
CAD Note:
Regulator input caps
Place across MOSFET
drain tab & source pins
RSNS SNS
35
D35
5
D34
U42
5
25V
5
CAD Note:
Place C1092 & C1102 across
regulator controller pin 33 & 34
C442
22uF
25V
1210
C1108
C465
0.1uF
1
2
3
0603
1/10W
CAD Note:
Place near regulator
controller pins
Design Note:
2.1A Irms/100uF
1
R421
D
12V
5
12V
Design Note:
Place 2.2 - 10 ohms
for channel isolation
R408
R409
R410
L13
10K
10K
10K
0.003
VCCAUX_VCCA_FPLL
2.5V_FPGA_FILTER
R248
0.003
VCCA_GXB
4A, 33 Ohm FB
C4
C3
C2
C1
LTC3880_SCL_2.5V
LTC3880_SDA_2.5V
LTC3880_ALERT_N_2.5V
LTC3880_GPIO0_N_2.5V
B3
PMBUS_LVL_SHIFTER_EN
Level Shifter, MAX13042
R249
19,25
19,25
19
19
0.003
A
Design Note:
To system controller
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
5
4
3
2
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
C1.1
150-0320806-A1 (6XX-44099R)
Friday, September 21, 2012
Sheet
1
27
of
34
8
7
6
5
4
3
2
1
Power 3 - 1.15V & 1.5V FPGA
E
E
Cad Note:
Place near INTVCC pin
VCCT_GXB
VCCL_VCCR_GXB
1.15V
L9
R229
2.2uF
C254
Design Note:
Soft-start, tss = 430000 ohm x Css
Css = 2.2nF, ramp rate ~ 1ms
0.001
3A, 30 Ohm FB
Design Note:
0.001 ohm sense resistor
minimized IR drop @ 3A
3.3V
Design Note:
DCR = 40m ohms
3.3V
C255
C256
R231
R230
2
LTC3633_BOOST1
25V
C258
0.1uF
LTC3633_SW1
1.15V
L10
1.2uH
PGOOD_1.5V
8
15
16
VON1
VON2
RUN_1.5V
18
LTC3633_V2P5
17
25V
LTC3633_BOOST2
C259
0.1uF LTC3633_SW2
14
13
DNI
LTC3633_FB1
28
LTC3633_ITH1
26
FB1
ITH1
RT
MODE/SYNC
25
R241
C268
357K
1%
8200pF
12V
4
6.81K
1%
47pF
C272
22uF
25V
1210
1.5V
C
1.5V_VCCIO
L11
R234
0.003
1.2uH
FB2
ITH2
9
LTC3633_FB2
11
LTC3633_ITH2
C263
R236
C264
C265
22pF
15K
1%
22uF
22uF
U31
LTC3633UFD
Cad Note:
Place output caps
near inductor
R238
R240
9.76K
LTC3633_INTVCC
C266
B
C257
12
R239
CAD Note:
Regulator input caps
Place near regulator controller
30,31
0.1uF
Isat = 11A
C260
15K
1%
16.5K
1%
C271
22uF
25V
1210
PVIN2
PVIN2
LTC3633_SS2
10
SW2B
SW2A
6
Isat = 11A
R235
R237
C270
22uF
25V
1210
INTVcc
LTC3633_SS1
LTC3633_INTVCC
21
22
PVIN1
PVIN1
SW1A
SW1B
PGND
22uF
BOOST2
29
C262
22uF
BOOST1
GND
C261
23
24
RUN2
V2P5
7
Cad Note:
Place output caps
near inductor
20
12V
PHMODE
5
C
RUN1
D
100K
PGOOD2
3
LTC3633_INTVCC
TRACK/SS2
RUN_1.15V_XVCR
31
PGOOD1
1
12V
19
100K
PGOOD_1.15V_XCVR
31
TRACK/SS1
D
2200pF
27
2200pF
10.0K
1%
1%
C267
B
47pF
C269
2200pF
C273
22uF
25V
1210
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
28
of
1
35
8
7
6
5
4
3
2
1
Power 3 - 2.5V Main
E
E
D32
3.3V
LTC3605_INTVCC
Design Note:
Added extra 1uF at INTVCC due to
sourcing Vbias pin of LTC3025-1
C281
1.0UF
C282
2.2uF
CMDSH-3
LTC3605_BOOST
12V
R246
19
20
21
22
23
24
LTC3605_SVIN
C436
R290
DNI
6
SVIN
BOOST
INTVCC
SW
1%
DNI
LTC3605_SVIN
3.3V
B
SGND
ITH
R255
18
17
16
D
CAD Note:
Regulator input caps
Place near regulator controller
Design Note:
Prefer 0603 size cap
25V rated voltage is sufficient
LTC3605_SW
2.5V @ 2.9A
2.5V
L14
15
1.2uH
Isat = 11A
14
13
PGND
DNI
LTC3605_ITH
C286
0.1UF
50V
C285
22uF
25V
1210
C289
R251
39pF
47.5K
1%
C287
C288
C290
C291
22uF
22uF
22uF
22uF
Cad Note:
Place output caps
near inductor
C
LTC3605_FB
U33
LTC3605EUF
R252
PGOOD_2.5V
C437
0
RUN
CAD Note:
Overlap R289 & R290
pads at 1 of the pins
Place resistor & cap
near pin 6
LTC3605_INTVCC R289
SW
EXPOSED PAD
7
Design Note:
Ith is tied to INTVCC for
internal compensation
TRACK/SS
25
C
SW
5
12
LTC3605_SS
3300pF
SW
SW
C292
FB
11
4
SW
PGND
LTC3605_FB
MODE
10
Design Note:
tss = Css x 0.6V/2uA
Ramp rate ~990us
PVIN
VON
3
PHMODE
9
1%
PVIN
PGOOD
2
RT
8
R250
178K
CLKOUT
CLKIN
1
C284
22uF
25V
1210
C283
0.1uF
25V
D
LTC3605_RT
10
15K
1%
B
100K
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
29
of
1
35
8
7
6
5
4
3
2
1
Power 4 - Linear Regulators
VCCD_FPLL & VCCBAT
E
Power Monitor VIN
6
C295
BIAS
OUT
IN
ADJ
SHDN
1.0UF
GND
EP_GND
4
5
R256
1.5V_FPGA_ADJ
R260
1.15K
1%
LTC3025-1
28,31
R258
VCCD_FPLL_VCCBAT
C294
2.2uF
25V
0.003
5
C296
C297
2.2uF
1.0UF
5.37V_MONITOR
2
3
OUTPUT
OUTPUT
SHDN
1
ADJ/NC
1%
2
7
Design Note:
Vout = 0.4V (1 + R2/R1)
R2 connects to Vout
R1 connects to GND
R1 < 50k Ohm
Source: LTC3025-1 datasheet
RUN_1.5V
3.16K
R257
IN
GND
3
4
GND
1
2.5V_FPGA
0.003
5.37V_MONITOR_ADJ
R259
90.9K
1%
TAB
U34
D
VCCH_GXB
1.5V_FPGA
0.1uF
5.37V @ 0.3mA
U35
LT3009xDC
12V
1.5V @ 242mA
C298
2.2UF
R261
11.5K
CAD Note:
Place caps & res
near regulator
7
C293
VCCH_GXB,
VDD33_LTC3880
Design Note:
Connect BIAS pin to VDD33_LTC3880
to minimize 1.5V_FPGA from rising
before 2.5V_FPGA is stable
VDD33_LTC3880 = 3.3V
6
E
1%
D
Design Note:
Vout = 600mV x (1 + R2/R1) - (Iadj x R2)
R2 connects to Vout
R1 connect to GND
Vadj = 600mV
Iadj = 0.3nA @ 25C
Source: LT3009 datasheet
CAD Note:
Place resistors near ADJ pin
VTT LDO, LCD Character, SPI Level Shifter
4
1.8V @ 200mA
C300
2.2uF
25V
U37
C
6
C304
OUT
IN
SHDN
1.0UF
ADJ
GND
EP_GND
5
2
7
LTC3025-1
1.8V_ADJ
R263
5
1%
R264
1.15K
1%
SHDN
C302
C303
2.2uF
1.0UF
1
ADJ/NC
4.02K
GND
3
BIAS
4
6
1
5.0V
2
3
OUTPUT
OUTPUT
R262
5.0V_ADJ
110K
1%
TAB
1.8V
0.1uF
2.5V
IN
GND
C299
5V @ 8.8mA
U36
LT3009xDC
12V
C301
2.2UF
R265
15K
1%
CAD Note:
Place caps & res
near regulator
7
Flash VCC/VPP & MAXV/MAXII VCCINT
5.0V
C
CAD Note:
Place resistors near ADJ pin
DDR3 VTT
1.5V
5.0V
U38
10
Ethernet PHY DVDD/VDDO
5.0V
B
TPS51100DGQ
VIN
VLDOIN
VDDQSNS
C305
2
1
10uF
1.0V @ 250mA
R266
R267
ENET_DVDD
U39
3
C311
1.0UF
6
BIAS
OUT
IN
SHDN
ADJ
GND
EP_GND
LTC3025-1
4
5
2
7
S3
S5
VREF_DDR3
6
15K
ENET_DVDD_ADJ R268
VTTREF
1%
R269
10.0K
1%
VTT
VTTSNS
4
8
11
1
2.5V
TPS51100_S3 7
TPS51100_S5 9
C309
C310
2.2uF
1.0UF
B
C312
1.0UF
3
5
PGND
GND
GND
C306
0.1uF
0.75V VTT (3A Sink/Src)
0.75V_VTT
10K
10K
C307
C308
10uF
10uF
CAD Note:
Place caps & res near regulator
Place U38 at the same side as
DDR3 addr/ctrl/cmd termination
resistor packs and capacitor arrays
Pour copper on outer layer to cover
these components
CAD Note:
Place resistors near ADJ pin
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
30
of
1
35
8
7
6
5
4
3
2
1
Power 5 - Power Monitor
5.37V_MONITOR
5.0V
SENSE_PAD
V12
1
RSNS SNS
1.5V_VCCIO
D
1.5V
2.5V_FPGA
1
SENSE_PAD
V18
1
RSNS SNS
2.5V_FPGA_FILTER
1
VCCD_FPLL_VCCBAT
1.5V_FPGA
1
B
A5_VCCA_GXB_P
A5_VCCA_GXB_N
3
4
A5_VCCIO_1.5V_N
A5_VCCH_GXB_P
A5_VCCH_GXB_N
5
6
A5_VCCIO_VCCPD_VCCPGM_P
12
LTC2418_REFR275
DNI
19
R276
17
20
18
16
5.0V
NC1
NC2
COM
GND
13
14
Fan Header
0.1uF
15
SENSE5_CS0n
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
R277
10K
2
A5_VCCA_GXB_P
3.3V
A5_VCCA_GXB_N
R381
R382
C1020
V23 SENSE_PAD
2
RSNS SNS
LTC2915_VM_0P5V
Design Note:
R2 = R1 (2*Vnom - 1) where
R2 is resistor connected to GND
R1 is resistor connected to power
rail being monitored
Vnom is nominal voltage of power
rail being monitored
C1105
CAD Note:
Overlap pads between
cap and resistor
14
13
12
11
10
9
8
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
1
2
3
4
5
6
7
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
0.1uF
SENSE_CS0n
SENSE_SDO
SENSE_SDI
SENSE_SCK
19
19
19
19
To/from system controller
VCC
RST
8
1.1V & 1.15 Switching Regulator Interface
Design Note:
1.1V power good generation
PGOOD_1.1V_VCC R399
LTC3880_1.1V_RUN
PGOOD_1.15V_XCVR
VM
TOL/MR
RT
SEL1
SEL2
GND
EPAD
1
9
R400
0
PGOOD_1.15V_XCVR
R406
DNI
LTC3880_1.1V_RUN
R401
DNI
PGOOD_1.1V_VCC
R407
0
LTC2915
1.1V Voltage Supervisor
C1106
0.1uF
C1107
U45
DNI
OVERTEMP_FPGA
R279
4.7k
OVERTEMP
5
LTC2915_TOL_2.5V
LTC2915_RT_2.5V
DNI
3.3V
TSENSE_FAN_CNTL
R278
9
Design Note:
2.5V power good generation
3.3V
4
DNI
DNI
28
LTC3880_2.5V_RUN
27
RUN_1.15V_XVCR
28
Design Note:
DNI for ES device
3.3V
R415
R416
C
27
3.3V
10K
A5_VCCD_FPLL_VCCBAT_N
Design Note:
Set TOL threshold outside
power supply tolerance band
OVERTEMP_R
4
0
LTC2915_TOL_1.1V 2
DNI LTC2915_RT_1.1V 7
3
DNI
6
R396
R386
A5_VCCD_FPLL_VCCBAT_P
5
3.3V
A5_VCCH_GXB_P
A5_VCCH_GXB_N
U44
12.4K
15K
0.1uF
2
C1209
U41
Design Note:
Set TOL threshold outside
power supply tolerance band
1.1V_VCC
3.3V
2
D
Level Shifter, MAX3378
A5_VCCAUX_VCCA_FPLL_N
12V
Q8
FDV305N
C1208
2.5V
3.3V
22_23_2021
1.0UF
2.5V
CH14
CH15
2.5V_VCCIO_VCCPD_VCCPGM
1
2
C1210
CH12
CH13
A5_VCCAUX_VCCA_FPLL_P
SENSE_PAD
J18
0
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
SENSE5_CS0n
ADC, LTC2418 16-Ch
2
R274
LTC2418_REF+
R273
11
10K
0
9
CH10
CH11
7
8
A5_VCCD_FPLL_VCCBAT_P
A5_VCCD_FPLL_VCCBAT_N
SDO
SDI
SCK
CSn
CH8
CH9
10
V21 SENSE_PAD
1
2
RSNS SNS
SENSE_PAD
V22
1
RSNS SNS
1
2
A5_VCCIO_1.5V_P
F0
CH6
CH7
A5_VCCIO_VCCPD_VCCPGM_N
V19 SENSE_PAD
2
RSNS SNS
SENSE_PAD
V20
1
RSNS SNS
VCCH_GXB
1.5V_FPGA
2
V17 SENSE_PAD
1
2
RSNS SNS
VCCA_GXB
C
2
V15 SENSE_PAD
2
RSNS SNS
SENSE_PAD
V16
1
RSNS SNS
VCCAUX_VCCA_FPLL
2.5V_FPGA_FILTER
SENSE_PAD
V14
1
RSNS SNS
A5_VCCL_VCCR_VCCT_GXB_P
A5_VCCAUX_VCCA_FPLL_P
A5_VCCAUX_VCCA_FPLL_N
REF-
CH4
CH5
A5_VCCL_VCCR_VCCT_GXB_N
V13 SENSE_PAD
1
2
RSNS SNS
2.5V_VCCIO_VCCPD_VCCPGM
CH2
CH3
A5_VCCIO_VCCPD_VCCPGM_P 27
A5_VCCIO_VCCPD_VCCPGM_N 28
V11 SENSE_PAD
1
2
RSNS SNS
VCC
REF+
25
26
A5_VCCIO_1.5V_P
A5_VCCIO_1.5V_N
2
CH0
CH1
A5_VCCL_VCCR_VCCT_GXB_P 23
A5_VCCL_VCCR_VCCT_GXB_N 24
A5_VCCINT_N
RSNS SNS
SENSE_PAD
V10
1
RSNS SNS
VCCL_VCCR_GXB
1.15V
SENSE_PAD
2
A5_VCCINT_P
R272
V9
1
2
10K
1.1V
RSNS SNS
21
22
A5_VCCINT_P
A5_VCCINT_N
V8
1
10uF
R271
1.1V_VCC
E
R270
10K
U40
C314
10K
C313
0.1uF
E
2
7
3
6
VCC
RST
8
3.3V
PGOOD_2.5V_FPGA R420
10K
VM
TOL/MR
RT
SEL1
SEL2
GND
EPAD
1
9
LTC3880_1.1V_RUN
LTC2915
CAD Note:
Overlap pads between
cap and resistor
R233
0
R232
DNI
RUN_1.5V
28,30
Design Note:
DNI for ES device
Cad Note:
Overlap pad on 1 pin
2.5V Voltage Supervisor
19
B
Cad Note:
Overlap pad on 1 pin
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
31
of
1
35
5
4
3
2
1
Power 6 - Arria V GX Power
D
D
2.5V_VCCIO_VCCPD_VCCPGM
U1I
U1K
U1J
Arria V GX IO Bank Power
VCCAUX_VCCA_FPLL
Arria V GX Core Power
2.5V_VCCIO_VCCPD_VCCPGM
Arria V GX Transceiver Power
1.1V_VCCP
P18
R13
R21
T10
U25
V10
W25
Y12
Y19
Y22
R14
R15
R19
R23
R25
T12
T14
T16
T18
T20
T22
T24
U11
U12
U13
U15
U17
U19
U20
U21
U22
U23
V12
V14
V16
V20
V22
V24
W13
W15
W17
W19
W21
W23
Y13
Y20
V18
1.1V_VCC
C
B
M9
AC26
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Auxiliary Pwr
2.5V
VCC Periphery
Pwr 1.1V
PLL Analog
Pwr 2.5V
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
AD30
AF27
AH30
AJ27
AK30
AM27
AE27
P12
P24
W11
Y24
Y18
R17
V26
V9
T26
T9
VREF_2.5V_VCCIO
VCCD_FPLL_VCCBAT
PLL Digital
Pwr 1.5V
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
Y17
R16
Y26
Y9
P26
P9
2.5V_VCCIO_VCCPD_VCCPGM
VCC Core Pwr
1.1V
I/O Pre-driver Pwr
2.5/3.0/3.3V
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD4A
VCCPD4A
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD7A
VCCPD7A
VCCPD7BCD
VCCPD7BCD
VCCPD7BCD
VCCPD8
VCCPD8
VCCPD8
VCCPD8
AB26
AC27
Y21
Y25
AF24
AJ24
AM24
AP24
Y23
AF21
AJ21
AM21
AP21
AC20
AF18
AJ18
AM18
AP18
AB18
AD5
AF5
AH5
AK5
AK6
AB6
AB9
Y10
Y14
Y16
AF9
AJ9
AM9
AP9
AE8
N8
N9
P14
P16
R11
AF12
AJ12
AM12
AP12
AK11
N26
N27
P20
P22
AF15
AJ15
AM15
AP15
AJ14
VCCPGM Configuration Pin Pwr
VCCPGM 1.8/2.5/3.0/3.3V
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VREFB3AN0
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VREFB7AN0
VCCIO7B
VCCIO7B
VCCIO7B
VCCIO7B
VREFB7BN0
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VREFB3BN0
VCCIO7C
VCCIO7C
VCCIO7C
VCCIO7C
VREFB7CN0
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VREFB3CN0
VCCIO7D
VCCIO7D
VCCIO7D
VCCIO7D
VREFB7DN0
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VREFB3DN0
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VREFB4AN0
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VREFB8AN0
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VREFB4BN0
VCCIO8B
VCCIO8B
VCCIO8B
VCCIO8B
VREFB8BN0
VCCIO4C
VCCIO4C
VCCIO4C
VCCIO4C
VREFB4CN0
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VREFB8CN0
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VREFB4DN0
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VREFB8DN0
C5
F2
F5
L7
M7
A9
C9
F9
J9
P11
Analog Pwr
TX/RX High Pwr
2.5V
VCCA_GXB
Y28
T28
Y7
T7
VREF_2.5V_VCCIO
A15
C15
F15
J15
N14
C27
C30
F27
F30
J29
M26
M27
V28
P28
V7
P7
VCCT_GXB
W29
Y30
R29
T30
W6
Y5
R6
T5
A24
C24
F24
J24
N24
VCCH_GXBL0
VCCH_GXBL1
VCCH_GXBR0
VCCH_GXBR1
1.5V
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
AA29
AA30
N30
U29
U30
AA5
AA6
N5
U5
U6
C
Version 2.0 Pin Out
5AGXFB3H4F35
A21
C21
F21
J21
N20
B
2.5V_VCCIO_VCCPD_VCCPGM
A18
C18
F18
J18
N18
R280
VREF_2.5V_VCCIO
10.0K
1%
R281
Version 2.0 Pin Out
10.0K
1%
5AGXFB3H4F35
VCCBAT Battery Backup Pwr
1.2V - 3.0V
VCCL_VCCR_GXB
V29
V30
P29
P30
V5
V6
P5
P6
Analog Pwr
RX Pwr
1.1V
VCCT_GXBL0
VCCT_GXBL0
VCCT_GXBL1
VCCT_GXBL1
VCCT_GXBR0
VCCT_GXBR0
VCCT_GXBR1
VCCT_GXBR1
VCCD_FPLL_VCCBAT
M28
VCCL_GXBL0
VCCL_GXBL0
VCCL_GXBL1
VCCL_GXBL1
VCCL_GXBR0
VCCL_GXBR0
VCCL_GXBR1
VCCL_GXBR1
Analog Pwr
TX Pwr
1.1V
1.5V_VCCIO
VREF_DDR3
VCCA_GXBL0
VCCA_GXBL1
VCCA_GXBR0
VCCA_GXBR1
Analog Pwr
TX Output Buffer Pwr
1.5V
VCCH_GXB
A12
C12
F12
J12
M13
Analog Pwr
CLK Network Pwr
1.1V
Version 2.0 Pin Out
5AGXFB3H4F35
2.5V_VCCIO_VCCPD_VCCPGM
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
5
4
3
2
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
C1.1
Sheet
1
32
of
35
5
4
3
2
1
Power 7 - Arria V GX Ground
D
D
U1L
Arria V GX GND
2.5V_VCCIO_VCCPD_VCCPGM
R291
Design Note:
For debug only
R291 is 1k resistor
Install R291 and DNI
R292 to bypass POR
CAD Note:
Overlap pad at 1 of the
R291 & R292 pins
C
B
DNI
TESTPOR
R292
0
H5
B33
AA26
AA33
AA34
AB27
AB28
AB29
AB30
AB31
AB32
AC30
AC33
AC34
AD31
AD32
AE30
AE33
AE34
AF31
AF32
AG30
AG33
AG34
AH31
AH32
AJ30
AJ33
AJ34
AK31
AK32
AL33
AL34
E34
F31
F32
G30
G33
G34
H31
H32
J30
J33
J34
K31
K32
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Version 2.0 Pin Out
5AGXFB3H4F35
U1M
Arria V GX GND
L30
L33
L34
M31
M32
N28
N29
N33
N34
P27
P31
P32
R28
R30
R33
R34
T27
T29
T31
T32
U28
U33
U34
V27
V31
V32
W28
W30
W33
W34
Y27
Y29
Y31
Y32
AA1
AA2
AA9
AB3
AB4
AB5
AB7
AB8
AC1
AC2
AC5
AD3
AD4
AE1
AE2
AE5
AF3
AF4
AG1
AG2
AG5
AH3
AH4
AJ1
AJ2
AJ5
AK3
AK4
AL1
AL2
AL3
AN1
F3
F4
G1
G2
G5
H3
H4
J1
J2
J5
K3
K4
L1
L2
L5
M3
M4
M5
N1
N2
N6
P3
P4
P8
R1
R2
R5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U1N
Arria V GX GND
R7
T3
T4
T6
T8
U1
U2
U7
V3
V4
V8
W1
W2
W5
W7
Y3
Y4
Y6
Y8
AA11
AA13
AA16
AA19
AA22
AA24
AD10
AD13
AD16
AD19
AD22
AD25
AD28
AD7
AG10
AG13
AG16
AG19
AG22
AG25
AG28
AG7
AK10
AK13
AK16
AK19
AK22
AK25
AK28
AK7
AN10
AN13
AN16
AN19
AN22
AN25
AN28
AN31
AN4
AN7
B1
B10
B13
B16
B19
B22
B25
B28
B31
B4
B7
D2
D4
E10
E13
E16
E19
E22
E25
E28
E31
E7
H10
H13
H16
H19
H22
H25
H28
H7
L10
L13
L16
L19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Version 2.0 Pin Out
5AGXFB3H4F35
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L22
L25
L28
L8
M6
N7
P10
P13
P15
P17
P19
P21
P23
P25
R10
R12
R18
R20
R22
R24
T11
T13
T15
T17
T19
T21
T23
T25
U10
U14
U16
U24
V11
V13
V15
V17
V19
V21
V23
V25
W10
W12
W14
W16
W18
W20
W22
W24
U18
C
B
Version 2.0 Pin Out
5AGXFB3H4F35
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Size
B
Date:
5
4
3
2
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
C1.1
Sheet
1
33
of
35
8
7
6
5
4
3
2
1
Arria V GX Decoupling
1.1V_VCC
1.1V_VCCP
E
C315
100UF
D
C
C1116
100UF
C1117
100UF
C1120
100UF
C1121
100UF
C1122
100UF
C1126
C1127
C1128
C1190
C1191
C441
C318
C1192
C1194
C425
C1193
C1168
22uF
22uF
22uF
100UF
100UF
4.7UF
0.47uF
0.22uF
0.1uF
47nF
47nF
22nF
C1129
C316
C1130
C1118
C1119
C323
C317
C1132
C1133
22uF
10uF
10uF
10uF
10uF
2.2uF
1uF
0.47uF
0.47uF
C319
C1140
C1123
C322
C324
C1141
C1142
C1143
C1144
0.22uF
0.22uF
0.22uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C1145
C326
C327
C328
C1148
C1149
C1150
C1151
C1152
0.1uF
47nF
47nF
47nF
47nF
47nF
47nF
47nF
47nF
C1153
C1154
C329
C330
C331
C332
C1156
C1124
C1125
47nF
47nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
CAD Note:
1.15V
CAD Note:
Place near VCCL_GXBR0
VCCL_VCCR_GXB Place near VCCR_GXBR pins pins (sch pg 33)
(sch pg 33)
C371
C372
C373
C387
C1197
C1195
47nF
22nF
22nF
1uF
1uF
C1134
C1135
C1136
C1137
C1138
C1139
C1146
C1147
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
C1155
C1167
22nF
22nF
C374
C375
C384
C385
C1196
10uF
47nF
22nF
22nF
1uF
1uF
C1157
C1158
C1159
C1160
C1161
C1162
C1163
C1164
47nF
47nF
47nF
47nF
47nF
47nF
47nF
47nF
C1165
C1166
47nF
47nF
SPACER1
SCREW3
SCREW4
STANDOFF2
SPACER2
SCREW5
STANDOFF3
SCREW6
STANDOFF4
1.5V
VCCH_GXB
C346
C1202
C342
C345
C1203
4.7UF
4.7UF
22nF
4.7UF
4.7UF
22nF
E
CAD Note:
Place each cap on each
VCCH_GXB pin (sch pg 33)
C431
C407
C408
C432
2.2uF
2.2uF
2.2uF
2.2uF
1.5V
VCCD_FPLL_VCCBAT
CAD Note:
Place near VCCT_GXBR1
pins (sch pg 33)
C344
CAD Note:
Place near VCCT_GXBL0
pins (sch pg 33)
B
STANDOFF1
D
CAD Note:
Place near VCCL_GXBL1
pins (sch pg 33)
C386
1.15V
VCCT_GXB CAD Note:
Place near VCCT_GXBR0
pins (sch pg 33)
C1131
CAD Note:
Place near VCCL_GXBL0
pins (sch pg 33)
SCREW2
CAD Note:
Place near VCCL_GXBR1
pins (sch pg 33)
10uF
CAD Note:
Place near VCCR_GXBL pins
(sch pg 33)
SCREW1
2.5V
VCCA_GXB
C420
C325
47nF
1uF
C
2.5V
VCCAUX_VCCA_FPLL
CAD Note:
Place near VCCT_GXBL1
pins (sch pg 33)
C426
C320
C321
C423
C424
10uF
10uF
0.22uF
0.1uF
47nF
C1206
C1207
22nF
22nF
B
C341
C343
C1201
C1200
C1198
C1204
4.7UF
4.7UF
22nF
4.7UF
4.7UF
22nF
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
2
Sheet
C1.1
34
of
1
35
5
4
3
2
1
Arria V GX Decoupling
VREF_2.5V_VCCIO
2.5V_VCCIO_VCCPD_VCCPGM
D
D
C333
10uF
C335
C337
C338
C339
C340
C334
1uF
0.1uF
0.1uF
22nF
22nF
22nF
C389
C390
C391
C392
0.1uF
0.1uF
0.1uF
0.1uF
C409
C410
C411
C412
0.1uF
0.1uF
0.1uF
0.1uF
VREF_DDR3
1.5V_VCCIO
C357
C358
10uF
0.47uF
C359
0.1uF
C361
47nF
C362
22nF
C363
22nF
C364
22nF
C
C
B
B
A
A
Altera Worldwide Service, Plot 6, Bayan Lepas Technoplex, Penang, Malaysia
Title
Size
B
Date:
5
4
3
2
Arria V GX Starter Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
Rev
C1.1
150-0320806-C1 (6XX-44099R)
Friday, September 21, 2012
Sheet
1
35
of
35
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