DK-SI-5SGXEA7N Signal Integrity Kit Schematic

5
4
3
2
1
REV
DATE
DESCRIPTION
A
03-2011
initial release
B
10-2011
rev B release
C
05-2012
rev C release
D
06-2012
rev D release
D
D
PAGE
C
DESCRIPTION
1
block diagram, revision history
2
power tree
3
power - DC-Input / 2.5V / 5V
4
power - S5GX_VCC
5
power - 3.3V / VCCA / VCCRT
6
power - 1.5V / Ethernet / XFP
7
power - XCVR - GTB
8
Decoupling
9
power monitor - VCC / GTB
10
power monitor - GXB
11
temperature sense
12
USB blaster
13
MAX FPP configuration
14
flash
15
10/100 ethernet
16
switches / LEDs / LCD
17
amphenol backplane interface
18
tyco backplane interface
19
molex backplane interface
20
XFP interface
21
SMAs / SFP+ interface
22
clocks - core
23
clocks - ss / 50MHz
24
clocks - XCVR left blocks
25
clocks - XCVR right blocks
26
S5 configuration / JTAG
27
S5 bank 3
28
S5 bank 4
29
S5 bank 7
30
S5 bank 8
31
S5 - block left 0-1
32
S5 - block left 2-3
33
S5 - block right 0-1
34
S5 - block right 2-3
C
B
B
A
35
S5 FPGA / XCVR power
36
S5 - GND
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
1
of
36
D
5
4
3
2
1
Power Tree / Power Sequence
D
D
C
C
B
B
Power Sequence
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
2
of
36
D
5
4
3
2
1
PWR - DC-Input - 2.5V / 5V
14V-20V DC INPUT
J1
D1
2
1
3
DC_INPUT
RAPC712X
FM540
D
D
DC_INPUT
5V
INTVCC_1
DC_INPUT
5V
R2
150
5 6
LTC3855EUJ
C3
4.7uF
SW1
EG2201A
26
25
24
100K
1
2 3
D3
Blue_Led
GO
C
EN_2p5V
power LED
R4
20K
GO
R48
20K
38
37
14
2
1
13
36
15
6
7
VIN
INTVCC
EXTVCC
RJK0305DPB
TG1
BOOST1
SW1
RUN1
ITEMP1
ILIM1
ITH1
TK/SS1
BG1
VFB1
RUN2
ITEMP2
ILIM2
ITH2
TK/SS2
SENSE1+
SENSE1PGOOD1
2p5V
Q1
4
29
C4
0.1uF
31
27
L1
2
1
0.68uH
Q2
drain-tab
RJK0301DPB
4
3
R5
2.37K
39
40
16
C134
100uF
C
R6
57.6K
0.1uF
PWR_GOOD
R10
20K
C8
C9
1000pF
1000pF
R11
169K
35
34
33
32
FREQ
MODE/PLLIN
PHSASMD
CLKOUT
D4
CMDSH-3
R3
47.5K
RJK0305DPB
5
R9
100K
R7
15K
Q3
drain-tab
R12
49.9K
R13
100K
C11
120pF
C135
BOOST2
SW2
gnd-pad
220pF
C7
56pF
B
STDOF1
Standoff Hole
R129
23.2K
C12
22pF
R16
47.5K
BG2
VFB2
12
10
11
SENSE2+
SENSE2-
DIFFOUT
DIFFP
DIFFN
PGOOD2
21
C10
0.1uF
L2
2
19
23
RJK0301DPB
4
5
1
1.2uH
Q4
drain-tab
C15
0.1uF
PG_5V
R15
110K
R14
4.12K
8
9
17
5V
5V
4
20
1
2
3
TG2
5
GND post
SGND1
SGND2
PGND1
PGND2
NC
1
2
3
4
41
28
22
18
J3
C5
330uF
C6
INTVCC_1
R8
49.9K
2.5V
drain-tab
30
5
4
C2
150uF
1
2
3
R1
C1
150uF
D2
CMDSH-3
U1
1
2
3
INTVCC_1
5
DC_INPUT
R17
113K
C14
C13
100uF
330uF
R18
15K
B
STDOF2
Standoff Hole
STDOF3
Standoff Hole
STDOF4
Standoff Hole
EN_2p5V
EN_2p5V
PWR_GOOD
PG_5V
10
PWR_GOOD
4,5,6,7,13
PG_5V
5,10
STDOF5
Standoff Hole
STDOF6
Standoff Hole
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
3
of
36
D
5
4
3
2
1
PWR S5GX - VCC
D
5V
DC_INPUT
INTVCC_2
C18
INTVCC_2
22uF
EN_S5GX_VCC
R21
20K
38
37
14
2
1
13
36
15
6
7
C
BOOST1
SW1
RUN1
ITEMP1
ILIM1
ITH1
TK/SS1
BG1
VFB1
RUN2
ITEMP2
ILIM2
ITH2
TK/SS2
SENSE1+
SENSE1PGOOD1
S5GX_VCC_SENSE
4
30
C20
0.1uF
L3
1
2
3
TG1
29
31
F1
10 AMPS
R19
F2
10 AMPS
.001
1
0.68uH
Q6
drain-tab
RJK0301DPB
4
27
2
R20
2.2K
C21
C22
C23
C24
330uF
330uF
100u
22uF
3
39
40
0.1uF
PWR_GOOD
C26
10uF
10uF
R22
300K
C27
16
C25
C
C28
22uF
R26
73.2K
R25
20K
RJK0305DPB
Q7
drain-tab
C31
3300pF
C32
470pF
FREQ
MODE/PLLIN
PHSASMD
CLKOUT
SGND1
SGND2
PGND1
PGND2
NC
TG2
BOOST2
SW2
VFB2
12
10
11
B
BG2
gnd-pad
R29
4.42K
SENSE2+
SENSE2-
DIFFOUT
DIFFP
DIFFN
PGOOD2
4
20
C30
0.1uF
21
L4
1
2
3
4
41
28
22
18
5
R28
100K
35
34
33
32
5
C29
1000pF
R27
49.9K
drain-tab
VIN
INTVCC
EXTVCC
5
26
25
24
S5GX_VCC
Q5
1
2
3
4.7uF
R24
100K
RJK0305DPB
LTC3855EUJ
C19
R23
49.9K
D5
CMDSH-3
U2
19
RJK0301DPB
4
23
2
drain-tab
R30
2.2K
5
8
9
C36
17
PWR_GOOD
0.1uF
CMDSH-3
D6
R312
52.3K
Refer to Datasheet for
recommended layout
1
0.68uH
Q8
C33
C34
C35
330uF
330uF
100u
1
2
3
220uF
C17
150uF
5
J6
C16
D
S5GX_VCC
(0.9V)
DC_INPUT
R31
300K
B
EN_S5GX_VCC
EN_S5GX_VCC
10
PWR_GOOD
R44
249K
INTVCC_2
PWR_GOOD
S5GX_VCC_VDACP6
3,5,6,7,13
S5GX_VCC_VDACP6
R33
102K
9
S5GX_VCC_VDACP6
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
4
of
36
D
5
4
3
2
1
U3
3.3V PWR
VCCA_GXB / VCCRT_GXB
5V
C38
C39
C40
330uF
330uF
330uF
10uF
H6
H5
H4
H3
H2
D
EN_VCCRT_GXB
C329
C330
DNI 2.2uf
DNI 2.2uf
EN_VCCA_GXB
E2
E3
E5
B6
B5
B4
B3
B2
F8
E7
K5
K4
K3
K2
K1
J5
J4
J3
J2
J1
C
RUN/SS1
TRACK1
COMP1
LTM4615EV
SW1A
SW1B
SW1C
SW1D
SW1E
RUN/SS2
TRACK2
COMP2
VOUT1A
VOUT1B
VOUT1C
VOUT1D
VOUT1E
VOUT1F
VOUT1G
VOUT1H
VOUT1I
VOUT1J
VOUT1K
VOUT1L
FB1
SW2A
SW2B
SW2C
SW2D
SW2E
PGOOD1
M12
M11
M10
M9
L12
L11
L10
L9
K12
K11
K10
K9
3p3V
3.3V
D
R202
10K
L6
L4
C41
100uF
R34
1.58K
J9
PG_3p3V
VCCRT_GXB
VCCRT_GXB_SENSE
R35
15.4K
VOUT2A
VOUT2B
VOUT2C
VOUT2D
VOUT2E
VOUT2F
VOUT2G
VOUT2H
VOUT2I
VOUT2J
EN3
BOOST3
VIN1A
VIN1B
VIN1C
VIN1D
VIN1E
VIN1F
VIN1G
VIN1H
VIN1I
VIN1J
FB2
PGOOD2
C9
C10
C11
C12
D9
D10
D11
D12
E11
E12
VCCRT_GXB_VDACP2
F6
R37
20K
19.1K
SW2
1
2
3
4
E6
E4
G4
G3
G2
G1
H1
H7
H8
H9
H10
H11
H12
J6
J7
J8
J9
J10
J11
J12
K6
K7
K8
L1
L7
L8
M1
M2
M3
M4
M5
M6
M7
M8
B
A
LDO_OUTA
LDO_OUTB
LDO_OUTC
LDO_OUTD
FB3
PGOOD3
R36
10uF
C42
100uF
8
7
6
5
C
PWR_GOOD
TDA04H0SB1
G9
G10
G11
G12
J12
R40
178
768
VCCA_GXB
VCCA_GXB_SENSE
F7
2 AMPS
F6
G5
LDO_INA
LDO_INB
LDO_INC
LDO_IND
GND1A
GND1B
GND1C
GND1D
GND1E
GND1F
GND1G
GND1H
GND1I
GND1J
GND1K
GND1L
GND1M
GND1N
GND1O
GND1P
GND1Q
GND1R
GND1S
GND1T
GND1U
GND1V
GND1W
GND1X
GND1Y
GND1Z
GND1AA
GND1AB
GND2A
GND2B
GND2C
GND2D
GND2E
GND2F
GND2G
GND2H
GND2I
GND2J
GND2K
GND2L
GND2M
GND2N
GND2O
GND2P
GND2Q
GND2R
GND2S
GND2T
GND2U
GND2V
GND2W
GND2X
GND2Y
GND2Z
GND2AA
GND2AB
R41
PWR_GOOD
R42
1.78K
VCCA_GXB_VDACP0
C684
G8
G7
G6
F12
F11
F10
F9
F7
F5
F4
F3
F2
F1
4
VCCA_GXB
(2.5V/3.0V)
.009
3p3V
C43
120ohm; 800mA
FB6
10uF
F8
2 AMPS
VCCA_GXB = 3.3V
Remove F7
Install Fuse at F8
VCCA_GXB = 2.5V/3.0V
Remove F8
Install Fuse at F7
E10
E9
E8
E1
D8
D7
D6
C8
C7
B12
B11
B10
B9
B8
B7
B1
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
B
EN_VCCRT_GXB
EN_VCCA_GXB
EN_VCCRT_GXB
EN_VCCA_GXB
VCCRT_GXB_VDACP2
VCCA_GXB_VDACP0
PG_3p3V
PWR_GOOD
PG_5V
10
10
VCCRT_GXB_VDACP2
VCCA_GXB_VDACP0
10
10
PG_3p3V
6
PWR_GOOD
3,4,6,7,13
PG_5V
3,10
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
.009
C683
10uF
GND3A
GND3B
GND3C
GND3D
GND3E
GND3F
GND3G
GND3H
GND3I
GND3J
GND3K
GND3L
GND3M
5A
VCCRT_GXB
(0.9V/1.0V)
2
3p3V
VIN2A
VIN2B
VIN2C
VIN2D
VIN2E
VIN2F
VIN2G
VIN2H
VIN2I
VIN2J
VIN2K
(SW2 Silkscreen Text)
SW2-1 open = 0.9V
SW2-1 close = 1.0V
SW2-2 open = 2.5V
SW2-2 close = 3.0V
R38
R39
D5
D4
D3
D2
D1
C6
C5
C4
C3
C2
C1
C682
10uF
1
C37
L2
L3
L5
OPEN
PG_5V
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
5
of
36
D
5
4
3
2
1
PWR S5GX - 1.5V
(Ethernet / XFP)
D
D
5V
1p5V
1.5V
5V
1p5V
Ethernet_1p2V
U5
U4
EN_1p5V
F1
F4
E5
C
DNI
R32
20K
DNI
R52
20K
B3
B5
B4
E3
B7
B8
C5
C4
C3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B9
B10
B
RUN/SS
1
2
C10
C11
D10
D11
E9
E10
E11
F9
F10
F11
G9
G10
G11
IN1
IN2
C347
4
SW
4.7uF
C47
100uF
OUT2
OUT1
6
SHDN
ADJ
PG
GND
GND
C46
100uF
BST
3
11
10uF
LTM4608AEV
VOUT-C10
VOUT-C11
VOUT-D10
VOUT-D11
VOUT-E9
VOUT-E10
VOUT-E11
VOUT-F9
VOUT-F10
VOUT-F11
VOUT-G9
VOUT-G10
VOUT-G11
5
Ethernet_1.2V
10
9
8
7
R43
8.06K
LTC3026
C48
C49
1u
10uF
PG_1p5V
R45
4.02K
R46
SVIN
TRACK
FB
CLKIN
MODE
PHMODE
PLLLPF
BSEL
MGN
ITH
ITHM
PGOOD
CLKOUT
C
E7
F6
6.65K
PWR_GOOD
F5
C7
PG_1p5V
F2
3p3V
5V
XFP_1p8V
SW1
SW2
SW3
U6
1
2
GND-A1
GND-A2
GND-A3
GND-A4
GND-A5
GND-A6
GND-A7
GND-A8
GND-A9
GND-A10
GND-A11
GND-B1
GND-B9
GND-B10
GND-G8
GND-G7
GND-G6
GND-G5
GND-G4
GND-G3
GND-G2
GND-G1
GND-F8
GND-F7
GND-F3
GND-B11
SGND
G8
G7
G6
G5
G4
G3
G2
G1
F8
F7
F3
B11
C348
4
4.7uF
6
IN1
IN2
BST
OUT2
OUT1
SW
SHDN
ADJ
PG
GND
GND
10uF
C45
VIN-E8
VIN-D9
VIN-D8
VIN-D7
VIN-D5
VIN-D4
VIN-D3
VIN-D1
VIN-C9
VIN-C8
VIN-C1
3
11
C44
E8
D9
D8
D7
D5
D4
D3
D1
C9
C8
C1
5
XFP_1.8V
10
9
8
7
R47
14K
LTC3026
C50
C51
1u
10uF
PG_3p3V
B
R49
4.02K
E1
PWR_GOOD
PWR_GOOD
PG_1p5V
PG_3p3V
PWR_GOOD
3,4,5,7,13
PG_1p5V
10
PG_3p3V
5
EN_1p5V
EN_1p5V
10
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
6
of
36
D
5
4
3
2
1
PWR XCVR - GTB
J15
5V
1p5V
VCCR_GTB
U7
1
2
C349
D
4
4.7uF
IN1
IN2
BST
OUT2
OUT1
SW
SHDN
3
11
GND
GND
6
VCCR_GTB_SENSE
ADJ
PG
5
F3
VCCR_GTB
(1.0V)
2 AMPS
10
9
8
7
R51
6.04K
C685
C53
1u
10uF
R50
.009
D
C52
10uF
LTC3026
EN_VCCR_GTB
R53
20K
R54
4.02K
VCCR_GTB_VDACP2
PWR_GOOD
J18
1p5V
5V
VCCT_GTB
C
U8
1
2
C350
4
4.7uF
IN1
IN2
BST
OUT2
OUT1
SW
SHDN
3
11
GND
GND
6
C
VCCT_GTB_SENSE
ADJ
PG
5
F4
VCCT_GTB
(1.0V)
2 AMPS
10
9
R55
C55
8
7
R56
6.04K
.009
C686
10uF
1u
C54
10uF
LTC3026
EN_VCCT_GTB
R58
20K
R59
4.02K
VCCT_GTB_VDACP0
PWR_GOOD
B
B
J21
1p5V
5V
VCCL_GTB
U9
1
2
C351
4
4.7uF
IN1
IN2
BST
OUT2
OUT1
SW
SHDN
3
11
GND
GND
6
VCCL_GTB_SENSE
ADJ
PG
5
F5
VCCL_GTB
(1.0V)
2 AMPS
10
9
8
7
R61
6.04K
C687
C57
1u
10uF
R60
PWR_GOOD
.009
3,4,5,6,13
EN_VCCR_GTB
EN_VCCT_GTB
EN_VCCL_GTB
VCCT_GTB_VDACP0
VCCR_GTB_VDACP2
VCCL_GTB_VDACP4
C56
LTC3026
PWR_GOOD
EN_VCCR_GTB
EN_VCCT_GTB
EN_VCCL_GTB
10
10
10
VCCT_GTB_VDACP0
VCCR_GTB_VDACP2
VCCL_GTB_VDACP4
9
9
9
10uF
EN_VCCL_GTB
R63
20K
R64
4.02K
A
A
VCCL_GTB_VDACP4
Altera Corporation, 101 Innovation Drive, San Jose, CA
PWR_GOOD
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
7
of
36
D
5
4
3
2
1
Decoupling
S5GX_VCC
(0.9V) S5GX_VCC
1.5V
2.5V
1p5V
2p5V
D
D
C580
C438
C485
C400
C578
C579
C437
C478
22nF
0.01uF
0.1uF
10uF
22nF
22nF
0.01uF
0.047uF 0.047uF 0.1uF
3.3V
5V
3p3V
C479
C483
C484
C505
C506
C591
C592
0.22uF
1u
1u
100uF
100uF
5V
C507
C508
C509
C510
C326
C345
1u
1u
1u
1u
2.2uf
4.7uF
C593
C594
C595
C596
C597
C598
C599
C600
C601
C602
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
C305
C306
C307
C308
C309
C310
C311
C312
330uF
330uF
330uF
330uF
330uF
330uF
330uF
330uF
C
C
C480
C401
0.047uF 10uF
C477
C482
C325
C398
C399
0.047uF
0.1uF
2.2uf
10uF
10uF
VCCR_GTB
(1.0V) VCCR_GTB
B
VCCRT_GXB
(0.9V/1.0V)
VCCL_GTB
(1.0V) VCCL_GTB
C440
C441
C489
C490
0.01uF
0.01uF
0.047uF 0.22uF
C604
C605
C447
C494
C328
100uF
100uF
0.01uF
0.047uF 2.2uf
VCCA_GXB
(2.5V/3.0V)
VCCRT_GXB
B
VCCA_GXB
C581
C582
C439
C481
C486
22nF
22nF
0.01uF
0.047uF 0.22uF
C487
C327
C603
C488
0.22uF
2.2uf
100uF
0.1uF
VCCT_GTB
(1.0V) VCCT_GTB
C583
C442
C443
C444
C445
C446
C491
C492
C493
22nF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.047uF 0.047uF 0.22uF
C346
C681
4.7uF
22uf
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
8
of
36
D
5
4
3
2
1
Power Monitor 1 - VCC / GTB
S5GX_VCC
S5GX_VCC_SENSE
VCCL_GTB
VCCL_GTB_SENSE
VCCR_GTB
VCCR_GTB_SENSE
D
I2C Interface
Power Monitor 1 - VCC / GTB
VCCT_GTB
VCCT_GTB_SENSE
J24
1
3
5
7
9
11
PM_CNTL1
5V
C
R65
R66
1K
1K
C58
R67
R68
1K
1K
C60
0.1uF C61
0.1uF
2
4
6
8
10
12
D
SDA_PM
SCL_PM
PM_ALERTB
U10
14
1K
1K
C63
R72
R73
1K
1K
C66
R74
R69
1K
1K
C65
R75
R76
1K
1K
C69
R82
R83
1K
1K
C71
1K
1K
0.1uF
2
4
6
8
10
12
2x6HDR
R70
R71
R84
R85
0.1uF C59
1
3
5
7
9
11
C73
0.1uF C64
0.1uF C67
0.1uF C68
0.1uF C70
0.1uF C72
0.1uF C74
36
37
42
43
46
47
48
49
52
53
62
63
64
1
2
3
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
SCL_PM
SDA_PM
PM1_ASEL0
PM1_ASEL1
PM_CNTL0
PM_CNTL1
PM_RSTn
0.1uF
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
these GND connections to
each VSENSEMx pin
needs to be placed close
to a GND pin of the BGA!
28
27
32
33
30
31
22
23
24
25
26
PM_SHARE_CLK 21
19
65
VIN_SNS
VSENSEP0
VSENSEM0
VSENSEP1
VSENSEM1
VSENSEP2
VSENSEM2
VSENSEP3
VSENSEM3
VSENSEP4
VSENSEM4
VSENSEP5
VSENSEM5
VSENSEP6
VSENSEM6
VSENSEP7
VSENSEM7
SCL
SDA
ASEL0
ASEL1
CONTROL0
CONTROL1
WDI/RESET
FAULTB00
FAULTB01
FAULTB10
FAULTB11
REFP
REFM
NC
VDACP0
VDACM0
VDACP1
VDACM1
VDACP2
VDACM2
VDACP3
VDACM3
VDACP4
VDACM4
VDACP5
VDACM5
VDACP6
VDACM6
VDACP7
VDACM7
VOUT_EN0
VOUT_EN1
VOUT_EN2
VOUT_EN3
VOUT_EN4
VOUT_EN5
VOUT_EN6
VOUT_EN7
SHARE_CLK
ALERTB
PWRGD
VPWR
VDD25
WP
E-PAD
GND pad
B
VIN_EN
LTC2978
VDD33_OUT
VDD33_IN
12
C62
0.1uf
34
35
13
39
38
40
41
44
45
50
51
55
54
56
57
59
58
60
61
VDD33_1
VCCT_GTB_VDACP0
R77
10K
VCCR_GTB_VDACP2
R78
10K
R79
10K
R80
10K
R81
R204 R203 R297 R296 R298
5.49K 10K
10K
10K
10K
10K
C
VCCL_GTB_VDACP4
S5GX_VCC_VDACP6
4
5
6
7
8
9
10
11
EN_VCCT
29
20
15
18
PM_ALERTB
PM_PWRGD
SDA_PM
SCL_PM
PM_RSTn
PM_PWRGD
PM_SHARE_CLK
PM_RSTn
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
EN_VCCR
EN_VCCL
EN_VCC
SCL_PM
SDA_PM
SCL_PM
SDA_PM
VDD33_1
16
17
LTC2978
Address Select
PWRMON1 = 7'h5C
C75
C76
C77
0.1uf
0.1uf
0.1uf
PM_SHARE_CLK
PM_CNTL0
PM_CNTL1
PM_RSTn
PM1_ASEL0
PM1_ASEL1
10,13,29
10,13,29
B
PM_SHARE_CLK
10,13,29
PM_CNTL0
10,13,29
PM_CNTL1
10,13,29
PM_RSTn
10,13,29
PM_ALERTB
PM_PWRGD
PM_ALERTB
PM_PWRGD
10,13,29
10,13,29
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
EN_VCCT
EN_VCCR
EN_VCCL
EN_VCC
EN_VCCT
EN_VCCR
EN_VCCL
EN_VCC
VCCT_GTB_VDACP0
VCCR_GTB_VDACP2
VCCL_GTB_VDACP4
S5GX_VCC_VDACP6
VCCT_GTB_VDACP0
VCCR_GTB_VDACP2
VCCL_GTB_VDACP4
S5GX_VCC_VDACP6
13,29
13,29
13,29
13,29
10
10
10
10
7
7
7
4
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
9
of
36
D
5
4
3
2
1
Power Monitor 2 - GXB
5V
5V
5V
5V
1P5V
D
2p5V
R130
10K
R96
10K
1
3
5
9
11
13
Power Monitor 2 - GXB
5V
R86
R87
1K
1K
C78
0.1uF C79
PG_5V
1A
2A
3A
4A
5A
6A
7
0.1uF
2
4
6
8
10
12
1Y
2Y
3Y
4Y
5Y
6Y
D
R270
10K
R99
10K
14
VCC
VCCRT_GXB
VCCRT_GXB_SENSE
VCCA_GXB
VCCA_GXB_SENSE
U37
U38
VCC
1
3
5
9
11
13
EN_S5GX_VCC
EN_VCCRT_GXB
EN_VCCA_GXB
EN_1p5V
EN_2p5V
PG_1p5V
7
GND
74LS07
C80
0.1uF C81
0.1uF
R90
R91
1K
1K
C83
0.1uF C88
0.1uF
R92
R94
1K
1K
C84
0.1uF C85
0.1uF
R93
R95
1K
1K
C86
R97
R98
1K
1K
C90
0.1uF C87
0.1uF C91
36
37
42
43
46
47
48
49
52
53
62
63
64
1
2
3
0.1uF
0.1uF
these GND connections to
each VSENSEMx pin
needs to be placed close
to a GND pin of the BGA!
SCL_PM
SDA_PM
PM2_ASEL0
PM2_ASEL1
PM_CNTL0
PM_CNTL1
PM_RSTn
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
28
27
32
33
30
31
22
23
24
25
26
PM_SHARE_CLK 21
B
19
65
VDD33_2
1Y
2Y
3Y
4Y
5Y
6Y
2
4
6
8
10
12
EN_VCCR_GTB
EN_VCCT_GTB
EN_VCCL_GTB
GND
74LS07
U11
14
VIN_SNS
VSENSEP0
VSENSEM0
VSENSEP1
VSENSEM1
VSENSEP2
VSENSEM2
VSENSEP3
VSENSEM3
VSENSEP4
VSENSEM4
VSENSEP5
VSENSEM5
VSENSEP6
VSENSEM6
VSENSEP7
VSENSEM7
SCL
SDA
ASEL0
ASEL1
CONTROL0
CONTROL1
WDI/RESET
FAULTB00
FAULTB01
FAULTB10
FAULTB11
REFP
REFM
NC
VDACP0
VDACM0
VDACP1
VDACM1
VDACP2
VDACM2
VDACP3
VDACM3
VDACP4
VDACM4
VDACP5
VDACM5
VDACP6
VDACM6
VDACP7
VDACM7
VOUT_EN0
VOUT_EN1
VOUT_EN2
VOUT_EN3
VOUT_EN4
VOUT_EN5
VOUT_EN6
VOUT_EN7
SHARE_CLK
ALERTB
PWRGD
VPWR
VDD25
WP
E-PAD
GND pad
R300 R303 R304 R301
10K
10K
10K
10K
VIN_EN
LTC2978
VDD33_OUT
VDD33_IN
LTC2978
Address Select
PWRMON2 = 7'h5D
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
12
C82
0.1uf
34
35
13
39
38
40
41
44
45
50
51
55
54
56
57
59
58
60
61
VCCA_GXB_VDACP0
R100 R101 R160 R191
10K
10K
10K
10K
SW3
VCCRT_GXB_VDACP2
EN_VCC
EN_VCCRT
EN_VCCA
EN1p5V
1
2
3
4
8
7
6
5
EN_S5GX_VCC
EN_VCCRT_GXB
EN_VCCA_GXB
EN_1p5V
5V
TDA04H0SB1
Sequence Enable - Switch 3
---------------------------------------------------------SW3-1 open = bypass PM control - S5GX_VCC
SW3-1 close = PM sequence enabled - S5GX_VCC
SW3-2 open = bypass PM control - VCCRT_GXB
SW3-2 close = PM sequence enabled - VCCRT_GXB
SW3-3 open = bypass PM control - VCCA_GXB
SW3-3 close = PM sequence enabled - VCCA_GXB
SW3-4 open = bypass PM control - 1p5V
SW3-4 close = PM sequence enabled - 1p5V
SW7
EN_VCCA
EN_VCCRT
EN2p5V
EN2p5V
EN_VCCR
EN_VCCT
EN_VCCL
EN1p5V
1
2
3
4
8
7
6
5
EN_2p5V
EN_VCCR_GTB
EN_VCCT_GTB
EN_VCCL_GTB
TDA04H0SB1
PM_ALERTB
PM_PWRGD
Sequence Enable - Switch 7
---------------------------------------------------------SW7-1 open = bypass PM control - 2p5V
SW7-1 close = PM sequence enabled - 2p5V
SW7-2 open = bypass PM control - VCCR_GTB
SW7-2 close = PM sequence enabled - VCCR_GTB
SW7-3 open = bypass PM control - VCCT_GTB
SW7-3 close = PM sequence enabled - VCCT_GTB
SW7-4 open = bypass PM control - VCCL_GTB
SW7-4 close = PM sequence enabled - VCCL_GTB
16
17
C93
C94
C95
0.1uf
0.1uf
0.1uf
SCL_PM
SDA_PM
PM_SHARE_CLK
PM_CNTL0
PM_CNTL1
PM_RSTn
PM2_ASEL0
PM2_ASEL1
SCL_PM
SDA_PM
9,13,29
9,13,29
PM_SHARE_CLK
9,13,29
PM_CNTL0
9,13,29
PM_CNTL1
9,13,29
PM_RSTn
9,13,29
PM_ALERTB
PM_PWRGD
PM_ALERTB
PM_PWRGD
9,13,29
9,13,29
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
13,29
13,29
13,29
13,29
PG_5V
PG_1p5V
PG_5V
3,5
PG_1p5V
6
EN_S5GX_VCC
EN_VCCRT_GXB
EN_VCCA_GXB
EN_1p5V
EN_2p5V
EN_VCCR_GTB
EN_VCCT_GTB
EN_VCCL_GTB
EN_VCC
EN_VCCR
EN_VCCT
EN_VCCL
EN_S5GX_VCC
4
EN_VCCRT_GXB
5
EN_VCCA_GXB
5
EN_1p5V
6
EN_2p5V
3
EN_VCCR_GTB
7
EN_VCCT_GTB
7
EN_VCCL_GTB
7
EN_VCC
9
EN_VCCR
9
EN_VCCT
9
EN_VCCL
9
VCCA_GXB_VDACP0
VCCRT_GXB_VDACP2
VCCA_GXB_VDACP0
VCCRT_GXB_VDACP2
5
5
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
4
B
VDD33_2
A
5
C
R268 R267 R269 R266
10K
10K
10K
10K
4
5
6
7
8
9
10
11
29
20
15
18
5V
OPEN
C
1K
1K
OPEN
R88
R89
1A
2A
3A
4A
5A
6A
14
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
10
of
36
D
5
4
3
2
1
Temperature Measure
D
D
2p5V
3p3V
2p5V
R102 R103
10.0K 10.0K
R104 R105
10.0K 10.0K
R106
160
TEMPDIODE_P
U12
route as matched pair
6
10
C96
2.2nF
3
4
TEMPDIODE_N
D7
ADD1
ADD0
OVERT
ALERT
DXP
DXN
SMBCLK
SMBDATA
3p3V
R107
15
1
200
C98
C
OVERTEMPn
ALERTn
14
12
SMBCLK_TEMP
SMBDATA_TEMP
FAN_LED
Amber_LED
2
7
8
C
5
13
16
0.1uF
GND1
GND2
GND3
STBY
VCC
9
11
NC1
NC2
NC3
MAX1619
SLAVE ADDR = 0011000b = 18h
FAN Select
-----------------------JUMPER 1-2 = FAN AUTO
JUMPER 2-3 = FAN ON
1uF
C101
0.1uF
C99
R108 R109
10.0K 10.0K
U13
7
SMBCLK_TEMP 8
SMBDATA_TEMP 1
2
B
2p5V
VCCB
VCCA
B1
B2
A1
A2
GND
OE
3
0.1uF
5
4
R110
10.0K
S5_SMBCLK_TEMP
S5_SMBDATA_TEMP
2p5V
FAN_CTRL
3
2
1
3
2
1
1x3Header
Q9
FDV305N
1
6
2
C100
J26
2p5V
3
3p3V
5V
1
2
3
2p5V
FAN
J25
3X1
B
TXS0102
S5_SMBCLK_TEMP
S5_SMBDATA_TEMP
S5_SMBCLK_TEMP
13,29
S5_SMBDATA_TEMP 13,29
FAN_CTRL
FAN_CTRL
FAN_LED
13,29
FAN_LED
OVERTEMPn
ALERTn
TEMPDIODE_P
TEMPDIODE_N
13,29
OVERTEMPn
13,29
ALERTn
13,29
TEMPDIODE_P
TEMPDIODE_N
26
26
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
11
of
36
D
5
4
3
2
1
2p5V
USB BLASTER
USBVCC
2p5V_USB
2p5V
FB1
1
R124
10.0K
2
120ohm, 800mA
C109
0.01uF
R111
470
10uF
C111
C108
CN1
CN-USB
C112
0.1uF
R112
1K
33nF
5
C114
31
C115
56pF
13
3
26
EECS
EESK
EEDATA
TXE#
RXF#
TEST
56pF
9
17
FT245BL
AGND
G1
G2
U17
SN65220
32
1
2
USB_EECS
USB_EESK
EEDATA
D0
D1
D2
D3
D4
D5
D6
D7
RD#
WR
RESET#
3
C
2
5
XTIN
XTOUT
4
/RESET
1
NC1 NC2
RSTOUT#
27
28
SI/WU
PWREN#
25
24
23
22
21
20
19
18
USB_D0
USB_D1
USB_D2
USB_D3
USB_D4
USB_D5
USB_D6
USB_D7
14
12
USB_TXEn
USB_RXFn
C122
C123
C124
1uF
0.1uF
0.1uF
0.1uF
2p5V
4
6
7
93LC64B_SO
USBVCC
CLKIN_24MHz
/RESET
USB_MAX_D7
R121
2.2K
USB_TXEn
USB_D1
USB_D0
USB_WR
USB_RDn
USB_D7
USB_D6
USB_D5
A1
A10
A11
A2
A3
A4
A5
A6
USB_D4
USB_D3
USB_D2
A7
A8
A9
B10
B11
B2
B3
B4
INIT_DONE
nSTATUS
CONF_DONE
F10
G11
1
EN
2
C105
0.01uF
GND
VCC
OUT
4
3
24MHz
C106
C107
0.01uF
4.7uF
C102
1
2
3
4
9
1uF
TCK
TDI
TDO
TMS
IOB1/DEV_CLRn
IOB1/DEV_OE
L7
L9
USB_MAX_D6
JTAG_TCK
2p5V
R116
10.0K
K1
J2
K2
J1
2p5V
J27
1
3
5
7
9
ISPTCK
ISPTDO
ISPTMS
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
C
R118
10.0K
MAX II
BANK2
IOB2_35
IOB2_36
IOB2_37
IOB2_38
IOB2_39
IOB2_40
IOB2_41
IOB2_42
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
IOB2_58
IOB2_43
IOB2_44
IOB2_45
IOB2_46
IOB2_47
IOB2_48
IOB2_49
IOB2_50
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_66
IOB2/CLK2
IOB2/CLK3
IOB2_67
IOB2_68
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
IOB2_74
B5
B6
B7
B8
B9
C10
C11
C5
PFL_STATUS
S5_Unlock
USB_MAX_D1
2p5V
C6
C7
D10
D11
D9
E10
E11
F11
S5_Unlock
PFL_STATUS
S5_Unlock
16
PFL_STATUS
13
INIT_DONE
nSTATUS
CONF_DONE
INIT_DONE
13,26
nSTATUS
13,26
CONF_DONE
13,26
USB_MAX_D2
USB_MAX_D[7..0]
F9
G10
H10
H11
H9
J10
J11
K11
USB_MAX_D[7..0]
USB_MAX_RDn
USB_MAX_WR
USB_MAX_TXEn
USB_MAX_RXFn
USB_MAX_PWR_ENn
USB_MAX_RDn
13
USB_MAX_WR
13
USB_MAX_TXEn 13
USB_MAX_RXFn
13
USB_MAX_PWR_ENn
USB_MAX_D5
MAX_2_MAX_INITDONE
MAX_2_MAX_INITDONE
JTAG_TMS
S5_TDI
LAST_TDO
JTAG_TCK
JTAG_TMS
S5_TDI
MAX II
Power
C117
D5
D7
E4
E8
G4
G8
H5
H7
1uF
R188
20.0K
A
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCINT
VCCINT
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
B
13
13
LAST_TDO
26
JTAG_TCK
13,26
JTAG_TMS
13,26
S5_TDI
26
BLASTER_DISn
BLASTER_DISn
U16C
C116
0.01uF
13
USB_MAX_D3
USB_MAX_D4
2p5V
R120
19.1K
LT3010
CLKIN_24MHz
K8
L8
IOB1/CLK0
IOB1/CLK1
USB_LED
LAST_TDO
USB_MAX_D0
USB_MAX_RXFn
USB_MAX_PWR_ENn
USB_MAX_TXEn
USB_MAX_RDn
USB_MAX_WR
EPM570M100
U15
IN
OUT
NC7 SENSE
NC6
NC3
SHDNn GND
EPAD
F2
E1
L1
L10
L11
L2
L3
L4
L5
L6
ISPTDI
2p5V_USB
8
7
6
5
Y1
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
D
2x5Header
USB_LED
2p5V
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
J7
K10
K3
K4
K5
K6
K7
K9
USB_SI_WU
USB_PWR_ENn
R119
10.0K
DO
ORG*
NC
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
U16B
8
VCC
GND
C121
DI
CLK
CS
5
D8
Green_LED
B
3
2
1
EEDATA
USB_EESK
USB_EECS
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
EPM570M100
11
10
R122
82
F3
G1
G2
H1
H2
H3
J5
J6
MAX II
BANK1
IOB1_33
IOB1_34
USB_RDn
USB_WR
USBVCC
USBVCC
MAX_2_MAX_INITDONE
16
15
USBVCC
U18
USB_EECS
USB_EESK
EEDATA
USB_SI_WU
BLASTER_DISn
USB_PWR_ENn
29
1.5K
2
6
4
A
B
X1
6MHZ
USBDM
USBDP
GND1
GND2
R115
VCC-IO
8
7
27
27
C113
0.1uF
1
3V3OUT
VCC1
VCC2
6
AVCC
U14
6
5
30
0.1uF
1
2
3
4
R113
R114
B1
C1
C2
D1
D2
D3
E2
F1
USB_RXFn
MAX_EN
R117
100K
C103
D
U16A
26
E9
G3
E3
J4
J8
C104
C110
C120
C118
0.1uF
0.1uF
0.1uF
0.22uF
A
C4
C8
G9
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
EPM570M100
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
12
of
36
D
5
4
3
2p5V
U19A
50MHz_MAXll_CLK
S5_SMBCLK_TEMP
S5_SMBDATA_TEMP
FAN_CTRL
FAN_LED
OVERTEMPn
ALERTn
D
USB_MAX_RDn
USB_MAX_WR
USB_MAX_TXEn
USB_MAX_RXFn
USB_MAX_PWR_ENn
MAXll_BEN0
MAXll_BEN1
MAXll_BEN2
MAXll_BEN3
MAXll_CLK
MAXll_CSN
MAXll_OEN
MAXll_WEN
MAX_2_MAX_INITDONE
PWR_GOOD
H5
J5
D3
C2
E3
C3
E4
D2
E5
D1
F3
E2
F4
E1
F5
F2
F6
F1
G3
G2
G4
G1
G5
H2
G6
H1
H3
J1
CLK0 / IOB1_0
CLK1 / IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
IOB1_33
IOB1_34
IOB1_35
IOB1_36
IOB1_37
IOB1_38
IOB1_39
IOB1_40
IOB1_41
IOB1_42
IOB1_43
IOB1_44
IOB1_45
IOB1_46
IOB1_47
IOB1_48
IOB1_49
IOB1_50
TCK_B1
TDI_B1
TDO_B1
TMS_B1
H4
J2
J4
K1
J3
K2
K6
L1
K5
L2
K4
M1
K3
M2
L5
M3
L4
N1
L3
N2
M4
N3
P2
PFL_STATUS
CONFIG_D9
RESETn
CONFIG_D10
CONFIG_D11
CONFIG_D12
PGM2
CONFIG_D13
CONFIG_D14
PGM1
CONFIG_D15
USB_MAX_D0
USB_MAX_D1
USB_MAX_D2
USB_MAX_D3
USB_MAX_D4
USB_MAX_D5
USB_MAX_D6
USB_MAX_D7
PGM0
USER_IMAGE
PGMSEL
FACTORY_IMAGE
JTAG_TCK
MAX_FPP_TDI
MAX_FPP_TDO
JTAG_TMS
DCLK
P4
R1
P5
T2
N5
R3
P6
R4
N6
T4
M6
R5
P7
T5
N7
R6
M7
T6
L7
R7
P8
T7
N8
R8
N9
T8
MAXII FPP CONFIGURATION
IOB4_2
IOB4_3
IOB4_4
IOB4_5
IOB4_6
IOB4_7
IOB4_8
IOB4_9
IOB4_10
IOB4_11
IOB4_12
IOB4_13
IOB4_14
IOB4_15
IOB4_16
IOB4_17
IOB4_18
IOB4_19
IOB4_20
IOB4_21
IOB4_22
IOB4_23
IOB4_24
IOB4_25
IOB4_26
IOB4_27
IOB4_28
IOB4_29
IOB4_30
IOB4_31
IOB4_32
IOB4_33
IOB4_34
IOB4_35
IOB4_36
IOB4_37
IOB4_38
IOB4_39
IOB4_40
IOB4_41
IOB4_42
IOB4_43
IOB4_44
IOB4_45
IOB4_46
IOB4_47
IOB4_48
IOB4_49
IOB4_50
IOB4_51
IOB4_52
IO/DEV_OE
IO/DEV_CLRn
T9
R9
P9
T10
L10
R10
M10
T11
N10
R11
P10
T12
M11
R12
N11
T13
P11
R13
M12
R14
N12
T15
P12
R16
P13
M8
M9
CONFIG_ERR
CONFIG_D1
CONFIG_D5
SPARE[7:0]
CONFIG_D0
F_AD[26:1]
CONFIG_D4
CONFIG_D7
F_WPn
F_D[15:0]
2p5V
CONF_DONE
CONFIG_D3
INIT_DONE
R123
10.0K
nCONFIG
CONFIG_D6
S5_RSTn
CONFIG_D2
F_CLK
F_ADVn
U19E
H8
H10
J7
J9
B
F_CEn
F_AD7
F_OEn
F_AD3
F_AD8
F_D8
F_AD5
F_AD18
F_AD4
F_D9
F_AD2
MSEL4
F_AD1
MSEL3
F_D0
F_AD21
F_D1
MSEL2
F_D2
MSEL1
F_D3
F_AD19
F_BSYn
F_AD6
F_D10
F_D4
2p5V
U19D
F_AD25
F_AD26
IOB3_29
IOB3_30
IOB3_31
IOB3_32
IOB3_33
IOB3_34
IOB3_35
IOB3_36
IOB3_37
IOB3_38
IOB3_39
IOB3_40
IOB3_41
IOB3_42
IOB3_43
IOB3_44
IOB3_45
IOB3_46
IOB3_47
IOB3_48
IOB3_49
IOB3_50
IOB3_51
IOB3_52
IOB3_53
IOB3_54
H13
H15
H14
G16
G12
G15
G11
F16
G13
F15
G14
E16
F11
E15
F12
D16
F13
D15
F14
D14
E12
C15
E13
C14
E14
D13
F_D11
F_D5
F_RSTn
F_D6
ENET_RSTn
F_AD24
F_D7
F_AD16
F_AD12
F_D12
F_AD11
F_WEn
F_AD23
F_AD10
F_AD15
F_AD17
SPARE4
F_AD13
F_D13
F_AD22
F_D14
F_AD20
F_AD14
SPARE5
SPARE0
SPARE6
F_AD9
F_D15
MSEL0
SPARE1
SPARE2
C13
B16
C12
A15
D12
B14
C11
B13
D11
A13
E11
B12
C10
A12
D10
B11
E10
A11
F10
B10
C9
A10
D9
B9
E9
A9
A8
IOB2_0
IOB2_1
IOB2_2
IOB2_3
IOB2_4
IOB2_5
IOB2_6
IOB2_7
IOB2_8
IOB2_9
IOB2_10
IOB2_11
IOB2_12
IOB2_13
IOB2_14
IOB2_15
IOB2_16
IOB2_17
IOB2_18
IOB2_19
IOB2_20
IOB2_21
IOB2_22
IOB2_23
IOB2_24
IOB2_25
IOB2_26
IOB2_27
IOB2_28
IOB2_29
IOB2_30
IOB2_31
IOB2_32
IOB2_33
IOB2_34
IOB2_35
IOB2_36
IOB2_37
IOB2_38
IOB2_39
IOB2_40
IOB2_41
IOB2_42
IOB2_43
IOB2_44
IOB2_45
IOB2_46
IOB2_47
IOB2_48
IOB2_49
IOB2_50
IOB2_51
IOB2_52
B8
E8
A7
D8
B7
C8
A6
F7
B6
E7
A5
D7
B5
C7
A4
E6
B4
D6
C4
C6
B3
C5
A2
D5
B1
D4
C1
H6
J6
P1
SPARE7
SPARE3
SCL_OSC
SDA_OSC
SCL_PM
SDA_PM
T3
L8
L9
T14
P16
J11
H11
C16
PR_DONE
PR_REQUEST
PR_READY
PR_ERROR
PM_SHARE_CLK
PM_CNTL0
PM_CNTL1
PM_RSTn
PM_ALERTB
PM_PWRGD
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
A14
F9
F8
A3
VCC_INT_0
VCC_INT_1
VCC_INT_2
VCC_INT_3
VCC_IO_3_0
VCC_IO_3_1
VCC_IO_3_2
VCC_IO_3_3
VCC_IO_4_0
VCC_IO_4_1
VCC_IO_4_2
VCC_IO_4_3
MAX_2_MAX_INITDONE
2p5V
J28
1K
S5_SMBCLK_TEMP
S5_SMBDATA_TEMP
D9
1
2
3
CONFIG_ERR
R125
160
FAN_CTRL
FAN_LED
OVERTEMPn
ALERTn
Red_LED
1x3Header
D10
FACTORY_IMAGE
2p5V
R127
160
Green_LED
A
PFL_STATUS
D11
USER_IMAGE
C126 C127 C128 C129
C130
0.01uF
C131
0.01uF
C132
0.01uF
C133
0.01uF
R128
GNO_IO_15
GND_IO_14
GND_IO_13
GND_IO_12
GND_IO_11
GND_IO_10
GND_IO_9
GND_IO_8
GND_IO_7
GND_IO_6
GND_IO_5
GND_IO_4
GND_IO_3
GND_IO_2
GND_IO_1
GND_IO_0
VCC_IO_2_0
VCC_IO_2_1
VCC_IO_2_2
VCC_IO_2_3
USB_MAX_RDn
USB_MAX_WR
USB_MAX_TXEn
USB_MAX_RXFn
USB_MAX_PWR_ENn
EPM2210_256FBGA
1
2
3
GND_INT0
GND_INT1
GND_INT2
GND_INT3
VCC_IO_1_0
VCC_IO_1_1
VCC_IO_1_2
VCC_IO_1_3
USB_MAX_D[7..0]
2p5V
R126
160
MAXll_BEN0
MAXll_BEN1
MAXll_BEN2
MAXll_BEN3
MAXll_CLK
MAXll_CSN
MAXll_OEN
MAXll_WEN
Green_LED
0.1uF 0.1uF 0.1uF 0.1uF
H7
H9
J8
J10
T16
T1
R15
R2
K10
K9
K8
K7
G10
G9
G8
G7
B15
B2
A16
A1
4
14,28
D
14,28
F_CEn
F_OEn
F_WEn
F_RSTn
F_BSYn
F_CEn
F_OEn
F_WEn
F_RSTn
F_BSYn
14,28
14,28
14,28
14,28
14,28
F_ADVn
F_WPn
F_CLK
F_ADVn
F_WPn
F_CLK
14,28
14,28
14,28
PWR_GOOD
JTAG_TCK
MAX_FPP_TDI
JTAG_TMS
MAX_FPP_TDO
PWR_GOOD
3,4,5,6,7
JTAG_TCK
12,26
MAX_FPP_TDI
26
JTAG_TMS
12,26
MAX_FPP_TDO
26
CONFIG_D[15:0]
CONFIG_D[15:0]
26
INIT_DONE
nSTATUS
CONF_DONE
RESETn
nCONFIG
DCLK
ENET_RSTn
S5_RSTn
INIT_DONE
12,26
nSTATUS
12,26
CONF_DONE
12,26
RESETn
16
nCONFIG
26
DCLK
26
ENET_RSTn
15,28
S5_RSTn
28
PGM0
PGM1
PGM2
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
PGM0
28
PGM1
28
PGM2
28
MSEL0
26
MSEL1
26
MSEL2
26
MSEL3
26
MSEL4
26
50MHz_MAXll_CLK
50MHz_MAXll_CLK
SCL_OSC
SDA_OSC
C
23
SCL_OSC
24,25
SDA_OSC
24,25
SCL_PM
9,10,29
SDA_PM
9,10,29
SCL_PM
SDA_PM
B
USB_MAX_D[7..0]
PM_CNTL0
PM_CNTL1
PM_RSTn
PM_SHARE_CLK
PM_ALERTB
PM_PWRGD
12
USB_MAX_RDn
12
USB_MAX_WR
12
USB_MAX_TXEn 12
USB_MAX_RXFn
12
USB_MAX_PWR_ENn
12
MAX_2_MAX_INITDONE
S5_SMBCLK_TEMP
12
11,29
S5_SMBDATA_TEMP 11,29
FAN_CTRL
11,29
FAN_LED
11,29
OVERTEMPn
11,29
ALERTn
11,29
PFL_STATUS
12
MAXll_BEN0
28
MAXll_BEN1
28
MAXll_BEN2
28
MAXll_BEN3
28
MAXll_CLK
28
MAXll_CSN
28
MAXll_OEN
28
MAXll_WEN
28
3
2
PM_CNTL0
9,10,29
PM_CNTL1
9,10,29
PM_RSTn
9,10,29
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
PM_SHARE_CLK
9,10,29
PM_ALERTB
9,10,29
PM_PWRGD
9,10,29
PM1_FAULTB00
9,29
PM1_FAULTB01
9,29
PM1_FAULTB10
9,29
PM1_FAULTB11
9,29
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
PR_DONE
PR_REQUEST
PR_READY
PR_ERROR
10,29
10,29
10,29
10,29
PR_DONE
26
PR_REQUEST
26
PR_READY
26
PR_ERROR
26
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
F_AD[26:1]
EPM2210_256FBGA
EPM2210_256FBGA
PGMSEL
28
F_D[15:0]
2p5V
C
CLK2 / IOB3_0
CLK3 / IOB3_1
IOB3_2
IOB3_3
IOB3_4
IOB3_5
IOB3_6
IOB3_7
IOB3_8
IOB3_9
IOB3_10
IOB3_11
IOB3_12
IOB3_13
IOB3_14
IOB3_15
IOB3_16
IOB3_17
IOB3_18
IOB3_19
IOB3_20
IOB3_21
IOB3_22
IOB3_23
IOB3_24
IOB3_25
IOB3_26
IOB3_27
IOB3_28
R293
10K
SPARE[7:0]
PWR_GOOD
EPM2210_256FBGA
J12
H12
P14
N13
P15
M14
N14
M13
N15
L14
N16
L13
M15
L12
M16
L11
L15
K14
L16
K13
K15
K12
K16
K11
J15
J14
J16
J13
H16
2p5V
nSTATUS
EPM2210_256FBGA
U19C
1
U19B
CONFIG_D8
P3
L6
M5
N4
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
13
of
36
D
5
4
3
2
1
FLASH MEMORY
XFP_1p8V
D
D
C137 C138 C139
0.1uF 0.1uF 0.1uF
2p5V
U21
F_AD[26:1]
C
10.0K
R135
10.0K
R134
10.0K
R133
10.0K
R132
R131
DNI
2p5V
F_AD1
F_AD2
F_AD3
F_AD4
F_AD5
F_AD6
F_AD7
F_AD8
F_AD9
F_AD10
F_AD11
F_AD12
F_AD13
F_AD14
F_AD15
F_AD16
F_AD17
F_AD18
F_AD19
F_AD20
F_AD21
F_AD22
F_AD23
F_AD24
F_AD25
F_AD26
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
E6
F_CLK
D4
B4
F8
G8
F6
C6
F_RSTn
F_CEn
F_OEn
F_WEn
F_ADVn
F_WPn
B
PC28FxxxP30B85
FLASH
VPP
A1
A2
VCC1
A3
VCC2
A4
A5
VCCQ1
A6
VCCQ2
A7
VCCQ3
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
A23
D13
A24
D14
A25(512M/1GIG)/NC D15
A26(1GIG)/NC
WAIT
CLK
GND1
GND2
GND3
GND4
RESET#
CE#
OE#
WE#
ADV#
WP#
RFU0
RFU1
RFU2
RFU3
A4
C140 C141 C142 C143 C144
A6
H3
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
D5
D6
G4
F_D[15:0]
F2
E2
G3
E4
E5
G5
G6
H7
F_D0
F_D1
F_D2
F_D3
F_D4
F_D5
F_D6
F_D7
E1
E3
F3
F4
F5
H5
G7
E7
F_D8
F_D9
F_D10
F_D11
F_D12
F_D13
F_D14
F_D15
F7
C
2p5V
R136
10.0K
F_BSYn
B2
H2
H4
H6
H1
G2
F1
E8
B
F_D[15:0]
F_D[15:0]
F_AD[26:1]
R137
10.0K
R138
10.0K
13,28
F_AD[26:1]
PC28F00AP30BF
13,28
F_BSYn
F_BSYn
F_CLK
F_CLK
13,28
F_RSTn
F_CEn
F_OEn
F_WEn
F_ADVn
F_WPn
F_RSTn
F_CEn
F_OEn
F_WEn
F_ADVn
F_WPn
13,28
13,28
13,28
13,28
13,28
13,28
13,28
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
14
of
36
D
5
4
3
2
2p5V
1
10/100/1000 Ethernet PHY
U22A
4.7K
4.7K
4.7K
4.7K
MDIO
MDC
ENET_INTn
ENET_RSTn
ENET_RSTn
D
J29
C147
0.01uF
C146
0.01uF
C148
0.01uF
R143
R146
R144
R147
R145
R148
R149
R150
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
VCC
TD0_P
TD0_N
TD1_P
TD1_N
TD2_P
TD2_N
GND_TAB
GND_TAB
TD3_P
TD3_N
1
2
3
6
4
5
7
8
10
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
29
31
33
34
39
41
42
43
MDIO
MDC
ENET_INTn
24
25
23
37
38
HFJ11-1G02E
ENET_RSET
R154
10.0K
C
X2
1
2
3
Ethernet_1p2V
C150
C151
C152
C153
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
OUT
NC2
VCC
25MHz
4
5
6
ENET_XTAL_25MHZ
3p3V
R158
4.99K
R159
4.7K
22
55
54
53
47
49
44
50
46
MDIO
MDC
INT_N
HSDAC_P
HSDAC_N
RXCLK
RX_DV
RX_ER
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
COL
RSET
SEL_FREQ
125CLK
XTAL1
XTAL2
VSSC
TRST_N
TCK
TDI
TDO
TMS
JTAG
C149
EN
NC1
GND
30
56
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TEST
12
11
3p3V
GND
ENET_LED_LINK1000
ENET_LED_LINK10
ENET_LED_RX
9
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
MGMT
0.01uF
GTX_CLK
TX_CLK
TX_EN
TX_ER
MDI INTERFACE
C145
2p5V
65
64
63
61
60
59
58
COMA
RESET_N
GMII/MII/TBI INTERFACE
R139
R141
R142
R140
27
28
SGMII INTERFACE
2p5V
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
8
4
9
7
GTXCLK
11
12
14
16
17
18
19
20
TXD0
TXD1
TXD2
TXD3
2
94
3
RXCLK
RXDV
95
92
93
91
90
89
87
86
RXD0
RXD1
RXD2
RXD3
TXEN
D
D12
Green_LED
ENET_LED_TX
ENET_LED_RX
C155
C156
C157
C158
C159
C160
C161
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
R152
160
D14
Green_LED
R153
ENET_LED_DUPLEX
160
84
83
D15
Green_LED
79
80
82
81
77
75
ENET_SGMII_TX_P
ENET_SGMII_TX_N
ENET_SGMII_RX_P
ENET_SGMII_RX_N
68
69
70
73
74
76
ENET_LED_TX
ENET_LED_RX
ENET_LED_DUPLEX
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
ENET_LED_LINK1000
R155
ENET_LED_LINK100
R156
160
D17
Green_LED
ENET_LED_LINK10
R157
ENET_SGMII_TX_P
ENET_SGMII_TX_N
ENET_SGMII_RX_P
ENET_SGMII_RX_N
ENET_RSTn
ENET_INTn
160
ENET_SGMII_TX_P
28
ENET_SGMII_TX_N
28
ENET_SGMII_RX_P
28
ENET_SGMII_RX_N
28
ENET_RSTn
ENET_INTn
2p5V
Ethernet_1p2V
13
51
97
NC1
NC2
72
66
52
VDDOH
VDDOH
VDDOH
5
21
88
96
VDDO
VDDO
VDDO
VDDO
26
48
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VDDOX
VDDOX
32
36
35
40
45
78
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
1
6
10
15
57
62
67
71
85
VSS
13,28
28
MDIO
MDC
28
28
RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK
RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK
28
28
28
28
28
28
GTXCLK
TXEN
TXD0
TXD1
TXD2
TXD3
GTXCLK
TXEN
TXD0
TXD1
TXD2
TXD3
28
28
28
28
28
28
MDIO
MDC
B
U22B
C
160
D16
Green_LED
Place near 88E1111 PHY
C154
160
D13
Green_LED
88E1111
2p5V
R151
2p5V
B
88E1111
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
15
of
36
D
5
4
3
2
1
BUTTONS, SWITCHES, LEDS, LCD DISPLAY
2p5V
D18
R161
USER_LED0
160
2p5V
Green_LED
D19
USER_LED1
R162
160
D
8
7
6
5
Green_LED
D20
R163
160
R164
160
RP1
10K
USER_LED3
1
2
3
4
Green_LED
D21
USER_DIP0
USER_DIP1
USER_DIP2
USER_DIP3
USER_DIP4
USER_DIP5
USER_DIP6
S5_Unlock
Green_LED
D22
USER_LED4
R165
160
R166
160
R167
160
R168
160
Green_LED
D23
USER_LED5
RP2
10K
1
2
3
4
USER_LED2
8
7
6
5
D
Green_LED
D24
1
2
3
4
5
6
7
8
USER_LED6
Green_LED
D25
C
USER_LED7
DIP_SW_8
SW4
2p5V
S1
1
2
S4
1
2
S5
1
2
S6
1
2
U24
B
1
14
3
12
5
10
7
Ain
Bin
Cin
Din
Ein
Fin
OSCin
C165
C166
0.1uF
0.1uF
5V
Aout
Bout
Cout
Dout
Eout
Fout
OSCout
15
2
13
4
11
6
9
USER_PB0
USER_PB1
USER_PB2
USER_PB3
RESETn
CPURSTn
LCD_WEn
LCD_DATA0
LCD_DATA2
LCD_DATA4
LCD_DATA6
1
3
5
7
9
11
13
Character LCD
J30
2
1
2 4
3
4 6
5
6 8
7
8 10
9
10 12
11
12 14
13
14
LCD_D_Cn
LCD_EN
LCD_DATA1
LCD_DATA3
LCD_DATA5
LCD_DATA7
HDR2X7
LCD DISPLAY HEADER
C167
0.001uf
MNT1
LCD MNT HOLE
MNT2
LCD MNT HOLE
1
1
1
MC14490
VDD
2
S3
VSS
1
16
R169
10K
R170
10K
R171
10K
R172
10K
R173
10K
R174
10K
1
2
S2
8
1
J31
USER_IO0
USER_IO1
USER_IO2
USER_IO3
1
3
5
7
1
3
5
7
2
4
6
8
C
USER_IO0
USER_IO1
USER_IO2
USER_IO3
16
15
14
13
12
11
10
9
Green_LED
2
4
6
8
USER_IO0
USER_IO1
USER_IO2
USER_IO3
30
30
30
30
USER_DIP0
USER_DIP1
USER_DIP2
USER_DIP3
USER_DIP4
USER_DIP5
USER_DIP6
S5_Unlock
USER_DIP0
USER_DIP1
USER_DIP2
USER_DIP3
USER_DIP4
USER_DIP5
USER_DIP6
S5_Unlock
30
30
30
30
30
30
30
12
USER_PB0
USER_PB1
USER_PB2
USER_PB3
RESETn
CPURSTn
USER_PB0
30
USER_PB1
30
USER_PB2
30
USER_PB3
30
RESETn
13
CPURSTn
30
USER_LED0
USER_LED1
USER_LED2
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7
USER_LED0
USER_LED1
USER_LED2
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7
LCD_D_Cn
LCD_EN
LCD_WEn
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
LCD_D_Cn
29
LCD_EN
29
LCD_WEn
29
LCD_DATA0
29
LCD_DATA1
29
LCD_DATA2
29
LCD_DATA3
29
LCD_DATA4
29
LCD_DATA5
29
LCD_DATA6
29
LCD_DATA7
29
B
30
30
30
30
30
30
30
30
2x4Header
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
16
of
36
D
5
4
3
2
1
FCI / Amphenol Backplane Interface
D
D
J32A
A1
B1
GXB_RXLn_19 C171 68nF
GXBRXLn_19
GXB_RXLp_19 C170 68nF
GXBRXLp_19
GXB_RXLn_21 C177 68nF
GXBRXLn_21
GXB_RXLp_21 C176 68nF
GXBRXLp_21
C1
D1
E1
F1
G1
H1
C
GXB_RXLn_20 C169 68nF
GXBRXLn_20
GXB_RXLp_20 C168 68nF
GXBRXLp_20
GXB_RXLn_22 C175 68nF
GXBRXLn_22
GXB_RXLp_22 C174 68nF
GXBRXLp_22
GXB_RXLn_23 C173 68nF
GXBRXLn_23
GXB_RXLp_23 C172 68nF
GXBRXLp_23
A2
B2
C2
D2
E2
F2
G2
H2
A3
B3
GXB_RXRn_23 C179 68nF
GXBRXRn_23
GXB_RXRp_23 C178 68nF
GXBRXRp_23
GXB_RXRn_18 C181 68nF
GXBRXRn_18
GXB_RXRp_18 C180 68nF
GXBRXRp_18
C3
D3
E3
F3
G3
H3
SIGA1
SIGB1
SIGC1
SIGD1
SIGE1
SIGF1
J32B
GND-B1
GND-C1
GND-D1
GND-E1
GND-F1
GND-G1
GND-H1
GND-I1
GB1
GC1
GD1
GE1
GF1
GG1
GH1
GI1
A4
B4
GXB_TXLn_23
GXB_TXLp_23
C4
D4
GXB_TXLn_21
GXB_TXLp_21
E4
F4
G4
H4
SIGG1
SIGH1
SIGA2
SIGB2
SIGC2
SIGD2
SIGE2
SIGF2
GND-A2
GND-B2
GND-C2
GND-D2
GND-E2
GND-F2
GND-G2
GND-H2
GA2
GB2
GC2
GD2
GE2
GF2
GG2
GH2
SIGG2
SIGH2
SIGA3
SIGB3
SIGC3
SIGD3
SIGE3
SIGF3
GND-B3
GND-C3
GND-D3
GND-E3
GND-F3
GND-G3
GND-H3
GND-I3
GB3
GC3
GD3
GE3
GF3
GG3
GH3
GI3
A5
B5
GXB_TXLn_22
GXB_TXLp_22
C5
D5
GXB_TXLn_20
GXB_TXLp_20
E5
F5
GXB_TXLn_19
GXB_TXLp_19
G5
H5
A6
B6
GXB_TXRn_23
GXB_TXRp_23
C6
D6
GXB_TXRn_18
GXB_TXRp_18
E6
F6
G6
H6
SIGG3
SIGH3
Amphenol_conn_C-950-400A-500
B
SIGA4
SIGB4
SIGC4
SIGD4
SIGE4
SIGF4
GND-A4
GND-B4
GND-C4
GND-D4
GND-E4
GND-F4
GND-G4
GND-H4
GA4
GB4
GC4
GD4
GE4
GF4
GG4
GH4
SIGG4
SIGH4
SIGA5
SIGB5
SIGC5
SIGD5
SIGE5
SIGF5
GND-B5
GND-C5
GND-D5
GND-E5
GND-F5
GND-G5
GND-H5
GND-I5
GB5
GC5
GD5
GE5
GF5
GG5
GH5
GI5
C
SIGG5
SIGH5
SIGA6
SIGB6
SIGC6
SIGD6
SIGE6
SIGF6
GND-A6
GND-B6
GND-C6
GND-D6
GND-E6
GND-F6
GND-G6
GND-H6
GA6
GB6
GC6
GD6
GE6
GF6
GG6
GH6
SIGG6
SIGH6
GXB_RXLp_[23:19]
GXB_RXLp_[23:19]
32
GXB_RXLn_[23:19]
GXB_RXLn_[23:19]
32
Amphenol_conn_C-950-400A-500
GXB_TXLp_[23:19]
GXB_TXLn_[23:19]
B
GXB_TXLp_[23:19]
32
GXB_TXLn_[23:19]
32
GXB_RXRp_18
GXB_RXRn_18
GXB_RXRp_23
GXB_RXRn_23
34
34
34
34
GXB_TXRp_18
GXB_TXRn_18
GXB_TXRp_23
GXB_TXRn_23
34
34
34
34
GXB_RXRp_18
GXB_RXRn_18
GXB_RXRp_23
GXB_RXRn_23
GXB_TXRp_18
GXB_TXRn_18
GXB_TXRp_23
GXB_TXRn_23
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
17
of
36
D
5
4
3
2
1
Tyco Backplane Interface
J33C
J33A
A1
GXB_RXLn_4
GXB_RXLp_4
D
GXB_RXLn_3
GXB_RXLp_3
GXB_RXRp_0
GXB_RXRn_0
C193
68nF
GXBRXLn_4
C192
68nF
C191
68nF
GXBRXLp_4
C190
68nF
C194
68nF
GXBRXLp_3
C195
68nF
GXBRXRn_0
A2
A3
A4
GXBRXLn_3
A5
A6
A7
GXBRXRp_0
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
C
A19
C1
GXB_RXLn_1 C187
68nF
A1-GND
A2
A3
GXBRXLn_1
C2
C3
GXB_RXLp_1 C186
68nF
A4-GND
GXBRXLp_1
C4
C5
C6
A5
A6
C7
A7-GND
C8
C9
A8
A9
A10-GND
A11
A12
A13-GND
A14
A15
A16-GND
A17
A18
A19-GND
REF_A1
REF_A2
REF_A3
REF_A4
REF_A5
REF_A6
REF_A7
REF_A8
REF_A9
REF_A10
REF_A11
REF_A12
REF_A13
REF_A14
REF_A15
REF_A16
REF_A17
REF_A18
REF_A19
REFA1
REFA2
REFA3
REFA4
REFA5
REFA6
REFA7
REFA8
REFA9
REFA10
REFA11
REFA12
REFA13
REFA14
REFA15
REFA16
REFA17
REFA18
REFA19
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
J33E
C1-GND
E1
C2
C3
E2
E3
C4-GND
E4
C5
C6
E5
E6
C7-GND
E7
C8
C9
C10-GND
C11
C12
C13-GND
C14
C15
C16-GND
C17
C18
C19-GND
REF_C1
REF_C2
REF_C3
REF_C4
REF_C5
REF_C6
REF_C7
REF_C8
REF_C9
REF_C10
REF_C11
REF_C12
REF_C13
REF_C14
REF_C15
REF_C16
REF_C17
REF_C18
REF_C19
E8
E9
REFC1
REFC2
REFC3
REFC4
REFC5
REFC6
REFC7
REFC8
REFC9
REFC10
REFC11
REFC12
REFC13
REFC14
REFC15
REFC16
REFC17
REFC18
REFC19
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E1-GND
B1
GXBRXLn_0
C183
68nF
C189
68nF
GXBRXLp_0
C188
68nF
GXB_RXRp_5 C184
68nF
GXBRXLp_2
GXB_RXRn_5 C185
68nF
GXBRXRn_5
GXB_RXLp_0
GXB_RXLn_2
GXB_RXLp_2
B2
B3
B4
GXBRXLn_2
B5
B6
B7
GXBRXRp_5
B8
B9
B10
B
B11
B12
B13
B16
B17
B18
3
GP1
2
1
B14
B15
B19
D1
B1-GND
D2
D3
B2
B3
D4
B4-GND
D5
D6
B5
B6
D7
B7-GND
B10-GND
B11
B12
B13-GND
B14
B15
B16-GND
B17
B18
B19-GND
REF_B1
REF_B2
REF_B3
REF_B4
REF_B5
REF_B6
REF_B7
REF_B8
REF_B9
REF_B10
REF_B11
REF_B12
REF_B13
REF_B14
REF_B15
REF_B16
REF_B17
REF_B18
REF_B19
D8
D9
REFB1
REFB2
REFB3
REFB4
REFB5
REFB6
REFB7
REFB8
REFB9
REFB10
REFB11
REFB12
REFB13
REFB14
REFB15
REFB16
REFB17
REFB18
REFB19
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
GP2
G7
E7-GND
G8
G9
E8
E9
E10-GND
E11
E12
E13-GND
E14
E15
E16-GND
E17
E18
E19-GND
REF_E1
REF_E2
REF_E3
REF_E4
REF_E5
REF_E6
REF_E7
REF_E8
REF_E9
REF_E10
REF_E11
REF_E12
REF_E13
REF_E14
REF_E15
REF_E16
REF_E17
REF_E18
REF_E19
REFE1
REFE2
REFE3
REFE4
REFE5
REFE6
REFE7
REFE8
REFE9
REFE10
REFE11
REFE12
REFE13
REFE14
REFE15
REFE16
REFE17
REFE18
REFE19
G10
GXB_TXLn_1
GXB_TXLp_1
G11
G12
G13
GXB_TXLn_4
GXB_TXLp_4
G14
G15
G16
GXB_TXRp_5
GXB_TXRn_5
G17
G18
G19
G2
G3
D
G4-GND
G5
G6
G7-GND
G8
G9
G10-GND
G11
G12
G13-GND
G14
G15
G16-GND
G17
G18
G19-GND
F1
F2
F3
D2
D3
F4
D4-GND
F5
F6
D5
D6
F7
D7-GND
F8
F9
D8
D9
D10-GND
D11
D12
D13-GND
D14
D15
D16-GND
D17
D18
D19-GND
REF_D1
REF_D2
REF_D3
REF_D4
REF_D5
REF_D6
REF_D7
REF_D8
REF_D9
REF_D10
REF_D11
REF_D12
REF_D13
REF_D14
REF_D15
REF_D16
REF_D17
REF_D18
REF_D19
REFD1
REFD2
REFD3
REFD4
REFD5
REFD6
REFD7
REFD8
REFD9
REFD10
REFD11
REFD12
REFD13
REFD14
REFD15
REFD16
REFD17
REFD18
REFD19
F10
GXB_TXLn_0
GXB_TXLp_0
F11
F12
F13
GXB_TXLn_3
GXB_TXLp_3
F14
F15
F16
GXB_TXRp_0
GXB_TXRn_0
F17
F18
F19
tyco_strada_2149323-1
REFG1
REFG2
REFG3
REFG4
REFG5
REFG6
REFG7
REFG8
REFG9
REFG10
REFG11
REFG12
REFG13
REFG14
REFG15
REFG16
REFG17
REFG18
REFG19
C
tyco_strada_2149323-1
J33F
D1-GND
REF_G1
REF_G2
REF_G3
REF_G4
REF_G5
REF_G6
REF_G7
REF_G8
REF_G9
REF_G10
REF_G11
REF_G12
REF_G13
REF_G14
REF_G15
REF_G16
REF_G17
REF_G18
REF_G19
J33H
H1
F1-GND
H2
H3
F2
F3
H4
F4-GND
H5
H6
F5
F6
H7
F7-GND
H8
H9
F8
F9
F10-GND
F11
F12
F13-GND
F14
F15
F16-GND
F17
F18
F19-GND
REF_F1
REF_F2
REF_F3
REF_F4
REF_F5
REF_F6
REF_F7
REF_F8
REF_F9
REF_F10
REF_F11
REF_F12
REF_F13
REF_F14
REF_F15
REF_F16
REF_F17
REF_F18
REF_F19
REFF1
REFF2
REFF3
REFF4
REFF5
REFF6
REFF7
REFF8
REFF9
REFF10
REFF11
REFF12
REFF13
REFF14
REFF15
REFF16
REFF17
REFF18
REFF19
H10
GXB_TXLn_2
GXB_TXLp_2
H11
H12
H13
H14
H15
H16
H17
H18
H19
H1-GND
H2
H3
H4-GND
H5
H6
H7-GND
H8
H9
H10-GND
H11
H12
H13-GND
H14
H15
H16-GND
H17
H18
H19-GND
tyco_strada_2149323-1
REF_H1
REF_H2
REF_H3
REF_H4
REF_H5
REF_H6
REF_H7
REF_H8
REF_H9
REF_H10
REF_H11
REF_H12
REF_H13
REF_H14
REF_H15
REF_H16
REF_H17
REF_H18
REF_H19
REF_I2
REF_I3
REF_I5
REF_I6
REF_I8
REF_I9
REF_I11
REF_I12
REF_I14
REF_I15
REF_I17
REF_I18
REFH1
REFH2
REFH3
REFH4
REFH5
REFH6
REFH7
REFH8
REFH9
REFH10
REFH11
REFH12
REFH13
REFH14
REFH15
REFH16
REFH17
REFH18
REFH19
B
REFI2
REFI3
REFI5
REFI6
REFI8
REFI9
REFI11
REFI12
REFI14
REFI15
REFI17
REFI18
tyco_strada_2149323-1
3
2
tyco_strada_2149323-1
1
G5
G6
E5
E6
G1-GND
tyco_strada_2149323-1
J33D
B8
B9
G4
E4-GND
tyco_strada_2149323-1
J33B
C182
68nF
G2
G3
E2
E3
tyco_strada_2149323-1
GXB_RXLn_0
J33G
G1
GXB_RXRp_0
GXB_RXRn_0
GXB_RXRp_5
GXB_RXRn_5
A
GXB_TXRp_0
GXB_TXRn_0
GXB_TXRp_5
GXB_TXRn_5
GXB_RXRp_0
GXB_RXRn_0
GXB_RXRp_5
GXB_RXRn_5
GXB_TXRp_0
GXB_TXRn_0
GXB_TXRp_5
GXB_TXRn_5
33
33
33
33
GXB_RXLp_[4:0]
GXB_RXLp_[4:0]
31
GXB_RXLn_[4:0]
GXB_RXLn_[4:0]
31
GXB_TXLp_[4:0]
33
33
33
33
GXB_TXLn_[4:0]
GXB_TXLp_[4:0]
31
GXB_TXLn_[4:0]
31
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
18
of
36
D
5
4
3
2
1
Molex Backplane Interface
J34A
A2
B2
D
A4
B4
A6
B6
A8
B8
A10
B10
B1
C1
B3
C3
B5
C5
B7
C7
C
GXB_TXLn_8
GXB_TXLp_8
B9
C9
A2-TX
B2-TX
A4-TX
B4-TX
J34C
GND-A1
GND-A3
GND-A5
GND-A7
GND-A9
A1
A3
A5
A7
A9
A6-TX
B6-TX
G2
H2
GXB_RXLn_8
C201 68nF
GXBRXLn_8
GXB_RXLp_8
C198 68nF
GXBRXLp_8
G4
H4
G6
H6
A8-TX
B8-TX
G8
H8
A10-TX
B10-TX
B1-TX
C1-TX
B3-TX
C3-TX
GXB_TXLp_6
GXB_TXLn_6
GND-C2
GND-C4
GND-C6
GND-C8
GND-C10
C2
C4
C6
C8
C10
G10
H10
H1
J1
GXB_RXLn_10
C205 68nF
GXBRXLn_10
GXB_RXLp_10
C204 68nF
GXBRXLp_10
H3
J3
B5-TX
C5-TX
H5
J5
B7-TX
C7-TX
H7
J7
B9-TX
C9-TX
GXB_TXLp_7
GXB_TXLn_7
H9
J9
G2-RX
H2-RX
G4-RX
H4-RX
GND-G1
GND-D3
GND-G5
GND-G7
GND-G9
G1
G3
G5
G7
G9
D
G6-RX
H6-RX
G8-RX
H8-RX
G10-RX
H10-RX
H1-RX
J1-RX
H3-RX
J3-RX
GND-J2
GND-J4
GND-J6
GND-J8
GND-J10
J2
J4
J6
J8
J10
H5-RX
J5-RX
C
H7-RX
J7-RX
H9-RX
J9-RX
Molex-conn_76160-5020
Molex-conn_76160-5020
J34B
J34D
D2
E2
D4
E4
D6
E6
D8
E8
GXB_TXLp_9
GXB_TXLn_9
B
D10
E10
E1
F1
E3
F3
E5
F5
E7
F7
GXB_TXLn_10
GXB_TXLp_10
E9
F9
D2-TX
E2-TX
D4-TX
E4-TX
GND-D1
GND-D3
GND-D5
GND-D7
GND-D9
D1
D3
D5
D7
D9
D6-TX
E6-TX
GXB_RXLp_7
C197 68nF
GXBRXLp_7
GXB_RXLn_7
C200 68nF
GXBRXLn_7
GXB_RXLp_6
C196 68nF
GXBRXLp_6
GXB_RXLn_6
C199 68nF
GXBRXLn_6
K2
L2
K4
L4
K6
L6
D8-TX
E8-TX
K8
L8
D10-TX
E10-TX
K10
L10
E1-TX
F1-TX
E3-TX
F3-TX
GND-F2
GND-F4
GND-F6
GND-F8
GND-F10
F2
F4
F6
F8
F10
E5-TX
F5-TX
L1
M1
GXB_RXLp_9
C202 68nF
GXBRXLp_9
GXB_RXLn_9
C203 68nF
GXBRXLn_9
L3
M3
L5
M5
E7-TX
F7-TX
L7
M7
E9-TX
F9-TX
L9
M9
K2-RX
L2-RX
K4-RX
L4-RX
GND-K1
GND-K3
GND-K5
GND-K7
GND-K9
K1
K3
K5
K7
K9
K6-RX
L6-RX
K8-RX
L8-RX
B
K10-RX
L10-RX
L1-RX
M1-RX
L3-RX
M3-RX
GND-M2
GND-M4
GND-M6
GND-M8
GND-M10
M2
M4
M6
M8
M10
L5-RX
M5-RX
L7-RX
M7-RX
L9-RX
M9-RX
MNT-1
MNT-2
Z0
Z1
GXB_RXLp_[10:6]
GXB_RXLp_[10:6]
31
GXB_RXLn_[10:6]
GXB_RXLn_[10:6]
31
GXB_TXLp_[10:6]
Molex-conn_76160-5020
Molex-conn_76160-5020
GXB_TXLn_[10:6]
GXB_TXLp_[10:6]
31
GXB_TXLn_[10:6]
31
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
19
of
36
D
5
4
3
2
1
XFP Interface
U25
To Bezel
3p3V
D
D
XFP_1p8V
XFP MSA 2.1
5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XFP_MOD_DESEL
XFP_T_INTERRUPT
XFP_TX_DIS
XFP_1p8V
C212
C213
C214
C215
100uF
100uF
100uF
2.2uF
3p3V
XFP_T_SCL
XFP_T_SDA
XFP_T_MOD_ABS
Place near XFP
31
32
33
34
35
36
37
C220
C218
C
100uF
2.2uF
C219
1uF
MTG1
MTG2
GND
GND
VEE5
TDp
MOD_DESEL
TDn
INTERRUPT
GND
TX_DIS
GND
VCC5
REFCLKn
GND
REFCLKp
VCC3
GND
VCC3
VCC2
SCL
P_DOWN/RST
SDA
VCC2
MOD_ABS
GND
MOD_NR
RDp
RX_LOS
RDn
GND
GND
C_GND1
C_GND2
C_GND3
C_GND4
C_GND5
C_GND6
C_GND7
5V
C_GND15
C_GND13
C_GND12
C_GND11
C_GND10
C_GND9
C_GND8
45
46
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GXB_TXLp_5
GXB_TXLn_5
REFCLKXFPp
C210 .068uF
REFCLK_XFPn
REFCLKXFPn
C211 .068uF
REFCLK_XFPp
XFP_PDOWN_RST
GXB_RXLp_5
GXB_RXLn_5
44
43
42
41
40
39
38
C
XFP_CON_CAGE
C221
C222
100uF
2.2uF
2p5V
XFP CAGE1
2p5V
3p3V
XFP_PDOWN_RST
XFP_TX_DIS
R176
R177
DNI
DNI
XFP_MOD_DESEL
R180
10.0K
3p3V
DNI
DNI
R178
R181
U26
7
8
1
2
XFP_T_SCL
XFP_T_SDA
B
VCC
VL
TRI_STATE
VCCIO1
VCCIO2
GND
VL_IO1
VL_IO2
3
6
DNI
DNI
R179
R182
5
4
XFP MODULE1
GXB_RXLp_5
GXB_RXLn_5
GXB_TXLp_5
GXB_TXLn_5
XFP_SCL
XFP_SDA
GXB_RXLp_5
GXB_RXLn_5
GXB_TXLp_5
GXB_TXLn_5
31
31
31
31
B
MAX3373
2p5V
REFCLK_XFPp
REFCLK_XFPn
REFCLK_XFPp
REFCLK_XFPn
24
24
3p3V
3p3V
DNI
DNI
R183
R185
U27
7
8
1
2
XFP_T_MOD_ABS
XFP_T_INTERRUPT
VCC
VL
TRI_STATE
VCCIO1
VCCIO2
GND
VL_IO1
VL_IO2
3
6
5
4
DNI
DNI
R184
R186
XFP_PDOWN_RST
XFP_MOD_DESEL
XFP_SCL
XFP_SDA
XFP_PDOWN_RST
XFP_MOD_DESEL
XFP_SCL
27
XFP_SDA
27
XFP_MOD_ABS
XFP_INTERRUPT
XFP_TX_DIS
XFP_INTERRUPT
XFP_MOD_ABS
MAX3373
27
27
XFP_TX_DIS
27
XFP_INTERRUPT
27
XFP_MOD_ABS
27
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
20
of
36
D
5
4
3
2
1
SMAs / SFP+ Interface
1RXLp_11
SFPA_VCCT
SFPA_VCCT
C224
1.0uH
J38 1RXLn_11
SFPA_VCCR
C229
C230
0.1uF
10uF
1RXLp_12
2p5V
68nF GXB_RXLn_11
C228
GXB_TXLn_11
68nF GXB_RXLp_12
C231
GXB_TXLp_12
1
J39
GXB_RXRp_12
External Clock channel
RXRn_12
C232 68nF
GXB_RXRn_12
2
3
4
5
J42 1
RX12 / TX12 - LEFT
2
3
4
5
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
5
4
3
2
R192
R193
R194
R195
R196
R197
R198
1
J41
5
4
3
2
J40
SFPA_MOD2_SDA
SFPA_MOD1_SCL
SFPA_MOD0_PRSNTn
SFPA_RATESEL1
SFPA_RATESEL0
SFPA_TXFAULT
SFPA_LOS
J45 1RXLn_12
68nF GXB_RXLn_12
C234
GXB_TXLn_12
68nF GXB_RXLp_13
C235
GXB_TXLp_13
1
J46
SFP+ Interface
SFPA_VCCT
SFPA_VCCR
C227 68nF
5
4
3
2
L11
RXRp_12
D
SFPA_VCCR
10uF
1
J37
5
4
3
2
0.1uF
1
J36
RX11 / TX11 - LEFT
C226
0.1uF
D
GXB_TXLp_11
5
4
3
2
C225
GXB_RXLp_11
2
3
4
5
1.0uH
68nF
C223
5
4
3
2
L10
J35
2
3
4
5
3p3V
1RXLp_13
J47
1
J48
21
22
23
24
25
26
27
28
29
30
31
VEER
VEER
VEER
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
MH1
MH2
2
3
4
5
2
3
4
5
5
4
3
2
1
17
20
1RXLp_14
10
11
14
32
33
34
35
36
37
38
39
40
41
42
J54
68nF GXB_RXLn_13
C239
GXB_TXLn_13
68nF GXB_RXLp_14
C240
GXB_TXLp_14
1
J53
1
J55
2
3
4
5
MOD_ABS
SCL
SDA
C
J52 1RXLn_13
RX14 / TX14 - LEFT
B1
2
3
4
5
6
5
4
VEET
VEET
VEET
RX13 / TX13 - LEFT
J56 1RXLn_14
68nF GXB_RXLn_14
C241
GXB_TXLn_14
1J57
1RXLp_15
68nF GXB_RXLp_15
C242
GXB_TXLp_15
1
J59
J58
GXB_RXRp_12
GXB_RXRn_12
GXB_RXRp_12
GXB_RXRn_12
34
34
GXB_RXLp_[17:11]
GXB_RXLp_[17:11]
31,32
GXB_RXLn_[17:11]
GXB_RXLn_[17:11]
31,32
2
3
4
5
SFPA_MOD0_PRSNTn
SFPA_MOD1_SCL
SFPA_MOD2_SDA
TX_DISABLE
RS0
RS1
SFPA_LOS
SFPA_TXFAULT
GXB_TXLp_[17:11]
GXB_TXLp_[17:11]
31,32
2
3
4
5
3
7
9
RX_LOS
TX_FAULT
8
2
GXB_TXLp_18
GXB_TXLn_18
5
4
3
2
SFPA_TXDISABLE
SFPA_RATESEL0
SFPA_RATESEL1
RD_P
RD_N
18
19
5
4
3
2
13
12
TD_P
TD_N
GXB_TXLn_[17:11]
GXB_TXLn_[17:11]
31,32
SFP+_CAGE
5
4
3
2
C
GXB_RXLp_18
GXB_RXLn_18
VCCT
VCCR
5
4
3
2
J51
16
15
RX15 / TX15 - LEFT
5
4
3
2
SFP+_AND_CAGE
B
B
J60 1RXLn_15
68nF GXB_RXLn_15
C243
GXB_TXLn_15
1J61
1RXLp_16
68nF GXB_RXLp_16
C244
GXB_TXLp_16
1
J63
5
4
3
2
NOTE 2: Bypass Capacitors should be placed as close to the 20-pin connector as
possible
2
3
4
5
5
4
3
2
RX16 / TX16 - LEFT
NOTE 3: Assuming that the Stratix V GX board shares a common 3.3 volt power plane
that the open drain IO pins can be pulled-up on. This assumption is made to simplify
such that the Tx_Fault and Rx_LOS signals do not need to be pulled-up by the
Protocal IC (Stratix IV GX) as specified in the MultiSource Agreement (MSA).
J64 1RXLn_16
68nF
C245
GXB_RXLn_16
GXB_TXLn_16
1J65
GXB_RXLp_18
GXB_RXLn_18
GXB_TXLp_18
GXB_TXLn_18
SFPA_TXDISABLE
1RXLp_17
GXB_TXLp_17
SFPA_RATESEL0
SFPA_RATESEL1
30
30
30
1
J67
2
3
4
5
68nF GXB_RXLp_17
C246
5
4
3
2
J66
32
32
32
32
SFPA_TXDISABLE
SFPA_RATESEL0
SFPA_RATESEL1
NOTE 4: Assuming that the 100-ohm termination on the Stratix V GX device will be
implemented via the on-chip termination circuit.
NOTE 5: Going to use the SPLC-20 SFP Optical SONET OC-48 transceiver, but not
limited to this. Any MSA SFP complient transceiver should be able to be plugged in.
SFPA_MOD0_PRSNTn
30
SFPA_MOD1_SCL
30
SFPA_MOD2_SDA
30
SFPA_TXFAULT
30
SFPA_LOS
30
GXB_RXLp_18
GXB_RXLn_18
GXB_TXLp_18
GXB_TXLn_18
2
3
4
5
J62
NOTE 1: 1uH ferrite bead should provide a real impedance of 220-ohms at 100MHz
SFPA_MOD0_PRSNTn
SFPA_MOD1_SCL
SFPA_MOD2_SDA
SFPA_TXFAULT
SFPA_LOS
2
3
4
5
5
4
3
2
RX17 / TX17 - LEFT
A
J68 1RXLn_17
68nF GXB_RXLn_17
C247
GXB_TXLn_17
A
1J69
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
21
of
36
D
5
4
3
2
1
GLOBAL CLOCKS
U29Q
D
50MHz_S5GX_CLK
AJ26
AK26
AJ27
AK27
AR20
AT20
AN21
AP21
S5GX_CLK11p
S5GX_CLK11n
AJ19
AK18
place termination at S5GX
AL19
AL18
AV7
AW7
C
5
4
3
2
R199
49.9
J70
AN7
AN8
1
R200
DNI
J71
S5GX_CLK10p
S5GX_CLK10n
AV8
AW8
1
5
4
3
2
AR9
AT9
FPLL_BL_CLKOUTp / IO3B-27
FPLL_BL_CLKOUTn / IO3B-28
CLK1p / IO3B-21
CLK1n / IO3B-22
AG29
AH28
D
CLK2p / IO3B-23
CLK2n / IO3B-24
FPLL_BL_FB/CLKOUTp / IO3B-29
FPLL_BL_FB/CLKOUTn / IO3B-30
AG28
AH27
CLK3p / IO3B-25
CLK3n / IO3B-26
CLK4p / IO3D-21
CLK4n / IO3D-22
CLK5p / IO3D-23
CLK5n / IO3D-24
2
3
4
5
AD27
AE27
Bank 3
CLK0p / IO3B-19
CLK0n / IO3B-20
Bank 4
CLK6p / IO4D-17
CLK6n / IO4D-18
FPLL_BC_CLKOUTp / IO4D-21
FPLL_BC_CLKOUTn / IO4D-22
CLK7p / IO4D-19
CLK7n / IO4D-20
FPLL_BC_FB/CLKOUTp / IO4D-23
FPLL_BC_FB/CLKOUTn / IO4D-24
CLK8p / IO4A-13
CLK8n / IO4A-14
CLK9p / IO4A-15
CLK9n / IO4A-16
FPLL_BR_CLKOUTp / IO4A-21
FPLL_BR_CLKOUTn / IO4A-22
CLK10p / IO4A-17
CLK10n / IO4A-18
FPLL_BR_FB/CLKOUTp / IO4A-23
FPLL_BR_FB/CLKOUTn / IO4A-24
AE17
AE18
SMA_CLKOUTp
SMA_CLKOUTn
AF19
AG20
1
J72
1
J73
2
3
4
5
AB28
AC28
CLOCKS / PLLs
AU8
AU9
C
AR8
AT8
CLK11p / IO4A-19
CLK11n / IO4A-20
R201
49.9
A6
A7
C7
B7
H8
G8
50MHz_CLK12p
J10
H10
F17
E17
B
E20
E19
50MHz_CLK16p
J23
H23
K22
J21
C32
C31
B31
A31
C30
C29
B29
A29
A
Bank 7
CLK12p / IO7A-14
CLK12n / IO7A-15
FPLL_TR_CLKOUTp / IO7A-22
FPLL_TR_CLKOUTn / IO7A-23
CLK13p / IO7A-16
CLK13n / IO7A-17
FPLL_TR_FB/CLKOUTp / IO7A-24
FPLL_TR_FB/CLKOUTn / IO7A-25
CLK14p / IO7A-18
CLK14n / IO7A-19
FPLL_TC_CLKOUTp / IO7D-45
FPLL_TC_CLKOUTn / IO7D-46
CLK15p / IO7A-20
CLK15n / IO7A-21
FPLL_TC_FB/CLKOUTp / IO7D-47
FPLL_TC_FB/CLKOUTn / IO7D-48
CLK18p / IO7D-41
CLK18n / IO7D-42
H7
G7
G6
F6
G20
F20
G18
F18
B
CLK19p / IO7D-43
CLK19n / IO7D-44
Bank 8
CLK16p / IO8D-45
CLK16n / IO8D-46
FPLL_TL_CLKOUTp / IO8A-33
FPLL_TL_CLKOUTn / IO8A-34
CLK17p / IO8D-47
CLK17n / IO8D-48
FPLL_TL_FB/CLKOUTp / IO8A-35
FPLL_TL_FB/CLKOUTn / IO8A-36
CLK20p / IO8A-25
CLK20n / IO8A-26
50MHz_CLK12p
50MHz_CLK16p
H31
G31
F30
E30
50MHz_CLK12p
50MHz_CLK16p
50MHz_S5GX_CLK
50MHz_S5GX_CLK
S5GX_CLK11p
S5GX_CLK11n
S5GX_CLK11p
S5GX_CLK11n
23
23
23
23
23
CLK21p / IO8A-27
CLK21n / IO8A-28
CLK22p / IO8A-29
CLK22n / IO8A-30
CLK23p / IO8A-31
CLK23n / IO8A-32
A
5SGXEA7N2F40
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
22
of
36
D
5
4
3
2
1
Spread Spectrum / 50MHz Clocks
3p3V
D
1
D
3p3V
C248
FB2
120ohm, 800mA
2
8
7
6
5
RP3
10K
3p3V
C249
place termination at S5GX
S5GX_CLK11p
1
2
3
4
R205
1K
6
9
R208
475
4
5
12
16
S0
S1
SS0
SS1
CLK1P
CLK1N
OE
IREF
X1/ICLK
X2
ICS557-03
ABM10-25MHz
CLK0P
CLK0N
R206
100
X3
15
14
R207
100
S5GX_CLK11n
1
11
10
J78
C
trigger
R209
49.9
R210 R211
49.9 150
0.2" Max
1
Route as matched pair
2
3
4
5
1
2
3
8
VDDODA
VDDXD
S0
S1
SS0
SS1
GNDODA
GNDXD
1
2
3
4
0.5" Max
R212
150
13
7
OPEN
U30
TDA04H0SB1
C
C250
0.01uF 0.1uF
SW5
8
7
6
5
0.01uF
0.2" Max
3
C252
2
4
C251
16pF
16pF
B
B
3p3V
FB3
2
1
C254
0.1uF U31
0.1uF
0.1uF 2
OUT
GND
OE
3
3
CLK
GND
C255
VCC
1
CTS_CB3LV
3p3V
VDDO
Y2
4
1
2
C253
VDD
120ohm, 800mA
ICS8304
R215
1K
Q3
Q2
Q1
Q0
8
7
6
5
2
50MHz_CLK12p
50MHz_CLK16p
120ohm, 800mA
50MHz_CLK12p
50MHz_CLK16p
50MHz_MAXll_CLK
50MHz_S5GX_CLK
R213
R214
R294
R295
33
33
33
33
50MHz_MAXll_CLK
50MHz_S5GX_CLK
50MHz_CLK12p
50MHz_CLK16p
22
22
50MHz_MAXll_CLK
50MHz_S5GX_CLK
S5GX_CLK11p
S5GX_CLK11n
S5GX_CLK11p
S5GX_CLK11n
13
22
22
22
4
1
2p5V
FB4
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
23
of
36
D
5
4
3
2
1
XCVR Clocks - Left Blocks
2p5V
R216
10K
1
SMA1_CLKp
External Clock Input
1
8
1
Gn
GL
28
21
SMA1_CLKn
SEL
PDn
5
4
3
2
49.9 R218
J80
2p5V
Y3
1
2
3
Silicon Labs Oscillator
factory program
@ 644.53125MHz
ADDR - 66h
C
C256
0.1uF
NC
OE
GND
7
VCC
nOUT
OUT
SDA
SCL
A2_CLKp
A2_CLKn
Q5
nQ5
NC
3
4
REFCLK_B0L0p
REFCLK_B0L0n
10
11
REFCLK_B1L2p
REFCLK_B1L2n
12
13
REFCLK_B2L4p
REFCLK_B2L4n
19
18
REFCLK_B3L6p
REFCLK_B3L6n
24
23
REFCLK_XFPp
REFCLK_XFPn
26
25
Q6
nQ6
22
1
C257
J81
0.1uf
29
GND
R223
DNI
IDT5T9306
SCL_OSC
Si570
Q4
nQ4
R222
100
6
5
4
8
Q2
nQ2
A1_CLKp
A1_CLKn
16
15
R221
10K
Q1
nQ1
Q3
nQ3
6
7
2p5V
D
2
5
9
14
17
20
27
U32
2
3
4
5
5
4
3
2
49.9 R217
J79
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
D
C
R224
DNI
SDA_OSC
2p5V
R225
1K
R226
1K
R227
1K
R228
1K
CLKSEL_BR_even
CLKSEL_BR_odd
SCL_OSC
SDA_OSC
8
7
6
5
OPEN
1
2
3
4
CLKSEL_BR_even
CLKSEL_BR_odd
SW6
R229
10K
1
28
21
SMA2_CLKn
2p5V
49.9 R231
J84
6
7
2p5V
16
15
Silicon Labs Oscillator
factory program
@ 706.25MHz
ADDR - 77h
A
R232
10K
C259
0.1uF
Y4
1
2
3
7
NC
OE
GND
VCC
nOUT
OUT
SDA
SCL
6
5
4
8
Si570
SEL
PDn
Q1
nQ1
Q2
nQ2
Q3
nQ3
A1_CLKp
A1_CLKn
A2_CLKp
A2_CLKn
R233
100
Q4
nQ4
Q5
nQ5
Q6
nQ6
22
SCL_OSC
Gn
GL
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
49.9 R230
1
1
8
NC
GND
3
4
REFCLK_B0L1p
REFCLK_B0L1n
10
11
REFCLK_B1L3p
REFCLK_B1L3n
12
13
REFCLK_B2L5p
REFCLK_B2L5n
19
18
REFCLK_B3L7p
REFCLK_B3L7n
13,25
13,25
REFCLK_B0L0p
REFCLK_B0L0n
REFCLK_B1L2p
REFCLK_B1L2n
REFCLK_B2L4p
REFCLK_B2L4n
REFCLK_B3L6p
REFCLK_B3L6n
REFCLK_B0L0p
REFCLK_B0L0n
REFCLK_B1L2p
REFCLK_B1L2n
REFCLK_B2L4p
REFCLK_B2L4n
REFCLK_B3L6p
REFCLK_B3L6n
31
31
31
31
32
32
32
32
REFCLK_B0L1p
REFCLK_B0L1n
REFCLK_B1L3p
REFCLK_B1L3n
REFCLK_B2L5p
REFCLK_B2L5n
REFCLK_B3L7p
REFCLK_B3L7n
REFCLK_B0L1p
REFCLK_B0L1n
REFCLK_B1L3p
REFCLK_B1L3n
REFCLK_B2L5p
REFCLK_B2L5n
REFCLK_B3L7p
REFCLK_B3L7n
31
31
31
31
32
32
32
32
REFCLK_XFPp
REFCLK_XFPn
REFCLK_XFPp
REFCLK_XFPn
B
20
20
24
23
1
C258
26
25
J85
0.1uf
29
R234
DNI
IDT5T9306
SCL_OSC
SDA_OSC
25
25
A
2
3
4
5
External Clock Input
U33
2
5
9
14
17
20
27
SMA2_CLKp
J83
5
4
3
2
select CLK source
SW5-1 open = SMA
SW5-1 close = Oscillator
SW5-2 open = SMA
SW5-2 close = Oscillator
SW5-3 open = SMA
SW5-3 close = Oscillator
SW5-4 open = SMA
SW5-4 close = Oscillator
5
4
3
2
B
CLKSEL_BR_even
CLKSEL_BR_odd
2p5V
TDA04H0SB1
R235
DNI
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
SDA_OSC
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
24
of
36
D
5
4
3
2
XCVR Clocks - Right Blocks
2p5V
R236
10K
D
5
4
3
2
49.9 R237
J86
External Clock Input
U34
1
8
1
28
21
SMA3_CLKn
5
4
3
2
49.9 R238
J87
2p5V
6
7
2p5V
16
15
Silicon Labs Oscillator
factory program
@ 625MHz
ADDR - 5Bh
R239
10K
C260
0.1uF
Y5
1
2
3
C
7
NC
OE
GND
VCC
nOUT
OUT
SDA
SCL
Q1
nQ1
Q2
nQ2
Q3
nQ3
A1_CLKp
A1_CLKn
Q4
nQ4
A2_CLKp
A2_CLKn
Q5
nQ5
Q6
nQ6
22
NC
GND
3
4
REFCLK_B0R0p
REFCLK_B0R0n
10
11
REFCLK_B1R2p
REFCLK_B1R2n
12
13
REFCLK_B2R4p
REFCLK_B2R4n
19
18
REFCLK_B3R6p
REFCLK_B3R6n
24
23
C261
1
26
25
J88
0.1uf
29
R241
DNI
IDT5T9306
SCL_OSC
Si570
SEL
PDn
R240
100
6
5
4
8
Gn
GL
2
3
4
5
SMA3_CLKp
2
5
9
14
17
20
27
1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
D
1
C
R242
DNI
SDA_OSC
2p5V
CLKSEL_BR_even
CLKSEL_BR_even
CLKSEL_BR_odd
CLKSEL_BR_even
CLKSEL_BR_odd
CLKSEL_BR_odd
SCL_OSC
SDA_OSC
External Clock Input
1
U35
1
8
28
21
SMA4_CLKn
2p5V
49.9 R245
5
4
3
2
J90
6
7
2p5V
16
15
Silicon Labs Oscillator
factory program
@ 875MHz
ADDR - 6Bh
R246
10K
Y6
1
2
3
7
A
C262
0.1uF
NC
OE
GND
VCC
nOUT
OUT
SDA
SCL
6
5
4
8
SEL
PDn
Q1
nQ1
Q2
nQ2
Q3
nQ3
A1_CLKp
A1_CLKn
A2_CLKp
A2_CLKn
R247
100
Q4
nQ4
Q5
nQ5
Q6
nQ6
22
SCL_OSC
Gn
GL
NC
GND
3
4
REFCLK_B0R1p
REFCLK_B0R1n
10
11
REFCLK_B1R3p
REFCLK_B1R3n
12
13
REFCLK_B2R5p
REFCLK_B2R5n
19
18
REFCLK_B3R7p
REFCLK_B3R7n
24
23
REFCLK_B0R0p
REFCLK_B0R0n
REFCLK_B1R2p
REFCLK_B1R2n
REFCLK_B2R4p
REFCLK_B2R4n
REFCLK_B3R6p
REFCLK_B3R6n
REFCLK_B0R0p
REFCLK_B0R0n
REFCLK_B1R2p
REFCLK_B1R2n
REFCLK_B2R4p
REFCLK_B2R4n
REFCLK_B3R6p
REFCLK_B3R6n
33
33
33
33
34
34
34
34
REFCLK_B0R1p
REFCLK_B0R1n
REFCLK_B1R3p
REFCLK_B1R3n
REFCLK_B2R5p
REFCLK_B2R5n
REFCLK_B3R7p
REFCLK_B3R7n
REFCLK_B0R1p
REFCLK_B0R1n
REFCLK_B1R3p
REFCLK_B1R3n
REFCLK_B2R5p
REFCLK_B2R5n
REFCLK_B3R7p
REFCLK_B3R7n
33
33
33
33
34
34
34
34
B
C263
1
26
25
J91
0.1uf
29
R248
DNI
IDT5T9306
13,24
13,24
2
3
4
5
5
4
3
2
B
49.9 R244
J89
2
5
9
14
17
20
27
R243
10K
SMA4_CLKp
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
1
SCL_OSC
SDA_OSC
24
24
R249
DNI
A
Si570
SDA_OSC
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
25
of
36
D
5
4
3
2
1
S5 Configuration / JTAG
U29A
CONFIGURATION
C
2p5V
PR_DONE
PR_REQUEST
PR_READY
PR_ERROR
DEV_OE
DEV_CLRn
R299 R302 R305 R306 R307 R308 R310 R311
10.0K 10.0K 10.0K 10.0K 10.0K 10.0K 10.0K 10.0K
10
COM1
9
7
8
V+
NC1
5V
nCONFIG
R256
10.0K
AF28
AE28
AG26
AF26
AB27
AB29
AE29
AD29
AC27
PR_DONE
PR_REQUEST
PR_READY
PR_ERROR
IN1
MAX_Bypass
1
DEV_CLRn
NPERST0
NPERST1
NPERST2
NPERST3
CVP_CONFDONE
U36
TS5A23157
2p5V
NO1
DEV_OE
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
D
2
CRC_ERROR
AR33
AU32
AT32
AW32
AV32
AM32
AL31
AN32
AN31
AM31
AL30
AK30
AJ30
AJ29
AJ28
AM29
DCLK
5V
GND
CONFIG_D0
CONFIG_D1
CONFIG_D2
CONFIG_D3
CONFIG_D4
CONFIG_D5
CONFIG_D6
CONFIG_D7
CONFIG_D8
CONFIG_D9
CONFIG_D10
CONFIG_D11
CONFIG_D12
CONFIG_D13
CONFIG_D14
CONFIG_D15
INIT_DONE
U28
AN34
U26
AM7
AB13
AP34
AP33
MAX_FPP_TDI
S5_TDO
3
nSTATUS
DCLK
CLKUSR
nCONFIG
nIO_PULLUP
nCE
DEV_OE
DEV_CLRn
LAST_TDO
MAX_FPP_TDO
NC2
CONF_DONE
AS_DATA0
AS_DATA1
AS_DATA2
AS_DATA3
CONF_DONE
nSTATUS
INIT_DONE
CRC_ERROR
NO2
T27
W29
U29
W28
AB12
AL10
AN33
AM34
AT33
V29
4
D
CONF_DONE
nSTATUS
INIT_DONE
CRC_ERROR
nCEO
nCSO
6
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
COM2
R250 R254 R251 R252 R255 R253
10.0K 10.0K 10.0K 10.0K 10.0K 10.0K
W12
Y11
AA12
AA11
W11
IN2
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
5
2p5V
C
2p5V
R257
1K
R258
1K
R259
1K
R260
1K
MDC
MDIO_IN
MDIO_OUT0
MDIO_OUT1
MDIO_OUT2
MDIO_OUT3
R261
1K
AP28
AN28
AP27
AN27
AR28
AR27
R309
1K
R262
1K
R263
10.0K
2p5V
R264
10.0K
MSEL0
MSEL2
MSEL3
OPEN
S7
1
2
3
4
5
6
MSEL1
TRST
TDI
TDO
TMS
TCK
12
11
10
9
8
7
MSEL4
SPST6
TEMPDIODE_P
TEMPDIODE_N
MAX_Bypass
V11
U11
TEMPDIODEp
TEMPDIODEn
UCLEAR
U27
AU33
AM33
AU34
AV34
AC14
R265
10.0K
J93
S5_TDI
S5_TDO
JTAG_TMS
JTAG_TCK
2
4
6
8
10
BLASTER_DISn
R271
1K
1
3
5
7
9
LAST_TDO
70247-1051
S5_TDI
JTAG_TMS
JTAG_TCK
5SGXEA7N2F40
Defualt Setting = FPP X16 (00100)
USB Blaster Programming Header
(uses JTAG mode only)
B
B
TEMPDIODE_P
TEMPDIODE_N
TEMPDIODE_P
TEMPDIODE_N
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
DCLK
DCLK
11
11
PR_DONE
PR_REQUEST
PR_READY
PR_ERROR
13
13
13
13
13
PR_DONE
13
PR_REQUEST
13
PR_READY
13
PR_ERROR
13
BLASTER_DISn
MAX_FPP_TDO
MAX_FPP_TDI
LAST_TDO
13
BLASTER_DISn
MAX_FPP_TDO
MAX_FPP_TDI
LAST_TDO
CONFIG_D[15:0]
CONFIG_D[15:0]
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
12
13
13
12
13
nCONFIG
13
nSTATUS
12,13
CONF_DONE
12,13
INIT_DONE
12,13
S5_TDI
JTAG_TCK
JTAG_TMS
S5_TDI
12
JTAG_TCK
12,13
JTAG_TMS
12,13
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
26
of
36
D
5
4
3
2
1
S5 Bank 3
U29B
D
AR34
AL29
AT30
AR30
AW31
AV31
AU31
AU30
AR31
AP31
AN30
AN29
AT29
AR29
AA29
Y29
AC29
AE26
AD26
AC25
AC24
AC26
AB25
AF25
AE25
AE23
AD24
C
AH25
AG25
AH24
AG24
AK23
AJ23
AG23
AF23
AM25
AL25
AJ25
AJ24
AL24
AK24
AP25
AN25
AT24
AR25
AR24
AP24
B
AN23
AM23
AL23
AN22
AM22
IO3A-1
IO3A-2
IO3A-3
IO3A-4 BANK-3A
IO3A-5
IO3A-6
IO3A-7
IO3A-8
IO3A-9
IO3A-10
IO3B-1
IO3B-2
IO3B-3
IO3B-4
IO3B-5
IO3B-6
IO3B-7
IO3B-8
IO3B-9
IO3B-10
IO3A-11
IO3A-12
IO3A-13
IO3A-14
IO3A-15
IO3A-16
IO3A-17
IO3B-11
IO3B-12
IO3B-13
IO3B-14
IO3B-15
IO3B-16
IO3B-17
IO3B-18
IO3C-1
IO3C-2
IO3C-3
IO3C-4
IO3C-5
IO3C-6
IO3C-7
IO3C-8
IO3C-9
IO3C-10
BANK-3B
BANK-3C
IO3C-11
IO3C-12
IO3C-13
IO3C-14
IO3C-15
IO3C-16
IO3C-17
IO3C-18
IO3C-19
IO3C-20
IO3C-21
IO3C-22
IO3C-23
IO3C-24
IO3C-25
IO3C-26
IO3C-27
IO3C-28
IO3C-29
IO3C-30
IO3C-31
IO3C-32
IO3C-33
IO3C-34
IO3C-35
IO3C-36
IO3C-37
IO3C-38
IO3C-39
IO3C-40
IO3C-41
IO3C-42
IO3C-43
IO3C-44
IO3C-45
IO3C-46
IO3C-47
IO3C-48
IO3D-1
IO3D-2
IO3D-3
IO3D-4
IO3D-5
IO3D-6
IO3D-7
IO3D-8
IO3D-9
IO3D-10
BANK-3D
IO3D-11
IO3D-12
IO3D-13
IO3D-14
IO3D-15
IO3D-16
IO3D-17
IO3D-18
IO3D-19
IO3D-20
D
AM28
AL28
AN26
AM26
AL27
AL26
AU29
AU28
AW29
AV29
AW28
AV28
AU27
AT27
AT26
AR26
AW26
AV26
AW23
AV23
AW25
AV25
AU24
AU23
AW22
AV22
AR23
AR22
XFP_MOD_ABS
XFP_PDOWN_RST
XFP_MOD_DESEL
XFP_SCL
XFP_SDA
C
XFP_TX_DIS
XFP_INTERRUPT
AU22
AT23
AN24
AE21
AE20
AH22
AG22
AF22
AE22
AL22
AL21
AK21
AJ22
B
AK20
AJ20
AW21
AV20
AU21
AU20
AT21
AR21
AM20
AL20
XFP_PDOWN_RST
XFP_MOD_DESEL
XFP_SCL
XFP_SDA
5SGXEA7N2F40
XFP_PDOWN_RST
XFP_MOD_DESEL
XFP_SCL
20
XFP_SDA
20
XFP_TX_DIS
XFP_INTERRUPT
XFP_MOD_ABS
20
20
XFP_TX_DIS
20
XFP_INTERRUPT
20
XFP_MOD_ABS
20
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
27
of
36
D
5
4
3
2
1
S5 Bank 4
D
D
U29D
U29C
F_CEn
F_OEn
F_WEn
F_RSTn
F_BSYn
F_ADVn
F_WPn
F_CLK
AP9
AN9
AM8
AL8
AR7
AP7
AP6
AN6
AU7
AU6
ENET_RSTn
AT6
AR6
IO4A-1
IO4A-2
IO4A-3
IO4A-4
IO4A-5
IO4A-6
IO4A-7
IO4A-8
IO4A-9
IO4A-10
MDIO
MDC
BANK-4A
RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK
IO4A-11
IO4A-12
C
F_AD1
F_AD2
F_AD3
F_AD4
F_AD5
F_AD6
F_AD7
F_AD8
F_AD9
F_AD10
F_AD11
F_AD12
F_AD13
F_AD14
F_AD15
F_AD16
F_AD17
F_AD18
F_AD19
F_AD20
F_AD21
F_AD22
F_AD23
F_AD24
B
AE14
AD14
AC13
AC12
AG14
AF14
AD11
AC11
AF11
AE11
AE13
AE12
AJ14
AH13
AG13
AF13
AJ13
AJ12
AH12
AG11
AK12
AK11
AL12
AL11
IO4B-1
IO4B-2
IO4B-3
IO4B-4
IO4B-5
IO4B-6
IO4B-7
IO4B-8
IO4B-9
IO4B-10
IO4B-11
IO4B-12
IO4B-13
IO4B-14
IO4B-15
IO4B-16
IO4B-17
IO4B-18
IO4B-19
IO4B-20
IO4B-21
IO4B-22
IO4B-23
IO4B-24
IO4B-25
IO4B-26
IO4B-27
IO4B-28
IO4B-29
IO4B-30
IO4B-31
IO4B-32
IO4B-33
IO4B-34
BANK-4B
IO4B-35
IO4B-36
IO4B-37
IO4B-38
IO4B-39
IO4B-40
IO4B-41
IO4B-42
IO4B-43
IO4B-44
IO4B-45
IO4B-46
IO4B-47
IO4B-48
AM13
AL13
AP13
AN13
AN11
AM11
AP12
AN12
AN10
AM10
AR11
AR10
AT12
AU13
AU12
AU11
AT11
AW13
AV13
AW11
AV11
AW10
AV10
AR12
F_AD25
F_AD26
F_D0
F_D1
F_D2
F_D3
F_D4
F_D5
AC16
AB16
AC15
AB15
AE16
AD15
AG17
AF17
AH16
AG16
GTXCLK
TXEN
TXD0
TXD1
TXD2
TXD3
ENET_SGMII_TX_N
ENET_SGMII_TX_P
ENET_SGMII_RX_N
ENET_SGMII_RX_P
AE15
AF16
AK17
AL17
AJ16
AJ17
AL15
AK15
AJ15
AH15
ENET_INTn
AL14
AK14
AM16
AL16
SPARE0
SPARE1
SPARE2
SPARE3
SPARE4
SPARE5
SPARE6
SPARE7
F_D6
F_D7
F_D8
F_D9
F_D10
F_D11
F_D12
F_D13
F_D14
F_D15
S5_RSTn
AH19
AG19
AJ18
AH18
AN19
AM19
AR19
AP19
AP18
AN18
AT18
AR18
AU19
AU18
AW19
AV19
IO4C-1
IO4C-2
IO4C-3
IO4C-4
IO4C-5
IO4C-6
IO4C-7
IO4C-8
IO4C-9
IO4C-10
BANK-4C
IO4C-25
IO4C-26
IO4C-27
IO4C-28
IO4C-29
IO4C-30
IO4C-31
IO4C-32
IO4C-33
IO4C-34
IO4C-11
IO4C-12
IO4C-13
IO4C-14
IO4C-15
IO4C-16
IO4C-17
IO4C-18
IO4C-19
IO4C-20
IO4C-35
IO4C-36
IO4C-37
IO4C-38
IO4C-39
IO4C-40
IO4C-41
IO4C-42
IO4C-43
IO4C-44
IO4C-21
IO4C-22
IO4C-23
IO4C-24
IO4C-45
IO4C-46
IO4C-47
IO4C-48
IO4D-1
IO4D-2
IO4D-3
IO4D-4
IO4D-5
IO4D-6
IO4D-7
IO4D-8
IO4D-9
IO4D-10
AN17
AM17
AN15
AN16
AR16
AR17
AN14
AM14
AR14
AR13
AR15
AP15
AU17
AT17
AT15
AT14
AU16
AU15
AW17
AV17
MAXll_BEN0
MAXll_BEN0
MAXll_BEN1
MAXll_BEN2
MAXll_BEN3
MAXll_CLK
MAXll_CSN
MAXll_OEN
MAXll_WEN
MAXll_BEN1
MAXll_BEN2
MAXll_BEN3
MAXll_CLK
MAXll_BEN0
MAXll_BEN1
MAXll_BEN2
MAXll_BEN3
MAXll_CLK
MAXll_CSN
MAXll_OEN
MAXll_WEN
MAXll_CSN
MAXll_OEN
13
13
13
13
13
13
13
13
MAXll_WEN
ENET_INTn
ENET_SGMII_TX_P
ENET_SGMII_TX_N
ENET_SGMII_RX_P
ENET_SGMII_RX_N
AW16
AV16
AW14
AV14
ENET_RSTn
S5_RSTn
ENET_RSTn
13,15
S5_RSTn
13
PGM0
PGM1
PGM2
BANK-4D
C
ENET_INTn
15
ENET_SGMII_TX_P
15
ENET_SGMII_TX_N
15
ENET_SGMII_RX_P
15
ENET_SGMII_RX_N
15
PGM0
PGM1
PGM2
MDIO
MDIO
MDC
MDC
RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK
RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK
13
13
13
15
15
15
15
15
15
15
15
B
IO4D-11
IO4D-12
IO4D-13
IO4D-14
IO4D-15
IO4D-16
GTXCLK
TXEN
TXD0
TXD1
TXD2
TXD3
GTXCLK
TXEN
TXD0
TXD1
TXD2
TXD3
SPARE[7:0]
SPARE[7:0]
F_AD[26:1]
PGM0
PGM1
PGM2
F_CEn
F_OEn
F_WEn
F_RSTn
F_BSYn
F_ADVn
F_WPn
F_CLK
5SGXEA7N2F40
13
F_AD[26:1]
F_D[15:0]
F_D[15:0]
5SGXEA7N2F40
15
15
15
15
15
15
13,14
13,14
F_CEn
13,14
F_OEn
13,14
F_WEn
13,14
F_RSTn
13,14
F_BSYn
13,14
F_ADVn
13,14
F_WPn
13,14
F_CLK
13,14
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
28
of
36
D
5
4
3
2
1
S5 Bank 7
D
D
U29F
U29E
FAN_CTRL
FAN_LED
OVERTEMPn
ALERTn
S5_SMBCLK_TEMP
S5_SMBDATA_TEMP
D6
C6
E6
E7
E8
D7
B8
A8
F8
G9
J9
J8
IO7A-2
IO7A-3
IO7A-4
IO7A-5
IO7A-6
IO7A-7
IO7A-8
IO7A-9
IO7A-10
BANK-7A
LCD_D_Cn
LCD_EN
LCD_WEn
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
B14
A14
B13
A13
B16
A16
C15
C14
D15
D16
LCD_DATA7
F14
E14
E16
F15
G15
G14
H17
G17
J14
H14
IO7A-11
IO7A-12
IO7A-13
C
H16
G16
J16
J17
IO7C-1
IO7C-2
IO7C-3
IO7C-4
IO7C-5
IO7C-6
IO7C-7
IO7C-8
IO7C-9
IO7C-10
BANK-7C
IO7C-25
IO7C-26
IO7C-27
IO7C-28
IO7C-29
IO7C-30
IO7C-31
IO7C-32
IO7C-33
IO7C-34
IO7C-11
IO7C-12
IO7C-13
IO7C-14
IO7C-15
IO7C-16
IO7C-17
IO7C-18
IO7C-19
IO7C-20
IO7C-35
IO7C-36
IO7C-37
IO7C-38
IO7C-39
IO7C-40
IO7C-41
IO7C-42
IO7C-43
IO7C-44
IO7C-21
IO7C-22
IO7C-23
IO7C-24
IO7C-45
IO7C-46
IO7C-47
IO7C-48
K15
J15
K16
L17
L15
L14
R14
P14
N14
M14
N15
M15
T15
R15
U16
U15
T16
R16
P16
N16
FAN_CTRL
FAN_LED
N17
M17
R17
P17
FAN_CTRL
FAN_LED
OVERTEMPn
ALERTn
E13
D13
E10
E9
D9
G10
F11
E12
E11
G12
B
F12
H13
G13
H11
IO7B-1
IO7B-2
IO7B-3
IO7B-4
IO7B-5
IO7B-6
IO7B-7
IO7B-8
IO7B-9
IO7B-10
BANK-7B
G11
K10
J11
M11
L11
K12
J12
K13
J13
M12
IO7B-25
IO7B-26
IO7B-27
IO7B-28
IO7B-29
IO7B-30
IO7B-31
IO7B-32
IO7B-33
IO7B-34
IO7B-11
IO7B-12
IO7B-13
IO7B-14
IO7B-15
IO7B-16
IO7B-17
IO7B-18
IO7B-19
IO7B-20
IO7B-35
IO7B-36
IO7B-37
IO7B-38
IO7B-39
IO7B-40
IO7B-41
IO7B-42
IO7B-43
IO7B-44
IO7B-21
IO7B-22
IO7B-23
IO7B-24
IO7B-45
IO7B-46
IO7B-47
IO7B-48
L12
V12
U12
U14
U13
R12
P11
T13
R13
P13
N13
N12
N11
D10
B20
A20
B19
A19
D21
C21
B17
A17
D19
C18
SDA_PM
SCL_PM
PM_CNTL0
PM_CNTL1
PM_RSTn
PM_SHARE_CLK
C20
C19
D18
C17
F21
H19
G19
J19
J18
K21
PM_ALERTB
PM_PWRGD
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
PM2_FAULTB10
PM2_FAULTB11
J20
L19
K19
L18
PM2_FAULTB00
PM2_FAULTB01
IO7D-1
IO7D-2
IO7D-3
IO7D-4
IO7D-5
IO7D-6
IO7D-7
IO7D-8
IO7D-9
IO7D-10
BANK-7D
IO7D-11
IO7D-12
IO7D-13
IO7D-14
IO7D-15
IO7D-16
IO7D-17
IO7D-18
IO7D-19
IO7D-20
IO7D-25
IO7D-26
IO7D-27
IO7D-28
IO7D-29
IO7D-30
IO7D-31
IO7D-32
IO7D-33
IO7D-34
IO7D-35
IO7D-36
IO7D-37
IO7D-38
IO7D-39
IO7D-40
K18
N18
M18
P19
N19
P20
N20
R20
R21
M20
L20
P22
N21
R23
R22
E21
IO7D-21
IO7D-22
IO7D-23
IO7D-24
5SGXEA7N2F40
S5_SMBCLK_TEMP
S5_SMBDATA_TEMP
SCL_PM
SDA_PM
SCL_PM
SDA_PM
PM_CNTL0
PM_CNTL1
PM_RSTn
PM_SHARE_CLK
PM_ALERTB
PM_PWRGD
PM_CNTL0
9,10,13
PM_CNTL1
9,10,13
PM_RSTn
9,10,13
11,13
11,13
9,10,13
9,10,13
PM1_FAULTB00
PM1_FAULTB01
PM1_FAULTB10
PM1_FAULTB11
PM_SHARE_CLK
9,10,13
PM_ALERTB
9,10,13
PM_PWRGD
9,10,13
PM1_FAULTB00
9,13
PM1_FAULTB01
9,13
PM1_FAULTB10
9,13
PM1_FAULTB11
9,13
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
PM2_FAULTB00
PM2_FAULTB01
PM2_FAULTB10
PM2_FAULTB11
LCD_D_Cn
LCD_EN
LCD_WEn
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
5SGXEA7N2F40
C
OVERTEMPn
11,13
ALERTn
11,13
S5_SMBCLK_TEMP
S5_SMBDATA_TEMP
C9
C10
B10
A10
B11
A11
C12
C11
D12
C13
11,13
11,13
B
10,13
10,13
10,13
10,13
LCD_D_Cn
16
LCD_EN
16
LCD_WEn
16
LCD_DATA0
16
LCD_DATA1
16
LCD_DATA2
16
LCD_DATA3
16
LCD_DATA4
16
LCD_DATA5
16
LCD_DATA6
16
LCD_DATA7
16
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
29
of
36
D
5
4
3
2
1
S5 Bank 8
D
D
U29H
U29G
USER_LED0
USER_LED1
USER_LED2
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7
USER_DIP0
USER_DIP1
USER_DIP2
USER_DIP3
C
USER_DIP4
USER_DIP5
USER_DIP6
SFPA_MOD0_PRSNTn
SFPA_MOD1_SCL
SFPA_MOD2_SDA
SFPA_TXFAULT
SFPA_LOS
SFPA_TXDISABLE
SFPA_RATESEL0
SFPA_RATESEL1
F29
E29
G30
G29
D31
D30
B32
A32
B34
A34
C34
C33
F32
E32
E33
D33
E34
D34
H32
G32
G33
F33
H34
G34
B26
A26
B25
A25
B28
A28
C27
C26
E28
D28
USER_PB0
USER_PB1
USER_PB2
USER_PB3
E27
D27
G27
F27
G26
F26
H29
G28
K27
J27
USER_IO0
USER_IO1
USER_IO2
USER_IO3
J26
H26
J28
H28
B
IO8A-1
IO8A-2
IO8A-3
IO8A-4
IO8A-5
IO8A-6
IO8A-7
IO8A-8
IO8A-9
IO8A-10
B22
A22
D22
C22
B23
A23
E23
E22
E24
D24
BANK-8A
C24
C23
G22
G21
J22
H22
G23
F23
H25
G25
IO8A-11
IO8A-12
IO8A-13
IO8A-14
IO8A-15
IO8A-16
IO8A-17
IO8A-18
IO8A-19
IO8A-20
G24
F24
E25
D25
IO8A-21
IO8A-22
IO8A-23
IO8A-24
IO8C-1
IO8C-2
IO8C-3
IO8C-4
IO8C-5
IO8C-6
IO8C-7
IO8C-8
IO8C-9
IO8C-10
IO8C-25
IO8C-26
IO8C-27
IO8C-28
IO8C-29
IO8C-30
IO8C-31
IO8C-32
IO8C-33
IO8C-34
BANK-8C
IO8C-11
IO8C-12
IO8C-13
IO8C-14
IO8C-15
IO8C-16
IO8C-17
IO8C-18
IO8C-19
IO8C-20
IO8C-35
IO8C-36
IO8C-37
IO8C-38
IO8C-39
IO8C-40
IO8C-41
IO8C-42
IO8C-43
IO8C-44
IO8C-21
IO8C-22
IO8C-23
IO8C-24
IO8C-45
IO8C-46
IO8C-47
IO8C-48
IO8D-1
IO8D-2
IO8D-3
IO8D-4
IO8D-5
IO8D-6
IO8D-7
IO8D-8
IO8D-9
IO8C-10
BANK-8D
IO8D-11
IO8D-12
IO8D-13
IO8D-14
IO8D-15
IO8D-16
IO8D-17
IO8D-18
IO8D-19
IO8D-20
IO8D-25
IO8D-26
IO8D-27
IO8D-28
IO8D-29
IO8D-30
IO8D-31
IO8D-32
IO8D-33
IO8D-34
IO8D-35
IO8D-36
IO8D-37
IO8D-38
IO8D-39
IO8D-40
IO8D-41
IO8D-42
IO8D-43
IO8D-44
J25
J24
M24
L23
L24
K24
L25
K25
N23
M23
R24
P23
N25
N24
U24
T24
R25
P25
U25
T25
SFPA_MOD0_PRSNTn
SFPA_MOD1_SCL
SFPA_MOD2_SDA
SFPA_TXFAULT
SFPA_LOS
IO8D-21
IO8D-22
IO8D-23
IO8D-24
L27
L26
N26
M26
L28
K28
R26
P26
N27
M27
P28
N28
M29
L29
R29
R28
P29
N29
L30
K30
J30
J29
K31
J31
CPURSTn
SFPA_MOD0_PRSNTn
21
SFPA_MOD1_SCL
21
SFPA_MOD2_SDA
21
SFPA_TXFAULT
21
SFPA_LOS
21
SFPA_TXDISABLE
SFPA_TXDISABLE
SFPA_RATESEL0
SFPA_RATESEL1
SFPA_RATESEL0
SFPA_RATESEL1
USER_DIP0
USER_DIP1
USER_DIP2
USER_DIP3
USER_DIP4
USER_DIP5
USER_DIP6
USER_DIP0
USER_DIP1
USER_DIP2
USER_DIP3
USER_DIP4
USER_DIP5
USER_DIP6
USER_PB0
USER_PB1
USER_PB2
USER_PB3
USER_PB0
USER_PB1
USER_PB2
USER_PB3
USER_IO0
USER_IO1
USER_IO2
USER_IO3
USER_IO0
USER_IO1
USER_IO2
USER_IO3
USER_LED0
USER_LED1
USER_LED2
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7
USER_LED0
USER_LED1
USER_LED2
USER_LED3
USER_LED4
USER_LED5
USER_LED6
USER_LED7
5SGXEA7N2F40
C
21
21
21
16
16
16
16
16
16
16
16
16
16
16
B
16
16
16
16
16
16
16
16
16
16
16
16
5SGXEA7N2F40
CPURSTn
CPURSTn
16
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
30
of
36
D
5
4
3
2
1
XCVR Left Blocks 0/1
U29I
Block-0-Left
GXB_RXLp_0
GXB_RXLn_0
AV38
AV39
D
TYCO BP
REFCLK_B0L0p
GXB_RXLp_1
GXB_RXLn_1
AT38
AT39
GXB_RXLp_2
GXB_RXLn_2
AP38
AP39
GXB_RXLp_3
GXB_RXLn_3
AM38
AM39
GXB_RXLp_4
GXB_RXLn_4
AJ36
AJ37
GXB_RXLp_5
GXB_RXLn_5
AK38
AK39
R272
100
REFCLK_B0L0n
REFCLK_B0L1p
GXB_RX_L1p / GXB_REFCLK_L1p
GXB_RX_L1n / GXB_REFCLK_L1n
GXB_TX_L1p
GXB_TX_L1n
GXB_RX_L2p / GXB_REFCLK_L2p
GXB_RX_L2n / GXB_REFCLK_L2n
GXB_TX_L2p
GXB_TX_L2n
GXB_RX_L3p / GXB_REFCLK_L3p
GXB_RX_L3n / GXB_REFCLK_L3n
GXB_TX_L3p
GXB_TX_L3n
GXB_RX_L4p / GXB_REFCLK_L4p
GXB_RX_L4n / GXB_REFCLK_L4n
GXB_TX_L4p
GXB_TX_L4n
GXB_RX_L5p / GXB_REFCLK_L5p
GXB_RX_L5n / GXB_REFCLK_L5n
GXB_TX_L5p
GXB_TX_L5n
AU36
AU37
GXB_TXLp_0
GXB_TXLn_0
D
AR36
AR37
GXB_TXLp_1
GXB_TXLn_1
AN36
AN37
GXB_TXLp_2
GXB_TXLn_2
AL36
AL37
GXB_TXLp_3
GXB_TXLn_3
AK34
AK35
GXB_TXLp_4
GXB_TXLn_4
AH34
AH35
GXB_TXLp_5
GXB_TXLn_5
TYCO BP
C265 .068uF
C266 .068uF
XFP
GXB_RXLp_[11:0]
AG32
AG33
REFCLKB0L0p
REFCLKB0L0n
AE31
AE32
REFCLKB0L1p
REFCLKB0L1n
R273
100
REFCLK_B0L1n
GXB_TX_L0p
GXB_TX_L0n
C264 .068uF
XFP
C
GXB_RX_L0p / GXB_REFCLK_L0p
GXB_RX_L0n / GXB_REFCLK_L0n
GXB_RXLn_[11:0]
REFCLK_B0L0p
REFCLK_B0L0n
REFCLK_B0L1p
REFCLK_B0L1n
GXB_RXLp_[11:0]
18,19,20,21
GXB_RXLn_[11:0]
18,19,20,21
GXB_TXLp_[11:0]
GXB_TXLp_[11:0]
18,19,20,21
GXB_TXLn_[11:0]
GXB_TXLn_[11:0]
18,19,20,21
REFCLK_B0L0p
REFCLK_B0L0n
REFCLK_B0L1p
REFCLK_B0L1n
5SGXEA7N2F40
C267 .068uF
U29J
REFCLK_B1L2p
REFCLK_B1L2n
REFCLK_B1L3p
REFCLK_B1L3n
Block-1-Left
MOLEX BP
B
REFCLK_B1L2p
GXB_RXLp_6
GXB_RXLn_6
AH38
AH39
GXB_RXLp_7
GXB_RXLn_7
AE36
AE37
GXB_RXLp_8
GXB_RXLn_8
AF38
AF39
GXB_RXLp_9
GXB_RXLn_9
AD38
AD39
GXB_RXLp_10
GXB_RXLn_10
AB38
AB39
GXB_RXLp_11
GXB_RXLn_11
AA36
AA37
R274
100
REFCLK_B1L2n
C269 .068uF
REFCLK_B1L3p
C270 .068uF
REFCLKB1L2p
REFCLKB1L2n
AC32
AC33
REFCLKB1L3p
REFCLKB1L3n
AA31
AA32
R275
100
REFCLK_B1L3n
GXB_TX_L6p
GXB_TX_L6n
GXB_RX_L7p / GXB_REFCLK_L7p
GXB_RX_L7n / GXB_REFCLK_L7n
GXB_TX_L7p
GXB_TX_L7n
GXB_RX_L8p / GXB_REFCLK_L8p
GXB_RX_L8n / GXB_REFCLK_L8n
GXB_TX_L8p
GXB_TX_L8n
GXB_RX_L9p / GXB_REFCLK_L9p
GXB_RX_L9n / GXB_REFCLK_L9n
GXB_TX_L9p
GXB_TX_L9n
GXB_RX_L10p / GXB_REFCLK_L10p
GXB_RX_L10n / GXB_REFCLK_L10n
GXB_TX_L10p
GXB_TX_L10n
GXB_RX_L11p / GXB_REFCLK_L11p
GXB_RX_L11n / GXB_REFCLK_L11n
GXB_TX_L11p
GXB_TX_L11n
GXB_TXLp_6
GXB_TXLn_6
AF34
AF35
GXB_TXLp_7
GXB_TXLn_7
AD34
AD35
GXB_TXLp_8
GXB_TXLn_8
AC36
AC37
GXB_TXLp_9
GXB_TXLn_9
AB34
AB35
GXB_TXLp_10
GXB_TXLn_10
Y34
Y35
GXB_TXLp_11
GXB_TXLn_11
24
24
24
24
REFCLK_B1L2p
REFCLK_B1L2n
REFCLK_B1L3p
REFCLK_B1L3n
24
24
24
24
MOLEX BP
B
C268 .068uF
SMA
A
GXB_RX_L6p / GXB_REFCLK_L6p
GXB_RX_L6n / GXB_REFCLK_L6n
AG36
AG37
REFCLK_B0L0p
REFCLK_B0L0n
REFCLK_B0L1p
REFCLK_B0L1n
C
SMA
REFCLK_B1L2p
REFCLK_B1L2n
REFCLK_B1L3p
REFCLK_B1L3n
A
5SGXEA7N2F40
Altera Corporation, 101 Innovation Drive, San Jose, CA
C271 .068uF
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
31
of
36
D
5
4
3
2
1
XCVR Left Blocks 2/3
U29K
Block-2-Left
GXB_RXLp_12
GXB_RXLn_12
Y38
Y39
GXB_RXLp_13
GXB_RXLn_13
V38
V39
D
GXB_RXLp_14
GXB_RXLn_14
U36
U37
GXB_RXLp_15
GXB_RXLn_15
T38
T39
GXB_RXLp_16
GXB_RXLn_16
P38
P39
GXB_RXLp_17
GXB_RXLn_17
M38
M39
SMA
REFCLK_B2L4p
REFCLK_B2L4n
C273 .068uF
REFCLK_B2L5p
C274 .068uF
REFCLKB2L4p
REFCLKB2L4n
W32
W33
REFCLKB2L5p
REFCLKB2L5n
U31
U32
R277
100
REFCLK_B2L5n
GXB_TX_L12p
GXB_TX_L12n
GXB_RX_L13p / GXB_REFCLK_L13p
GXB_RX_L13n / GXB_REFCLK_L13n
GXB_TX_L13p
GXB_TX_L13n
GXB_RX_L14p / GXB_REFCLK_L14p
GXB_RX_L14n / GXB_REFCLK_L14n
GXB_TX_L14p
GXB_TX_L14n
GXB_RX_L15p / GXB_REFCLK_L15p
GXB_RX_L15n / GXB_REFCLK_L15n
GXB_TX_L15p
GXB_TX_L15n
GXB_RX_L16p / GXB_REFCLK_L16p
GXB_RX_L16n / GXB_REFCLK_L16n
GXB_TX_L16p
GXB_TX_L16n
GXB_RX_L17p / GXB_REFCLK_L17p
GXB_RX_L17n / GXB_REFCLK_L17n
GXB_TX_L17p
GXB_TX_L17n
W36
W37
GXB_TXLp_12
GXB_TXLn_12
V34
V35
GXB_TXLp_13
GXB_TXLn_13
D
T34
T35
GXB_TXLp_14
GXB_TXLn_14
R36
R37
GXB_TXLp_15
GXB_TXLn_15
P34
P35
GXB_TXLp_16
GXB_TXLn_16
N36
N37
GXB_TXLp_17
GXB_TXLn_17
SMA
C272 .068uF
R276
100
C
GXB_RX_L12p / GXB_REFCLK_L12p
GXB_RX_L12n / GXB_REFCLK_L12n
REFCLK_B2L4p
REFCLK_B2L4n
C
REFCLK_B2L5p
REFCLK_B2L5n
5SGXEA7N2F40
C275 .068uF
U29L
Block-3-Left
SFP
AMPHENOL BP
B
REFCLK_B3L6p
GXB_RXLp_18
GXB_RXLn_18
L36
L37
GXB_RXLp_19
GXB_RXLn_19
K38
K39
GXB_RXLp_20
GXB_RXLn_20
H38
H39
GXB_RXLp_21
GXB_RXLn_21
F38
F39
GXB_RXLp_22
GXB_RXLn_22
D38
D39
GXB_RXLp_23
GXB_RXLn_23
B38
B39
REFCLK_B3L6n
C277 .068uF
REFCLK_B3L7p
C278 .068uF
REFCLKB3L6p
REFCLKB3L6n
R32
R33
REFCLKB3L7p
REFCLKB3L7n
N31
N32
R279
100
REFCLK_B3L7n
GXB_TX_L18p
GXB_TX_L18n
GXB_RX_L19p / GXB_REFCLK_L19p
GXB_RX_L19n / GXB_REFCLK_L19n
GXB_TX_L19p
GXB_TX_L19n
GXB_RX_L20p / GXB_REFCLK_L20p
GXB_RX_L20n / GXB_REFCLK_L20n
GXB_TX_L20p
GXB_TX_L20n
GXB_RX_L21p / GXB_REFCLK_L21p
GXB_RX_L21n / GXB_REFCLK_L21n
GXB_TX_L21p
GXB_TX_L21n
GXB_RX_L22p / GXB_REFCLK_L22p
GXB_RX_L22n / GXB_REFCLK_L22n
GXB_TX_L22p
GXB_TX_L22n
GXB_RX_L23p / GXB_REFCLK_L23p
GXB_RX_L23n / GXB_REFCLK_L23n
GXB_TX_L23p
GXB_TX_L23n
M34
M35
GXB_TXLp_18
GXB_TXLn_18
K34
K35
GXB_TXLp_19
GXB_TXLn_19
J36
J37
GXB_TXLp_20
GXB_TXLn_20
SFP
GXB_RXLp_[23:12]
G36
G37
GXB_TXLp_21
GXB_TXLn_21
GXB_RXLp_[23:12]
17,21
GXB_RXLn_[23:12]
17,21
GXB_TXLp_[23:12]
GXB_TXLp_[23:12]
17,21
GXB_TXLn_[23:12]
17,21
GXB_RXLn_[23:12]
AMPHENOL BP
E36
E37
GXB_TXLp_22
GXB_TXLn_22
GXB_TXLn_[23:12]
C36
C37
GXB_TXLp_23
GXB_TXLn_23
REFCLK_B2L4p
REFCLK_B2L4n
REFCLK_B2L5p
REFCLK_B2L5n
B
C276 .068uF
R278
100
A
GXB_RX_L18p / GXB_REFCLK_L18p
GXB_RX_L18n / GXB_REFCLK_L18n
REFCLK_B3L6p
REFCLK_B3L6n
REFCLK_B3L7p
REFCLK_B3L7n
REFCLK_B3L6p
REFCLK_B3L6n
REFCLK_B2L4p
REFCLK_B2L4n
REFCLK_B2L5p
REFCLK_B2L5n
24
24
24
24
REFCLK_B3L6p
REFCLK_B3L6n
REFCLK_B3L7p
REFCLK_B3L7n
24
24
24
24
REFCLK_B3L7p
REFCLK_B3L7n
5SGXEA7N2F40
C279 .068uF
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
32
of
36
D
5
4
3
2
1
XCVR Right Blocks 0/1
U29M
Block-0-Right
GXB_RXRp_0
GXB_RXRn_0
AV2
AV1
GXB_RXRp_5
GXB_RXRn_5
AJ4
AJ3
TYCO BP
J94
2.4mm
via-gnd
ATTRXRp_0
68nF
C280
GXB_TX_R0p
GXB_TX_R0n
GXB_RX_R5p / GXB_REFCLK_R5p
GXB_RX_R5n / GXB_REFCLK_R5n
GXB_TX_R5p
GXB_TX_R5n
ATT_RX_R0p
ATT_RX_R0n
ATT_TX_R0p
ATT_TX_R0n
AU4
AU3
GXB_TXRp_0
GXB_TXRn_0
AH6
AH5
GXB_TXRp_5
GXB_TXRn_5
TYCO BP
D
gnd
ATT_RXRp_0
ATT_RXRn_0
AM2
AM1
gnd
ATTRXRn_0
via-gnd
2.4mm
J96
AP2
AP1
J95
2.4mm
ATT_TXRp_0
ATT_TXRn_0
gnd
gnd
REFCLK_B0R0p
via-gnd
68nF
C281
via-gnd
D
GXB_RX_R0p / GXB_REFCLK_R0p
GXB_RX_R0n / GXB_REFCLK_R0n
2.4mm
J97
C282 .068uF
R280
100
REFCLK_B0R0n
C283 .068uF
REFCLK_B0R1p
C284 .068uF
REFCLKB0R0p
REFCLKB0R0n
AG8
AG7
REFCLKB0R1p
REFCLKB0R1n
AE9
AE8
REFCLK_B0R0p
REFCLK_B0R0n
C
C
R281
100
REFCLK_B0R1n
REFCLK_B0R1p
REFCLK_B0R1n
5SGXEA7N2F40
C285 .068uF
U29N
Block-1-Right
AH2
AH1
J98
2.4mm
AA4
AA3
68nF
C286
GXB_TX_R11p
GXB_TX_R11n
AG4
AG3
Y6
Y5
gnd
ATT_RXRp_1
ATT_RXRn_1
B
AB2
AB1
gnd
via-gnd
2.4mm
J100
GXB_RX_R11p / GXB_REFCLK_R11p
GXB_RX_R11n / GXB_REFCLK_R11n
GXB_TX_R6p
GXB_TX_R6n
ATTRXRn_1
ATT_RX_R1p
ATT_RX_R1n
ATT_TX_R1p
ATT_TX_R1n
AD2
AD1
J99
2.4mm
ATT_TXRp_1
ATT_TXRn_1
gnd
gnd
REFCLK_B1R2p
via-gnd
68nF
C287
2.4mm
J101
C288 .068uF
REFCLK_B1R2n
C289 .068uF
REFCLK_B1R3p
C290 .068uF
AC8
AC7
REFCLKB1R3p
REFCLKB1R3n
AA9
AA8
R283
100
18
18
18
18
GXB_TXRp_0
GXB_TXRn_0
GXB_TXRp_5
GXB_TXRn_5
GXB_TXRp_0
GXB_TXRn_0
GXB_TXRp_5
GXB_TXRn_5
18
18
18
18
B
REFCLK_B1R2p
REFCLK_B1R2n
REFCLK_B1R3p
REFCLK_B1R3n
REFCLK_B1R2p
REFCLK_B1R2n
REFCLK_B0R0p
REFCLK_B0R0n
REFCLK_B0R1p
REFCLK_B0R1n
25
25
25
25
REFCLK_B1R2p
REFCLK_B1R2n
REFCLK_B1R3p
REFCLK_B1R3n
25
25
25
25
REFCLK_B1R3p
REFCLK_B1R3n
5SGXEA7N2F40
A
REFCLK_B1R3n
GXB_RXRp_0
GXB_RXRn_0
GXB_RXRp_5
GXB_RXRn_5
REFCLK_B0R0p
REFCLK_B0R0n
REFCLK_B0R1p
REFCLK_B0R1n
R282
100
REFCLKB1R2p
REFCLKB1R2n
GXB_RXRp_0
GXB_RXRn_0
GXB_RXRp_5
GXB_RXRn_5
via-gnd
via-gnd
ATTRXRp_1
GXB_RX_R6p / GXB_REFCLK_R6p
GXB_RX_R6n / GXB_REFCLK_R6n
A
C291 .068uF
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
33
of
36
D
5
4
3
2
1
XCVR Right Blocks 2/3
U29O
Block-2-Right
CLK IN
GXB_RXRp_12
GXB_RXRn_12
Y2
Y1
GXB_RX_R12p / GXB_REFCLK_R12p
GXB_RX_R12n / GXB_REFCLK_R12n
GXB_TX_R12p
GXB_TX_R12n
GXB_RX_R17p / GXB_REFCLK_R17p
GXB_RX_R17n / GXB_REFCLK_R17n
GXB_TX_R17p
GXB_TX_R17n
W4
W3
D
D
J102
2.4mm
68nF
C292
N4
N3
gnd
ATT_RXRp_2
ATT_RXRn_2
P2
P1
gnd
T2
T1
J103
2.4mm
ATT_TXRp_2
ATT_TXRn_2
gnd
gnd
2.4mm
J105
C294 .068uF
ATT 8" Test Trace
J111
2.4mm
R284
100
via-gnd
REFCLK_B2R4n
C295 .068uF
REFCLK_B2R5p
C296 .068uF
W8
W7
REFCLKB2R5p
REFCLKB2R5n
U9
U8
R285
100
REFCLK_B2R5n
gnd
gnd
via-gnd
REFCLK_B2R4p
REFCLK_B2R4n
C
via-gnd
C
REFCLKB2R4p
REFCLKB2R4n
J113
2.4mm
ATT_TSTp
REFCLK_B2R5p
REFCLK_B2R5n
gnd
REFCLK_B2R4p
via-gnd
68nF
C293
gnd
ATTRXRn_2
ATT_TX_R2p
ATT_TX_R2n
via-gnd
via-gnd
2.4mm
J104
ATT_RX_R2p
ATT_RX_R2n
via-gnd
via-gnd
ATTRXRp_2
M2
M1
ATT_TSTn
2.4mm
J110
2.4mm
J112
5SGXEA7N2F40
C297 .068uF
U29P
Block-3-Right
GXB_RXRp_18
GXB_RXRn_18
L4
L3
AMPHENOL BP
J106
2.4mm
68nF
C298
B2
B1
GXB_RX_R23p / GXB_REFCLK_R23p
GXB_RX_R23n / GXB_REFCLK_R23n
GXB_TX_R18p
GXB_TX_R18n
GXB_TX_R23p
GXB_TX_R23n
M6
M5
GXB_TXRp_18
GXB_TXRn_18
AMPHENOL BP
C4
C3
GXB_TXRp_23
GXB_TXRn_23
gnd
B
ATT_RXRp_3
ATT_RXRn_3
F2
F1
gnd
via-gnd
ATTRXRn_3
2.4mm
J108
ATT_RX_R3p
ATT_RX_R3n
ATT_TX_R3p
ATT_TX_R3n
H2
H1
J107
2.4mm
ATT_TXRp_3
ATT_TXRn_3
gnd
gnd
REFCLK_B3R6p
via-gnd
68nF
C299
2.4mm
J109
C300 .068uF
C301 .068uF
REFCLK_B3R7p
C302 .068uF
REFCLKB3R6p
REFCLKB3R6n
R8
R7
REFCLKB3R7p
REFCLKB3R7n
N9
N8
R287
100
A
REFCLK_B3R7n
GXB_RXRp_12
GXB_RXRn_12
GXB_RXRp_18
GXB_RXRn_18
GXB_RXRp_23
GXB_RXRn_23
21
21
17
17
17
17
GXB_TXRp_18
GXB_TXRn_18
GXB_TXRp_23
GXB_TXRn_23
GXB_TXRp_18
GXB_TXRn_18
GXB_TXRp_23
GXB_TXRn_23
17
17
17
17
B
REFCLK_B3R6p
REFCLK_B3R6n
REFCLK_B3R7p
REFCLK_B3R7n
R286
100
REFCLK_B3R6n
GXB_RXRp_12
GXB_RXRn_12
GXB_RXRp_18
GXB_RXRn_18
GXB_RXRp_23
GXB_RXRn_23
REFCLK_B2R4p
REFCLK_B2R4n
REFCLK_B2R5p
REFCLK_B2R5n
via-gnd
via-gnd
ATTRXRp_3
GXB_RXRp_23
GXB_RXRn_23
GXB_RX_R18p / GXB_REFCLK_R18p
GXB_RX_R18n / GXB_REFCLK_R18n
REFCLK_B2R4p
REFCLK_B2R4n
REFCLK_B2R5p
REFCLK_B2R5n
25
25
25
25
REFCLK_B3R6p
REFCLK_B3R6n
REFCLK_B3R7p
REFCLK_B3R7n
25
25
25
25
REFCLK_B3R6p
REFCLK_B3R6n
REFCLK_B3R7p
REFCLK_B3R7n
A
5SGXEA7N2F40
C303 .068uF
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
34
of
36
D
5
4
3
2
1
FPGA / XCVR Power
D
S5GX_VCC
S5GX_VCC
2p5V
D
2p5V
U29S
U29T
VCCRT_GXB
AD17
AD19
AD21
AD23
T17
T19
T21
T23
AA17
AA18
AA19
AA20
AA23
AB17
AB18
AB20
AB22
AC18
AC19
AC20
AC21
AC22
AC23
U17
U18
U20
U21
U22
V17
V18
V19
C
2p5V
2p5V_FLTR
FB5
2
1
120ohm, 800mA
AK32
AH21
AK8
L8
M21
L32
AD30
R30
AC10
P10
C495
0.1uF
B
FPGA CORE PWR
VCCA_FPLL_BL
VCCA_FPLL_BC
VCCA_FPLL_BR
VCCA_FPLL_TR
VCCA_FPLL_TC
VCCA_FPLL_TL
VCCA_FPLL_L1
VCCA_FPLL_L2
VCCA_FPLL_R1
VCCA_FPLL_R2
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCCHSSI_L1
VCCHSSI_L2
VCCHSSI_L3
VCCHSSI_L4
VCCHSSI_L5
VCCHSSI_L6
VCCHSSI_R1
VCCHSSI_R2
VCCHSSI_R3
VCCHSSI_R4
VCCHSSI_R5
VCCHSSI_R6
V20
V21
V23
W17
W18
W19
W21
W22
W23
Y18
Y20
Y21
Y22
AA22
AW30
AW33
AU26
AW27
AU25
AW24
AW20
AA26
AA27
V26
W27
Y26
Y28
C8
A12
A9
A15
C16
A18
A21
AW9
AU10
AW12
AU14
AW15
AW18
AA13
AA14
V14
W13
Y12
Y14
A30
A33
A27
C28
A24
C25
1p5V
VCCD_FPLL_BL
VCCD_FPLL_BC
VCCD_FPLL_BR
VCCD_FPLL_TR
PLL PWR VCCD_FPLL_TC
VCCD_FPLL_TL
VCCD_FPLL_L1
VCCD_FPLL_L2
VCCD_FPLL_R1
VCCD_FPLL_R2
AK29
AG27
AE24
AG21
AL32
AJ21
AK9
K9
L21
L31
AC30
T30
AB10
R10
AL9
AG12
AG15
AG18
L9
L13
L16
R18
RREF_TL
RREF_BL
RREF_TR
RREF_BR
J32
R27
L22
VCCIO3A_1
VCCIO3A_2
VCCIO3B_1
VCCIO3B_2
VCCIO3C_1
VCCIO3C_2
VCCIO3D_1
VCCPD_3AB_1
VCCPD_3AB_2
VCCPD_3CD
FPGA PWR
VCCPD_4_1
VCCPD_4_2
VCCPD_7_1
VCCPD_7_2
VCCPD_7_3
VCCIO4A_1
VCCIO4B_1
VCCIO4B_2
VCCIO4C_1
VCCIO4C_2
VCCIO4D_1
VCCPD_8_1
VCCPD_8_2
VCCIO7A_1
VCCIO7B_1
VCCIO7B_2
VCCIO7C_1
VCCIO7C_2
VCCIO7D_1
VCCIO7D_2
VCCPT_1
VCCPT_2
VCCPT_3
VCCPT_4
VCCPT_5
VCCPT_6
VCCAUX_1
VCCAUX_2
VCCAUX_3
VCCAUX_4
VCCAUX_5
VCCAUX_6
VCCIO8A_1
VCCIO8A_2
VCCIO8C_1
VCCIO8C_2
VCCIO8D_1
VCCIO8D_2
VCCPGM_1
VCCPGM_2
VREF_B3A
VREF_B3B
VREF_B3C
VREF_B3D
VCCBAT
AP30
AR32
AP22
VCCA_GXB
U29R
XCVR PWR
AP10
AP16
AH32
AD32
Y32
T32
E15
E18
F9
E26
E31
AH8
AD8
Y8
T8
1p5V
AD12
AE19
AF29
R11
R19
T28
AF31
AG31
AB31
AC31
V31
W31
P31
R31
2p5V_FLTR
AJ11
AJ31
AN20
H20
L10
M30
AF9
AG9
AB9
AC9
V9
W9
P9
R9
VCCR_GTB
AJ32
AJ9
AJ10
AK1
AK2
AC3
AC4
R3
R4
D1
D2
R288
27
VREF_B4A
VREF_B4B
VREF_B4C
VREF_B4D
VCCT_GTB
D26
AT1
AT2
AF1
AF2
V1
V2
K1
K2
VREF_B7A
VREF_B7B
VREF_B7C
VREF_B7D
VREF_B8A
VREF_B8C
VREF_B8D
VCCR_GXB_BL0
VCCR_GXB_BL1
VCCR_GXB_BL2
VCCR_GXB_BL3
VCCA_GXB_BL0
VCCA_GXB_BL1
VCCA_GXB_BL2
VCCA_GXB_BL3
VCCR_GXB_BR0
VCCR_GXB_BR1
VCCR_GXB_BR2
VCCR_GXB_BR3
VCCA_GXB_BR0
VCCA_GXB_BR1
VCCA_GXB_BR2
VCCA_GXB_BR3
VCCT_GXB_BL0_1
VCCT_GXB_BL0_2
VCCT_GXB_BL1_1
VCCT_GXB_BL1_2
VCCT_GXB_BL2_1
VCCT_GXB_BL2_2
VCCT_GXB_BL3_1
VCCT_GXB_BL3_2
VCCH_GXB_BL0
VCCH_GXB_BL1
VCCH_GXB_BL2
VCCH_GXB_BL3
VCCH_GXB_BR0
VCCH_GXB_BR1
VCCH_GXB_BR2
VCCH_GXB_BR3
VCCT_GXB_BR0_1
VCCT_GXB_BR0_2
VCCT_GXB_BR1_1
VCCT_GXB_BR1_2
VCCT_GXB_BR2_1
VCCT_GXB_BR2_2
VCCT_GXB_BR3_1
VCCT_GXB_BR3_2
VCCHIP_L1
VCCHIP_L2
VCCHIP_L3
VCCHIP_L4
VCCHIP_L5
VCCHIP_L6
VCCR_GTB_BR0_1
VCCR_GTB_BR0_2
VCCR_GTB_BR1_1
VCCR_GTB_BR1_2
VCCR_GTB_BR2_1
VCCR_GTB_BR2_2
VCCR_GTB_BR3_1
VCCR_GTB_BR3_2
VCCHIP_R1
VCCHIP_R2
VCCHIP_R3
VCCHIP_R4
VCCHIP_R5
VCCHIP_R6
VCCT_GTB_BR0_1
VCCT_GTB_BR0_2
VCCT_GTB_BR1_1
VCCT_GTB_BR1_2
VCCT_GTB_BR2_1
VCCT_GTB_BR2_2
VCCT_GTB_BR3_1
VCCT_GTB_BR3_2
VCCL_GTB_BR0_1
VCCL_GTB_BR0_2
VCCL_GTB_BR1_1
VCCL_GTB_BR1_2
VCCL_GTB_BR2_1
VCCL_GTB_BR2_2
VCCL_GTB_BR3_1
VCCL_GTB_BR3_2
AE33
AA33
U33
N33
AE7
AA7
U7
N7
1p5V
AF33
AB33
V33
P33
C
AF7
AB7
V7
P7
S5GX_VCC
AA24
V25
W24
W25
Y24
Y25
AA16
V15
W15
W16
Y15
Y16
VCCL_GTB
AL3
AL4
AE3
AE4
U3
U4
G3
G4
B
1
A36
AW36
A4
AW4
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
5SGXEA7N2F40
R289
1.8K
R290
1.8K
BT1
R292
1.8K
5SGXEA7N2F40
C304
0.1uF
5SGXEA7N2F40
2
R291
1.8K
A
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
35
of
36
D
5
4
3
2
1
GROUND
U29U
D
C
B
A
A35
A37
A38
AA34
AA35
AA38
AA39
AB32
AB36
AB37
AC34
AC35
AC38
AC39
AD31
AD33
AD36
AD37
AE34
AE35
AE38
AE39
AF32
AF36
AF37
AG34
AG35
AG38
AG39
AH31
AH33
AH36
AH37
AJ34
AJ35
AJ38
AJ39
AK36
AK37
AL34
AL35
AL38
AL39
AM36
AM37
AN38
AN39
AP36
AP37
AR35
AR38
AR39
AT35
AT36
AT37
AU35
AU38
AU39
AV35
AV36
AV37
AW37
AW38
B35
B36
B37
C35
C38
C39
D35
D36
D37
E35
E38
E39
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
5SGXEA7N2F40
U29V
GND
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
F35
F36
F37
G35
G38
G39
H35
H36
H37
J34
J35
J38
J39
K36
K37
L34
L35
L38
L39
M31
M36
M37
N34
N35
N38
N39
P32
P36
P37
R34
R35
R38
R39
T31
T33
T36
T37
U34
U35
U38
U39
V32
V36
V37
W34
W35
W38
W39
Y31
Y33
Y36
Y37
A2
A3
A5
AA1
AA2
AA5
AA6
AB3
AB4
AB8
AC1
AC2
AC5
AC6
AD3
AD4
AD7
AD9
AE1
AE2
AE5
AE6
AF3
AF4
AF8
AG1
AG2
AG5
AG6
AH3
AH4
AH7
AH9
AJ1
AJ2
AJ5
AJ6
AK3
AK4
AL1
AL2
AL5
AL6
AM3
AM4
AN1
AN2
AP3
AP4
AR1
AR2
AR5
AT3
AT4
AT5
AU1
AU2
AU5
AV3
AV4
AV5
AW2
AW3
B3
B4
B5
C1
C2
C5
D3
D4
D5
E1
E2
E5
F3
F4
F5
G1
G2
G5
H3
H4
H5
J1
J2
J5
J6
K3
K4
L1
L2
L5
L6
M3
M4
M9
N1
U29W
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
GND223
GND224
GND225
5SGXEA7N2F40
GND
GND226
GND227
GND228
GND229
GND230
GND231
GND232
GND233
GND234
GND235
GND236
GND237
GND238
GND239
GND240
GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252
GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
N2
N5
N6
P3
P4
P8
R1
R2
R5
R6
T3
T4
T7
T9
U1
U2
U5
U6
V3
V4
V8
W1
W2
W5
W6
Y3
Y4
Y7
Y9
AA10
AA15
AA25
AA28
AA30
AB11
AB14
AB19
AB23
AB24
AB26
AB30
AC17
AD10
AD13
AD16
AD18
AD20
AD22
AD25
AD28
AE10
AE30
AF10
AF12
AF15
AF18
AF21
AF24
AF27
AF30
AG10
AG30
AH10
AH11
AH14
AH17
AH20
AH23
AH26
AH29
AH30
AJ33
AJ7
AJ8
AK10
AK13
AK16
AK19
AK22
AK25
AK28
AK31
AK33
AK7
AL33
AL7
AM12
AM15
AM18
AM21
AM24
AM27
AM30
AM35
AM5
AM6
AM9
AN35
AN5
AP11
AP14
AP17
AP20
AP23
AP26
AP29
AP32
AP35
AP5
AP8
AT10
AT13
AT16
AT19
AT22
AT25
AT28
AT31
AT34
AT7
AV12
AV15
AV18
AV21
AV24
AV27
AV30
AV33
AV6
AV9
B12
B15
B18
B21
B24
B27
B30
B33
B6
B9
D11
D14
D17
D20
D23
D26
D29
D32
D8
F10
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343
GND344
GND345
GND346
GND347
GND348
GND349
GND350
GND351
GND352
GND353
GND354
GND355
GND356
GND357
GND358
GND359
GND360
GND361
GND362
GND363
GND364
GND365
GND366
GND367
GND368
GND369
GND370
GND371
GND372
GND373
GND374
GND375
GND
GND376
GND377
GND378
GND379
GND380
GND381
GND382
GND383
GND384
GND385
GND386
GND387
GND388
GND389
GND390
GND391
GND392
GND393
GND394
GND395
GND386
GND397
GND398
GND399
GND400
GND401
GND402
GND403
GND404
GND405
GND406
GND407
GND408
GND409
GND410
GND411
GND412
GND413
GND414
GND415
GND416
GND417
GND418
GND419
GND420
GND421
GND422
GND423
GND424
GND425
GND426
GND427
GND428
GND429
GND430
GND431
GND432
GND433
GND434
GND435
GND436
GND437
GND438
GND439
GND440
GND441
GND442
GND443
GND444
GND445
GND446
GND447
GND448
GND449
GND450
F13
F16
F19
F22
F25
F28
F31
F34
F7
H12
H15
H18
H21
H24
H27
H30
H33
H9
J33
J7
K11
K14
K17
K20
K23
K26
K29
K32
K33
K7
K8
L33
L7
M10
M13
M16
M19
M22
M25
M28
M32
M33
M7
M8
N10
N30
P12
P15
P18
P21
P24
P27
P30
T10
T11
T14
T18
T20
T22
T26
T29
U10
U19
U23
U30
V10
V13
V16
V22
V24
V28
V30
W10
W14
W20
D
U29X
W26
W30
Y10
Y13
Y17
Y19
Y23
Y27
Y30
AB21
T12
AW34
AW35
V27
AF20
AW5
AW6
H6
N22
AA21
GND451
GND452
GND453
GND454
GND455
GND456
GND457
GND458
GND459
GND460
GND461
GND
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
AB5
AB6
AD5
AD6
AF5
AF6
AK5
AK6
AN3
AN4
AR3
AR4
E3
E4
J3
J4
K5
K6
P5
P6
T5
T6
V5
V6
C
B
5SGXEA7N2F40
5SGXEA7N2F40
A
Altera Corporation, 101 Innovation Drive, San Jose, CA
Title
Stratix V GX SI Development Board
Size
B
Date:
5
4
3
2
Rev
Document Number
150-0320305-D1 (6XX-44151R)
Thursday, June 28, 2012
Sheet
1
36
of
36
D
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