CY8C28xxx TRM CY8C28xxx PSoC® Programmable System-on-Chip™ TRM (Technical Reference Manual) Document No. 001-52594 Rev. *F July 5, 2013 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com Copyrights Copyrights Copyright © 2009-2013 Cypress Semiconductor Corporation. All rights reserved. PSoC® is a registered trademark and PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks of Cypress Semiconductor Corporation (Cypress), along with Cypress® and Cypress Semiconductor™. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. The information in this document is subject to change without notice and should not be construed as a commitment by Cypress. While reasonable precautions have been taken, Cypress assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Cypress. Made in the U.S.A. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Flash Code Protection Cypress products meet the specifications contained in their particular Cypress Data Sheets. Cypress believes that its family of PSoC products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. 2 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Contents Overview Section A: Overview 1. Section B: PSoC® Core 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 21 Pin Information .................................................................................................................... 29 35 CPU Core (M8C) ................................................................................................................. 39 Supervisory ROM (SROM) ................................................................................................... 49 RAM Paging ........................................................................................................................ 57 Interrupt Controller .............................................................................................................. 65 General Purpose I/O (GPIO) ................................................................................................ 73 Analog Output Drivers ......................................................................................................... 79 Internal Main Oscillator (IMO) .............................................................................................. 81 Internal Low Speed Oscillator (ILO) ..................................................................................... 85 External Crystal Oscillator (ECO)......................................................................................... 87 Phase-Locked Loop (PLL) ................................................................................................... 93 Sleep and Watchdog ........................................................................................................... 97 Section C: Register Reference 109 13. Register Details................................................................................................................. 125 Section D: Digital System 14. 15. 16. 17. Section E: Analog System 18. 19. 20. 21. 311 Global Digital Interconnect (GDI) ....................................................................................... 317 Array Digital Interconnect (ADI) ......................................................................................... 325 Row Digital Interconnect (RDI) .......................................................................................... 327 Digital Blocks .................................................................................................................... 335 Analog Analog Analog Analog 383 Interface ................................................................................................................ 393 Array ..................................................................................................................... 409 Input Configuration ................................................................................................ 417 Reference ............................................................................................................. 421 22. Continuous Time PSoC ® Block .......................................................................................... 425 23. Switched Capacitor PSoC ® Block ...................................................................................... 431 24. Two Column Limited Analog System .................................................................................. 441 Section F: System Resources 461 25. Digital Clocks .................................................................................................................... 465 26. Multiply Accumulate (MAC)................................................................................................ 477 27. Decimator ......................................................................................................................... 483 28. 29. 30. 31. 32. I 2 C .................................................................................................................................... 493 Internal Voltage Reference ................................................................................................ 511 System Resets .................................................................................................................. 513 Switch Mode Pump (SMP) ................................................................................................. 519 POR and LVD .................................................................................................................... 523 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F iii Contents Overview 33. I/O Analog Multiplexer....................................................................................................... 525 34. Real Time Clock (RTC) ..................................................................................................... 533 35. 10-Bit SAR ADC Controller ............................................................................................... 537 Section H: Glossary 545 Index 561 iv CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Contents Section A: Overview 21 Document Organization ...................................................................................................................21 Top Level Architecture .....................................................................................................................22 PSoC Core ..............................................................................................................................22 Digital System .........................................................................................................................22 Analog System ........................................................................................................................22 System Resources ..................................................................................................................22 PSoC Device Characteristics ...........................................................................................................24 PSoC Device Distinctions ................................................................................................................25 Getting Started .................................................................................................................................26 Support ...................................................................................................................................26 Product Upgrades ...................................................................................................................26 Development Kits ....................................................................................................................26 Document History .............................................................................................................................26 Documentation Conventions ............................................................................................................27 Register Conventions ..............................................................................................................27 Numeric Naming .....................................................................................................................27 Units of Measure .....................................................................................................................27 Acronyms ................................................................................................................................28 1. Pin Information 1.1 29 Pinouts for the CY8C28xxx.....................................................................................................29 1.1.1 20-Pin Part Pinouts ...................................................................................................30 1.1.2 28-Pin Part Pinouts ....................................................................................................31 1.1.3 44-Pin Part Pinouts ...................................................................................................32 1.1.4 48-Pin Part Pinouts ...................................................................................................33 1.1.5 56-Pin Part Pinout......................................................................................................34 Section B: PSoC® Core 35 Top Level Core Architecture ............................................................................................................35 Interpreting the Core Documentation ...............................................................................................35 Core Register Summary ...................................................................................................................36 2. CPU Core (M8C) 2.1 2.2 2.3 2.4 2.5 39 Overview.................................................................................................................................39 Internal Registers....................................................................................................................39 Address Spaces......................................................................................................................39 Instruction Set Summary ........................................................................................................40 Instruction Formats .................................................................................................................42 2.5.1 One-Byte Instructions ................................................................................................42 2.5.2 Two-Byte Instructions ................................................................................................42 2.5.3 Three-Byte Instructions..............................................................................................43 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F v Contents 2.6 2.7 3. Supervisory ROM (SROM) 3.1 3.2 3.3 4. 4.2 49 Architectural Description......................................................................................................... 49 3.1.1 Additional SROM Feature.......................................................................................... 50 3.1.2 SROM Function Descriptions .................................................................................... 50 3.1.2.1 SWBootReset Function ............................................................................... 50 3.1.2.2 HWBootReset Function............................................................................... 51 3.1.2.3 ReadBlock Function .................................................................................... 51 3.1.2.4 WriteBlock Function .................................................................................... 52 3.1.2.5 EraseBlock Function ................................................................................... 52 3.1.2.6 ProtectBlock Function ................................................................................. 52 3.1.2.7 TableRead Function .................................................................................... 52 3.1.2.8 EraseAll Function ........................................................................................ 53 3.1.2.9 Checksum Function..................................................................................... 53 3.1.2.10 Calibrate0 Function ..................................................................................... 53 3.1.2.11 Calibrate1 Function ..................................................................................... 53 3.1.2.12 WriteAndVerify Function.............................................................................. 54 Register Definitions ................................................................................................................ 54 3.2.1 FLS_PR1 Register .................................................................................................... 54 3.2.2 Related Registers ...................................................................................................... 54 Clocking Strategy ................................................................................................................... 55 3.3.1 DELAY Parameter ..................................................................................................... 55 3.3.2 CLOCK Parameter .................................................................................................... 55 RAM Paging 4.1 vi Addressing Modes.................................................................................................................. 43 2.6.1 Source Immediate ..................................................................................................... 43 2.6.2 Source Direct.............................................................................................................44 2.6.3 Source Indexed ......................................................................................................... 44 2.6.4 Destination Direct ...................................................................................................... 45 2.6.5 Destination Indexed................................................................................................... 45 2.6.6 Destination Direct Source Immediate ........................................................................ 45 2.6.7 Destination Indexed Source Immediate..................................................................... 46 2.6.8 Destination Direct Source Direct ............................................................................... 46 2.6.9 Source Indirect Post Increment ................................................................................. 47 2.6.10 Destination Indirect Post Increment........................................................................... 47 Register Definitions ................................................................................................................ 48 2.7.1 CPU_F Register ....................................................................................................... 48 57 Architectural Description......................................................................................................... 57 4.1.1 Basic Paging..............................................................................................................57 4.1.2 Stack Operations ....................................................................................................... 58 4.1.3 Interrupts ................................................................................................................... 58 4.1.4 MVI Instructions......................................................................................................... 58 4.1.5 Current Page Pointer................................................................................................. 58 4.1.6 Index Memory Page Pointer ...................................................................................... 59 Register Definitions ................................................................................................................ 60 4.2.1 TMP_DRx Registers.................................................................................................. 60 4.2.2 CUR_PP Register...................................................................................................... 60 4.2.3 STK_PP Register ...................................................................................................... 61 4.2.4 IDX_PP Register ....................................................................................................... 61 4.2.5 MVR_PP Register ..................................................................................................... 61 4.2.6 MVW_PP Register .................................................................................................... 62 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Contents 4.2.7 4.2.8 4.2.9 4.2.10 5. Interrupt Controller 5.1 5.2 5.3 6. 6.2 8. 8.3 79 Architectural Description.........................................................................................................79 Register Definitions.................................................................................................................80 7.2.1 ABF_CR0 Register ....................................................................................................80 Internal Main Oscillator (IMO) 8.1 8.2 73 Architectural Description.........................................................................................................73 6.1.1 Digital I/O ..................................................................................................................73 6.1.2 Global I/O ..................................................................................................................73 6.1.3 Analog Input ..............................................................................................................74 6.1.4 GPIO Block Interrupts ................................................................................................75 Register Definitions.................................................................................................................76 6.2.1 PRTxDR Registers ....................................................................................................76 6.2.2 PRTxIE Registers .....................................................................................................76 6.2.3 PRTxGS Registers ....................................................................................................76 6.2.4 PRTxDMx Registers ..................................................................................................77 6.2.5 PRTxICx Registers ....................................................................................................77 Analog Output Drivers 7.1 7.2 65 Architectural Description.........................................................................................................65 5.1.1 Posted versus Pending Interrupts..............................................................................66 Application Description ...........................................................................................................67 Register Definitions.................................................................................................................68 5.3.1 INT_CLRx Registers .................................................................................................68 5.3.1.1 INT_CLR0 Register .....................................................................................68 5.3.1.2 INT_CLR1 Register .....................................................................................69 5.3.1.3 INT_CLR2 Register .....................................................................................69 5.3.1.4 INT_CLR3 Register .....................................................................................69 5.3.2 INT_MSKx Registers ................................................................................................70 5.3.2.1 INT_MSK3 Register.....................................................................................70 5.3.2.2 INT_MSK2 Register.....................................................................................70 5.3.2.3 INT_MSK0 Register.....................................................................................70 5.3.2.4 INT_MSK1 Register.....................................................................................71 5.3.3 INT_VC Register........................................................................................................71 5.3.4 CPU_F Register ........................................................................................................72 General Purpose I/O (GPIO) 6.1 7. CPU_F Register.........................................................................................................62 MVR_PP Register......................................................................................................62 MVW_PP Register ....................................................................................................63 CPU_F Register.........................................................................................................63 81 Architectural Description.........................................................................................................81 Application Description ...........................................................................................................81 8.2.1 Trimming the IMO ......................................................................................................81 8.2.2 Engaging Slow IMO ...................................................................................................81 Register Definitions.................................................................................................................82 8.3.1 CPU_SCR1 Register .................................................................................................82 8.3.2 OSC_CR2 Register ...................................................................................................82 8.3.3 IMO_TR Register .......................................................................................................83 8.3.4 IMO_TR1 Register.....................................................................................................83 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F vii Contents 9. Internal Low Speed Oscillator (ILO) 9.1 9.2 85 Architectural Description.........................................................................................................85 Register Definitions ...............................................................................................................85 9.2.1 ILO_TR Register .......................................................................................................85 10. External Crystal Oscillator (ECO) 87 10.1 Architectural Description.........................................................................................................87 10.1.1 ECO External Components .......................................................................................88 10.2 Register Definitions ...............................................................................................................89 10.2.1 CPU_SCR1 Register ................................................................................................89 10.2.2 OSC_CR0 Register ..................................................................................................90 10.2.3 OSC_CR2 Register ..................................................................................................91 10.2.4 ECO_TR Register .....................................................................................................91 11. Phase-Locked Loop (PLL) 93 11.1 Architectural Description.........................................................................................................93 11.2 Register Definitions ................................................................................................................93 11.2.1 OSC_CR0 Register ...................................................................................................94 11.2.2 OSC_CR2 Register ...................................................................................................95 12. Sleep and Watchdog 97 12.1 Architectural Description.........................................................................................................97 12.1.1 32 kHz Clock Selection..............................................................................................97 12.1.2 Sleep Timer ...............................................................................................................97 12.2 Application Description ...........................................................................................................98 12.3 Register Definitions ................................................................................................................99 12.3.1 INT_MSK0 Register...................................................................................................99 12.3.2 RES_WDT Register...................................................................................................99 12.3.3 CPU_SCR1 Register ...............................................................................................100 12.3.4 CPU_SCR0 Register ...............................................................................................101 12.3.5 OSC_CR0 Register .................................................................................................102 12.3.6 OSC_CR2 Register ................................................................................................103 12.3.7 ILO_TR Register......................................................................................................103 12.3.8 ECO_TR Register....................................................................................................104 12.4 Timing Diagrams ..................................................................................................................104 12.4.1 Sleep Sequence ......................................................................................................104 12.4.2 Wakeup Sequence ..................................................................................................105 12.4.3 Bandgap Refresh.....................................................................................................107 12.4.4 Watchdog Timer.......................................................................................................107 12.5 Power Consumption .............................................................................................................108 Section C: Register Reference 109 Register General Conventions .......................................................................................................109 Register Naming Conventions .......................................................................................................109 Register Mapping Tables ...............................................................................................................109 CY8C28x03 Register Maps ..................................................................................................110 Register Map Bank 0 Table: User Space .................................................................110 Register Map Bank 1 Table: Configuration Space ...................................................111 CY8C28x13 Register Maps ..................................................................................................112 Register Map Bank 0 Table: User Space .................................................................112 Register Map Bank 1 Table: Configuration Space ...................................................113 viii CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CY8C28x23 Register Maps ...................................................................................................114 Register Map Bank 0 Table: User Space .................................................................114 Register Map Bank 1 Table: Configuration Space ...................................................115 CY8C28x33 Register Maps ...................................................................................................116 Register Map Bank 0 Table: User Space .................................................................116 Register Map Bank 1 Table: Configuration Space ...................................................117 CY8C28x43 Register Maps ...................................................................................................118 Register Map Bank 0 Table: User Space .................................................................118 Register Map Bank 1 Table: Configuration Space ...................................................119 CY8C28x45 Register Maps ...................................................................................................120 Register Map Bank 0 Table: User Space .................................................................120 Register Map Bank 1 Table: Configuration Space ...................................................121 CY8C28x52 Register Maps ...................................................................................................122 Register Map Bank 0 Table: User Space .................................................................122 Register Map Bank 1 Table: Configuration Space ...................................................123 13. Register Details 125 13.1 Maneuvering Around the Registers ......................................................................................125 Register Conventions ............................................................................................................126 13.1.1 Register Naming Conventions .................................................................................126 13.2 Bank 0 Registers ..................................................................................................................127 13.2.1 PRTxDR ..................................................................................................................127 13.2.2 PRTxIE ...................................................................................................................128 13.2.3 PRTxGS ..................................................................................................................129 13.2.4 PRTxDM2 ...............................................................................................................130 13.2.5 DxCxxDR0 ..............................................................................................................131 13.2.6 DxCxxDR1 ..............................................................................................................132 13.2.7 DxCxxDR2 ..............................................................................................................133 13.2.8 DxCxxCR0 (Timer Control:000) ..............................................................................134 13.2.9 DxCxxCR0 (Counter Control:001) ..........................................................................135 13.2.10 DxCxxCR0 (Dead Band Control:100) .....................................................................136 13.2.11 DxCxxCR0 (CRCPRS Control:010) ........................................................................137 13.2.12 DxCxxCR0 (PWMDBL Control:011) .......................................................................138 13.2.13 DCCxxCR0 (SPIM Control:0-110) ..........................................................................140 13.2.14 DCCxxCR0 (SPIS Control:1-110) ...........................................................................141 13.2.15 DxCxxCR0 (DSM Control:111) ...............................................................................142 13.2.16 DCCxxCR0 (UART Transmitter Control) ................................................................143 13.2.17 DCCxxCR0 (UART Receiver Control) ....................................................................144 13.2.18 AMX_IN ..................................................................................................................145 13.2.19 AMUX_CFG ............................................................................................................146 13.2.20 CLK_CR3 ................................................................................................................147 13.2.21 ARF_CR .................................................................................................................148 13.2.22 CMP_CR0 ...............................................................................................................149 13.2.23 ASY_CR .................................................................................................................150 13.2.24 CMP_CR1 ...............................................................................................................151 13.2.25 SADC_DH ...............................................................................................................153 13.2.26 SADC_DL ...............................................................................................................154 13.2.27 TMP_DRx ...............................................................................................................155 13.2.28 ACCxxCR3 .............................................................................................................156 13.2.29 ACCxxCR0 .............................................................................................................157 13.2.30 ACCxxCR1 .............................................................................................................159 13.2.31 ACCxxCR2 .............................................................................................................160 13.2.32 ASCxxCR0 ..............................................................................................................161 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ix Contents 13.2.33 ASCxxCR1 .............................................................................................................162 13.2.34 ASCxxCR2 .............................................................................................................163 13.2.35 ASCxxCR3 .............................................................................................................164 13.2.36 ASDxxCR0 .............................................................................................................165 13.2.37 ASDxxCR1 .............................................................................................................166 13.2.38 ASDxxCR2 .............................................................................................................167 13.2.39 ASDxxCR3 .............................................................................................................168 13.2.40 DECx_DH ...............................................................................................................169 13.2.41 DECx_DL ................................................................................................................170 13.2.42 MULx_X ..................................................................................................................171 13.2.43 MULx_Y ..................................................................................................................172 13.2.44 MULx_DH ...............................................................................................................173 13.2.45 MULx_DL ................................................................................................................174 13.2.46 MACx_X/ACCx_DR1 ..............................................................................................175 13.2.47 MACx_Y/ACCx_DR0 ..............................................................................................176 13.2.48 MACx_CL0/ACCx_DR3 ..........................................................................................177 13.2.49 MACx_CL1/ACCx_DR2 ..........................................................................................178 13.2.50 RDIxRI ....................................................................................................................179 13.2.51 RDIxSYN ................................................................................................................180 13.2.52 RDIxIS ....................................................................................................................181 13.2.53 RDIxLT0 .................................................................................................................182 13.2.54 RDIxLT1 .................................................................................................................184 13.2.55 RDIxRO0 ................................................................................................................186 13.2.56 RDIxRO1 ................................................................................................................187 13.2.57 RDIxDSM ................................................................................................................188 13.2.58 CUR_PP .................................................................................................................189 13.2.59 STK_PP ..................................................................................................................190 13.2.60 IDX_PP ...................................................................................................................191 13.2.61 MVR_PP .................................................................................................................192 13.2.62 MVW_PP ................................................................................................................193 13.2.63 I2Cx_CFG ...............................................................................................................194 13.2.64 I2Cx_SCR ...............................................................................................................195 13.2.65 I2Cx_DR .................................................................................................................197 13.2.66 I2Cx_MSCR ............................................................................................................198 13.2.67 INT_CLR0 ...............................................................................................................199 13.2.68 INT_CLR1 ...............................................................................................................201 13.2.69 INT_CLR2 ...............................................................................................................203 13.2.70 INT_CLR3 ...............................................................................................................204 13.2.71 INT_MSK3 ..............................................................................................................206 13.2.72 INT_MSK2 ..............................................................................................................207 13.2.73 INT_MSK0 ..............................................................................................................208 13.2.74 INT_MSK1 ..............................................................................................................209 13.2.75 INT_VC ...................................................................................................................210 13.2.76 RES_WDT ..............................................................................................................211 13.2.77 DEC_CR0 ...............................................................................................................212 13.2.78 DEC_CR1 ...............................................................................................................213 13.2.79 CPU_F ....................................................................................................................214 13.2.80 IDACx_D .................................................................................................................215 13.2.81 CPU_SCR1 ............................................................................................................216 13.2.82 CPU_SCR0 ............................................................................................................217 13.3 Bank 1 Registers ..................................................................................................................218 13.3.1 PRTxDM0 ...............................................................................................................218 13.3.2 PRTxDM1 ...............................................................................................................219 x CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 13.3.3 PRTxIC0 .................................................................................................................220 13.3.4 PRTxIC1 .................................................................................................................221 13.3.5 DxCxxFN ................................................................................................................222 13.3.6 DxCxxIN ..................................................................................................................224 13.3.7 DxCxxOU ................................................................................................................226 13.3.8 DxCxxCR1 (Timer Control:000) ..............................................................................228 13.3.9 DxCxxCR1 (Counter Control:001) ..........................................................................229 13.3.10 DxCxxCR1 (CRCPRS Control:010) ........................................................................230 13.3.11 DxCxxCR1 (PWMDBL Control:011) .......................................................................231 13.3.12 DxCxxCR1 (Dead Band Control:100) .....................................................................232 13.3.13 DxCxxCR1 (SPIM Control:0-110) ...........................................................................233 13.3.14 DxCxxCR1 (SPIS Control:0-110) ............................................................................234 13.3.15 DxCxxCR1 (DSM Control:111) ...............................................................................235 13.3.16 CLK_CR0 ................................................................................................................236 13.3.17 CLK_CR1 ................................................................................................................237 13.3.18 ABF_CR0 ................................................................................................................238 13.3.19 AMD_CR0 ...............................................................................................................239 13.3.20 CMP_GO_EN .........................................................................................................240 13.3.21 CMP_GO_EN1 .......................................................................................................241 13.3.22 AMD_CR1 ...............................................................................................................242 13.3.23 ALT_CR0 ................................................................................................................243 13.3.24 ALT_CR1 ................................................................................................................244 13.3.25 CLK_CR2 ................................................................................................................245 13.3.26 AMUX_CFG1 ..........................................................................................................246 13.3.27 SADC_TSCR0 ........................................................................................................247 13.3.28 SADC_TSCR1 ........................................................................................................248 13.3.29 ACE_AMD_CR0 .....................................................................................................249 13.3.30 ACE_AMX_IN .........................................................................................................250 13.3.31 ACE_CMP_CR0 .....................................................................................................251 13.3.32 ACE_CMP_CR1 .....................................................................................................252 13.3.33 ACE_CMP_GI_EN ..................................................................................................253 13.3.34 ACE_ALT_CR0 .......................................................................................................254 13.3.35 ACE_ABF_CR0 .....................................................................................................255 13.3.36 ACExxCR1 ..............................................................................................................256 13.3.37 ACExxCR2 ..............................................................................................................257 13.3.38 ASExxCR0 ..............................................................................................................258 13.3.39 SADC_TSCMPL .....................................................................................................259 13.3.40 SADC_TSCMPH .....................................................................................................260 13.3.41 ACE_AMD_CR1 .....................................................................................................261 13.3.42 ACE_PWM_CR ......................................................................................................262 13.3.43 ACE_ADCx_CR ......................................................................................................263 13.3.44 ACE_CLK_CR0 ......................................................................................................264 13.3.45 ACE_CLK_CR1 ......................................................................................................265 13.3.46 ACE_CLK_CR3 ......................................................................................................266 13.3.47 DECx_CR0 .............................................................................................................267 13.3.48 DEC_CR3 ...............................................................................................................268 13.3.49 DEC_CR4 ...............................................................................................................269 13.3.50 DEC_CR5 ...............................................................................................................270 13.3.51 GDI_O_IN_CR ........................................................................................................271 13.3.52 GDI_E_IN_CR ........................................................................................................272 13.3.53 GDI_O_OU_CR ......................................................................................................273 13.3.54 GDI_E_OU_CR ......................................................................................................274 13.3.55 RTC_H ....................................................................................................................275 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F xi Contents 13.3.56 RTC_M ...................................................................................................................276 13.3.57 RTC_S ....................................................................................................................277 13.3.58 RTC_CR .................................................................................................................278 13.3.59 SADC_CR0 ............................................................................................................279 13.3.60 SADC_CR1 ............................................................................................................280 13.3.61 SADC_CR2 ............................................................................................................281 13.3.62 SADC_CR3 ............................................................................................................282 13.3.63 SADC_CR4 ............................................................................................................283 13.3.64 I2Cx_ADDR ............................................................................................................284 13.3.65 AMUX_CLK ............................................................................................................285 13.3.66 GDI_O_IN ...............................................................................................................286 13.3.67 GDI_E_IN ...............................................................................................................287 13.3.68 GDI_O_OU .............................................................................................................288 13.3.69 GDI_E_OU .............................................................................................................289 13.3.70 DECx_CR ...............................................................................................................290 13.3.71 MUX_CRx ...............................................................................................................291 13.3.72 IDAC_CR1 ..............................................................................................................292 13.3.73 OSC_GO_EN .........................................................................................................293 13.3.74 OSC_CR4 ...............................................................................................................294 13.3.75 OSC_CR3 ...............................................................................................................295 13.3.76 OSC_CR0 ...............................................................................................................296 13.3.77 OSC_CR1 ...............................................................................................................297 13.3.78 OSC_CR2 ...............................................................................................................298 13.3.79 VLT_CR ..................................................................................................................299 13.3.80 VLT_CMP ...............................................................................................................300 13.3.81 ADCx_TR ...............................................................................................................301 13.3.82 IDAC_MODE ..........................................................................................................302 13.3.83 IMO_TR ..................................................................................................................303 13.3.84 ILO_TR ...................................................................................................................304 13.3.85 BDG_TR .................................................................................................................305 13.3.86 ECO_TR .................................................................................................................306 13.3.87 IMO_TR1 ................................................................................................................307 13.3.88 FLS_PR1 ................................................................................................................308 13.3.89 IDAC_CR0 ..............................................................................................................309 Section D: Digital System 311 Top-Level Digital Architecture ........................................................................................................311 Interpreting the Digital Documentation ...........................................................................................311 Digital Register Summary ..............................................................................................................312 14. Global Digital Interconnect (GDI) 317 14.1 Architectural Description.......................................................................................................317 14.1.1 20-Pin Global Interconnect ......................................................................................318 14.1.2 28-Pin Global Interconnect ......................................................................................319 14.1.3 44-Pin Global Interconnect ......................................................................................320 14.1.4 48-Pin Global Interconnect ......................................................................................321 14.1.5 56-Pin Global Interconnect ......................................................................................322 14.2 Register Definitions ..............................................................................................................322 14.2.1 GDI_x_IN Registers/GDI_x_IN_CR Registers.........................................................322 14.2.2 GDI_x_OU/GDI_x_OU_CR Registers .....................................................................323 xii CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 15. Array Digital Interconnect (ADI) 325 15.1 Architectural Description.......................................................................................................325 16. Row Digital Interconnect (RDI) 327 16.1 Architectural Description.......................................................................................................327 16.2 Register Definitions...............................................................................................................329 16.2.1 RDIxRI Register.......................................................................................................329 16.2.2 RDIxSYN Register ...................................................................................................330 16.2.3 RDIxIS Register .......................................................................................................331 16.2.4 RDIxLTx Registers ...................................................................................................332 16.2.5 RDIxROx Registers .................................................................................................333 16.2.5.1 RDIxRO0 Register.....................................................................................333 16.2.5.2 RDIxRO1 Register.....................................................................................333 16.2.6 RDIxDSM Register ..................................................................................................334 16.3 Timing Diagram ....................................................................................................................334 17. Digital Blocks 335 17.1 Architectural Description.......................................................................................................335 17.1.1 Input Multiplexers.....................................................................................................336 17.1.2 Input Clock Resynchronization ................................................................................336 17.1.2.1 Clock Resynchronization Summary...........................................................337 17.1.3 Output Demultiplexers .............................................................................................337 17.1.4 Block Chaining Signals ............................................................................................337 17.1.5 Input Data Synchronization......................................................................................337 17.1.6 Timer Function ........................................................................................................337 17.1.6.1 Usability Exceptions ..................................................................................338 17.1.6.2 Block Interrupt ...........................................................................................338 17.1.7 Counter Function .....................................................................................................338 17.1.7.1 Counter Timing ..........................................................................................338 17.1.7.2 Usability Exceptions ..................................................................................339 17.1.7.3 Block Interrupt ...........................................................................................339 17.1.8 Dead Band Function ................................................................................................339 17.1.8.1 Usability Exceptions ..................................................................................340 17.1.8.2 Block Interrupt ...........................................................................................340 17.1.9 PWMDBL Function ..................................................................................................340 17.1.9.1 Usability Exceptions ..................................................................................341 17.1.9.2 Block Interrupt ...........................................................................................341 17.1.10 CRCPRS Function ..................................................................................................341 17.1.10.1 Usability Exceptions ..................................................................................342 17.1.10.2 Block Interrupt ...........................................................................................342 17.1.11 SPI Protocol Function .............................................................................................343 17.1.11.1 SPI Protocol Signal Definitions..................................................................343 17.1.12 SPI Master Function ................................................................................................344 17.1.12.1 Usability Exceptions ..................................................................................344 17.1.12.2 Block Interrupt ...........................................................................................344 17.1.13 SPI Slave Function ..................................................................................................344 17.1.13.1 Usability Exceptions ..................................................................................345 17.1.13.2 Block Interrupt ...........................................................................................345 17.1.14 Asynchronous Transmitter and Receiver Functions ................................................345 17.1.14.1 Asynchronous Transmitter Function..........................................................345 17.1.14.2 Usability Exceptions ..................................................................................346 17.1.14.3 Block Interrupt ...........................................................................................346 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F xiii Contents 17.1.14.4 Asynchronous Receiver Function..............................................................346 17.1.14.5 Usability Exceptions ..................................................................................346 17.1.14.6 Block Interrupt ...........................................................................................346 17.1.15 DSM function ...........................................................................................................346 17.1.15.1 Usability Exception ....................................................................................347 17.1.15.2 Block interrupt ...........................................................................................347 17.2 Register Definitions .............................................................................................................348 17.2.1 DxCxxDRx Registers ..............................................................................................349 17.2.1.1 Timer Register Definitions .........................................................................349 17.2.1.2 Counter Register Definitions .....................................................................350 17.2.1.3 Dead Band Register Definitions ................................................................350 17.2.1.4 PWMDBL Register Definitions ..................................................................351 17.2.1.5 CRCPRS Register Definitions ...................................................................351 17.2.1.6 SPI Master Register Definitions ................................................................352 17.2.1.7 SPI Slave Register Definitions ..................................................................352 17.2.1.8 Transmitter Register Definitions ................................................................352 17.2.1.9 Receiver Register Definitions ....................................................................353 17.2.1.10 DSM Register Definitions ..........................................................................353 17.2.2 DxCxxCR0 Register.................................................................................................353 17.2.3 DxCxxCR1 Register.................................................................................................357 17.2.4 INT_MSK1 Register ..............................................................................................359 17.2.5 DxCxxFN Registers ................................................................................................360 17.2.6 DxCxxIN Registers .................................................................................................361 17.2.7 DxCxxOU Registers ................................................................................................361 17.3 Timing Diagrams .................................................................................................................363 17.3.1 Timer Timing ...........................................................................................................363 17.3.2 Counter Timing .......................................................................................................366 17.3.3 Dead Band Timing ..................................................................................................367 17.3.3.1 Changing the PWM Duty Cycle .................................................................367 17.3.3.2 Kill Operation.............................................................................................368 17.3.4 PWMDBL Timing .....................................................................................................369 17.3.5 CRCPRS Timing .....................................................................................................370 17.3.6 SPI Mode Timing ....................................................................................................370 17.3.7 SPIM Timing ...........................................................................................................371 17.3.8 SPIS Timing ............................................................................................................374 17.3.9 Transmitter Timing ..................................................................................................377 17.3.10 Receiver Timing ......................................................................................................379 17.3.11 DSM Timing ............................................................................................................382 Section E: Analog System 383 Top Level Analog Architecture .......................................................................................................383 Interpreting the Analog Documentation .........................................................................................387 Application Description ..................................................................................................................387 Defining the Analog Blocks ...................................................................................................387 Analog Functionality ..............................................................................................................388 Analog Register Summary .............................................................................................................389 18. Analog Interface 393 18.1 Architectural Description.......................................................................................................393 18.1.1 Analog Data Bus Interface.......................................................................................394 18.1.2 Analog Comparator Bus Interface ...........................................................................394 18.1.3 Analog Column Clock Generation ...........................................................................394 xiv CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 18.1.3.1 Column Clock Synchronization..................................................................395 18.1.4 Decimator and Incremental ADC Interface ..............................................................395 18.1.4.1 Decimator ..................................................................................................395 18.1.4.2 Incremental ADC ......................................................................................395 18.1.5 Analog Modulator Interface (Mod Bits) ....................................................................396 18.1.6 Analog Synchronization Interface (Stalling) .............................................................396 18.2 Application Description .........................................................................................................396 18.2.1 SAR Hardware Acceleration ....................................................................................396 18.2.1.1 Architectural Description............................................................................396 18.2.1.2 Application Description ..............................................................................397 18.2.1.3 SAR Timing ...............................................................................................399 18.3 Register Definitions...............................................................................................................400 18.3.1 CLK_CR3 Register ..................................................................................................400 18.3.2 CMP_CR0 Register .................................................................................................401 18.3.3 ASY_CR Register ....................................................................................................402 18.3.4 CMP_CR1 Register .................................................................................................403 18.3.5 DEC_CR0 Register..................................................................................................403 18.3.6 DEC_CR1 Register..................................................................................................404 18.3.7 CLK_CR0 Register ..................................................................................................404 18.3.8 CLK_CR1 Register ..................................................................................................405 18.3.9 AMD_CR0 Register .................................................................................................405 18.3.10 CMP_GO_EN Register ............................................................................................406 18.3.11 CMP_GO_EN1 Register ..........................................................................................406 18.3.12 AMD_CR1 Register .................................................................................................407 18.3.13 ALT_CR0 Register ..................................................................................................407 18.3.14 ALT_CR1 Register ..................................................................................................407 18.3.15 CLK_CR2 Register .................................................................................................408 19. Analog Array 409 19.1 Architectural Description.......................................................................................................409 19.1.1 NMux Connections ..................................................................................................410 19.1.2 PMux Connections...................................................................................................411 19.1.3 RBotMux Connections .............................................................................................412 19.1.4 AMux Connections...................................................................................................413 19.1.5 CMux Connections ..................................................................................................414 19.1.6 BMux SC/SD Connections.......................................................................................415 19.1.7 Analog Comparator Bus .........................................................................................416 19.2 Temperature Sensing Capability .........................................................................................416 20. Analog Input Configuration 417 20.1 Architectural Description.......................................................................................................417 20.1.1 Six Column Analog Input Configuration ...................................................................418 20.2 Register Definitions .............................................................................................................419 20.2.1 AMX_IN Register ....................................................................................................419 20.2.2 ABF_CR0 Register .................................................................................................420 20.2.3 AMUX_CFG1 Register ...........................................................................................420 21. Analog Reference 421 21.1 Architectural Description.......................................................................................................421 21.2 Register Definitions ..............................................................................................................422 21.2.1 ARF_CR Register ...................................................................................................422 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F xv Contents 22. Continuous Time PSoC ® Block 425 22.1 Architectural Description ......................................................................................................425 22.2 Register Definitions .............................................................................................................426 22.2.1 ACCxxCR3 Register ...............................................................................................427 22.2.2 ACCxxCR0 Register ...............................................................................................429 22.2.3 ACCxxCR1 Register ...............................................................................................429 22.2.4 ACCxxCR2 Register ...............................................................................................430 23. Switched Capacitor PSoC ® Block 431 23.1 Architectural Description.......................................................................................................431 23.2 Application Description .........................................................................................................433 23.3 Register Definitions .............................................................................................................434 23.3.1 ASCxxCR0 Register ...............................................................................................435 23.3.2 ASCxxCR1 Register ...............................................................................................436 23.3.3 ASCxxCR2 Register ...............................................................................................436 23.3.4 ASCxxCR3 Register ...............................................................................................437 23.3.5 ASDxxCR0 Register ...............................................................................................438 23.3.6 ASDxxCR1 Register ...............................................................................................439 23.3.7 ASDxxCR2 Register ...............................................................................................439 23.3.8 ASDxxCR3 Register ...............................................................................................440 24. Two Column Limited Analog System 441 24.1 Architectural Description ......................................................................................................441 24.1.1 Analog Interface .....................................................................................................441 24.1.1.1 Analog Comparator Bus Interface ............................................................442 24.1.1.2 Analog Column Clock Generation ............................................................442 24.1.1.3 Single Slope ADC .....................................................................................442 24.1.1.4 PWM ADC Interface ..................................................................................444 24.1.1.5 Analog Modulator Interface (Mod Bits) .....................................................444 24.1.1.6 Sample and Hold Feature .........................................................................444 24.1.2 Analog Array ...........................................................................................................445 24.1.2.1 NMux Connections ...................................................................................445 24.1.2.2 PMux Connections ....................................................................................446 24.1.2.3 Temperature Sensing Capability ..............................................................446 24.1.3 Analog Input Configuration .....................................................................................446 24.1.4 Analog Reference ...................................................................................................450 24.1.5 Continuous Time PSoC Block ................................................................................450 24.1.6 Switched Capacitor PSoC Block .............................................................................450 24.1.6.1 Application Description for the SC Block ...................................................450 24.2 PSoC Device Distinctions .....................................................................................................450 24.3 Register Definitions .............................................................................................................452 24.3.1 Summary Table for Two Column Limited Analog System Registers .......................452 24.3.2 DEC_CR0 Register..................................................................................................453 24.3.3 DEC_CR1 Register..................................................................................................453 24.3.4 ADCx_TR Register .................................................................................................454 24.3.5 ACE_AMD_CR0 Register .......................................................................................454 24.3.6 ACE_AMX_IN Register ...........................................................................................454 24.3.7 ACE_CMP_CR0 Register .....................................................................................455 24.3.8 ACE_CMP_CR1 Register .....................................................................................455 24.3.9 ACE_CMP_GI_EN Register ...................................................................................455 24.3.10 ACE_ALT_CR0 Register ........................................................................................456 xvi CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 24.3.11 ACE_ABF_CR0 Register ........................................................................................456 24.3.12 ACExxCR1 Register ...............................................................................................456 24.3.13 ACExxCR2 Register ...............................................................................................457 24.3.14 ASExxCR0 Register ...............................................................................................457 24.3.15 ACE_AMD_CR1 Register .......................................................................................457 24.3.16 ACE_PWM_CR Register ........................................................................................458 24.3.17 ACE_ADCx_CR Register .......................................................................................458 24.3.18 ACE_CLK_CR0 Register ........................................................................................459 24.3.19 ACE_CLK_CR1 Register ........................................................................................459 24.3.20 ACE_CLK_CR3 Register ........................................................................................459 Section F: System Resources 461 Top-Level System Resources Architecture ....................................................................................461 Interpreting the System Resources Documentation .......................................................................461 System Resources Register Summary ..........................................................................................462 25. Digital Clocks 465 25.1 Architectural Description.......................................................................................................465 25.1.1 Internal Main Oscillator ...........................................................................................465 25.1.2 Internal Low Speed Oscillator .................................................................................465 25.1.3 32.768 kHz Crystal Oscillator...................................................................................467 25.1.4 External Clock .......................................................................................................467 25.1.4.1 Clock Doubler ............................................................................................467 25.1.4.2 Switch Operation .......................................................................................467 25.2 Register Definitions ..............................................................................................................469 25.2.1 INT_CLR0 Register ................................................................................................469 25.2.2 INT_MSK0 Register ................................................................................................469 25.2.3 OSC_GO_EN Register ...........................................................................................470 25.2.4 OSC_CR4 Register ................................................................................................471 25.2.5 OSC_CR3 Register ................................................................................................472 25.2.6 OSC_CR0 Register ..............................................................................................473 25.2.7 OSC_CR1 Register ................................................................................................474 25.2.8 OSC_CR2 Register ..............................................................................................475 26. Multiply Accumulate (MAC) 477 26.1 Architectural Description ......................................................................................................477 26.2 Application Description .........................................................................................................478 26.2.1 Multiplication with No Accumulation .......................................................................478 26.2.2 Accumulation After Multiplication .............................................................................478 26.3 Register Definitions ..............................................................................................................478 26.3.1 MULx_X Register ....................................................................................................479 26.3.2 MULx_Y Register ....................................................................................................479 26.3.3 MULx_DH Register .................................................................................................479 26.3.4 MULx_DL Register .................................................................................................480 26.3.5 MACx_X/ACCx_DR1 Register ................................................................................480 26.3.6 MACx_Y/ACCx_DR0 Register ................................................................................480 26.3.7 MACx_CL0/ACCx_DR3 Register ...........................................................................481 26.3.8 MACx_CL1/ACCx_DR2 Register ...........................................................................481 27. Decimator 483 27.1 Architectural Description.......................................................................................................483 27.1.1 Type 2 Decimator Block ..........................................................................................483 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F xvii Contents 27.1.1.1 Dedicated Data/Clock Input Selections for Single Decimator Row ...........485 27.1.1.2 Single External Decimation Clock Supports Four Decimators ..................486 27.1.1.3 Single Incremental Gating Clock Supports Six Analog Compare Outputs 486 27.1.1.4 ACC/ACE Interrupts Replacement ............................................................487 27.2 Register Definitions .............................................................................................................488 27.2.1 DECx_DH Register .................................................................................................488 27.2.2 DECx_DL Register .................................................................................................488 27.2.3 DEC_CR0 Register..................................................................................................489 27.2.4 DEC_CR1 Register..................................................................................................489 27.2.5 DECx_CR0 Register ...............................................................................................490 27.2.6 DEC_CR3 Register .................................................................................................490 27.2.7 DEC_CR4 Register .................................................................................................491 27.2.8 DEC_CR5 Register .................................................................................................491 27.2.9 DECx_CR Registers ...............................................................................................492 28. I 2 C 493 28.1 Architectural Description.......................................................................................................493 28.1.1 Dual I2C HW............................................................................................................493 28.1.2 Basic I2C Data Transfer ...........................................................................................494 28.2 Application Description .........................................................................................................494 28.2.1 Slave Operation ......................................................................................................494 28.2.2 Master Operation ....................................................................................................496 28.3 Register Definitions .............................................................................................................497 28.3.1 I2Cx_ADDR Register ..............................................................................................497 28.3.2 I2Cx_CFG Register ................................................................................................498 28.3.3 I2Cx_SCR Register ................................................................................................500 28.3.4 I2Cx_DR Register ...................................................................................................502 28.3.5 I2Cx_MSCR Register .............................................................................................502 28.4 PSoC Device Distinctions .....................................................................................................504 28.5 Timing Diagrams ..................................................................................................................504 28.5.1 Clock Generation .....................................................................................................504 28.5.2 Basic Input/Output Timing .......................................................................................505 28.5.3 Status Timing ...........................................................................................................505 28.5.4 Master Start Timing..................................................................................................506 28.5.5 Master Restart Timing .............................................................................................508 28.5.6 Master Stop Timing .................................................................................................508 28.5.7 Master/Slave Stall Timing .......................................................................................509 28.5.8 Master Lost Arbitration Timing ................................................................................509 28.5.9 Master Clock Synchronization .................................................................................510 29. Internal Voltage Reference 511 29.1 Architectural Description.......................................................................................................511 29.2 Register Definitions .............................................................................................................511 29.2.1 BDG_TR Register ................................................................................................... 511 30. System Resets 513 30.1 Architectural Description.......................................................................................................513 30.2 Pin Behavior During Reset ...................................................................................................513 30.2.1 GPIO Behavior on Power Up...................................................................................513 30.2.2 GPIO Behavior on External Reset ...........................................................................513 30.3 Register Definitions .............................................................................................................514 30.3.1 CPU_SCR1 Register ..............................................................................................514 xviii CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 30.3.2 CPU_SCR0 Register ..............................................................................................515 30.4 Timing Diagrams ..................................................................................................................516 30.4.1 Power On Reset .....................................................................................................516 30.4.2 External Reset ........................................................................................................516 30.4.3 Watchdog Timer Reset ...........................................................................................516 30.4.4 Reset Details ...........................................................................................................518 30.5 Power Consumption ............................................................................................................518 31. Switch Mode Pump (SMP) 519 31.1 Architectural Description.......................................................................................................519 31.2 Application Description .........................................................................................................520 31.2.1 Component Value Selection.....................................................................................520 31.3 Register Definitions ..............................................................................................................521 31.3.1 VLT_CR Register ....................................................................................................521 32. POR and LVD 523 32.1 Architectural Description.......................................................................................................523 32.2 Register Definitions ..............................................................................................................523 32.2.1 VLT_CR Register ....................................................................................................523 32.2.2 VLT_CMP Register .................................................................................................524 33. I/O Analog Multiplexer 525 33.1 Architectural Description ......................................................................................................525 33.1.1 IOMUX and GPIO ....................................................................................................525 33.1.2 Dual Channel 8-Bit IDAC .........................................................................................525 33.2 PSoC Device Distinctions .....................................................................................................526 33.3 Application Description .........................................................................................................526 33.3.1 Capacitive Sensing .................................................................................................526 33.3.2 Chip-Wide Analog Input ..........................................................................................528 33.3.3 Crosspoint Switch ...................................................................................................528 33.3.4 Charging Current .....................................................................................................528 33.4 Register Definitions ..............................................................................................................528 33.4.1 AMUX_CFG Register .............................................................................................528 33.4.2 IDAC1_D Register ..................................................................................................529 33.4.3 IDAC0_D Register ...................................................................................................529 33.4.4 AMUX_CFG1 Register ...........................................................................................529 33.4.5 AMUX_CLK Register ..............................................................................................530 33.4.6 MUX_CRx Registers ...............................................................................................530 33.4.7 IDAC_MODE ...........................................................................................................531 33.4.8 IDAC_CR0 Register.................................................................................................531 33.4.9 IDAC_CR1 Register ................................................................................................531 34. Real Time Clock (RTC) 533 34.1 Architectural Description.......................................................................................................533 34.1.1 BCD Code Counter ..................................................................................................533 34.1.2 Writing RTC Data.....................................................................................................533 34.1.3 Reading RTC Data...................................................................................................533 34.1.4 General Timer ..........................................................................................................534 34.2 Register Definitions ..............................................................................................................534 34.2.1 RTC_H .....................................................................................................................534 34.2.2 RTC_M.....................................................................................................................534 34.2.3 RTC_S .....................................................................................................................534 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F xix Contents 34.2.4 RTC_CR ..................................................................................................................535 35. 10-Bit SAR ADC Controller 537 35.1 Architectural Description.......................................................................................................537 35.1.1 ADC Clock Generation ............................................................................................537 35.1.2 Voltage Doubler Clock Generation ..........................................................................538 35.1.3 ADC FSM ................................................................................................................538 35.1.4 SAR Algorithm and Data Process............................................................................538 35.1.5 A-D-C Operation Mode ............................................................................................539 35.1.6 ‘Ready’ Bit, ‘Ongoing’ Bit and Interrupt....................................................................540 35.1.7 Converted Data Format and Read Sequence .........................................................540 35.2 Application Description .........................................................................................................540 35.2.1 ADC Sample Rate and Clock Selection...................................................................540 35.2.2 Voltage Doubler Enable ...........................................................................................540 35.2.3 Reference Selection ................................................................................................540 35.3 Register Definitions .............................................................................................................541 35.3.1 SADC_DH ...............................................................................................................541 35.3.2 SADC_DL ................................................................................................................541 35.3.3 SADC_TSCR0 .........................................................................................................541 35.3.4 SADC_TSCR1 .........................................................................................................542 35.3.5 SADC_TSCMPL ......................................................................................................542 35.3.6 SADC_TSCMPH......................................................................................................542 35.3.7 SADC_CR0 .............................................................................................................543 35.3.8 SADC_CR1 .............................................................................................................543 35.3.9 SADC_CR2 .............................................................................................................544 35.3.10 SADC_CR3 .............................................................................................................544 35.3.11 SADC_CR4 .............................................................................................................544 35.4 PSoC Device Distinctions .....................................................................................................544 35.5 Clocking................................................................................................................................544 Section H: Glossary 545 Index 561 xx CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Section A: Overview The PSoC® platform consists of many Programmable System-on-Chip devices. As described in this technical reference manual (TRM), a PSoC device includes configurable blocks of analog circuits and digital logic, as well as programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable input/output (I/ O) are included in a range of pinouts. This document is a technical reference manual for all PSoCs with a base part number of CY8C28xxx. To use this manual effectively, you must know how many digital rows and how many analog columns your PSoC device has (see the PSoC Device Characteristics table on page 24) and be aware of your PSoC device’s distinctions (see the PSoC Device Distinctions on page 25). For the most up-to-date Ordering, Pinout, Packaging, or Electrical Specification information, refer to the individual PSoC device’s data sheet. For the most current technical reference manual information, refer to the addendum. To obtain the newest product documentation, go to the Cypress web site at http://www.cypress.com/psoc. This section encompasses the following chapter: ■ Pin Information on page 29 Document Organization This manual is organized into sections and chapters, according to PSoC® functionality. Each section begins with documentation interpretation, a top-level architectural explanation, PSoC device distinctions (if relevant), and a register summary (if applicable). Most chapters within the sections have an introduction, an architectural/application description, PSoC device distinctions (if relevant), register definitions, and timing diagrams. The sections are as follows: ■ Overview – Presents the PSoC top-level architecture, PSoC device characteristics and distinctions, how to get started with helpful information, and document history and conventions. The PSoC device pinouts are detailed in the Pin Information chapter on page 29. ■ PSoC Core – Describes the heart of the PSoC device in various chapters, beginning with an architectural overview and a summary list of registers pertaining to the PSoC core. See “PSoC® Core” on page 35. ■ Register Reference – Lists all PSoC device registers in Register Mapping Tables, on page 109, and presents bit-level detail of each PSoC register in its own Register Details chapter on page 125. Where applicable, detailed register descriptions are also located in each chapter. ■ Digital System – Describes the configurable PSoC digital system in various chapters, beginning with an architectural overview and a summary list of registers pertaining to the digital system. See the “Digital System” on page 311. ■ Analog System – Describes the configurable PSoC analog system in various chapters, beginning with an architectural overview and a summary list of registers pertaining to the analog system. See the “Analog System” on page 383. ■ System Resources – Presents additional PSoC system resources, depending on the PSoC device, beginning with an overview and a summary list of registers pertaining to system resources. See “System Resources” on page 461. ■ Glossary – Defines the specialized terminology used in this manual. Glossary terms are presented in bold, italic font throughout this manual. See the “Glossary” on page 545. ■ Index – Lists the location of key topics and elements that constitute and empower the PSoC device. See the “Index” in the TRM. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 21 Top Level Architecture The PSoC block diagram on the next page illustrates the top level architecture of the CY8C28xxx family of PSoC devices. Each major grouping in the diagram is covered in this manual in its own section: PSoC Core, Digital System, Analog System, and the System Resources. Banding these four main areas together is the communication network of the system bus. PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses the SRAM for data storage, an interrupt controller for easy program execution to new addresses, sleep and watchdog timers, and multiple clock sources that include the phase locked loop (PLL), IMO (internal main oscillator), ILO (internal low speed oscillator), and ECO (32.768 kHz external crystal oscillator) for precision, programmable clocking. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. Analog System The Analog System is composed of analog columns in a block array, analog references, analog input muxing, and analog drivers. The analog system block is composed of up to four analog columns with up to 12 analog blocks, depending on the characteristics of your PSoC device (see “PSoC Device Characteristics” on page 24). Each configurable block is comprised of an opamp circuit allowing the creation of complex analog signal flows. Each analog column contains one Continuous Time (CT) block, Type C (ACC); one Switched Capacitor (SC) block, Type C (ASC); and one Switched Capacitor block, Type D (ASD). Two of the analog columns in the CY8C28x13, CY8C28x33, CY8C28x45, and CY8C28x52 PSoC devices each contain one Type E CT block (ACE) and one Type E SC block (ASE), as described in the Two Column Limited Analog System chapter on page 441. System Resources The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. Within the CPU core are the SROM and Flash memory components that provide flexible programming. The smallest PSoC devices have a slightly different analog configuration. The System Resources provide additional PSoC capability, depending on the features of your PSoC device (see the table titled “Availability of System Resources for CY8C28xxx Devices” on page 24). These system resources include: ■ Digital clocks to increase the flexibility of the PSoC mixed-signal arrays. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. ■ Up to two multiply accumulates (MACs) that provide fast 8-bit multipliers or fast 8-bit multipliers with 32-bit accumulate. ■ Up to two decimators for digital signal processing applications. ■ I2C functionality for implementing either I2C slave or master. ■ An internal voltage reference that provides an absolute value of 1.3 V to a variety of PSoC subsystems. ■ A switch mode pump (SMP) that generates normal operating voltages off a single battery cell. ■ An enhanced analog multiplexer (mux) that allows every I/O pin to connect to a common internal analog mux bus. ■ A five endpoint full-speed (12 Mbps) USB device. ■ Various system resets supported by the M8C. Digital System The Digital System is composed of digital rows in a block array, and the Global, Array, and Row Digital Interconnects (GDI, ADI, and RDI, respectively). Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device (see “PSoC Device Characteristics” on page 24). This allows you the optimum choice of system resources for your application. The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. 22 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F PSoC Top-Level Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC® CORE SYSTEM BUS Global Digital Interconnect Global Analog Interconnect SRAM 1K Supervisory ROM (SROM) Flash Nonvolatile Memory 16K CPU Core (M8C) Interrupt Controller 24 MHz Internal Main Oscillator (IMO) Internal Low Speed Oscillator (ILO) Sleep and Watchdog Phase Locked Loop (PLL) 32 kHz Crystal Oscillator (ECO) Multiple Clock Sources DIGITAL SYSTEM ANALOG SYSTEM Digital PSoC Block Array DBC DBC DCC Analog PSoC Block Array ACC ACC ACC ACC ASC ASD ASC ASD ASD ASC ASD ASC ACE ACE ASE ASE Analog Ref DCC DBC DBC DCC DCC DBC DBC DCC DCC 10-Bit SAR ADC Analog Input Muxing SYSTEM BUS Digital Clocks 2 Multiply Accumulate (MACs) 4 Type 2 Decimators 2 I2C Blocks POR and LVD System Resets Switch Mode Pump Internal Voltage Reference SYSTEM RESOURCES CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 23 PSoC Device Characteristics Y 12 0 4 1 2 up to 40 up to 40 0 CY8C28x23 N 12 6 0 2 2 up to 44 up to 10 2 CY8C28x33 Y 12 6 4 1 4 up to 40 up to 40 2 CY8C28x43 N 12 12 0 2 4 up to 44 up to 44 4 CY8C28x45 Y 12 12 4 2 4 up to 44 up to 44 4 CY8C28x52 Y 8 12 4 1 4 up to 24 up to 24 4 24 2 CY8C28x13 1 2 CY8C28x23 2 2 CY8C28x33 1 2 CY8C28x43 2 2 CY8C28x45 2 2 CY8C28x52 1 2 CapSense 2 Decimators CY8C28x13 0 XRES Pin 0 CY8C28x03 CY8C28xxx Part Number SAR10 ADC 2 Multiply Accumulate 0 System Resets Analog Inputs 0 Analog Outputs Digital IO 12 HW I2C N up to 8 Digital Blocks CY8C28x03 up to 24 PSoC Part Number CapSense Decimators Limited Analog Blocks Regular Analog Blocks CY8C28xxx Device Characteristics POR and LVD Availability of System Resources for CY8C28xxx Devices Internal Voltage Ref The digital system can have 3 or 2 digital rows. The analog system can have 4, 2, or 0 regular analog columns. Additionally, some CY8C28xxx devices have two additional Type-E analog columns. Each PSoC device has a unique combination of digital rows and analog columns. The following table lists the device characteristics for specific CY8C28xxx device groups. Remember the particular CY8C28xxx device characteristics when referencing functionality in this manual. I2C The following table lists the resources available for specific CY8C28xxx device groups. The check mark or appropriate information denotes that a system resource is available for the device. Blank fields indicate that the system resource is not available. These resources are detailed in the section titled “System Resources” on page 461. Digital Clocks There are a number of parts in the CY8C28xxx PSoC Programmable System-on-Chip family. Besides differentiating these by way of part numbers, each part is easily distinguished by the unique number of digital rows and/or analog columns it has. This unique characteristic is the foundation for how this manual presents information. 0 2 2 4 4 4 4 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F PSoC Device Distinctions The PSoC Programmable System-on-Chip device distinctions are listed in the following table and in each chapter section where it is appropriate. The PSoC device distinctions are significant exceptions or differences between CY8C28xxx PSoC groups and devices. They represent a unique difference from the information otherwise presented in this manual which encompasses all CY8C28xxx PSoC devices. PSoC Device Distinctions Device Distinctions Devices Affected Described in Chapter GPIO Pins: The CY8C28x13, CY8C28x33, CY8C28x43, CY8C28x45, and CY8C28x52 PSoC devices differ from the other CY8C28xxx PSoC devices in that GPIO pins can connect to the internal analog bus. CY8C28x13 CY8C28x33 CY8C28x43 CY8C28x45 CY8C28x52 I/O Analog Multiplexer chapter on page 525 Interrupt Differences exist between CY8C28xxx device groups. All Interrupt Controller chapter on page 65 I2C1 Hardware Resource Availability. Some CY8C28xxx groups do not have a second hardware I2C resource (I2C1). The following registers are reserved for these devices: I2C1_DR, I2C1_SCR, I2C1_MSCR, I2C1_CFG, I2C1_ADDR. CY8C28x13 CY8C28x33 CY8C28x52 I2C chapter on page 493 Dedicated 10-bit SAR ADC Availability. Some CY8C28xxx groups do not have a dedicated 10-bit SAR ADC. The following registers are reserved for these devices: SADC_DH, SADC_DL, SADC_TSCR0, SADC_TSCR1, SADC_TSCMPL, SADC_TSCMPH, SADC_CR0, SADC_CR1, SADC_CR2, SADC_CR3, SADC_CR4. CY8C28x23 CY8C28x52 10-Bit SAR ADC Controller chapter on page 537 Limited Decimator Availability. Some CY8C28xxx groups only have 2 decimator resources. The following registers are reserved for these devices: CY8C28x13 DEC2_DH, DEC2_DL, DEC3_DH, DEC3_DL, DEC_CR4, DEC2_CR0, CY8C28x23 DEC3_CR0, DEC2_CR, DEC3_CR. Decimator chapter on page 483 No Decimator Availability. Some CY8C28xxx groups have no decimator resources. The following registers are reserved for these devices: DEC0_DH, DEC0_DL, DEC1_DH, DEC1_DL, DEC2_DH, DEC2_DL, DEC3_DH, DEC3_DL, DEC_CR0, DEC_CR1, DEC_CR3, DEC_CR4, DEC_CR5, DEC0_CR0, DEC1_CR0, DEC2_CR0, DEC3_CR0, DEC0_CR, DEC1_CR, DEC2_CR, DEC3_CR. Decimator chapter on page 483 CY8C28x03 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 25 Getting Started The quickest path to understanding PSoC is by reading the PSoC device’s data sheet and using the PSoC Designer™ Integrated Development Environment (IDE). This manual is useful for understanding the details of the PSoC integrated circuit. Important Note: For the most up-to-date Ordering, Packaging, or Electrical Specification information, refer to the individual PSoC device’s data sheet or go to http://www.cypress.com/psoc. Support Free support for PSoC products is available online at http://www.cypress.com. Resources include Training Seminars, Discussion Forums, Application Notes, PSoC Consultants, TightLink Technical Support Email/Knowledge Base, and Application Support Technicians. Technical Support can be reached at http://www.cypress.com/support/login.cfm or can be contacted by phone at: 1-800-541-4736. Product Upgrades Cypress provides scheduled upgrades and version enhancements for PSoC Designer free of charge. You can order the upgrades from your distributor on CD-ROM or download them directly from http://www.cypress.com under Software and Drivers. Also provided are critical updates to system documentation under Design Support > Design Resources > More Resources or go to http://www.cypress.com. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. Document History This section serves as a chronicle of the CY8C28xxx PSoC Programmable System-on-Chip Technical Reference Manual. PSoC Technical Reference Manual History Version/ 001-52594, Rev. ** Originator DSG Description of Change Initial release 001-52594, Rev. *A DSG Addressed multiple CDTs. Changes throughout document. 001-52594, Rev. *B DSG CDTs 49952, 49275, 49280, 53590, 52998, 52995 001-52594, Rev. *C DSG CDT 58791 001-52594, Rev. *D VED CDT 66721 001-52594, Rev. *E SHEA CDT 131854 001-52594, Rev. *F RJVB CDT 145093 26 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Documentation Conventions Units of Measure There are only four distinguishing font types used in this manual, besides those found in the headings. The following table lists the units of measure used in this manual. ■ The first is the use of italics when referencing a document title or file name. Units of Measure ■ The second is the use of bold italics when referencing a term described in the Glossary of this manual. ■ The third is the use of Times New Roman font, distinguishing equation examples. ■ The fourth is the use of Courier New font, distinguishing code examples. Register Conventions The following table lists the register conventions that are specific to this manual. A more detailed set of register conventions is located in the Register Details chapter on page 125. Register Conventions Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz k kilo, 1000 K 210, 1024 KB 1024 bytes Kbit 1024 bits kHz kilohertz (32.000) k kilohms MHz megahertz M megaohms A microamperes F microfarads s microseconds microvolts Convention Example ‘x’ in a register name ACCxxCR1 Multiple instances/address ranges of the same register R R : 00 Read register or bit(s) V W W : 00 Write register or bit(s) Vrms L RL : 00 Logical register or bit(s) mA milliamperes C RC : 00 Clearable register or bit(s) ms millisecond 00 RW : 00 Reset value is 0x00 or 00h mV millivolts XX RW : XX Register is not reset nA nanoamperes 0, 0,04h Register is in bank 0 1, 1,23h Register is in bank 1 x, x,F7h Empty, grayedout table cell Description Symbol Register exists in register bank 0 and register bank 1 Reserved bit or group of bits, unless otherwise stated Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’) and hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. microvolts root-mean-square ns nanoseconds nV nanovolts ohms pF picofarads pp peak-to-peak ppm parts per million sps samples per second sigma: one standard deviation V volts CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 27 Acronyms Acronyms (continued) Acronym Description The following table lists the acronyms that are used in this manual. PC program counter PCH program counter high Acronyms PCL program counter low PD power down PMA PSoC™ memory arbiter POR power on reset PPOR precision power on reset PRS pseudo random sequence PSoC® Programmable System-on-Chip PSSDC power system sleep duty cycle PWM pulse width modulator RAM random access memory RETI return from interrupt RI row input RO row output ROM read only memory RW read/write SAR successive approximation register SC switched capacitor SIE serial interface engine SE0 single-ended zero SOF start of frame SP stack pointer SPI serial peripheral interconnect SPIM serial peripheral interconnect master SPIS serial peripheral interconnect slave SRAM static random access memory SROM supervisory read only memory SSADC single slope ADC SSC supervisory system call TC terminal count USB universal serial bus WDT watchdog timer WDR watchdog reset XRES external reset Acronym ABUS AC ADC API BC BR BRA BRQ CBUS CI CMP CO CPU CRC CT DAC DC DI DMA DO ECO FB GIE GPIO ICE IDE ILO IMO I/O IOR Description analog output bus alternating current analog-to-digital converter Application Programming Interface broadcast clock bit rate bus request acknowledge bus request comparator bus carry in compare carry out central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current digital or data input direct memory access digital or data output external crystal oscillator feedback global interrupt enable general purpose I/O in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator input/output I/O read IOW I/O write IPOR imprecise power on reset IRQ interrupt request ISR interrupt service routine ISSP in system serial programming IVR interrupt vector read LFSR linear feedback shift register LRb last received bit LRB last received byte LSb least significant bit LSB least significant byte LUT look-up table MISO master-in-slave-out MOSI master-out-slave-in MSb most significant bit MSB most significant byte 28 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 1. Pin Information This chapter lists, describes, and illustrates all CY8C28xxx PSoC device pins and pinout configurations. For up-to-date Ordering, Pinout, and Packaging information, refer to the individual PSoC device's data sheet or go to: http://www.cypress.com/psoc. This chapter encompasses the following: ■ Pinouts for the CY8C28xxx on page 29 1.1 Pinouts for the CY8C28xxx The CY8C28xxx PSoC devices are available in a variety of packages. Refer to the following information for details on individual devices. Every port pin (labeled with a “P”), except for Vss, Vdd, and XRES in the following tables and illustrations, is capable of Digital I/O and Analog Mux Bus (L or R). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 29 Pin Information 1.1.1 20-Pin Part Pinouts Table 1-1. 20-Pin Part Pinout (SSOP) Digital Analog Type Pin No. 1 I/O I, M, S 2 3 4 Pin Name P0[7] Analog column mux input; Integration Cap for MR; ADC input channel. I/O I/O, M, S P0[5] Analog column mux input and column output; Integration Cap for ML; ADC input channel. I/O I/O, M, S P0[3] Analog column mux input and column output; ADC input channel. I/O 5 I, M, S Output P0[1] Analog column mux input; ADC input channel. SMP Switch Mode Pump (SMP) connection to required external components. 6 I/O M P1[7] I2C Serial Clock (SCL) 7 I/O M P1[5] I2C Serial Data (SDA) 8 I/O M P1[3] 9 I/O M P1[1]* Crystal (XTALin), I2C Serial Clock (SCL) Vss Ground connection. Crystal (XTALout), I2C Serial Data (SDA) 10 Power 11 I/O M P1[0]* 12 I/O M P1[2] 13 I/O M P1[4] 14 I/O M P1[6] 15 Input XRES Active high pin reset with internal pull down. P0[0] Analog column mux input; ADC input channel. I/O 17 I/O I/O, M, S P0[2] Analog column mux input and column output; ADC input channel. 18 I/O I/O, M, S P0[4] Analog column mux input and column output; ADC input channel. 19 I/O I, M, S Power S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] SMP I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 SSOP 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA Optional External Clock Input (EXTCLK) 16 20 I, M, S CY8C28243 PSoC Device Description P0[6] Analog column mux input; ADC input channel. Vdd Supply voltage. LEGEND A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). 30 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Pin Information 1.1.2 28-Pin Part Pinouts Table 1-2. 28-Pin Part Pinout (SSOP) Digital Analog Type Pin No. 1 I/O I, M, S Pin Name Description P0[7] Analog column mux and SAR ADC inputa 2 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input. Analog column outputa, b 3 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input. Analog column outputa, b 4 I/O I, M, S P0[1] 5 I/O M P2[7] 6 I/O M P2[5] 7 I/O I, M P2[3] Direct switched capacitor block inputc 8 I/O I, M P2[1] Direct switched capacitor block inputc SMP Switch Mode Pump (SMP) connection to external components. 9 Output Analog column mux and SAR ADC inputa 10 I/O M P1[7] I2C0 Serial Clock (SCL). 11 I/O M P1[5] I2C0 Serial Data (SDA). 12 I/O M P1[3] 13 I/O M P1[1]* 14 Power Vss Ground connection. 15 I/O M P1[0]* 16 I/O M P1[2] I2C1 Serial Data (SDA)d 17 I/O M P1[4] Optional External Clock Input (EXTCLK). 18 I/O M P1[6] I2C1 Serial Clock (SCL)d XRES Active high external reset with internal pull down. Input 20 I/O I, M P2[0] Direct switched capacitor block inpute 21 I/O I, M P2[2] Direct switched capacitor block inpute 22 I/O M P2[4] External Analog Ground (AGND). 23 I/O M P2[6] External Voltage Reference (VRef). 24 I/O I, M, S P0[0] Analog column mux and SAR ADC inputa 25 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. Analog column outputa, f 26 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. ;Analog column outputa, f 27 I/O 28 I, M, S Power S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] M, P2[7] M, P2[5] AI, M, P2[3] AI, M, P2[1] SMP I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef P2[4], M, External AGND P2[2], M, AI P2[0], M, AI XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA 19 CY8C28403, CY8C28413, CY8C28433, CY8C28445, and CY8C28452 28-Pin PSoC Devices P0[6] Analog column mux and SAR ADC inputa Vdd Supply voltage. LEGEND A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). a. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices. b. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices. c. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices. d. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices. e. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices. f. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog column output for these devices. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 31 Pin Information 1.1.3 44-Pin Part Pinouts Table 1-3. 44-Pin Part Pinout (TQFP) CY8C28513, CY8C28533, and CY8C28545 PSoC Devices 1 I/O 2 I/O I, M P2[3] Direct switched capacitor block input. 3 I/O I, M P2[1] Direct switched capacitor block input. 4 I/O M P4[7] 5 I/O M P4[5] 6 I/O M P4[3] 7 I/O M P4[1] M P3[7] I/O M P3[5] 11 I/O M P3[3] 12 I/O M P3[1] 13 I/O M P1[7] I2C0 Serial Clock (SCL) 14 I/O M P1[5] I2C0 Serial Data (SDA) 15 I/O M P1[3] 16 I/O M P1[1]* Crystal (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK Vss Ground connection Crystal (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA 37 P0[4], M, AIO, S 36 P0[2], M, AIO, S 35 P0[0], M, AI, S 39 Vdd 38 P0[6], M, AI, S 34 P2[6], M, External VRef M , E xternal A G N D M , AI M , AI M M M M M M M , I2 C1 SC L 18 I/O M P1[0]* 19 I/O M P1[2] I2C1 Serial Data (SDA)a 20 I/O M P1[4] Optional External Clock Input (EXTCLK) 21 I/O M P1[6] I2C1 Serial Clock (SCL)a 22 I/O M P3[0] I2C1 Serial Data (SDA)a Pin No. Analog Power P 2[4], P 2[2], P 2[0], P 4[6], P 4[4], P 4[2], P 4[0], X RE S P 3[6], P 3[4], P 3[2], Digital 17 TQ FP 33 32 31 30 29 28 27 26 25 24 23 I2C1 SCL, M, P1[6] 21 I2C1 SDA, M, P3[0] 22 I/O 1 2 3 4 5 6 7 8 9 10 11 I2C1 SDA, M, P1[2] 19 EXTCLK, M, P1[4] 20 9 10 P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SM P M , P3[7] M , P3[5] M , P3[3] Vss 17 SMP M, AI, M , AI, M , M, M, M, M, I2C0 SDA, XTALout, M, P1[0] 18 Output Switch Mode Pump (SMP) connection to external components. 42 P0[3], M, AIO, S 41 P0[5], M, AIO, S 40 P0[7], M, AI, S P2[5] M, P1[3] 15 I2C0 SCL, XTALin, M, P1[1] 16 M Description 44 P2[7], M 43 P0[1], M, AI, S Pin Name M, P3[1] 12 I2C0 SCL, M, P1[7] 13 I2C0 SDA, M, P1[5] 14 8 Analog Digital Type Pin No. Name 23 I/O M P3[2] I2C1 Serial Clock (SCL)a 34 I/O M P2[6] External Voltage Reference (VRef) input. 24 I/O M P3[4] 35 I/O I, M, S P0[0] Analog column mux and SAR ADC inputb 36 I/O I/O, M S P0[2] Analog column mux and SAR ADC input. Analog column outputb, c 37 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. Analog column outputb, c I/O I, M, S P0[6] Analog column mux and SAR ADC inputb 25 26 I/O M Input P3[6] XRES Active high pin reset with internal pull down. Description 27 I/O M P4[0] 38 28 I/O M P4[2] 39 Vdd Supply voltage. 29 I/O M P4[4] 40 I/O I, M, S P0[7] Analog column mux and SAR ADC inputb 30 I/O M P4[6] 41 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input. Analog column outputb, d 31 I/O I, M P2[0] Direct switched capacitor block inpute 42 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input. Analog column outputb, d 32 I/O I, M P2[2] Direct switched capacitor block inpute 43 I/O I, M, S P0[1] Analog column mux and SAR ADC inputb 33 I/O External Analog Ground (AGND) input. 44 I/O M P2[4] Power P2[7] LEGEND A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). a. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices. b. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices. c. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog column output for these devices. d. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices. e. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices. 32 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Pin Information 1.1.4 48-Pin Part Pinouts Table 1-4. 48-Pin Part Pinout (QFN**) CY8C28623, CY8C28643, and CY8C28645 PSoC Devices I/O I, M P2[3] Direct switched capacitor block inputa 2 I/O I, M P2[1] Direct switched capacitor block inputa 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] 6 I/O M P4[1] Output SMP 7 I/O M P3[7] 9 I/O M P3[5] 10 I/O M P3[3] 11 I/O M P3[1] 12 I/O M P5[3] 13 I/O M P5[1] 14 I/O M P1[7] I2C0 Serial Clock (SCL) 15 I/O M P1[5] I2C0 Serial Data (SDA) 16 I/O M P1[3] 17 I/O M P1[1]* 1 2 3 4 5 6 7 8 9 10 11 12 QFN (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL P3[0], M, I2C1 SDA Vss Ground connection. I/O M P1[0]* Crystal (XTALout), I2C0 Serial Data (SDA) 20 I/O M P1[2] I2C1 Serial Data (SDA)b 21 I/O M P1[4] Pin Optional External Clock Input (EXTCLK) No. Digital Analog Crystal (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK 19 Pin Name 22 I/O M P1[6] I2C1 Serial Clock (SCL)b 36 I/O M P2[4] External Analog Ground (AGND) input. 23 I/O M P5[0] 37 I/O M P2[6] External Voltage Reference (VRef) input. 24 I/O M P5[2] 38 I/O I, M, S P0[0] Analog column mux and SAR ADC inputc 25 I/O M P3[0] I2C1 Serial Data (SDA)b 39 I/O I/O, M, P0[2] S Analog column mux and SAR ADC input. Analog column outputc, d 26 I/O M P3[2] I2C1 Serial Clock (SCL)b 40 I/O I/O, M, P0[4] S Analog column mux and SAR ADC input. Analog column outputc, d 27 I/O M P3[4] 41 I/O 28 I/O M P3[6] 42 29 Power AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[3] Switch Mode Pump (SMP) connection to external components. 8 18 P2[5], M P2[7], M P0[1], M, AI, S P0[3], M, AIO, S P0[5], M, AIO, S P0[7], M, AI, S Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef 1 48 47 46 45 44 43 42 41 40 39 38 37 Description 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name M, P5[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss I2C0 SDA, XTALout, M, P1[0] I2C1 SDA, M, P1[2] EXTCLK, M, P1[4] I2C1 SCL, M, P1[6] M, P5[0] M, P5[2] Analog Digital Type Pin No. Input XRES Active high pin reset with internal pull down. I, M, S Power 43 I/O I, M, S Description P0[6] Analog column mux and SAR ADC inputc Vdd Supply voltage. P0[7] Analog column mux and SAR ADC inputb 30 I/O M P4[0] 44 I/O I/O, M, P0[5] S Analog column mux and SAR ADC input. Analog column outputc, e 31 I/O M P4[2] 45 I/O I/O, M, P0[3] S Analog column mux and SAR ADC input. Analog column outputc, e 32 I/O M P4[4] 46 I/O I, M, S P0[1] Analog column mux input; ADC input channel. 33 I/O M P4[6] 47 I/O M P2[7] 34 I/O I, M P2[0] Direct switched capacitor block inputf 48 I/O M P2[5] 35 I/O I, M P2[2] Direct switched capacitor block inputf LEGEND A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). ** The QFN package has a center pad that must be connected to ground (Vss). a. b. c. d. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog column output for these devices. e. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices. f. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 33 Pin Information 1.1.5 56-Pin Part Pinout The 56-pin SSOP package is for the CY8C28000 On-Chip Debug (OCD) PSoC device. Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production. Table 1-5. 56-Pin Part Pinout (SSOP) CY8C28000 PSoC Devices Digital Analog Type Pin No. 1 NC 2 I/O 3 I/O 4 I/O 5 I/O 6 7 8 9 10 11 12 13 14 15 I/O I/O I/O I/O I/O I/O I/O I/O OCD OCD 16 Pin Name I, M, S P0[7] I/O, M, P0[5] S I/O, M, P0[3] S I, M, S P0[1] M M I I M M I, M I, M M M Output P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO SMP 17 18 19 20 21 22 23 24 25 26 I/O I/O I/O I/O I/O I/O I/O I/O M M M M M M M M I/O M P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] NC P1[3] 27 I/O M P1[1]* 28 29 30 Power Vss NC NC Description No connection. Analog column mux and SAR ADC input. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Direct switched capacitor block input. Direct switched capacitor block input. OCD even data I/O. OCD odd data output. Switch Mode Pump (SMP) connection to required external components. I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). No connection. Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK Ground connection. No connection. No connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA I2C1 Serial Data (SDA). Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL). NC S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] M, P2[7] M, P2[5] AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] OCDE OCDO SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[3] M, P5[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] NC M, P1[3] SCLK, I2C0 SCL, XTALIn, M, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SSOP 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M CCLK HCLK XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL P3[0], M, I2C1 SDA P5[2], M P5[0], M P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALOut, I2C0 SDA, SDATA NC NC Type Pin No. Digital Analog 41 Input 42 OCD M 43 OCD M XRES Active high external reset with internal pull down. HCLK OCD high-speed clock output. CCLK OCD CPU clock output. 44 I/O M P4[0] 45 46 47 I/O I/O I/O M M M P4[2] P4[4] P4[6] 48 I/O I, M P2[0] Direct switched capacitor block input. 49 I/O I, M P2[2] Direct switched capacitor block input. 50 I/O M P2[4] External Analog Ground (AGND). 51 52 I/O I/O P2[6] P0[0] External Voltage Reference (VRef). Analog column mux and SAR ADC input. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Supply voltage. 31 I/O M P1[0]* 32 I/O M P1[2] 33 I/O M P1[4] 34 35 I/O I/O M M P1[6] P5[0] 36 I/O M P5[2] 37 I/O M P3[0] I2C1 Serial Data (SDA). 54 38 39 40 I/O I/O I/O M M M P3[2] P3[4] P3[6] I2C1 Serial Clock (SCL). 55 56 53 M I, M, S I/O, M, I/O S I/O, M, I/O S I/O I, M, S Power Name P0[2] P0[4] P0[6] Vdd Description LEGEND A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR (Power On Reset). 34 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Section B: PSoC® Core The PSoC® Core section discusses the core components of a PSoC device with a base part number of CY8C28xxx. This section encompasses the following chapters: ■ CPU Core (M8C) on page 39 ■ Internal Main Oscillator (IMO) on page 81 ■ Supervisory ROM (SROM) on page 49 ■ Internal Low Speed Oscillator (ILO) on page 85 ■ RAM Paging on page 57 ■ External Crystal Oscillator (ECO) on page 87 ■ Interrupt Controller on page 65 ■ Phase-Locked Loop (PLL) on page 93 ■ General Purpose I/O (GPIO) on page 73 ■ Sleep and Watchdog on page 97 Top Level Core Architecture The following figure displays the top-level architecture of the PSoC device’s core. Each component of the figure is discussed at length in this section. PSoC Core Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers SYSTEM BUS PSoC® CORE Supervisory ROM (SROM) SRAM Interrupt Controller 24 MHz Internal Main Oscillator (IMO) The core section covers the heart of the PSoC device which includes the M8C microcontroller; SROM, interrupt controller, GPIO, analog output drivers, and SRAM paging; multiple clock sources such as IMO, ILO, ECO, and PLL; and sleep and watchdog functionality. The analog output drivers are described in this section and not the Analog System section because they are part of the PSoC core input and output signals. Flash Nonvolatile Memory CPU Core (M8C) Internal Low Speed Oscillator (ILO) Interpreting the Core Documentation Phase Locked Loop (PLL) Sleep and Watchdog 32 kHz Crystal Oscillator (ECO) Multiple Clock Sources CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 35 Core Register Summary The following table lists all the PSoC registers for the CPU core in address order within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. For the core registers, the first ‘x’ in some register addresses represents either bank 0 or bank 1. These registers are listed throughout this manual in bank 0, even though they are also available in bank 1. Note that all CY8C28xxx devices have a combination of 4, 2, or 0 analog columns and 3 or 2 digital rows. The registers that are specifically constrained by the number of analog columns have the number of analog columns (Cols.) listed within the Address column of the table. The registers specifically pertaining to digital rows have the number of rows (Rows) listed within the Address column of the table. To determine the number of analog columns and digital rows in your device, refer to the table titled “CY8C28xxx Device Characteristics” on page 24. Summary Table of the Core Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Carry Zero GIE RL : 02 M8C REGISTER (page 48) x,F7h CPU_F 0,D1h STK_PP Page Bits[2:0] 0,D4h MVR_PP Page Bits[2:0] RW : 00 0,D5h MVW_PP Page Bits[2:0] RW : 00 x,FEh CPU_SCR1 1,FAh FLS_PR1 x,6Ch TMP_DRx Data[7:0] RW : 00 x,6Dh TMP_DR1 Data[7:0] RW : 00 x,6Eh TMP_DR2 Data[7:0] RW : 00 x,6Fh TMP_DR3 Data[7:0] 0,D0h CUR_PP Page Bits[2:0] RW : 00 0,D1h STK_PP Page Bits[2:0] RW : 00 0,D3h IDX_PP Page Bits[2:0] RW : 00 0,D4h MVR_PP Page Bits[2:0] RW : 00 0,D5h MVW_PP Page Bits[2:0] RW : 00 x,F7h CPU_F PgMode[1:0] XIO SUPERVISORY ROM (SROM) REGISTERS (page 54) IRESS SLIMO ECO EXW ECO EX RW : 00 IRAMDIS # : 00 Bank RW : 00 RAM PAGING (SRAM) REGISTERS (page 60) PgMode[1:0] RW : 00 XIO Carry Zero GIE RL : 02 INTERRUPT CONTROLLER REGISTERS (page 68) 0,DAh 4 Cols. 2 Cols. INT_CLR0 0,DBh INT_CLR1 0,DCh INT_CLR2 0,DDh INT_CLR3 0,DEh INT_MSK3 0,DF INT_MSK2 0,E0h 4 Cols. 2 Cols. INT_MSK0 VC3 Sleep GPIO VC3 Sleep GPIO DCC13 DCC12 DBC11 ENSWINT Analog 3 DBC10 AEC1 AEC0 AEC1 AEC0 VC3 Sleep GPIO VC3 Sleep GPIO DCC13 DCC12 DBC11 Analog 3 DBC10 Analog 2 Analog 1 Analog 0 V Monitor Analog 1 Analog 0 V Monitor DCC03 DCC02 DBC01 DBC00 DCC23 DCC22 DBC21 DBC20 RW : 00 RTC SARADC I2C1 I2C0 RW : 00 RW : 00 RW : 00 RTC SARADC I2C1 I2C0 RW : 00 DCC23 DCC22 DBC21 DBC20 RW : 00 Analog 2 Analog 1 Analog 0 V Monitor Analog 1 Analog 0 V Monitor DCC02 DBC01 DBC00 Carry Zero GIE DCC03 RW : 00 0,E1h INT_MSK1 0,E2h INT_VC x,F7h CPU_F 0,00h PRT0DR Data[7:0] 0,01h PRT0IE Interrupt Enables[7:0] RW : 00 0,02h PRT0GS Global Select[7:0] RW : 00 Pending Interrupt[7:0] PgMode[1:0] XIO RW : 00 RC : 00 RL : 02 GENERAL PURPOSE I/O (GPIO) REGISTERS (page 76) RW : 00 0,03h PRT0DM2 Drive Mode 2[7:0] RW : FFh 1,00h PRT0DM0 Drive Mode 0[7:0] RW : 00 36 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Summary Table of the Core Registers (continued) Address 1,01h Name Bit 7 Bit 6 Bit 5 PRT0DM1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Drive Mode 1[7:0] Access RW : FFh 1,02h PRT0IC0 Interrupt Control 0[7:0] RW : 00 1,03h PRT0IC1 Interrupt Control 1[7:0] RW : 00 0,04h PRT1DR Data[7:0] RW : 00 0,05h PRT1IE Interrupt Enables[7:0] RW : 00 0,06h PRT1GS Global Select[7:0] RW : 00 0,07h PRT1DM2 Drive Mode 2[7:0] RW : FFh 1,04h PRT1DM0 Drive Mode 0[7:0] RW : 00 1,05h PRT1DM1 Drive Mode 1[7:0] RW : FFh 1,06h PRT1IC0 Interrupt Control 0[7:0] RW : 00 1,07h PRT1IC1 Interrupt Control 1[7:0] RW : 00 0,08h PRT2DR Data[7:0] RW : 00 0,09h PRT2IE Interrupt Enables[7:0] RW : 00 0,0Ah PRT2GS Global Select[7:0] RW : 00 0,0Bh PRT2DM2 Drive Mode 2[7:0] RW : FFh 1,08h PRT2DM0 Drive Mode 0[7:0] RW : 00 1,09h PRT2DM1 Drive Mode 1[7:0] RW : FFh 1,0Ah PRT2IC0 Interrupt Control 0[7:0] RW : 00 1,0Bh PRT2IC1 Interrupt Control 1[7:0] RW : 00 0,0Ch PRT3DR Data[7:0] RW : 00 0,0Dh PRT3IE Interrupt Enables[7:0] RW : 00 0,0Eh PRT3GS Global Select[7:0] RW : 00 0,0Fh PRT3DM2 Drive Mode 2[7:0] RW : FFh 1,0Ch PRT3DM0 Drive Mode 0[7:0] RW : 00 1,0Dh PRT3DM1 Drive Mode 1[7:0] RW : FFh 1,0Eh PRT3IC0 Interrupt Control 0[7:0] RW : 00 1,0Fh PRT3IC1 Interrupt Control 1[7:0] RW : 00 0,10h PRT4DR Data[7:0] RW : 00 0,11h PRT4IE Interrupt Enables[7:0] RW : 00 0,12h PRT4GS Global Select[7:0] RW : 00 0,13h PRT4DM2 Drive Mode 2[7:0] RW : FFh 1,10h PRT4DM0 Drive Mode 0[7:0] RW : 00 1,11h PRT4DM1 Drive Mode 1[7:0] RW : FFh 1,12h PRT4IC0 Interrupt Control 0[7:0] RW : 00 1,13h PRT4IC1 Interrupt Control 1[7:0] RW : 00 INTERNAL MAIN OSCILLATOR (IMO) REGISTERS (page 82) x,FEh CPU_SCR1 1,E2h OSC_CR2 1,E8h IMO_TR IRESS SLIMO ECO EXW SLP_EXTEN WDR32_SE D PLLGAIN ECO EX IRAMDIS # : 00 EXTCLKEN SYSCLKX2 DIS RW : 00 RSVD Trim[7:0] W : 00 INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER (page 85) 1,E9h ILO_TR Bias Trim[1:0] Freq Trim[3:0] W : 00 EXTERNAL CRYSTAL OSCILLATOR (ECO) REGISTERS (page 89) x,FEh CPU_SCR1 1,E0h OSC_CR0 1,EBh ECO_TR IRESS 32k Select SLIMO PLL Mode No Buzz ECO EXW ECO EX Sleep[1:0] IRAMDIS CPU Speed[2:0] # : 00 RW : 00 PSSDC[1:0] W : 00 PHASE-LOCKED LOOP (PLL) REGISTERS (page 93) 1,E0h 1,E2h OSC_CR0 OSC_CR2 32k Select PLLGAIN PLL Mode No Buzz Sleep[1:0] SLP_EXTEN WDR32_SE D CPU Speed[2:0] EXTCLKEN CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RSVD RW : 00 SYSCLKX2 DIS RW : 00 37 Summary Table of the Core Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SLEEP AND WATCHDOG REGISTERS (page 99) 0,E0h 4 Cols. 2 Cols. INT_MSK0 VC3 Sleep GPIO VC3 Sleep GPIO 0,E3h RES_WDT x,FEh CPU_SCR1 IRESS x,FFh CPU_SCR0 GIES 1,E0h OSC_CR0 1,E2h OSC_CR2 1,E9h ILO_TR 1,EBh ECO_TR Analog 3 Analog 2 Analog 1 Analog 0 V Monitor Analog 1 Analog 0 V Monitor WDSL_Clear[7:0] WDRS 32k Select PLL Mode PLLGAIN SLIMO ECO EXW PORS Sleep No Buzz W : 00 ECO EX Sleep[1:0] SLP_EXTEN WDR32_SE D Bias Trim[1:0] RW : 00 IRAMDIS # : 00 STOP # : XX CPU Speed[2:0] EXTCLKEN RSVD Freq Trim[3:0] PSSDC[1:0] RW : 00 SYSCLKX2 DIS RW : 00 W : 00 W : 00 LEGEND L The and f, expr; or f, expr; and xor f, expr instructions can be used to modify this register. # Access is bit specific. Refer to the Register Details chapter on page 125 for additional information. X The value for power on reset is unknown. x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. C Clearable register or bit(s). R Read register or bit(s). W Write register or bit(s). 38 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 2. CPU Core (M8C) This chapter explains the CPU Core, called M8C, and its associated register. It covers the internal M8C registers, address spaces, instruction formats, and addressing modes. For additional information concerning the M8C instruction set, refer to the PSoC ® Designer™ Assembly Language User Guide available at the Cypress web site (http://www.cypress.com/psoc). For a complete table of the CPU Core registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC® registers in address order, refer to the Register Details chapter on page 125. 2.1 Overview The M8C is a four MIPS 8-bit Harvard architecture microprocessor. Selectable processor clock speeds from 93.7 kHz to 24 MHz allow the M8C to be tuned to a particular application’s performance and power requirements. The M8C supports a rich instruction set which allows for efficient low level language support. 2.2 Internal Registers The M8C has five internal registers that are used in program execution. The following is a list of these registers. ■ Accumulator (A) ■ Index (X) ■ Program Counter (PC) ■ Stack Pointer (SP) ■ Flags (F) All of the internal M8C registers are eight bits in width, except for the PC which is 16 bits wide. Upon reset, A, X, PC, and SP are reset to 00h. The Flag register (F) is reset to 02h, indicating that the Z flag is set. With each stack operation, the SP is automatically incremented or decremented so that it always points to the next stack byte in RAM. If the last byte in the stack is at address FFh, the stack pointer will wrap to RAM address 00h. It is the firmware developer’s responsibility to ensure that the stack does not overlap with user-defined variables in RAM. With the exception of the F register, the M8C internal registers are not accessible via an explicit register address. The internal M8C registers are accessed using the following instructions: ■ MOV A, expr ■ MOV X, expr ■ SWAP A, SP ■ OR F, expr ■ JMP LABEL The F register can be read by using address F7h in either register bank 2.3 Address Spaces The M8C has three address spaces: ROM, RAM, and registers. The ROM address space includes the supervisory ROM (SROM) and the Flash. The ROM address space is accessed via its own address and data bus. The ROM address space is composed of the Supervisory ROM and the on-chip Flash program store. Flash is organized into 64-byte blocks. The user need not be concerned with program store page boundaries, as the M8C automatically increments the 16-bit PC on every instruction making the block boundaries invisible to user code. Instructions occurring on a 256-byte Flash page boundary (with the exception of jmp instructions) incur an extra M8C clock cycle, as the upper byte of the PC is incremented. The register address space is used to configure the PSoC microcontroller’s programmable blocks. It consists of two banks of 256 bytes each. To switch between banks, the XIO bit in the Flag register is set or cleared (set for Bank1, cleared for Bank0). The common convention is to leave the bank set to Bank0 (XIO cleared), switch to Bank1 as needed (set XIO), then switch back to Bank0. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 39 CPU Core (M8C) 2.4 Instruction Set Summary The instruction set is summarized in both Table 2-1 and Table 2-2 (in numeric and mnemonic order, respectively), and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (refer to the http://www.cypress.com/psoc web site). Opcode Hex Cycles 8 2 OR [X+expr], A Z 5A 5 2 MOV [expr], X 2 ADD A, expr C, Z 2E 9 3 OR [expr], expr Z 5B 4 1 MOV A, X 02 6 2 ADD A, [expr] C, Z 2F 10 3 OR [X+expr], expr Z 5C 4 1 MOV X, A 03 7 2 ADD A, [X+expr] C, Z 30 9 1 HALT 5D 6 2 MOV A, reg[expr] Z 04 7 2 ADD [expr], A C, Z 31 4 2 XOR A, expr Z 5E 7 2 MOV A, reg[X+expr] Z 05 8 2 ADD [X+expr], A C, Z 32 6 2 XOR A, [expr] Z 5F 10 3 MOV [expr], [expr] 06 9 Flags Instruction Format Flags Bytes Cycles 2D 4 Instruction Format Bytes Opcode Hex 1 SSC 01 Bytes 00 15 Cycles Opcode Hex Table 2-1. Instruction Set Summary Sorted Numerically by Opcode Instruction Format Flags Z 3 ADD [expr], expr C, Z 33 7 2 XOR A, [X+expr] Z 60 5 2 MOV reg[expr], A 07 10 3 ADD [X+expr], expr C, Z 34 7 2 XOR [expr], A Z 61 6 2 MOV reg[X+expr], A 08 4 1 PUSH A 35 8 2 XOR [X+expr], A Z 62 8 3 MOV reg[expr], expr 09 4 2 ADC A, expr C, Z 36 9 3 XOR [expr], expr Z 63 9 3 MOV reg[X+expr], expr 0A 6 2 ADC A, [expr] C, Z 37 10 3 XOR [X+expr], expr Z 64 4 1 ASL A C, Z 0B 7 2 ADC A, [X+expr] C, Z 38 5 2 ADD SP, expr 65 7 2 ASL [expr] C, Z 0C 7 2 ADC [expr], A C, Z 39 5 2 CMP A, expr 66 8 2 ASL [X+expr] C, Z 0D 8 2 ADC [X+expr], A C, Z 3A 7 2 CMP A, [expr] 67 4 1 ASR A C, Z 0E 9 3 ADC [expr], expr C, Z 3B 8 2 CMP A, [X+expr] 68 7 2 ASR [expr] C, Z 0F 10 3 ADC [X+expr], expr C, Z 3C 8 3 CMP [expr], expr 69 8 2 ASR [X+expr] C, Z 10 4 1 PUSH X 3D 9 3 CMP [X+expr], expr 6A 4 1 RLC A C, Z 11 4 2 SUB A, expr C, Z 3E 10 2 MVI A, [ [expr]++ ] 6B 7 2 RLC [expr] C, Z 12 6 2 SUB A, [expr] C, Z 3F 10 2 MVI [ [expr]++ ], A 6C 8 2 RLC [X+expr] C, Z 13 7 2 SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1 RRC A C, Z 14 7 2 SUB [expr], A C, Z 41 9 3 AND reg[expr], expr Z 6E 7 2 RRC [expr] C, Z 15 8 2 SUB [X+expr], A C, Z 42 10 3 AND reg[X+expr], expr Z 6F 8 2 RRC [X+expr] C, Z 16 9 3 SUB [expr], expr C, Z 43 3 OR reg[expr], expr Z 70 4 2 AND F, expr C, Z 17 10 3 SUB [X+expr], expr C, Z 44 10 3 OR reg[X+expr], expr Z 71 4 2 OR F, expr C, Z 18 5 1 POP A 45 3 XOR reg[expr], expr Z 72 4 2 XOR F, expr C, Z 19 4 2 SBB A, expr C, Z 46 10 3 XOR reg[X+expr], expr Z 73 4 1 CPL A Z 1A 6 2 SBB A, [expr] C, Z 47 8 3 TST [expr], expr Z 74 4 1 INC A C, Z Z 9 9 if (A=B) Z=1 if (A<B) C=1 Z 1B 7 2 SBB A, [X+expr] C, Z 48 9 3 TST [X+expr], expr Z 75 4 1 INC X C, Z 1C 7 2 SBB [expr], A C, Z 49 9 3 TST reg[expr], expr Z 76 7 2 INC [expr] C, Z 1D 8 2 SBB [X+expr], A C, Z 4A 10 3 TST reg[X+expr], expr Z 77 8 2 INC [X+expr] C, Z 1E 9 3 SBB [expr], expr C, Z 4B 5 1 SWAP A, X Z 78 4 1 DEC A C, Z 1F 10 3 SBB [X+expr], expr C, Z 4C 7 2 SWAP A, [expr] Z 79 4 1 DEC X C, Z 20 5 1 POP X 4D 7 2 SWAP X, [expr] 7A 7 2 DEC [expr] C, Z 21 4 2 AND A, expr Z 4E 5 1 SWAP A, SP 7B 8 2 DEC [X+expr] C, Z 22 6 2 AND A, [expr] Z 4F 4 1 MOV X, SP 23 7 2 AND A, [X+expr] Z 50 4 2 MOV A, expr 24 7 2 AND [expr], A Z 51 5 2 MOV A, [expr] 25 8 2 AND [X+expr], A Z 52 6 2 MOV A, [X+expr] 26 9 Z 7C 13 3 LCALL Z 7D 7 3 LJMP Z 7E 10 1 RETI Z 7F 8 1 RET 5 2 JMP 3 AND [expr], expr Z 53 5 2 MOV [expr], A 8x 27 10 3 AND [X+expr], expr Z 54 6 2 MOV [X+expr], A 9x 11 2 CALL 28 11 1 ROMX Z 55 8 3 MOV [expr], expr Ax 5 2 JZ 29 4 2 OR A, expr Z 56 9 3 MOV [X+expr], expr Bx 5 2 JNZ 2A 6 2 OR A, [expr] Z 57 4 2 MOV X, expr Cx 5 2 JC 2B 7 2 OR A, [X+expr] Z 58 6 2 MOV X, [expr] Dx 5 2 JNC 2C 7 2 OR [expr], A Z 59 7 2 MOV X, [X+expr] Ex 7 2 JACC Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles. Note 2 The number of cycles required by an instruction is increased by one for instructions that span 256 byte page boundaries in the Flash memory space. 40 Fx 13 2 INDEX C, Z Z CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CPU Core (M8C) Opcode Hex Cycles Bytes Opcode Hex Cycles Bytes 2 ADC A, expr C, Z 76 7 2 INC [expr] C, Z 20 5 1 POP X 0A 6 2 ADC A, [expr] C, Z 77 8 2 INC [X+expr] C, Z 18 5 1 POP A 0B 7 2 ADC A, [X+expr] C, Z Fx 13 2 INDEX Z 10 4 1 PUSH X 0C 7 2 ADC [expr], A C, Z Ex 7 2 JACC 08 4 1 PUSH A 0D 8 2 ADC [X+expr], A C, Z Cx 5 2 JC 7E 10 1 RETI 0E 9 3 ADC [expr], expr C, Z 8x 5 2 JMP 7F 8 1 RET 0F 10 3 ADC [X+expr], expr C, Z Dx 5 2 JNC 6A 4 1 RLC A C, Z 01 4 2 ADD A, expr C, Z Bx 5 2 JNZ 6B 7 2 RLC [expr] C, Z 02 6 2 ADD A, [expr] C, Z Ax 5 2 JZ 6C 8 2 RLC [X+expr] C, Z 03 7 2 ADD A, [X+expr] C, Z 7C 13 3 LCALL 28 11 1 ROMX Z 04 7 2 ADD [expr], A C, Z 7D 7 3 LJMP 6D 4 1 RRC A C, Z 05 8 2 ADD [X+expr], A C, Z 4F 4 1 MOV X, SP 6E 7 2 RRC [expr] C, Z 06 9 3 ADD [expr], expr C, Z 50 4 2 MOV A, expr Z 6F 8 2 RRC [X+expr] C, Z 07 10 3 ADD [X+expr], expr C, Z 51 5 2 MOV A, [expr] Z 19 4 2 SBB A, expr C, Z 38 5 2 ADD SP, expr 52 6 2 MOV A, [X+expr] Z 1A 6 2 SBB A, [expr] C, Z 21 4 2 AND A, expr Z 53 5 2 MOV [expr], A 1B 7 2 SBB A, [X+expr] C, Z 22 6 2 AND A, [expr] Z 54 6 2 MOV [X+expr], A 1C 7 2 SBB [expr], A C, Z 23 7 2 AND A, [X+expr] Z 55 8 3 MOV [expr], expr 1D 8 2 SBB [X+expr], A C, Z 24 7 2 AND [expr], A Z 56 9 3 MOV [X+expr], expr 1E 9 3 SBB [expr], expr C, Z 25 8 2 AND [X+expr], A Z 57 4 2 MOV X, expr 1F 10 3 SBB [X+expr], expr C, Z 26 9 3 AND [expr], expr Z 58 6 2 MOV X, [expr] 00 15 1 SSC 27 10 3 AND [X+expr], expr Z 59 7 2 MOV X, [X+expr] 11 4 2 SUB A, expr C, Z 70 4 2 AND F, expr C, Z 5A 5 2 MOV [expr], X 12 6 2 SUB A, [expr] C, Z 41 9 3 AND reg[expr], expr Z 5B 4 1 MOV A, X 13 7 2 SUB A, [X+expr] C, Z 42 10 3 AND reg[X+expr], expr Z 5C 4 1 MOV X, A 14 7 2 SUB [expr], A C, Z 64 4 1 ASL A C, Z 5D 6 2 MOV A, reg[expr] Z 15 8 2 SUB [X+expr], A C, Z 65 7 2 ASL [expr] C, Z 5E 7 2 MOV A, reg[X+expr] Z 16 9 3 SUB [expr], expr C, Z 66 8 2 ASL [X+expr] C, Z 5F 10 3 MOV [expr], [expr] 17 10 3 SUB [X+expr], expr C, Z 67 4 1 ASR A C, Z 60 5 2 MOV reg[expr], A 4B 5 1 SWAP A, X Z 68 7 2 ASR [expr] C, Z 61 6 2 MOV reg[X+expr], A 4C 7 2 SWAP A, [expr] Z 69 8 2 ASR [X+expr] C, Z 62 8 3 MOV reg[expr], expr 4D 7 2 SWAP X, [expr] 9x 11 2 CALL 63 9 3 MOV reg[X+expr], expr 4E 5 1 SWAP A, SP Z 39 5 2 CMP A, expr 3E 10 2 MVI A, [ [expr]++ ] 47 8 3 TST [expr], expr Z 3A 7 2 CMP A, [expr] 3F 10 2 MVI [ [expr]++ ], A 48 9 3 TST [X+expr], expr Z 3B 8 2 CMP A, [X+expr] 40 4 1 NOP 49 9 3 TST reg[expr], expr Z 3C 8 3 CMP [expr], expr 29 4 2 OR A, expr Z 4A 10 3 TST reg[X+expr], expr Z 3D 9 3 CMP [X+expr], expr 2A 6 2 OR A, [expr] Z 72 4 2 XOR F, expr C, Z 73 4 1 CPL A Z 2B 7 2 OR A, [X+expr] Z 31 4 2 XOR A, expr Z 78 4 1 DEC A C, Z 2C 7 2 OR [expr], A Z 32 6 2 XOR A, [expr] Z 79 4 1 DEC X C, Z 2D 8 2 OR [X+expr], A Z 33 7 2 XOR A, [X+expr] Z 7A 7 2 DEC [expr] C, Z 2E 9 3 OR [expr], expr Z 34 7 2 XOR [expr], A Z 7B 8 2 DEC [X+expr] C, Z 2F 10 3 OR [X+expr], expr Z 35 8 2 XOR [X+expr], A Z 30 9 1 HALT 43 9 OR reg[expr], expr Z 36 9 3 XOR [expr], expr Z 74 4 1 INC A C, Z 44 10 3 OR reg[X+expr], expr Z 37 10 3 XOR [X+expr], expr Z 75 4 1 INC X C, Z 71 4 OR F, expr C, Z 45 XOR reg[expr], expr Z XOR reg[X+expr], expr Z Bytes 09 4 Cycles Opcode Hex Table 2-2. Instruction Set Summary Sorted Alphabetically by Mnemonic Instruction Format Flags if (A=B) Z=1 if (A<B) C=1 3 2 Instruction Format Flags Z Z Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles. 9 3 46 10 3 Instruction Format Flags Z C, Z Note 2 The number of cycles required by an instruction is increased by one for instructions that span 256 byte page boundaries in the Flash memory space. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 41 CPU Core (M8C) 2.5 Instruction Formats The M8C has a total of seven instruction formats which use instruction lengths of one, two, and three bytes. All instruction bytes are fetched from the program memory (Flash), using an address and data bus that are independent from the address and data buses used for register and RAM access. While examples of instructions are given in this section, refer to the PSoC Designer Assembly Language User Guide for detailed information on individual instructions. 2.5.1 One-Byte Instructions Many instructions, such as some of the MOV instructions, have single-byte forms, because they do not use an address or data as an operand. As shown in Table 2-3, one-byte instructions use an 8-bit opcode. The set of one-byte instructions can be divided into four categories, according to where their results are stored. Table 2-3. One-Byte Instruction Format Byte 0 8-Bit Opcode The first category of one-byte instructions are those that do not update any registers or RAM. Only the one-byte NOP and SSC instructions fit this category. While the program counter is incremented as these instructions execute, they do not cause any other internal M8C registers to be updated, nor do these instructions directly affect the register space or the RAM address space. The SSC instruction will cause SROM code to run, which will modify RAM and the M8C internal registers. The second category has only the two PUSH instructions in it. The PUSH instructions are unique, because they are the only one-byte instructions that cause a RAM address to be modified. These instructions automatically increment the SP. The third category has only the HALT instruction in it. The HALT instruction is unique, because it is the only a one-byte instruction that causes a user register to be modified. The HALT instruction modifies user register space address FFh (CPU_SCR register). 2.5.2 Two-Byte Instructions The majority of M8C instructions are two bytes in length. While these instructions can be divided into categories identical to the one-byte instructions, this does not provide a useful distinction between the three two-byte instruction formats that the M8C uses. Table 2-4. Two-Byte Instruction Formats Byte 0 Byte 1 4-Bit Opcode 12-Bit Relative Address 8-Bit Opcode 8-Bit Data 8-Bit Opcode 8-Bit Address The first two-byte instruction format, shown in the first row of Table 2-4, is used by short jumps and calls: CALL, JMP, JACC, INDEX, JC, JNC, JNZ, JZ. This instruction format uses only four bits for the instruction opcode, leaving 12 bits to store the relative destination address in a two’s-complement form. These instructions can change program execution to an address relative to the current address by -2048 or +2047. The second two-byte instruction format, shown in the second row of Table 2-4, is used by instructions that employ the Source Immediate addressing mode (see “Source Immediate” on page 43). The destination for these instructions is an internal M8C register, while the source is a constant value. An example of this type of instruction is ADD A, 7. The third two-byte instruction format, shown in the third row of Table 2-4, is used by a wide range of instructions and addressing modes. The following is a list of the addressing modes that use this third two-byte instruction format: ■ Source Direct (ADD A, [7]) ■ Source Indexed (ADD A, [X+7]) ■ Destination Direct (ADD [7], A) ■ Destination Indexed (ADD [X+7], A) ■ Source Indirect Post Increment (MVI A, [7]) ■ Destination Indirect Post Increment (MVI [7], A) For more information on addressing modes see “Addressing Modes” on page 43. The final category for one-byte instructions are those that cause updates of the internal M8C registers. This category holds the largest number of instructions: ASL, ASR, CPL, DEC, INC, MOV, POP, RET, RETI, RLC, ROMX, RRC, SWAP. These instructions can cause the A, X, and SP registers or SRAM to update. 42 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CPU Core (M8C) 2.5.3 Three-Byte Instructions The three-byte instruction formats are the second most prevalent instruction formats. These instructions need three bytes because they either move data between two addresses in the user-accessible address space (registers and RAM) or they hold 16-bit absolute addresses as the destination of a long jump or long call. Table 2-5. Three-Byte Instruction Formats Byte 0 Byte 1 Byte 2 8-Bit Opcode 16-Bit Address (MSB, LSB) 8-Bit Opcode 8-Bit Address 8-Bit Data 8-Bit Opcode 8-Bit Address 8-Bit Address The first instruction format, shown in the first row of Table 2-5, is used by the LJMP and LCALL instructions. 2.6 These instructions change program execution unconditionally to an absolute address. The instructions use an 8-bit opcode, leaving room for a 16-bit destination address. The second three-byte instruction format, shown in the second row of Table 2-5, is used by the following two addressing modes: ■ Destination Direct Source Immediate (ADD [7], 5) ■ Destination Indexed Source Immediate (ADD [X+7], 5) The third three-byte instruction format, shown in the third row of Table 2-5, is for the Destination Direct Source Direct addressing mode, which is used by only one instruction. This instruction format uses an 8-bit opcode followed by two 8-bit addresses. The first address is the destination address in RAM, while the second address is the source address in RAM. The following is an example of this instruction: MOV [7], [5] Addressing Modes The M8C has ten addressing modes. These modes are detailed and located on the following pages: ■ “Source Immediate” on page 43. ■ “Destination Direct Source Immediate” on page 45. ■ “Source Direct” on page 44. ■ “Destination Indexed Source Immediate” on page 46. ■ “Source Indexed” on page 44. ■ “Destination Direct Source Direct” on page 46. ■ “Destination Direct” on page 45. ■ “Source Indirect Post Increment” on page 47. ■ “Destination Indexed” on page 45. ■ “Destination Indirect Post Increment” on page 47. 2.6.1 Source Immediate For these instructions, the source value is stored in operand 1 of the instruction. The result of these instructions is placed in either the M8C A, F, or X register as indicated by the instruction’s opcode. All instructions using the Source Immediate addressing mode are two bytes in length. Table 2-6. Source Immediate Opcode Instruction Operand 1 Immediate Value Source Immediate Examples: Source Code Machine Code Comments ADD A, 7 01 07 The immediate value 7 is added to the Accumulator. The result is placed in the Accumulator. MOV X, 8 57 08 The immediate value 8 is moved into the X register. AND F, 9 70 09 The immediate value of 9 is logically ANDed with the F register and the result is placed in the F register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 43 CPU Core (M8C) 2.6.2 Source Direct For these instructions, the source address is stored in operand 1 of the instruction. During instruction execution, the address will be used to retrieve the source value from RAM or register address space. The result of these instructions is placed in either the M8C A or X register as indicated by the instruction’s opcode. All instructions using the Source Direct addressing mode are two bytes in length. Table 2-7. Source Direct Opcode Operand 1 Instruction Source Address Source Direct Examples: Source Code Machine Code Comments ADD A, [7] 02 07 The value in memory at address 7 is added to the Accumulator and the result is placed into the Accumulator. MOV A, REG[8] 5D 08 The value in the register space at address 8 is moved into the Accumulator. 2.6.3 Source Indexed For these instructions, the source offset from the X register is stored in operand 1 of the instruction. During instruction execution, the current X register value is added to the signed offset, to determine the address of the source value in RAM or register address space. The result of these instructions is placed in either the M8C A or X register as indicated by the instruction’s opcode. All instructions using the Source Indexed addressing mode are two bytes in length. Table 2-8. Source Indexed Opcode Instruction Operand 1 Source Index Source Indexed Examples: Source Code Machine Code Comments ADD A, [X+7] 03 07 The value in memory at address X+7 is added to the Accumulator. The result is placed in the Accumulator. MOV X, [X+8] 59 08 The value in RAM at address X+8 is moved into the X register. 44 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CPU Core (M8C) 2.6.4 Destination Direct For these instructions, the destination address is stored in the machine code of the instruction. The source for the operation is either the M8C A or X register as indicated by the instruction’s opcode. All instructions using the Destination Direct addressing mode are two bytes in length. Table 2-9. Destination Direct Opcode Operand 1 Instruction Destination Address Destination Direct Examples: Source Code Machine Code Comments ADD [7], A 04 07 The value in the Accumulator is added to memory at address 7. The result is placed in memory at address 7. The Accumulator is unchanged. MOV REG[8], A 60 08 The Accumulator value is moved to register space at address 8. The Accumulator is unchanged. 2.6.5 Destination Indexed For these instructions, the destination offset from the X register is stored in the machine code for the instruction. The source for the operation is either the M8C A register or an immediate value as indicated by the instruction’s opcode. All instructions using the Destination Indexed addressing mode are two bytes in length. Table 2-10. Destination Indexed Opcode Instruction Operand 1 Destination Index Destination Indexed Example: Source Code Machine Code Comments ADD 05 07 The value in memory at address X+7 is added to the Accumulator. The result is placed in memory at address X+7. The Accumulator is unchanged. 2.6.6 [X+7], A Destination Direct Source Immediate For these instructions, the destination address is stored in operand 1 of the instruction. The source value is stored in operand 2 of the instruction. All instructions using the Destination Direct Source Immediate addressing mode are three bytes in length. Table 2-11. Destination Direct Source Immediate Opcode Instruction Operand 1 Destination Address Operand 2 Immediate Value Destination Direct Source Immediate Examples: Source Code Machine Code Comments ADD [7], 5 06 07 05 The value in memory at address 7 is added to the immediate value 5. The result is placed in memory at address 7. MOV REG[8], 6 62 08 06 The immediate value 6 is moved into register space at address 8. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 45 CPU Core (M8C) 2.6.7 Destination Indexed Source Immediate For these instructions, the destination offset from the X register is stored in operand 1 of the instruction. The source value is stored in operand 2 of the instruction. All instructions using the Destination Indexed Source Immediate addressing mode are three bytes in length. Table 2-12. Destination Indexed Source Immediate Opcode Instruction Operand 1 Destination Index Operand 2 Immediate Value Destination Indexed Source Immediate Examples: Source Code Machine Code Comments ADD [X+7], 5 07 07 05 The value in memory at address X+7 is added to the immediate value 5. The result is placed in memory at address X+7. MOV REG[X+8], 6 63 08 06 The immediate value 6 is moved into the register space at address X+8. 2.6.8 Destination Direct Source Direct Only one instruction uses this addressing mode. The destination address is stored in operand 1 of the instruction. The source address is stored in operand 2 of the instruction. The instruction using the Destination Direct Source Direct addressing mode is three bytes in length. Table 2-13. Destination Direct Source Direct Opcode Instruction Operand 1 Destination Address Operand 2 Source Address Destination Direct Source Direct Example: Source Code Machine Code Comments MOV 5F 07 08 The value in memory at address 8 is moved to memory at address 7. 46 [7], [8] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CPU Core (M8C) 2.6.9 Source Indirect Post Increment Only one instruction uses this addressing mode. The source address stored in operand 1 is actually the address of a pointer. During instruction execution, the pointer’s current value is read to determine the address in RAM where the source value is found. The pointer’s value is incremented after the source value is read. For PSoC microcontrollers with more than 256 bytes of RAM, the Data Page Read (MVR_PP) register is used to determine which RAM page to use with the source address. Therefore, values from pages other than the current page can be retrieved without changing the Current Page Pointer (CUR_PP). The pointer is always read from the current RAM page. For information on the MVR_PP and CUR_PP registers, see the Register Details chapter on page 125. The instruction using the Source Indirect Post Increment addressing mode is two bytes in length. Table 2-14. Source Indirect Post Increment Opcode Instruction Operand 1 Source Address Pointer Source Indirect Post Increment Example: Source Code Machine Code Comments MVI 3E 08 The value in memory at address 8 (the indirect address) points to a memory location in RAM. The value at the memory location, pointed to by the indirect address, is moved into the Accumulator. The indirect address, at address 8 in memory, is then incremented. 2.6.10 A, [8] Destination Indirect Post Increment Only one instruction uses this addressing mode. The destination address stored in operand 1 is actually the address of a pointer. During instruction execution, the pointer’s current value is read to determine the destination address in RAM where the Accumulator’s value is stored. The pointer’s value is incremented, after the value is written to the destination address. For PSoC microcontrollers with more than 256 bytes of RAM, the Data Page Write (MVW_PP) register is used to determine which RAM page to use with the destination address. Therefore, values can be stored in pages other than the current page without changing the Current Page Pointer (CUR_PP). The pointer is always read from the current RAM page. For information on the MVR_PP and CUR_PP registers, see the Register Details chapter on page 125. The instruction using the Destination Indirect Post Increment addressing mode is two bytes in length. Table 2-15. Destination Indirect Post Increment Opcode Instruction Operand 1 Destination Address Pointer Destination Indirect Post Increment Example: Source Code Machine Code Comments MVI 3F 08 The value in memory at address 8 (the indirect address) points to a memory location in RAM. The Accumulator value is moved into the memory location pointed to by the indirect address. The indirect address, at address 8 in memory, is then incremented. [8], A CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 47 CPU Core (M8C) 2.7 Register Definitions The following register is associated with the CPU Core (M8C). The register description has an associated register table showing the bit structure. The bits that are grayed out in the table are reserved bits and are not detailed in the register description that follows. Reserved bits should always be written with a value of ‘0’. 2.7.1 Address x,F7h CPU_F Register Name CPU_F Bit 7 Bit 6 Bit 5 PgMode[1:0] Bit 4 XIO Bit 3 Bit 2 Bit 1 Bit 0 Access Carry Zero GIE RL : 02h LEGEND L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register. x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. The M8C Flag Register (CPU_F) provides read access to the M8C flags. the PSoC Designer Assembly Guide User Manual for more details. Bits 7 and 6: PgMode[1:0]. PgMode determines how the CUR_PP, STK_PP, and IDX_PP registers are used in forming effective RAM addresses for Direct Address mode and Indexed Address mode operands. PgMode also determines whether the stack page is determined by the STK_PP or IDX_PP register. Bit 1: Zero. The Zero flag bit is set or cleared in response to the result of several instructions. It can also be manipulated by the flag-logic opcodes (for example, OR F, 2). See the PSoC Designer Assembly Guide User Manual for more details. Bit 4: XIO. The I/O Bank Select bit, also known as the register bank select bit, is used to select the register bank that is active for a register read or write. This bit allows the PSoC device to have 512 8-bit registers and therefore, can be thought of as the ninth address bit for registers. The address space accessed when the XIO bit is set to ‘0’ is called the user space, while the address space accessed when the XIO bit is set to ‘1’ is called the configuration space. Bit 2: Carry. The Carry flag bit is set or cleared in response to the result of several instructions. It can also be manipulated by the flag-logic opcodes (for example, OR F, 4). See 48 Bit 0: GIE. The state of the Global Interrupt Enable bit determines whether interrupts (by way of the interrupt request (IRQ)) will be recognized by the M8C. This bit is set or cleared by the user, using the flag-logic instructions (for example, OR F, 1). GIE is also cleared automatically when an interrupt is processed, after the flag byte has been stored on the stack, preventing nested interrupts. If desired, the bit can be set in an interrupt service routine (ISR). For GIE = 1, the M8C samples the IRQ input for each instruction. For GIE = 0, the M8C ignores the IRQ. For additional information, refer to the CPU_F register on page 214. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 3. Supervisory ROM (SROM) This chapter discusses the Supervisory ROM (SROM) functions. For a quick reference of all PSoC® registers in address order, refer to “Register Reference” on page 109. 3.1 Architectural Description The SROM holds code that boots the PSoC device, calibrate circuitry, and perform Flash operations. The functions provided by the SROM are called from code stored in the Flash or by device programmers. Table 3-1. List of SROM Functions Function Code The SROM boots the part and provide interface functions to the Flash banks. (Table 3-1 lists the SROM functions.) The SROM functions are accessed by using the Supervisory System Call instruction (SSC), which has an opcode of 00h. Before executing the SSC, the M8C’s accumulator needs to load with the desired SROM function code from Table 3-1. Attempting to access undefined functions causes a HALT. The SROM functions execute code with calls; therefore, the functions require stack space. With the exception of Reset, all of the SROM functions have a parameter block in SRAM that you must configure before executing the SSC. Table 3-2 lists all possible parameter block variables. The meaning of each parameter, with regards to a specific SROM function, is described later in this chapter. Because the SSC instruction clears the CPU_F PgMode bits, all parameter block variable addresses are in SRAM Page 0. The CPU_F value is automatically restored at the end of the SROM function. The MVR_PP and the MVW_PP pointers are not disabled by clearing the CPU_F PgMode bits. Therefore, the POINTER parameter is interpreted as an address in the page indicated by the MVI page pointers, when the supervisory operation is called. This allows the data buffer used in the supervisory operation to be located in any SRAM page. (See the RAM Paging chapter on page 57 for more details regarding the MVR_PP and MVW_PP pointers.) Function Name Stack Space Needed Page 00h SWBootReset 0 50 01h ReadBlock 7 51 02h WriteBlock 10 52 03h EraseBlock 9 52 06h TableRead 3 52 07h CheckSum 3 53 08h Calibrate0 4 53 09h Calibrate1 3 53 0Ah WriteAndVerify 7 54 0Fh HWBootReset 3 51 Note ProtectBlock (described on page 52) and EraseAll (described on page 53) SROM functions are not listed in the table because they depend upon external programming. Table 3-2. SROM Function Variables Variable Name KEY1 / RETURN CODE SRAM Address 0,F8h KEY2 0,F9h BLOCKID 0,FAh POINTER 0,FBh CLOCK 0,FCh Reserved 0,FDh DELAY 0,FEh Reserved 0,FFh Two important variables that are used for all functions are KEY1 and KEY2. These variables are used to help discriminate between valid SSCs and inadvertent SSCs. KEY1 must always have a value of 3Ah, while KEY2 must have the same value as the stack pointer when the SROM function begins execution. This is the SP (Stack Pointer) value when the SSC opcode is executed, plus three. For all SROM functions except SWBootReset, if either of the keys do not match the expected values, the M8C will halt. The SWBootReset function does not check the key values. It only checks to see if the accumulator’s value is 0x00. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 49 Supervisory ROM (SROM) The following code example puts the correct value in KEY1 and KEY2. The code is preceded by a HALT, to force the program to jump directly into the setup code and not accidentally run into it. 1. halt 2. SSCOP: mov [KEY1], 3ah 3. mov X, SP 4. mov A, X 5. add A, 3 6. mov [KEY2], A 3.1.1 In PSoC devices with more than 256 bytes of SRAM, no SRAM is modified by the SWBootReset function in SRAM pages numbered higher than ‘0’. Additional SROM Feature The SROM has these feature. Return Codes: Return codes aid in the determination of success or failure of a particular function. The return code is stored in KEY1’s position in the parameter block. The CheckSum and TableRead functions do not have return codes because KEY1’s position in the parameter block is used to return other data. Table 3-3. SROM Return Code Meanings Return Code Value more information on which SRAM addresses are modified.) If the checksum is not valid, an internal reset is executed and the boot process starts over. If this condition occurs, the internal reset status bit (IRESS) is set in the CPU_SCR1 register. Table 3-4 documents the value of all the SRAM addresses in Page 0 after a successful SWBootReset. A value of “xx” indicates that the SRAM address is not modified by the SWBootReset function. A hex value indicates that the address should always have the indicated value after a successful SWBootReset. A “??” indicates that the value, after a SWBootReset, is determined by the value of the IRAMDIS bit in the CPU_SCR1 register. If IRAMDIS is not set, these addresses will be initialized to 00h. If IRAMDIS is set, these addresses will not be modified by a SWBootReset after a watchdog reset. The IRAMDIS bit allows the preservation of variables even if a watchdog reset (WDR) occurs. The IRAMDIS bit is reset by all system resets except watchdog reset. Therefore, this bit is only useful for watchdog resets and not general resets. Description 00h Success 01h Function not allowed due to level of protection on the block. 02h Software reset without hardware reset. 03h Fatal error, SROM halted. Note Read, write, and erase operations may fail if the target block is read or write protected. Block protection levels are set during device programming and cannot be modified from code in the PSoC device. 3.1.2 3.1.2.1 SROM Function Descriptions SWBootReset Function The SROM function SWBootReset is responsible for transitioning the device from a reset state to running user code. See “System Resets” on page 513 for more information on what events causes the SWBootReset function to execute. The SWBootReset function is executed whenever the SROM is entered with an M8C accumulator value of 00h; the SRAM parameter block is not used as an input to the function. This happens, by design, after a hardware reset because the M8C's accumulator is reset to 00h or when user code executes the SSC instruction with an accumulator value of 00h. If the checksum of the calibration data is valid, the SWBootReset function ends by setting the internal M8C registers to 00h, writing 00h to most SRAM addresses in SRAM Page 0, and then begins to execute user code at address 0000h. (See Table 3-4 and the following paragraphs for 50 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Supervisory ROM (SROM) Table 3-4. SRAM Map Post SWBootReset (00h) Address 0x0_ 0x1_ 0x2_ 0x3_ 0x4_ 0x5_ 0x6_ 0x7_ 0x8_ 0x9_ 0xA_ 0xB_ 0xC_ 0xD_ 0xE_ 0xF_ 0 1 2 3 4 5 6 7 8 9 A B C D E F 0x00 0x00 0x00 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? Address Type ?? ?? ?? ?? ?? ?? ?? ?? KEY1 0,F8h RAM 3Ah ?? ?? ?? ?? ?? ?? ?? ?? KEY2 0,F9h RAM ?? ?? ?? ?? ?? ?? ?? ?? Stack Pointer value+3, when SSC is executed. ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ?? ?? 0x00 0x02 xx 0x00 0x00 0xn xx 0x00 0x00 Address F8h is the return code byte for all SROM functions (except Checksum and TableRead); for this function, the only acceptable values are 00h and 02h. Address FCh is the fail count variable. After POR (Power on Reset), WDR, or XRES (External Reset), the variable is initialized to 00h by the SROM. Each time the checksum fails, the fail count is incremented. Therefore, if it takes two passes through SWBootReset to get a good checksum, the fail count is 01h. 3.1.2.2 The HWBootReset function only requires that the CPU_A, KEY1, and KEY2 be setup correctly. As with all other SROM functions, if the setup is incorrect, the SROM executes a HALT. Then, either a POR, XRES, or WDR is needed to clear the HALT. See the System Resets chapter on page 123 for more information. HWBootReset Function The HWBootReset function forces a hardware reset of the PSoC. A hardware rest causes all registers to return to their POR state. Then, the SROM SWBootReset function executes, followed by Flash code execution beginning at address 0x0000. Table 3-5. HWBootReset Parameters (0Fh) Name 3.1.2.3 Description ReadBlock Function The ReadBlock function reads 64 contiguous bytes from Flash: a block. The CY8C28xxx PSoC devices have 16 KB of Flash and therefore have 256 64-byte blocks. Valid block IDs are 0x00 to 0xFF. Table 3-6. Flash Memory Organization PSoC Device Amount of Flash Amount of SRAM Number of Blocks per Bank Number of Banks 16 KB 1 KB 128 2 CY8C28xxx The first thing the ReadBlock function does is to check the protection bits to determine if the desired BLOCKID is readable. If read protection is turned on, the ReadBlock function exits setting the accumulator and KEY2 back to 00h. KEY1 has a value of 01h indicating a read failure. If read protection is not enabled, the function reads 64 bytes from the Flash using a ROMX instruction and stores the results in SRAM using an MVI instruction. The 64 bytes are stored in SRAM, beginning at the address indicated by the value of the POINTER parameter. When the ReadBlock completes successfully, the accumulator, KEY1, and KEY2 will all have a value of 00h. Note A MVI [expr], A is used to store the Flash block contents in SRAM; thus, you can the MVW_PP register to indicate which SRAM pages receive the data. Table 3-7. ReadBlock Parameters (01h) Name Address Type MVW_PP 0,D5h Register Description KEY1 0,F8h RAM 3Ah Stack Pointer value+3, when SSC is executed. MVI write page pointer register KEY2 0,F9h RAM BLOCKID 0,FAh RAM Flash block number RAM Addresses in SRAM where returned data should be stored. POINTER 0,FBh CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 51 Supervisory ROM (SROM) 3.1.2.4 WriteBlock Function The WriteBlock function stores data in the Flash. Data moves 64 bytes at a time from SRAM to Flash using this function. Before doing a write, you must successfully complete an EraseAll or an EraseBlock. The first thing the WriteBlock function does is check the protection bits and determine if the desired BLOCKID is writeable. If write protection is turned on, the WriteBlock function will exit, setting the accumulator and KEY2 back to 00h. KEY1 will have a value of 01h, indicating a write failure. Write protection is set when the PSoC device is programmed externally and cannot be changed through the SSC function. The BLOCKID of the Flash block, where the data is stored, must be determined and stored at SRAM address FAh. Valid block IDs are 0x00 to 0xFF. An MVI A, [expr] instruction is used to move data from SRAM into Flash. Therefore, the MVI read pointer (MVR_PP register) can be used to specify which SRAM page data is pulled from. Using the MVI read pointer and the parameter blocks POINTER value allows the SROM WriteBlock function to move data from any SRAM page into any Flash block. The SRAM address, of the first of the 64 bytes to be stored in Flash, must be indicated using the POINTER variable in the parameter block (SRAM address FBh). Finally, the CLOCK and DELAY value must be set correctly. The CLOCK value determines the length of the write pulse that will be used to store the data in the Flash. The CLOCK and DELAY values are dependent on the CPU speed and must be set correctly. Refer to “Clocking Strategy” on page 55 for additional information. Table 3-8. WriteBlock Parameters (02h) Address Type MVR_PP Name 0,D4h Register Description KEY1 0,F8h RAM 3Ah Stack Pointer value+3, when SSC is executed. MVI read page pointer register. 3.1.2.5 EraseBlock Function The EraseBlock function is used to erase a block of 64 contiguous bytes in Flash. The first thing the EraseBlock function does is check the protection bits and determine if the desired BLOCKID is writeable. If write protection is turned on, the EraseBlock function exits, setting the accumulator and KEY2 back to 00h. KEY1 has a value of 01h, indicating a write failure. To set up the parameter block for the EraseBlock function, store the correct key values in KEY1 and KEY2. The block number to erased must be stored in the BLOCKID variable, and the CLOCK and DELAY values must be set based on the current CPU speed. For more information on setting the CLOCK and DELAY values, see “Clocking Strategy” on page 55. Table 3-9. EraseBlock Parameters (03h) Address Type KEY1 Name 0,F8h RAM 3Ah Description KEY2 0,F9h RAM Stack Pointer value+3, when SSC is executed. BLOCKID 0,FAh RAM Flash block number CLOCK 0,FCh RAM Clock divider used to set the erase pulse width. DELAY 0,FEh RAM For a CPU speed of 12 MHz set to 56h. The CPU must be less than or equal to 12 MHz for the operation to work correctly. 3.1.2.6 ProtectBlock Function The PSoC devices offer Flash protection on a block-byblock basis. Table 3-10 lists the protection modes available. In the table, ER and EW are used to indicate the ability to perform external reads and writes (that is, by an external programmer). For internal writes, IW is used. Internal reading is always permitted by way of the ROMX instruction. The ability to read by way of the SROM ReadBlock function is indicated by SR. KEY2 0,F9h RAM BLOCKID 0,FAh RAM Flash block number In this table, note that all protection is removed by EraseAll. Table 3-10. Protect Block Modes POINTER 0,FBh RAM First of 64 addresses in SRAM, where the data to be stored in Flash is located prior to calling WriteBlock. CLOCK 0,FCh RAM Clock divider used to set the write pulse width. DELAY 0,FEh RAM For a CPU speed of 12 MHz set to 56h. The CPU must be less than or equal to 12 MHz for the operation to work correctly. Mode Settings 00b SR ER EW IW 01b 10b 11b 3.1.2.7 Description In PSoC Designer Unprotected U = Unprotected SR ER EW IW Read protect F = Factory upgrade SR ER EW IW Disable external write R = Field upgrade SR ER EW IW Disable internal write W = Full protection TableRead Function The TableRead function gives the user access to part-specific data stored in the Flash during manufacturing. The Flash for these tables is separate from the program Flash and is not directly accessible. 52 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Supervisory ROM (SROM) One of the uses of the TableRead function is to retrieve the values needed to optimize Flash programming for temperature. More information about how to use these values is in the section titled “Clocking Strategy” on page 55. 3.1.2.8 protection block in each Flash bank to all zeros (the unprotected state). This function is only executed by an external programmer. If EraseAll is executed from code, the M8C will HALT without touching the Flash or protections. See Table 3-11. EraseAll Function The EraseAll function performs a series of steps that destroys the user data in the Flash banks and resets the Table 3-11. Flash Tables with Assigned Values in Flash Bank 0 F8h F9h Table 0 Silicon ID Table 1 Voltage Reference Trim for 3.3 V FAh Room Temperature Calibration for 3.3 V IMO Trim for 3.3 V reg[1,E8] reg[1,EA] FBh Hot Temperature Calibration for 3.3 V 3.1.2.9 M (cold) B (cold) Mult (cold) Checksum Function The 16-bit checksum is returned in KEY1 and KEY2. The parameter KEY1 holds the lower 8 bits of the checksum and the parameter KEY2 holds the upper 8 bits of the checksum. Table 3-12. Checksum Parameters (07h) Address Type KEY1 0,F8h RAM 3Ah KEY2 0,F9h RAM Stack Pointer value+3, when SSC is executed. BLOCKID 0,FAh RAM Number of Flash blocks to calculate checksum on. 3.1.2.10 Voltage Reference Trim for 5 V FEh Room Temperature Calibration for 5 V IMO Trim for 5 V reg[1,E8] reg[1,EA] M (hot) The Checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single Flash bank starting at block zero. The BLOCKID parameter is used to pass in the number of blocks to checksum. A BLOCKID value of ‘1’ calculates the checksum of only block 0, while a BLOCKID value of ‘0’ calculates the checksum of the entire Flash bank. Name FDh IMO Slow Trim 6 MHz Vdd = 3.3 V Table 2 Table 3 FCh Description Calibrate0 Function The Calibrate0 function transfers the calibration values stored in a special area of the Flash to their appropriate registers. This function may be executed at any time to set all calibration values back to their 5-V values. However, it is unnecessary to call this function. This function is simply documented for completeness. 3.3-V calibration values are accessed by way of the TableRead function, which is described in the section titled “TableRead Function” on page 52. B (hot) FFh Hot Temperature Calibration for 5 V IMO Slow Trim 6 MHz Vdd = 5.0 V Mult (hot) 00h 01h Table 3-13. Calibrate0 Parameters (08h) Address Type KEY1 Name 0,F8h RAM 3Ah KEY2 0,F9h RAM Stack Pointer value+3, when SSC is executed. 3.1.2.11 Description Calibrate1 Function While the Calibrate1 function is a completely separate function from Calibrate0, they perform the same task, which is to transfer the calibration values stored in a special area of the Flash to their appropriate registers. What is unique about Calibrate1 is that it calculates a checksum of the calibration data and, if that checksum is determined as invalid, Calibrate1 causes a hardware reset by generating an internal reset. If this occurs, it is indicated by setting the Internal Reset Status bit (IRESS) in the CPU_SCR1 register. The Calibrate1 function uses SRAM to calculate a checksum of the calibration data. The POINTER value is used to indicate the address of a 30-byte buffer used by this function. When the function completes, the 30 bytes are set to 00h. An MVI A, [expr] and an MVI [expr], A instruction are used to move data between SRAM and Flash. Therefore, the MVI write pointer (MVW_PP) and the MVI read pointer (MVR_PP) must be specified to the same SRAM page to control the page of RAM used for the operations. Calibrate1 was created as a subfunction of SWBootReset and the Calibrate1 function code was added to provide CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 53 Supervisory ROM (SROM) 3.1.2.12 direct access. For more information on how Calibrate1 works, see the “SWBootReset Function” on page 50. The WriteAndVerify function works exactly the same as the WriteBlock function with one exception. When the write operation has completed, the SROM will then read back the contents of Flash and compare those values against the values in SRAM thus verifying that the write was successful. The write and verify is one SROM operation; therefore, the SROM is not exited until the verify is completed. This function may be executed at any time to set all calibration values back to their 5-V values. However, it is unnecessary to call this function. This function is simply documented for completeness. This function has no argument to select between 5-V and 3.3-V calibration values; therefore, it always defaults to 5-V values. 3.3-V calibration values are accessed by way of the TableRead function, which is described in the section titled “TableRead Function” on page 52. The parameters for this block are identical to the WriteBlock (see “WriteBlock Parameters (02h)” on page 52). If the verify operation fails, the 0x04 error code is returned at SRAM address 0xF8. If the write fails, the 0x01 error code returns at SRAM address 0xF8. Table 3-14. Calibrate1 Parameters (09h) Address Type KEY1 Name 0,F8h RAM 3Ah KEY2 0,F9h RAM Stack Pointer value+3, when SSC is executed. First of 30 SRAM addresses used by this function. Description POINTER 0,FBh RAM MVR_PP 0,D4h Register MVI write page pointer MVW_PP 0,D5h Register MVI read page pointer 3.2 3.2.1 Address 1,FAh Table 3-15. WriteAndVerify Parameters (0Ah) Name Address Type Description KEY1 0,F8h RAM 3Ah KEY2 0,F9h RAM Stack Pointer value+3, when SSC is executed. BLOCKID 0,FAh RAM Flash block number. POINTER 0,FBh RAM First of 64 addresses in SRAM, where the data to be stored in Flash is located prior to calling WriteBlock. CLOCK 0,FCh RAM Clock divider used to set the write pulse width. DELAY 0,FEh RAM For a CPU speed of 12 MHz set to 56h. Register Definitions FLS_PR1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 FLS_PR1 The Flash Program Register 1 (FLS_PR1) is used to specify which Flash bank should be used for SROM operations. Note This register has no effect on products with one Flash bank. Refer to the table titled “Flash Memory Organization” on page 51 to determine the number of Flash banks in PSoC devices. 3.2.2 WriteAndVerify Function Access RW : 00 Bit 0: Bank. The Bank bit in this register indicates which Flash bank the SROM Flash functions should operate on. The default value for the Bank bit is zero. Flash bank 0 holds up to the first 8K of user code, as well as the cal table. The optional Flash bank 1 holds additional user code. For additional information, refer to the FLS_PR1 register on page 308. Related Registers ■ “STK_PP Register” on page 61. ■ “MVW_PP Register” on page 62. ■ “MVR_PP Register” on page 61. ■ “CPU_SCR1 Register” on page 514. 54 Bit 0 Bank CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Supervisory ROM (SROM) 3.3 Clocking Strategy Successful programming and erase operations, on the Flash, require you to set the CLOCK and DELAY parameters correctly. To determine the proper value for the DELAY parameter only, you must consider CPU speed. Use three factors to determine the proper value for CLOCK: operating temperature, CPU speed, and characteristics of the individual device. Equations and additional information on calculating the DELAY and CLOCK values follow. 3.3.1 DELAY Parameter To determine the proper value for the DELAY parameter, you must consider CPU speed during a Flash operation. Equation 1 displays the equation for calculating DELAY based on a CPU speed value. In this equation the units for CPU are hertz (Hz). –6 100 10 CPU – 80 DELAY = ---------------------------------------------------------- 13 Equation 1 Using the correct values for B, M, and T, in the Equation 3, is required to achieve the endurance specifications of the Flash. However, for device programmers where this calculation is difficult to perform, the equation is simplified by setting T to 0°C and using the hot value for B and M. This simplification is acceptable only if the total number of erase write cycles are kept to less than 10 and the operation is performed near room temperature. When T is set to ‘0’, Equation 3 simplifies to. CLOCK E = B Equation 4 When a value for the erase CLOCK value is determined, the write CLOCK value can be calculated. The equation to calculate the CLOCK value for a write is. CLOCK E Mult CLOCK W = ---------------------------------------64 Equation 5 In this equation, the correct value for Mult must be determined, based upon temperature, in the same way that the B and M values were determined for Equation 3. 3MHz CPU 12MHz Equation 2 shows the calculation of the DELAY value for a CPU speed of 12 MHz. The numerical result of this calculation should be rounded to the nearest whole number. In the case of a 12 MHz CPU speed, the correct value for DELAY is 86 (0x56). –6 6 10 12 10 – 80 DELAY = 100 --------------------------------------------------------------13 3.3.2 Equation 2 CLOCK Parameter The CLOCK parameter must be calculated using different equations for erase and write operations. The erase value for CLOCK must be calculated first. In Equation 3, the erase CLOCK value is indicated by a subscript E after the word CLOCK. In Equation 5, the write CLOCK value is indicated by a subscript W after the word CLOCK. Before either CLOCK value can be calculated, the values for M, B, and Mult must be determined. These are device specific values that are stored in the Flash Table 3 and are accessed by way of the TableRead SROM function (see the “TableRead Function” on page 52). If the operating temperature is at or below 0°C, use the cold values. For operating temperatures at or above 0°C, use the hot values. See Table 3-11 for more information. Equations for calculating the correct value of CLOCK for write operations are first introduced with the assumption that the CPU speed is 12 MHz. The equation for calculating the CLOCK value for an erase Flash operation is shown in Equation 3. In this equation the T has units of °C. TCLOCK E = B – 2M --------------256 Equation 3 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 55 Supervisory ROM (SROM) 56 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 4. RAM Paging This chapter explains the PSoC® device’s use of RAM Paging and its associated registers. For a complete table of the RAM Paging registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 4.1 Architectural Description The M8C is an 8-bit CPU with an 8-bit address bus. The 8bit memory address bus allows the M8C to access up to 256 bytes of SRAM, to increase the amount of available SRAM and preserve the M8C assembly language. PSoC devices with more than 256 bytes of SRAM have a paged memory architecture. The CY8C28xxx devices have 1 KB of RAM; thus, they have four pages. To take full advantage of the paged memory architecture of the PSoC device, several registers must be used and two CPU_F register bits must be managed. However, the Power On Reset (POR) value for all of the paging registers and CPU_F bits is zero. This places the PSoC device in a mode identical to PSoC devices with only 256 bytes of SRAM. It is not necessary to understand all of the Paging registers to take advantage of the additional SRAM available in some devices. Very simple modifications to the reset state of the memory paging logic can be made, to begin to take advantage of the additional SRAM pages. The memory paging architecture consists of five areas: ■ Stack Operations ■ Interrupts ■ MVI Instructions ■ Current Page Pointer ■ Indexed Memory Page Pointer The first three of these areas have no dependency on the CPU_F register's PgMode bits and are covered in the next subsections after Basic Paging. The function of the last two depend on the CPU_F PgMode bits and will be covered last. 4.1.1 Basic Paging The M8C is an 8-bit CPU with an 8-bit memory address bus. The memory address bus allows the M8C to access up to 256 bytes of SRAM. To increase the amount of SRAM, the M8C accesses memory page bits. The memory page bits are located in the CUR_PP register and allow for selection of one of eight SRAM pages. In addition to setting the page bits, Page mode must be enabled by setting the CPU_F[7] bit. If Page mode is not enabled, the page bits are ignored and all non-stack memory access is directed to Page 0. After Page mode is enabled and the page bits are set, all instructions that operate on memory access the SRAM page indicated by the page bits. The exceptions to this are the instructions that operate on the stack and the MVI instructions: PUSH, POP, LCALL, RETI, RET, CALL, and MVI. See the description of “Stack Operations” on page 58 and see “MVI Instructions” on page 58 for a more detailed discussion. Figure 4-1. Data Memory Organization 00h Page 0 SRAM 256 Bytes FFh Page 1 SRAM 256 Bytes Page 2 SRAM 256 Bytes Page 3 SRAM 256 Bytes Page 4 SRAM 256 Bytes Page 5 SRAM 256 Bytes Page 6 SRAM 256 Bytes Page 7 SRAM 256 Bytes ISR CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 57 RAM Paging 4.1.2 Stack Operations As mentioned previously, the paging architecture's reset state puts the PSoC in a mode that is identical to that of a 256 byte PSoC device. Therefore, upon rest, all memory accesses will be to Page 0. The SRAM page that stack operations will use is determined by the value of the three least significant bits of the stack page pointer register (STK_PP). Stack operations have no dependency on the PgMode bits in the CPU_F register. Stack operations are those that use the Stack Pointer (SP) to calculate their affected address. Refer to the PSoC Designer Assembly Language User Guide for more information on all M8C instructions. Stack memory accesses must be treated as a special case. If they are not, the stack can be fragmented across several pages. To prevent the stack from becoming fragmented, all instructions that operate on the stack automatically use the page indicated by the STK_PP register. Therefore, if a CALL is encountered in the program, the PSoC device will automatically push the program counter onto the stack page indicated by STK_PP. When the program counter is pushed, the SRAM paging mode automatically switches back to the precall mode. All other stack operations, such as RET and POP, follow the same rule as CALL. The stack is confined to a single SRAM page and the Stack Pointer will wrap from 00h to FFh and FFh to 00h. The user code must ensure that the stack is not damaged due to stack wrapping. Because the value of the STK_PP register can be changed at any time, it is theoretically possible to manage the stack in such a way as to allow it to grow beyond one SRAM page or manage multiple stacks. However, the only supported use of the STK_PP register is when its value is set prior to the first stack operation and not changed again. 4.1.3 Interrupts Interrupts, in a multi-page SRAM PSoC device, operate the same as interrupts in a 256 byte PSoC device. However, because the CPU_F register is automatically set to 0x00 on an interrupt and because of the non-linear nature of interrupts in a system, other parts of the PSoC memory paging architecture can be affected. Interrupts are an abrupt change in program flow. If no special action is taken on interrupts by the PSoC device, the interrupt service routine (ISR) could be thrown into any SRAM page. To prevent this problem, the special addressing modes for all memory accesses, except for stack and MVI, are disabled when an ISR is entered. The special addressing modes are disabled when the CUP_F register is cleared. At the end of the ISR, the previous SRAM addressing mode is restored when the CPU_F register value is restored by the RETI instruction. Therefore, all interrupt service routine code will start execution in SRAM Page 0. If it is necessary for the ISR to change to another SRAM page, it can be accomplished by changing the values of the CPU_F[7:6] bits to enable the special 58 SRAM addressing modes. However, any change made to the CUR_PP, IDX_PP, or STK_PP registers will persist after the ISR returns. Therefore, the ISR should save the current value of any paging register it modifies and restore its value before the ISR returns. 4.1.4 MVI Instructions MVI instructions use data page pointers of their own (MVR_PP and MVW_PP). This allows a data buffer to be located away from other program variables, but accessible without changing the Current Page Pointer (CUR_PP). An MVI instruction performs three memory operations. Both forms of the MVI instruction access an address in SRAM that holds the data pointer (a memory read 1st access), incrementing that value and then storing it back in SRAM (a memory write 2nd access). This pointer value must reside in the current page, just as all other non-stack and nonindexed operations on memory must. However, the third memory operation uses the MVx_PP register. This third memory access can be either a read or a write, depending on which MVI instruction is used. The MVR_PP pointer is used for the MVI instruction that moves data into the accumulator. The MVW_PP pointer is used for the MVI instruction that moves data from the accumulator into SRAM. The MVI pointers are always enabled, regardless of the state of the Flag register page bits (CPU_F register). 4.1.5 Current Page Pointer The Current Page Pointer is used to determine which SRAM page should be used for all memory accesses. Normal memory accesses are those not covered by other pointers including all non-stack, non-MVI, and non-indexed memory access instructions. The normal memory access instructions have the SRAM page they operate on determined by the value of the CUR_PP register. By default, the CUR_PP register has no affect on the SRAM page that will be used for normal memory access, because all normal memory access is forced to SRAM Page 0. The upper bit of the PgMode bits in the CPU_F register determine whether or not the CUR_PP register affects normal memory access. When the upper bit of the PgMode bits is set to ‘0’, all normal memory access is forced to SRAM Page 0. This mode is automatically enabled when an Interrupt Service Routine (ISR) is entered. This is because, before the ISR is entered, the M8C pushes the current value of the CPU_F register onto the stack and then clears the CPU_F register. Therefore, by default, any normal memory access in an ISR is guaranteed to occur in SRAM Page 0. When the RETI instruction is executed, to end the ISR, the previous value of the CPU_F register is restored, restoring the previous page mode. Note that this ISR behavior is the default and that the PgMode bits in the CPU_F register can be changed while in an ISR. If the PgMode bits are changed while in an ISR, the pre-ISR value is still restored by the CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RAM Paging RETI; but if the CUR_PP register is changed in the ISR, the ISR is also required to restore the value before executing the RETI instruction. When the upper bit of the PgMode bits is set to ‘1’, all normal memory access is forced to the SRAM page indicated by the value of the CUR_PP register. Table 4-1 gives a summary of the PgMode bit values and the corresponding Memory Paging mode. 4.1.6 Index Memory Page Pointer The source indexed and destination indexed addressing modes to SRAM are treated as a unique addressing mode in a PSoC device, with more than one page of SRAM. An example of an indexed addressing mode is the MOV A, [X+expr] instruction. Note that register access also has indexed addressing; however, those instructions are not affected by the SRAM paging architecture. Important Note If you are not using assembly to program a PSoC device, be aware that the compiler writer may restrict the use of some memory paging modes. Review the conventions in your compiler’s user guide for more information on restrictions or conventions associated with memory paging modes. Indexed SRAM accesses operate in one of three modes: ■ Index memory access modes are forced to SRAM Page 0. ■ Index memory access modes are directed to the SRAM page indicated by the value in the STK_PP register. ■ Index memory access is forced to the SRAM page indicated by the value in the IDX_PP register. The mode is determined by the value of the PgMode bits in the CPU_F register. However, the final SRAM page that is used also requires setting either the Stack Page Pointer (STK_PP) register or the Index Page Pointer (IDX_PP) register. Table 4-1 shows the three indexed memory access modes. The third column of the table is provided for reference only. After reset, the PgMode bits are set to 00b. In this mode, index memory accesses are forced to SRAM Page 0, just as they are in a PSoC device with only 256 bytes of SRAM. This mode is also automatically enabled when an interrupt occurs in a PSoC device and is therefore considered the default ISR mode. This is because before the ISR is entered, the M8C pushes the current value of the CPU_F register on to the stack and then clears the CPU_F register. Therefore, by default, any indexed memory access in an ISR is guaranteed to occur in SRAM Page 0. When the RETI instruction is executed to end the ISR, the previous value of the CPU_F register is restored and the previous page mode is then also restored. Note that this ISR behavior is the default and that the PgMode bits in the CPU_F register may be changed while in an ISR. If the PgMode bits are changed while in an ISR, the pre-ISR value is still restored by the RETI; but if the STK_PP or IDX_PP registers are changed in the ISR, the ISR is also required to restore the values before executing the RETI instruction. The most likely PgMode bit change, while in an ISR, is from the default value of 00b to 01b. In the 01b mode, indexed memory access is directed to the SRAM page indicated by the value of the STK_PP register. By using the PgMode, the value of the STK_PP register is not required to be modified. The STK_PP register is the register that determines which SRAM page the stack is located on. The 01b paging mode is intended to provide easy access to the stack, while in an ISR, by setting the CPU_X register (just X in the instruction format) equal to the value of SP using the MOV X, SP instruction. The two previous paragraphs covered two of the three indexed memory access modes: STK_PP and forced to SRAM Page 0. Note, as shown in Table 4-1, that the STK_PP mode for indexed memory access is available under two PgMode settings. The 01b mode is intended for ISR use and the 11b mode is intended for non-ISR use. The third indexed memory access mode requires the PgMode bits to be set to 10b. In this mode indexed memory access is forced to the SRAM page indicated by the value of the IDX_PP register. Table 4-1. CPU_F PgMode Bit Modes CPU_F PgMode BIts Current SRAM Page Indexed SRAM Page 00b 0 0 01b 0 STK_PP 10b CUR_PP IDX_PP 11b CUR_PP STK_PP Typical Use ISR* ISR with variables on stack * Mode used by SROM functions initiated by the SSC instruction. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 59 RAM Paging 4.2 Register Definitions The following registers are associated with RAM Paging and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. For a complete table of RAM Paging registers, refer to the “Summary Table of the Core Registers” on page 36. 4.2.1 Address x,6xh TMP_DRx Registers Name Bit 7 Bit 6 Bit 5 Bit 4 TMP_DRx Bit 3 Bit 2 Bit 1 Bit 0 Data[7:0] Access RW : 00 LEGEND x An ‘x’ before the comma in the address field indicates that this register can be read or written to no matter what bank is used. An “x” after the comma in the address field indicates that there are multiple instances of the register. The Temporary Data Registers (TMP_DR0, TMP_DR1, TMP_DR2, and TMP_DR3) are used to enhance the performance in multiple SRAM page PSoC devices. changing the current page. The TMP_DRx registers are readable and writeable registers that are provided to improve the performance of multiple SRAM page PSoC devices, by supplying some register space for data that is always accessible. These registers have no pre-defined function (for example, the compiler and hardware do not use these registers) and exist for the user to use as desired. For an expanded listing of the TMP_DRx registers, refer to the “Summary Table of the Core Registers” on page 36. For additional information, refer to the TMP_DRx register on page 155. Bits 7 to 0: Data[7:0]. Due to the paged SRAM architecture of PSoC devices with more than 256 bytes of SRAM, a value in SRAM may not always be accessible without first 4.2.2 Address 0,D0h CUR_PP Register Name Bit 7 Bit 6 Bit 5 CUR_PP Bit 4 Bit 3 Bit 2 Bit 1 Page Bits[2:0] Bit 0 Access RW : 00 The Current Page Pointer Register (CUR_PP) is used to set the effective SRAM page for normal memory accesses in a multi-SRAM page PSoC device. Bits 2 to 0: Page Bits[2:0]. These bits affect the SRAM page that is accessed by an instruction when the CPU_F[7:0] bits have a value of either 10b or 11b. Source indexed and destination indexed addressing modes, as well as stack instructions, are never affected by the value of the CUR_PP register. (See the STK_PP and IDX_PP registers for more information.) The source indirect post increment and destination indirect post increment addressing modes, better know as MVI, are only partially affected by the value of the CUR_PP register. For MVI instructions, the pointer address is in the SRAM page indicated by CUR_PP, but the address pointed to may be in another SRAM page. See the MVR_PP and MVW_PP register descriptions for more information. For additional information, refer to the CUR_PP register on page 189. 60 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RAM Paging 4.2.3 Address 0,D1h STK_PP Register Name Bit 7 Bit 6 Bit 5 Bit 4 For additional information, refer to the STK_PP register on page 190. IDX_PP Register Name Bit 7 Bit 6 Bit 5 Bit 4 Address Bit 3 Bit 2 IDX_PP Bit 1 Bit 0 Page Bits[2:0] Access RW : 00 When CPU_F[7:6] is set to 10b and an indexed memory access is made, the access is directed to the SRAM page indicated by the value of the IDX_PP register. See the STK_PP register description for more information on other indexed memory access modes. Bits 2 to 0: Page Bits[2:0]. These bits allow instructions, which use the source indexed and destination indexed address modes, to operate on an SRAM page that is not equal to the current SRAM page. However, the effect this register has on indexed addressing modes is only enabled when the CPU_F[7:6] is set to 10b. 0,D4h Access RW : 00 The second type of memory accesses that the STK_PP register affects are indexed memory accesses when the CPU_F[7:6] bits are set to 11b. In this mode, source indexed and destination indexed memory accesses are directed to the stack SRAM page, rather than the SRAM page indicated by the IDX_PP register or SRAM Page 0. The Index Page Pointer Register (IDX_PP) is used to set the effective SRAM page for indexed memory accesses in a multi-SRAM page PSoC device. 4.2.5 Bit 0 Note that the impact that the STK_PP register has on the stack is independent of the SRAM Paging bits in the CPU_F register. The purpose of this register is to determine which SRAM page the stack will be stored on. In the reset state, this register's value will be 0x00 and the stack will therefore be in SRAM Page 0. However, if the STK_PP register value is changed, the next stack operation will occur on the SRAM page indicated by the new STK_PP value. Therefore, the value of this register should be set early in the program and never be changed. If the program changes the STK_PP Address Bit 1 value after the stack has grown, the program must ensure that the STK_PP value is restored when needed. Bits 2 to 0: Page Bits[2:0]. These bits have the potential to affect two types of memory access. 0,D3h Bit 2 Page Bits[2:0] The Stack Page Pointer Register (STK_PP) is used to set the effective SRAM page for stack memory accesses in a multi-SRAM page PSoC device. 4.2.4 Bit 3 STK_PP For additional information, refer to the IDX_PP register on page 191. MVR_PP Register Name Bit 7 Bit 6 Bit 5 MVR_PP The MVI Read Page Pointer Register (MVR_PP) is used to set the effective SRAM page for MVI read memory accesses in a multi-SRAM page PSoC device. Bits 2 to 0: Page Bits[2:0]. These bits are only used by the MVI A, [expr] instruction, not to be confused with the MVI [expr], A instruction covered by the MVW_PP register. This instruction is considered a read because data is transferred from SRAM to the microprocessor's A register (CPU_A). Bit 4 Bit 3 Bit 2 Bit 1 Page Bits[2:0] Bit 0 Access RW : 00 is read by the instruction is determined by the value of the least significant bits in this register. However, the pointer for the MVI A, [expr] instruction is always located in the current SRAM page. See the PSoC Designer Assembly Language User Guide for more information on the MVI A, [expr] instruction. The function of this register and the MVI instructions are independent of the SRAM Paging bits in the CPU_F register. For additional information, refer to the MVR_PP register on page 192. When an MVI A, [expr] instruction is executed in a device with more than one page of SRAM, the SRAM address that CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 61 RAM Paging 4.2.6 Address 0,D5h MVW_PP Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Access RW : 00 The function of this register and the MVI instructions are independent of the SRAM Paging bits in the CPU_F register. For additional information, refer to the MVW_PP register on page 193. When an MVI [expr], A instruction is executed in a device with more than one page of SRAM, the SRAM address that Address Bit 1 is written by the instruction is determined by the value of the least significant bits in this register. However, the pointer for the MVI [expr], A instruction is always located in the current SRAM page. See the PSoC Designer Assembly Language User Guide for more information on the MVI [expr], A instruction. Bits 2 to 0: Page Bits[2:0]. These bits are only used by the MVI [expr], A instruction, not to be confused with the MVI A, [expr] instruction covered by the MVR_PP register. This instruction is considered a write because data is transferred from the microprocessor's A register (CPU_A) to SRAM. x,F7h Bit 2 Page Bits[2:0] The MVI Write Page Pointer Register (MVW_PP) is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page PSoC device. 4.2.7 Bit 3 MVW_PP CPU_F Register Name CPU_F Bit 7 Bit 6 Bit 5 PgMode[1:0] Bit 4 Bit 3 XIO Bit 2 Bit 1 Bit 0 Access Carry Zero GIE RL : 02 LEGEND L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register. x An ‘x’ before the comma in the address field indicates that this register can be read or written to no matter what bank is used. The M8C Flag Register (CPU_F) provides read access to the M8C flags. space accessed when the XIO bit is set to ‘0’ is called the user space, while the address space accessed when the XIO bit is set to ‘1’ is called the configuration space. Bits 7 and 6: PgMode[1:0]. PgMode determines how the CUR_PP and IDX_PP registers are used in forming effective RAM addresses for Direct Address mode and Indexed Address mode operands. Bit 2: Carry. The Carry Flag bit is set or cleared in response to the result of several instructions. It can also be manipulated by the flag-logic opcodes (for example, OR F, 4). See the PSoC Designer Assembly Guide User Manual for more details. Bit 4: XIO. The I/O Bank Select bit, also know as the register bank select bit, is used to select the register bank that is active for a register read or write. This bit allows the PSoC device to have 512 8-bit registers and therefore, can be thought of as the ninth address bit for registers. The address 4.2.8 Address 0,D4h MVR_PP Register Name Bit 7 Bit 6 Bit 5 MVR_PP Bit 4 Bit 3 Bit 2 Bit 1 Page Bits[2:0] The MVI Read Page Pointer Register (MVR_PP) is used to set the effective SRAM page for MVI read memory accesses in a multi-SRAM page PSoC device. Bits 2 to 0: Page Bits[2:0]. These bits are only used by the MVI A, [expr] instruction, not to be confused with the MVI [expr], A instruction covered by the MVW_PP register. This 62 Bit 1: Zero. The Zero Flag bit is set or cleared in response to the result of several instructions. It can also be manipulated by the flag-logic opcodes (for exam Bit 0 Access RW : 00 instruction is considered a read because data is transferred from SRAM to the microprocessor's A register (CPU_A). When an MVI A, [expr] instruction is executed in a device with more than one page of SRAM, the SRAM address that is read by the instruction is determined by the value of the least significant bits in this register. However, the pointer for the MVI A, [expr] instruction is always located in the current SRAM page. See the PSoC Designer Assembly Language CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RAM Paging User Guide for more information on the MVI A, [expr] instruction. 4.2.9 Address 0,D5h The function of this register and the MVI instructions are independent of the SRAM Paging bits in the CPU_F register. For additional information, refer to the MVR_PP register on page 192. MVW_PP Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 MVW_PP Bit 1 Bit 0 Page Bits[2:0] The MVI Write Page Pointer Register (MVW_PP) is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page PSoC device. Access RW : 00 is written by the instruction is determined by the value of the least significant bits in this register. However, the pointer for the MVI [expr], A instruction is always located in the current SRAM page. See the PSoC Designer Assembly Language User Guide for more information on the MVI [expr], A instruction. Bits 2 to 0: Page Bits[2:0]. These bits are only used by the MVI [expr], A instruction, not to be confused with the MVI A, [expr] instruction covered by the MVR_PP register. This instruction is considered a write because data is transferred from the microprocessor's A register (CPU_A) to SRAM. The function of this register and the MVI instructions are independent of the SRAM Paging bits in the CPU_F register. For additional information, refer to the MVW_PP register on page 193. When an MVI [expr], A instruction is executed in a device with more than one page of SRAM, the SRAM address that 4.2.10 Address x,F7h CPU_F Register Name CPU_F Bit 7 Bit 6 Bit 5 PgMode[1:0] Bit 4 XIO Bit 3 Bit 2 Bit 1 Bit 0 Access Carry Zero GIE RL : 02 LEGEND L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register. x An ‘x’ before the comma in the address field indicates that this register can be read or written to no matter what bank is used. The M8C Flag Register (CPU_F) provides read access to the M8C flags. OR F, 4). See the PSoC Designer Assembly Guide User Manual for more details. Bits 7 and 6: PgMode[1:0]. PgMode determines how the CUR_PP and IDX_PP registers are used in forming effective RAM addresses for Direct Address mode and Indexed Address mode operands. Bit 1: Zero. The Zero Flag bit is set or cleared in response to the result of several instructions. It can also be manipulated by the flag-logic opcodes (for example, OR F, 2). See the PSoC Designer Assembly Guide User Manual for more details. Bit 4: XIO. The I/O Bank Select bit, also know as the register bank select bit, is used to select the register bank that is active for a register read or write. This bit allows the PSoC device to have 512 8-bit registers and therefore, can be thought of as the ninth address bit for registers. The address space accessed when the XIO bit is set to ‘0’ is called the user space, while the address space accessed when the XIO bit is set to ‘1’ is called the configuration space. Bit 2: Carry. The Carry Flag bit is set or cleared in response to the result of several instructions. It can also be manipulated by the flag-logic opcodes (for example, Bit 0: GIE. The state of the Global Interrupt Enable bit determines whether interrupts (by way of the IRQ) will be recognized by the M8C. This bit is set or cleared by the user, using the flag-logic instructions (for example, OR F, 1). GIE is also cleared automatically by the M8C upon entering the interrupt service routine (ISR), after the flag byte has been stored on the stack, preventing nested interrupts. Note that the bit can be set in an ISR if desired. For GIE = 1, the M8C samples the IRQ input for each instruction. For GIE = 0, the M8C ignores the IRQ. For additional information, refer to the CPU_F register on page 214. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 63 RAM Paging 64 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 5. Interrupt Controller This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a hardware resource in PSoC® devices, to change program execution to a new address without regard to the current task being performed by the code being executed. For a complete table of the Interrupt Controller registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 5.1 Architectural Description A block diagram of the PSoC Interrupt Controller is shown in Figure 5-1, illustrating the concepts of posted interrupts and pending interrupts. Figure 5-1. Interrupt Controller Block Diagram Priority Encoder Interrupt Taken or Interrupt Vector INT_CLRx:n Write Posted Interrupt Interrupt Request Pending Interrupt 0 1 Interrupt Source (Timer, GPIO, etc.) D Q n M8C Core ... ... R CPU_F[0] GIE INT_MSKx:n Mask Bit Setting The sequence of events that occur during interrupt processing is as follows. a. The PCH, PCL, and Flag register (CPU_F) are pushed onto the stack (in that order). 1. An interrupt becomes active, either because (a) the interrupt condition occurs (for example, a timer expires), (b) a previously posted interrupt is enabled through an update of an interrupt mask register, or (c) an interrupt is pending and GIE is set from ‘0’ to ‘1’ in the CPU Flag register. b. The CPU_F register is then cleared. Because this clears the GIE bit to 0, additional interrupts are temporarily disabled. 2. The current executing instruction finishes. 3. The internal interrupt routine executes, taking 13 cycles. During this time, the following actions occur: c. The PCH (PC[15:8]) is cleared to zero. d. The interrupt vector is read from the interrupt controller and its value is placed into PCL (PC[7:0]). This sets the program counter to point to the appropriate address in the interrupt table (for example, 001Ch for the GPIO interrupt). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 65 Interrupt Controller 4. Program execution vectors to the interrupt table. Typically, a LJMP instruction in the interrupt table sends execution to the user's interrupt service routine (ISR) for this interrupt. (See “Instruction Set Summary” on page 40.) 5. The ISR executes. Note that interrupts are disabled because GIE = 0. In the ISR, interrupts can be reenabled if desired, by setting GIE = 1 (take care to avoid stack overflow in this case). 6. The ISR ends with a RETI instruction. This pops the Flag register, PCL, and PCH from the stack, restoring those registers. The restored Flag register re-enables interrupts, because GIE = 1 again. Interrupt Priority. The priorities of the interrupts only come into consideration if more than one interrupt is pending during the same instruction cycle. In this case, the priority encoder (see Figure 5-1) generates an interrupt vector for the highest priority interrupt that is pending. 5.1.1 Posted versus Pending Interrupts An interrupt is posted when its interrupt conditions occur. This results in the flip-flop in Figure 5-1 clocking in a ‘1’. The interrupt will remain posted until the interrupt is taken or until it is cleared by writing to the appropriate INT_CLRx register. 7. Execution resumes at the next instruction, after the one that occurred before the interrupt. However, if there are more pending interrupts, the subsequent interrupts will be processed before the next normal program instruction. A posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate INT_MSKx register). All pending interrupts are processed by the Priority Encoder to determine the highest priority interrupt which will be taken by the M8C if the Global Interrupt Enable bit is set in the CPU_F register. Interrupt Latency. The time between the assertion of an enabled interrupt and the start of its ISR can be calculated using the following equation: Disabling an interrupt by clearing its interrupt mask bit (in the INT_MSKx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. It simply prevents a posted interrupt from becoming pending. Latency = Equation 1 Time for current instruction to finish + Time for M8C to change program counter to interrupt address + Time for LJMP instruction in interrupt table to execute. For example, if the 5-cycle JMP instruction is executing when an interrupt becomes active, the total number of CPU clock cycles before the ISR begins is as follows: (1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine) + (7 cycles for LJMP) = 21 to 25 cycles. Equation 2 In the example above, at 24 MHz, 25 clock cycles take 1.042 s. 66 It is especially important to understand the functionality of clearing posted interrupts, if the configuration of the PSoC device is changed by the application. For example, if a digital PSoC block is configured as a counter and has posted an interrupt but is later reconfigured to a serial communications receiver, the posted interrupt from the counter will remain. Therefore, if the digital PSoC block's INT_MSKx bit is set after configuring the block as a serial communications receiver, a pending interrupt is generated immediately. To prevent the carryover of posted interrupts from one configuration to the next, the INT_CLRx registers should be used to clear posted interrupts prior to enabling the digital PSoC block. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Interrupt Controller 5.2 Application Description The interrupt controller and its associated registers allow the user's code to respond to an interrupt from almost every functional block in the PSoC devices. Interrupts for all the digital blocks and each of the analog columns are available, as well as interrupts for supply voltage, sleep, variable clocks, and a general GPIO (pin) interrupt. clear all pending and posted interrupts, or clear individual posted or pending interrupts. A software mechanism is provided to set individual interrupts. Setting an interrupt by way of software is very useful during code development, when one may not have the complete hardware system necessary to generate a real interrupt. The registers associated with the interrupt controller allow interrupts to be disabled either globally or individually. The registers also provide a mechanism by which a user can The following table lists the interrupts for all CY8C28xxx devices and the priorities that are available in each CY8C28xxx device. CY8C28x23 CY8C28x33 CY8C28x43 CY8C28x45 CY8C28x52 Interrupt Address CY8C28x13 Interrupt Priority CY8C28x03 Table 5-1. Device Interrupts and Priorities Interrupt Name 0 (Highest) 0000h 1 0004h 2 0008h 3 000Ch 4 0010h 5 0014h 6 0018h 7 001Ch 8 0020h 9 0024h 10 0028h 11 002Ch 12 0030h 13 0034h 14 0038h 15 003Ch 16 0040h 17 0044h 18 0048h 19 004Ch 20 0050h Reserved 21 0054h Reserved 22 0058h Reserved 23 005Ch 24 0060h 25 0064h 26 0068h 27 006Ch 28 0070h 29 0074h 30 0078h 31 (Lowest) 007Ch Reset Supply Voltage Monitor Analog Column 0/Decimator0 Analog Column 1/Decimator1 Analog Column 2/Decimator2 Analog Column 3/Decimator3 VC3 GPIO PSoC Block DBC00 PSoC Block DBC01 PSoC Block DCC02 PSoC Block DCC03 PSoC Block DBC10 PSoC Block DBC11 PSoC Block DCC12 PSoC Block DCC13 PSoC Block DBC20 PSoC Block DBC21 PSoC Block DCC22 PSoC Block DCC23 Reserved I2C0 I2C1 SAR ADC RTC Analog Column 4 Analog Column 5 Reserved Sleep Timer CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 67 Interrupt Controller 5.3 Register Definitions The following registers are associated with the Interrupt Controller and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of '0'. For a complete table of Interrupt Controller registers, refer to the “Summary Table of the Core Registers” on page 36. Depending on the CY8C28xxx device you have, only certain bits are accessible to be read or written. See Table 5-1 on page 67 for the interrupt availability by subfamily. 5.3.1 Address INT_CLRx Registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,DAh INT_CLR0 Name VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor RW : 00 0,DBh INT_CLR1 DCC13 DCC12 DBC11 DBC10 DCC03 DCC02 DBC01 DBC00 RW : 00 DCC23 DCC22 DBC21 DBC20 RW : 00 Analog 5 Analog 4 RTC SARADC I2C1 I2C0 RW : 00 0,DCh INT_CLR2 0,DDh INT_CLR3 The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources’ ability to clear posted interrupts. There are four interrupt clear registers (INT_CLR0, INT_CLR1, INT_CLR2, and INT_CLR3) which may be referred to in general as INT_CLRx.The INT_CLRx registers are similar to the INT_MSKx registers in that they hold a bit for each interrupt source. Functionally the INT_CLRx registers are similar to the INT_VC register, although their operation is completely independent. When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore, reading these registers gives the user the ability to determine all posted interrupts. The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7] determines the way an individual bit value written to an INT_CLR0 register is interpreted. When ENSWINT is cleared (the default state), writing 1's to an INT_CLRx register has no effect. However, writing 0's to an INT_CLRx register, when ENSWINT is cleared, will cause the corresponding interrupt to clear. If the ENSWINT bit is set, any 0's written to the INT_CLRx registers are ignored. However, 1's written to an INT_CLRx register, while ENSWINT is set, will cause an interrupt to post for the corresponding interrupt. Note When using the INT_CLRx register to post an interrupt, the hardware interrupt source, such as a digital clock, must not have its interrupt output high. Therefore, it may be difficult to use software interrupts with interrupt sources that do not have enables such as VC3. 5.3.1.1 INT_CLR0 Register Depending on the analog column configuration of your PSoC device (see the table titled “CY8C28xxx Device Characteristics” on page 24), some bits may not be available in the INT_CLR0 register. Bit 7: VC3. This bit allows posted VC3 interrupts to be read, cleared, or set. Bit 6: Sleep. This bit allows posted sleep interrupts to be read, cleared, or set. Bit 5: GPIO. This bit allows posted GPIO interrupts to be read, cleared, or set. Bit 4: Analog 3. This bit allows posted analog column 3 interrupts to be read, cleared, or set. Bit 3: Analog 2. This bit allows posted analog column 2 interrupts to be read, cleared, or set. Bit 2: Analog 1. This bit allows posted analog column 1 interrupts to be read, cleared, or set. Bit 1: Analog 0. This bit allows posted analog column 0 interrupts to be read, cleared, or set. Bit 0: V Monitor. This bit allows posted V monitor interrupts to be read, cleared, or set. For additional information, refer to the INT_CLR0 register on page 199. Software interrupts can aid in debugging interrupt service routines by eliminating the need to create system level interactions that are sometimes necessary to create a hardwareonly interrupt. 68 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Interrupt Controller 5.3.1.2 INT_CLR1 Register Depending on the digital row configuration of your PSoC device (see the table titled “CY8C28xxx Device Characteristics” on page 24), some bits may not be available in the INT_CLR1 register. Bit 7: DCC13. This bit allows posted DCC13 interrupts to be read, cleared, or set for row 1 block 3. Bit 6: DCC12. This bit allows posted DCC12 interrupts to be read, cleared, or set for row 1 block 2. Bit 5: DBC11. This bit allows posted DBC11 interrupts to be read, cleared, or set for row 1 block 1. 5.3.1.3 INT_CLR2 Register Bit 3: DCC23. This bit allows posted DCC23 interrupts to be read, cleared, or set for row 2 block 3. Bit 2: DCC22. This bit allows posted DCC22 interrupts to be read, cleared, or set for row 2 block 2. Bit 1: DBC21. This bit allows posted DBC21 interrupts to be read, cleared, or set for row 2 block 1. Bit 0: DBC20. This bit allows posted DBC20 interrupts to be read, cleared, or set for row 2 block 0. For additional information, refer to the INT_CLR2 register on page 203. Bit 4: DBC10. This bit allows posted DBC10 interrupts to be read, cleared, or set for row 1 block 0. 5.3.1.4 Bit 3: DCC03. This bit allows posted DCC03 interrupts to be read, cleared, or set for row 0 block 3. Bit 5: Analog 5. This bit allows posted analog column 5 interrupts to be read, cleared, or set. Bit 2: DCC02. This bit allows posted DCC02 interrupts to be read, cleared, or set for row 0 block 2. Bit 4: Analog 4. This bit allows posted analog column 4 interrupts to be read, cleared, or set. Bit 1: DBC01. This bit allows posted DBC01 interrupts to be read, cleared, or set for row 0 block 1. Bit 3: RTC. This bit allows posted RTC interrupts to be read, cleared, or set. Bit 0: DBC00. This bit allows posted DBC00 interrupts to be read, cleared, or set for row 0 block 0. Bit 2: SARADC. This bit allows posted SARADC interrupts to be read, cleared, or set. For additional information, refer to the INT_CLR1 register on page 201. INT_CLR3 Register Bit 1: I2C1. This bit allows posted I2C1 interrupts to be read, cleared, or set. Bit 0: I2C0. This bit allows posted I2C0 interrupts to be read, cleared, or set. For additional information, refer to the INT_CLR3 register on page 204. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 69 Interrupt Controller 5.3.2 Address INT_MSKx Registers Name Bit 7 Bit 6 ENSWINT Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Analog 5 Analog 4 RTC SARADC I2C1 I2C0 RW : 00 DCC23 DCC22 DBC21 DBC20 RW : 00 Analog 3 Analog 2 Analog 1 Analog 0 V Monitor RW : 00 DBC10 DCC03 DCC02 DBC01 DBC00 RW : 00 0,DEh INT_MSK3 0,DFh INT_MSK2 0,E0h INT_MSK0 VC3 Sleep GPIO 0,E1h INT_MSK1 DCC13 DCC12 DBC11 The Interrupt Mask Registers (INT_MSKx) are used to enable the individual interrupt sources’ ability to create pending interrupts. There are four interrupt mask registers (INT_MSK0, INT_MSK1, INT_MSK2, and INT_MSK3) which may be referred to in general as INT_MSKx. If cleared, each bit in an INT_MSKx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). However, an interrupt can still post even if its mask bit is zero. All INT_MSKx bits are independent of all other INT_MSKx bits. If an INT_MSKx bit is set, the interrupt source associated with that mask bit may generate an interrupt that will become a pending interrupt. For example, if INT_MSK0[5] is set and at least one GPIO pin is configured to generate an interrupt, the interrupt controller will allow a GPIO interrupt request to post and become a pending interrupt for the M8C to respond to. If a higher priority interrupt is generated before the M8C responds to the GPIO interrupt, the higher priority interrupt will be responded to and not the GPIO interrupt. Each interrupt source may require configuration at a block level. Refer to the other chapters in this manual for information on how to configure an individual interrupt source. 5.3.2.1 Bit 0: I2C0. This bit allows posted I2C0 interrupts to be read, masked, or set. For additional information, refer to the INT_MSK3 register on page 206. 5.3.2.2 Depending on the digital row characteristics of your PSoC device (see the table titled “CY8C28xxx Device Characteristics” on page 24), you may not be able to use this register. The bits in this register are only for PSoC devices with 4 and 3 digital rows. Bit 3: DCC23. This bit allows posted DCC23 interrupts to be read, masked, or set for row 2 block 3. Bit 2: DCC22. This bit allows posted DCC22 interrupts to be read, masked, or set for row 2 block 2. Bit 1: DBC21. This bit allows posted DBC21 interrupts to be read, masked, or set for row 2 block 1. Bit 0: DBC20. This bit allows posted DBC20 interrupts to be read, masked, or set for row 2 block 0. For additional information, refer to the INT_MSK2 register on page 207. INT_MSK3 Register 5.3.2.3 Bit 7: ENSWINT. This bit is a special non-mask bit that controls the behavior of the INT_CLRx registers. See the INT_CLRx register in this section for more information. Bit 5: Analog 5. This bit allows posted analog column 5 interrupts to be read, masked, or set. Bit 4: Analog 4. This bit allows posted analog column 4 interrupts to be read, masked, or set. Bit 3: RTC. This bit allows posted RTC interrupts to be read, masked, or set. Bit 2: SARADC. This bit allows posted SARADC interrupts to be read, masked, or set. Bit 1: I2C1. This bit allows posted I2C1 interrupts to be read, masked, or set. 70 INT_MSK2 Register INT_MSK0 Register Depending on the analog column characteristics of your PSoC device (see the table titled “CY8C28xxx Device Characteristics” on page 24), some bits may not be available in the INT_MSK0 register. Bit 7: VC3. This bit allows posted VC3 interrupts to be read, masked, or set. Bit 6: Sleep. This bit allows posted sleep interrupts to be read, masked, or set. Bit 5: GPIO. This bit allows posted GPIO interrupts to be read, masked, or set. Bit 4: Analog 3. This bit allows posted analog column 3 interrupts to be read, masked, or set. Bit 3: Analog 2. This bit allows posted analog column 2 interrupts to be read, masked, or set. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Interrupt Controller Bit 2: Analog 1. This bit allows posted analog column 1 interrupts to be read, masked, or set. Bit 6: DCC12. This bit allows posted DCC12 interrupts to be read, masked, or set for row 1 block 2. Bit 1: Analog 0. This bit allows posted analog column 0 interrupts to be read, masked, or set. Bit 5: DBC11. This bit allows posted DBC11 interrupts to be read, masked, or set for row 1 block 1. Bit 0: V Monitor. This bit allows posted V monitor interrupts to be read, masked, or set. Bit 4: DBC10. This bit allows posted DBC10 interrupts to be read, masked, or set for row 1 block 0. For additional information, refer to the INT_MSK0 register on page 208. 5.3.2.4 INT_MSK1 Register Depending on the digital row characteristics of your PSoC device (see the table titled “CY8C28xxx Device Characteristics” on page 24), some bits may not be available in the INT_MSK1 register. The bits in this register are available for all PSoC devices, with the exception of one digital row devices. Bit 7: DCC13. This bit allows posted DCC13 interrupts to be read, masked, or set for row 1 block 3. 5.3.3 Address 0,E2h Bit 3: DCC03. This bit allows posted DCC03 interrupts to be read, masked, or set for row 0 block 3. Bit 2: DCC02. This bit allows posted DCC02 interrupts to be read, masked, or set for row 0 block 2. Bit 1: DBC01. This bit allows posted DBC01 interrupts to be read, masked, or set for row 0 block 1. Bit 0: DBC00. This bit allows posted DBC00 interrupts to be read, masked, or set for row 0 block 0. For additional information, refer to the INT_MSK1 register on page 209. INT_VC Register Name Bit 7 Bit 6 Bit 5 INT_VC Bit 4 Bit 3 Bit 2 Pending Interrupt[7:0] Bit 1 Bit 0 Access RC : 00 LEGEND C Clearable register or bits. The Interrupt Vector Clear Register (INT_VC) returns the next pending interrupt and clears all pending interrupts when written. Bits 7 to 0: Pending Interrupt[7:0]. When the register is read, the least significant byte (LSB), of the highest priority pending interrupt, is returned. For example, if the GPIO and I2C interrupts were pending and the INT_VC register was read, the value 1Ch will be read. However, if no interrupt were pending, the value 00h will be returned. This is the reset vector in the interrupt table; however, reading 00h from the INT_VC register should not be considered an indication that a system reset is pending. Rather, reading 00h from the INT_VC register simply indicates that there are no pending interrupts. The highest priority interrupt, indicated by the value returned by a read of the INT_VC register, is removed from the list of pending interrupts when the M8C services an interrupt. Reading the INT_VC register has limited usefulness. If interrupts are enabled, a read to the INT_VC register cannot determine that an interrupt was pending before the interrupt was actually taken. However, while in an interrupt, a user may wish to read the INT_VC register to see what the next interrupt will be. When the INT_VC register is written, with any value, all pending and posted interrupts are cleared by asserting the clear line for each interrupt. For additional information, refer to the INT_VC register on page 210. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 71 Interrupt Controller 5.3.4 Address x,F7h CPU_F Register Name CPU_F Bit 7 Bit 6 Bit 5 PgMode[1:0] Bit 4 XIO Bit 3 Bit 2 Bit 1 Bit 0 Access Carry Zero GIE RL : 02 LEGEND L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register. x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. The M8C Flag Register (CPU_F) provides read access to the M8C flags. Note that only the GIE (Global Interrupt Enable) bit is related to the interrupt controller. Bits 7 to 1. The CPU_F register holds bits that are used by different resources. For information on the other bits in this register, refer to the CPU Core (M8C) chapter on page 39. Bit 0: GIE. The state of the Global Interrupt Enable bit determines whether interrupts (by way of the IRQ) will be recognized by the M8C. This bit is set or cleared by the user, 72 using the flag-logic instructions (for example, OR F, 1). GIE is also cleared automatically by the M8C upon entering the interrupt service routine (ISR), after the flag byte has been stored on the stack, preventing nested interrupts. Note that the bit can be set in an ISR if desired. For GIE = 1, the M8C samples the IRQ input for each instruction. For GIE = 0, the M8C ignores the IRQ. For additional information, refer to the CPU_F register on page 214. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 6. General Purpose I/O (GPIO) This chapter discusses the General Purpose I/O (GPIO) and its associated registers, which is the circuit responsible for interfacing to the I/O pins of a PSoC® device. The GPIO blocks provide the interface between the M8C core and the outside world. They offer a large number of configurations to support several types of input/output (I/O) operations for both digital and analog systems. For a complete table of the GPIO registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 6.1 Architectural Description The GPIO contains input buffers, output drivers, register bit storage, and configuration logic for connecting the PSoC device to the outside world. I/O Ports are arranged with (up to) 8 bits per port. Each full port contains eight identical GPIO blocks, with connections to identify a unique address and register bit number for each block. Each GPIO block can be used for the following types of I/O: ■ Digital I/O (digital input and output controlled by software) ■ Global I/O (digital PSoC block input and output) ■ Analog I/O (analog PSoC block input and output) Each I/O pin also has several drive modes, as well as interrupt capabilities. While all GPIO pins are identical and provide digital I/O, some pins may not connect internally to analog functions. The main block diagram for the GPIO block is shown in Figure 6-1. Note that some pins do not have all of the functionality shown, depending on internal connections. The CY8C28x13, CY8C28x33, CY8C28x43, CY8C28x45, and CY8C28x52 PSoC devices contain an enhanced capability to connect any GPIO to an internal analog bus. This is described in detail in the I/O Analog Multiplexer chapter on page 525. 6.1.1 Digital I/O One of the basic operations of the GPIO ports is to allow the M8C to send information out of the PSoC device and get information into the M8C from outside the PSoC device. This is accomplished by way of the port data register (PRTxDR). Writes from the M8C to the PRTxDR register store the data state, one bit per GPIO. In the standard nonbypass mode, the pin drivers drive the pin in response to this data bit, with a drive strength determined by the Drive mode setting (see Figure 6-1). The actual voltage on the pin depends on the Drive mode and the external load. The M8C can read the value of a port by reading the PRTxDR register address. When the M8C reads the PRTxDR register address, the current value of the pin voltage is translated into a logic value and returned to the M8C. Note that the pin voltage can represent a different logic value than the last value written to the PRTxDR register. This is an important distinction to remember in situations such as the use of a read modify write to a PRTxDR register. Examples of read modify write instructions include AND, OR, and XOR. The following is an example of how a read modify write, to a PRTxDR register, can have an unexpected and even indeterminate result in certain systems. Consider a scenario where all bits of Port 1 on the PSoC device are in the strong 1 resistive 0 drive mode; so that in some cases, the system the PSoC is in may pull up one of the bits. mov or reg[PRT1DR], 0x00 reg[PRT1DR], 0x80 In the first line of code above, writing a 0x00 to the port will not affect any bits that happen to be driven by the system the PSoC is in. However, in the second line of code, it can not guarantee that only bit 7 will be the one set to a strong 1. Because the OR instruction will first read the port, any bits that are in the pull up state will be read as a ‘1’. These ones will then be written back to the port. When this happens, the pin will go in to a strong 1 state; therefore, if the pull up condition ends in the system, the PSoC will keep the pin value at a logic 1. 6.1.2 Global I/O The GPIO ports are also used to interconnect signals to and from the digital PSoC blocks, as global inputs or outputs. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 73 General Purpose I/O (GPIO) 6.1.3 The global I/O feature of each GPIO (port pin) is off by default. To access the feature, two parameters must be changed. To configure a GPIO as a global input, the port global select bit must be set for the desired GPIO using the PRTxGS register. This sets BYP = 1 in Figure 6-1 and disconnects the output of the PRTxDR register from the pin. Also, the Drive mode for the GPIO must be set to the digital High-Z state. (Refer to the “PRTxDMx Registers” on page 77 for more information.) To configure a GPIO as a global output, the port global select bit must again be set. But in this case, the drive state must be set to any of the non-High-Z states. Analog Input Analog signals can pass into the PSoC device core from PSoC device pins through the block’s AOUT pin. This provides a resistive path (~300 ohms) directly through the GPIO block. For analog modes, the GPIO block is typically configured into a High impedance Analog Drive mode (High-Z). The mode turns off the Schmitt trigger on the input path, which may reduce power consumption and decrease internal switching noise when using a particular I/O as an analog input. Refer to the Electrical Specifications chapter in the individual PSoC device data sheet. Figure 6-1. GPIO Block Diagram Drive Modes DM2 DM1 DM0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0. Diagram Number Data = 0 Drive Mode Resistive Pull Down Strong Drive High Impedance Resistive Pull Up Open Drain, Drives High Slow Strong Drive High Impedance Analog Open Drain, Drives Low 1. 2. 0 1 2 3 4 5 6 7 Resistive Strong Hi-Z Strong Hi-Z Strong (Slow) Hi-Z Strong (Slow) 3. Data = 1 Strong Strong Hi-Z Resistive Strong (Slow) Strong (Slow) Hi-Z Hi-Z BYP DM1 DM0 Input Path Global Input Bus Read PRTxDR Data Bus I2C Input 4. 5. 6. 7. INBUF DM[2:0]=110b RESET D CELLRD R EN Q QinLatch (To Readmux, Interrupt Logic) AIN Vdd Output Path Vdd BYP Write PRTxDR Vdd 2:1 Global Output Bus 2:1 DATA 5.6K Drive Logic I2C Output I2C Enable DM2 DM1 DM0 Slew Control PIN 5.6K AOUT 74 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F General Purpose I/O (GPIO) 6.1.4 GPIO Block Interrupts Each GPIO block can be individually configured for interrupt capability. Blocks are configured by pin interrupt enables and also by selection of the interrupt state. Blocks can be set to interrupt when the pin is high, low, or when it changes from the last time it was read. The block provides an opendrain interrupt output (INTO) that is connected to other GPIO blocks in a wire-OR fashion. All pin interrupts that are wire-ORed together are tied to the same system GPIO interrupt. Therefore, if interrupts are enabled on multiple pins, the user’s interrupt service routine must provide a mechanism to determine which pin was the source of the interrupt. Using a GPIO interrupt requires the following steps: If no GPIO interrupts are asserting, a GPIO interrupt will occur whenever a GPIO pin interrupt enable is set and the GPIO pin transitions, if not already transitioned, appropriately high or low, to match the interrupt mode configuration. When this happens, the INTO line will pull low to assert the GPIO interrupt. This assumes the other system-level enables are on, such as setting the global GPIO interrupt enable and the Global Interrupt Enable. Setting the pin interrupt enable may immediately assert INTO, if the Interrupt mode conditions are already being met at the pin. After INTO pulls low, it will continue to hold INTO low until one of these conditions changes. ■ The pin interrupt enable is cleared ■ The voltage at pin transitions to the opposite state ■ In interrupt-on-change mode, the GPIO data register is read, thus setting the local interrupt level to the opposite state ■ The Interrupt mode is changed so that the current pin state does not create an interrupt 1. Set the Interrupt mode in the GPIO pin block. 2. Enable the bit interrupt in the GPIO block. 3. Set the mask bit for the (global) GPIO interrupt. 4. Assert the overall Global Interrupt Enable. The first two steps, bit interrupt enable and Interrupt mode, are set at the GPIO block level (that is, at each port pin), by way of the block’s configuration registers. The last two steps are common to all interrupts and are described in the Interrupt Controller chapter on page 65. At the GPIO block level, asserting the INTO line depends only on the bit interrupt enable and the state of the pin relative to the chosen Interrupt mode. At the PSoC device level, due to their wire-OR nature, the GPIO interrupts are neither true edge-sensitive interrupts nor true level-sensitive interrupts. They are considered edge-sensitive for asserting, but level-sensitive for release of the wire-OR interrupt line. When one of these conditions is met, the INTO releases. At this point, another GPIO pin (or this pin again) can assert its INTO pin, pulling the common line low to assert a new interrupt. Note the following behavior from this level-release feature. If one pin is asserting INTO and then a second pin asserts its INTO, when the first pin releases its INTO, the second pin is already driving INTO and thus no change is seen (that is, no new interrupt is asserted on the GPIO interrupt). Care must be taken, using polling or the states of the GPIO pin and Global Interrupt Enables, to catch all interrupts among a set of wire-OR GPIO blocks. Figure 6-2 shows the interrupt logic portion of the block. Figure 6-2. GPIO Interrupt Logic Diagram PRTxIE:n PRTxIC1:n PRTxIC0:n Low INTO PRTxIC1:n PRTxIC0:n QinLatch CELLRD Change S Vss D Q EN R Interrupt Mode PRTxIC1:n PRTxIC0:n PRTxIC1:n PRTxIC0:n INBUF High 0 0 1 1 0 1 0 1 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Output Disabled Low High Change from last read 75 General Purpose I/O (GPIO) 6.2 Register Definitions The following registers are associated with the General Purpose I/O (GPIO) and are listed in address order. The register descriptions in this section have an associated register table showing the bit structure for that register. For a complete table of GPIO registers, refer to the “Summary Table of the Core Registers” on page 36. For a selected GPIO block, the individual registers are addressed in the Summary Table of the Core Registers. In the register names, the ‘x’ is the port number, configured at the PSoC device level (x = 0 to 7 typically). All register values are readable, except for the PRTxDR register; reads of this register return the pin state instead of the register bit state. 6.2.1 Address 0,xxh PRTxDR Registers Name Bit 7 Bit 6 Bit 5 Bit 4 PRTxDR Bit 3 Bit 2 Bit 1 Bit 0 Data[7:0] Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Core Register Summary” on page 36. Reading the PRTxDR register returns the actual pin state, as seen by the input buffer. This may not be the same as the expected output state, if the load pulls the pin more strongly than the pin’s configured output drive. See “Digital I/O” on page 73 for a detailed discussion of digital I/O. The Port Data Register (PRTxDR) allows for write or read access of the current logical equivalent of the voltage on the pin. Bits 7 to 0: Data[7:0]. Writing the PRTxDR register bits set the output drive state for the pin to high (for DR = 1) or low (DR = 0), unless a bypass mode is selected (either I2C Enable = 1 or the global select register written high). 6.2.2 Address 0,xxh For additional information, refer to the PRTxDR register on page 127. PRTxIE Registers Name Bit 7 Bit 6 Bit 5 PRTxIE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt Enables[7:0] Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Core Register Summary” on page 36. Bits 7 to 0: Interrupt Enables[7:0]. A ‘1’ enables the INTO output at the block and a ‘0’ disables INTO so it is only High-Z. The Port Interrupt Enable Register (PRTxIE) is used to enable/disable the interrupt enable internal to the GPIO block. 6.2.3 Address 0,xxh For additional information, refer to the PRTxIE register on page 128. PRTxGS Registers Name Bit 7 Bit 6 Bit 5 PRTxGS Bit 4 Bit 3 Global Select[7:0] Bit 2 Bit 1 Bit 0 Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Core Register Summary” on page 36. The Port Global Select Register (PRTxGS) is used to select the block for connection to global inputs or outputs. global output (the Global Output Bus drives to PIN), bypassing the data register value (assuming I2C Enable = 0). Bits 7 to 0: Global Select[7:0]. Writing this register high enables the global bypass (BYP = 1 in Figure 6-1). If the Drive mode is set to digital High-Z (DM[2:0] = 010b), then the pin is selected for global input (PIN drives to the Global Input Bus). In non-High-Z modes, the block is selected for If the PRTxGS register is written to zero, the global in/out function is disabled for the pin and the pin reflects the value of PRT_DR. 76 For additional information, refer to the PRTxGS register on page 129. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F General Purpose I/O (GPIO) 6.2.4 Address PRTxDMx Registers Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,xxh PRTxDM2 Drive Mode 2[7:0] RW : FFh 1,xxh PRTxDM0 Drive Mode 0[7:0] RW : 00 1,xxh PRTxDM1 Drive Mode 1[7:0] RW : FFh LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Core Register Summary” on page 36. The Port Drive Mode Bit Registers (PRTxDMx) are used to specify the Drive mode for GPIO pins. Table 6-1. Pin Drive Modes Drive Modes DM2 DM1 DM0 Bits 7 to 0: Drive Mode x[7:0]. In the PRTxDMx registers there are eight possible drive modes for each port pin. Three mode bits are required to select one of these modes, and these three bits are spread into three different registers (PRTxDM0, PRTxDM1, and PRTxDM2). The bit position of the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the three drive mode register bits that control the Drive mode for that pin (for example, bit[2] in PRT0DM0, bit[2] in PRT0DM1, and bit[2] in PRT0DM2). The three bits from the three registers are treated as a group. These are referred to as DM2, DM1, and DM0, or together as DM[2:0]. Drive modes are shown in Table 6-1. 0 0 0 Resistive pull down Strong high, resistive low 0 0 1 Strong drive Strong high, strong low 0 1 0 High impedance High-Z high and low, digital input enabled 0 1 1 Resistive pull up Resistive high, strong low 1 0 0 Open drain high Slow strong high, High-Z low 1 0 1 Slow strong drive Slow strong high, slow strong low 1 1 0 High-Z high and low, digital input High impedance, disabled (for zero power) (reset analog (reset state) state) 1 1 1 Open drain low Slow strong low, High-Z high The resistive drive modes place a resistance in series with the output, for low outputs (mode 000b) or high outputs (mode 011b). Strong Drive mode 001b gives the fastest edges at high DC drive strength. Mode 101b gives the same drive strength but with slower edges. The open-drain modes (100b and 111b) also use the slower edge rate drive. These modes enable open-drain functions such as I2C mode 111b (although the slow edge rate is not slow enough to meet the I2C fast mode specification). For global input modes, the Drive mode must be set to 010b. Address Description The GPIO provides a default Drive mode of high impedance, analog (High-Z). This is achieved by forcing the reset state of all PRTxDM1 and PRTxDM2 registers to FFh. For analog I/O, the Drive mode should be set to one of the High-Z modes, either 010b or 110b. The 110b mode has the advantage that the block’s digital input buffer is disabled, so no crowbar current flows even when the analog input is not close to either power rail. When digital inputs are needed on the same pin as analog inputs, the 010b Drive mode should be used. If the 110b Drive mode is used, the pin will always be read as a zero by the CPU and the pin will not be able to generate a useful interrupt. (It is not strictly required that a High-Z mode be selected for analog operation.) 6.2.5 Pin State For additional information, refer to the PRTxDM2 register on page 130, the PRTxDM0 register on page 218, and the PRTxDM1 register on page 219. PRTxICx Registers Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,xxh PRTxIC0 Interrupt Control 0[7:0] RW : 00 1,xxh PRTxIC1 Interrupt Control 1[7:0] RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Core Register Summary” on page 36. The Port Interrupt Control Registers (PRTxIC1 and PRTxIC0) are used to specify the Interrupt mode for GPIO pins. Bits 7 to 0: Interrupt Control x[7:0]. In the PRTxICx registers, the Interrupt mode for the pin is determined by bits in these two registers. These are referred to as IC1 and IC0, or together as IC[1:0]. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 77 General Purpose I/O (GPIO) There are four possible interrupt modes for each port pin. Two mode bits are required to select one of these modes and these two bits are spread into two different registers (PRTxIC0 and PRTxIC1). The bit position of the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the interrupt control register bits that control the Interrupt mode for that pin (for example, bit[2] in PRT0IC0 and bit[2] in PRT0IC1). The two bits from the two registers are treated as a group. Figure 6-3. GPIO Interrupt Mode 11b Last Value Read From Pin was ‘0’ Pin State Waveform (a) GPIO pin interrupt enable set The Interrupt mode must be set to one of the non-zero modes listed in Table 6-2, to get an interrupt from the pin. The GPIO Interrupt mode “disabled” (00b) disables interrupts from the pin, even if the GPIO’s bit interrupt enable is on (from the PRTxIE register). Interrupt mode 01b means that the block will assert the interrupt line (INTO) when the pin voltage is low, providing the block’s bit interrupt enable line is set (high). Interrupt mode 10b means that the block will assert the interrupt line (INTO) when the pin voltage is high, providing the block’s bit interrupt enable line is set (high). Interrupt mode 11b means that the block will assert the interrupt line (INTO) when the pin voltage is the opposite of the last state read from the pin, providing the block’s bit interrupt enable line is set high. This mode switches between low mode and high mode, depending on the last value that was read from the port during reads of the data register (PRTxDR). If the last value read from the GPIO was ‘0’, the GPIO will subsequently be in Interrupt High mode. If the last value read from the GPIO was ‘1’, the GPIO will then be in Interrupt Low mode. Pin State Waveform (b) Interrupt occurs GPIO pin interrupt enable set Interrupt occurs Last Value Read From Pin was ‘1’ Pin State Waveform (c) GPIO pin interrupt enable set Pin State Waveform (d) Interrupt occurs GPIO pin interrupt enable set Interrupt occurs Figure 6-3 assumes that the GIE is set, GPIO interrupt mask is set, and that the GPIO Interrupt mode has been set to 11b. The Change Interrupt mode is different from the other modes, in that it relies on the value of the GPIO’s read latch to determine if the pin state has changed. Therefore, the port that contains the GPIO in question must be read during every interrupt service routine. If the port is not read, the Interrupt mode will act as if it is in high mode when the latch value is ‘0’ and low mode when the latch value is ‘1’. For additional information, refer to the PRTxIC0 register on page 220 and the PRTxIC1 register on page 221. Table 6-2. GPIO Interrupt Modes Interrupt Modes 78 Description IC1 IC0 0 0 0 1 Assert INTO when PIN = low 1 0 Assert INTO when PIN = high 1 1 Assert INTO when PIN = change from last read Bit interrupt disabled, INTO deasserted CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 7. Analog Output Drivers This chapter presents the Analog Output Drivers and their associated register. The analog output drivers provide a means for driving analog signals off the PSoC® device. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. For information on the analog system, refer to the “Analog System” on page 383. 7.1 Architectural Description Depending on which PSoC device you have (see Table 7-1), the PSoC device has up to four analog drivers used to output analog values on port pins. Note that there are no analog output drivers for the CY8C28x13 and CY8C28x03 devices. CY8C28x23 CY8C28x33 CY8C28x43 CY8C28x45 CY8C28x52 P0[5] CY8C28x13 Port Pin CY8C28x03 Table 7-1. PSoC Analog Output Drivers P0[4] P0[3] P0[2] Each of these drivers is a resource available to all the analog blocks in a particular analog column. Therefore, the number of analog output drivers will match the number of analog columns in a device. The user must select no more than one analog block per column to drive a signal on its analog output bus (ABUS), to serve as the input to the analog driver for that column. The output from the analog output driver for each column can be enabled and disabled using the Analog Output Driver register ABF_CR0. If the analog output driver is enabled, then it must have an analog block driving the ABUS for that column. Otherwise, the analog output driver can enter a high current consumption mode. Figure 7-1 illustrates the drivers and their relationship within the analog array. For a detailed drawing of the analog output drivers in relation to the analog system, refer to the Analog Input Configuration chapter on page 417. Figure 7-1. Analog Output Drivers P0[5] P0[4] Analog Output Drivers P0[3] ACC00 ACC01 ASC10 ASD20 Analog Array P0[2] ACC02 ACC03 ASD11 ASC12 ASD13 ASC21 ASD22 ASC23 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 79 Analog Output Drivers 7.2 Register Definitions The following register is associated with the Analog Output Drivers. The register description has an associated register table showing the bit structure of the register. The bits that are grayed out in the following table are reserved bits and are not detailed in the register description that follows. Reserved bits should always be written with a value of ‘0’. Depending on the number of analog columns your PSoC device has (see the Cols. column in the register table), some bits may be reserved (refer to the table titled “CY8C28xxx Device Characteristics” on page 24). 7.2.1 Add. 1,62h ABF_CR0 Register Name ABF_CR0 Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 ACol1Mux ACol2Mux ABUF1EN ABUF2EN ABUF0EN ABUF3EN Bypass PWR 2 ACol1Mux Bypass PWR ABUF1EN The Analog Output Buffer Control Register 0 (ABF_CR0) controls analog input muxes from Port 0 and the output buffer amplifiers that drive column outputs to device pins. For more information on bits 7 and 6, see the Analog Input Configuration chapter on page 417. Bit 7: ACol1MUX. A mux selects the output of column 0 input mux or column 1 input mux. When set, this bit sets the column 1 input to column 0 input mux output. Bit 6: ACol2MUX. A mux selects the output of column 2 input mux or column 3 input mux. When set, this bit sets the column 2 input to column 3 input mux output. ABUF0EN Access RW : 00 Bits 5 to 2: ABUFxEN. These bits enable or disable the column output amplifiers. Bit 1: Bypass. Bypass mode connects the analog output driver input directly to the output. When this bit is set, all analog output drivers will be in bypass mode. This is a high impedance connection used primarily for measurement and calibration of internal references. Use of this feature is not recommended for customer designs. Bit 0: PWR. This bit is used to set the power level of the analog output drivers. When this bit is set, all of the analog output drivers will be in a High Power mode. For additional information, refer to the ABF_CR0 register on page 238. 80 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 8. Internal Main Oscillator (IMO) This chapter presents the Internal Main Oscillator (IMO) and its associated registers. The IMO produces clock signals of 24 MHz and 48 MHz. For a complete table of the IMO registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC® registers in address order, refer to the Register Details chapter on page 125. 8.1 Architectural Description The Internal Main Oscillator (IMO) outputs two clocks: a SYSCLK, which can be the internal 24 MHz clock or an external clock, and a SYSCLKX2 that is always twice the SYSCLK frequency. In the absence of a high-precision input source from the 32.768 kHz crystal oscillator, the accuracy of the internal 24/48 MHz clocks will be ±2.5% over temperature variation and two voltage ranges (3.3 V ± 0.3 V and 5.0 V ± 0.25 V). No external components are required to achieve this level of accuracy. There is an option to phase lock this oscillator to the External Crystal Oscillator (ECO). The choice of crystal and its inherent accuracy will determine the overall accuracy of the oscillator. The ECO must be stable prior to locking the frequency of the IMO to this reference source. The frequency doubler circuit, which produces SYSCLKX2, can be disabled to save power. On CY8C28xxx PSoC devices, lower frequency SYSCLK settings are available by setting the slow IMO (SLIMO) bit in the CPU_SCR1 register. With this bit set and the corresponding factory trim value applied to the IMO_TR register, SYSCLK can be lowered to 6 MHz. This offers lower device power consumption for systems that can operate with the reduced system clock. Slow IMO mode is discussed further in the “Application Description” on page 81. 8.2 Application Description ter, in conjunction with the Trim values in the IMO_TR register. How to do this is described in the sections that follow. 8.2.1 Trimming the IMO An 8-bit register (IMO_TR) is used to trim the IMO. Bit 0 is the LSB and bit 7 is the MSB. The trim step size is approximately 80 kHz. A factory trim setting is loaded into the IMO_TR register at boot time for 5 V ± 0.25 V operation,. For operation in the voltage ranges of 3.3 V ± 0.3 V, user code must modify the contents of this register with values stored in Flash bank 0 as shown in Table 3-11 on page 53. This is done with a Table Read command to the Supervisory ROM. 8.2.2 Engaging Slow IMO Forcing CPU_SCR1 register bit 4 high engages the Slow IMO feature. The IMO will immediately drop to a lower frequency. Factory trim settings are stored in Flash bank 0 as shown in Table 3-11 on page 53 for the following voltage/frequency combinations. Voltage Normal IMO Frequency Slow IMO Frequency 5.0 V ± 0.25 V 24 MHz 6 MHz 3.3 V ± 0.3 V 24 MHz 6 MHz A Table Read command to the Supervisory ROM is performed to set the IMO to the different frequencies. To save power, the IMO frequency can be reduced from 24 MHz to 6 MHz using the SLIMO bit in the CPU_SCR1 regis- CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 81 Internal Main Oscillator (IMO) 8.3 Register Definitions The following registers are associated with the Internal Main Oscillator (IMO). The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. For a complete table showing all oscillator registers, refer to the “Summary Table of the Core Registers” on page 36. 8.3.1 Address x,FEh CPU_SCR1 Register Name Bit 7 CPU_SCR1 IRESS Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SLIMO ECO EXW ECO EX Bit 1 Bit 0 Access IRAMDIS # : 00 LEGEND x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. # Access is bit specific. Refer to the Register Details chapter on page 125 for additional information. Bit 3: ECO EXW. The ECO Exists Written bit is used as a status bit to indicate that the ECO EX bit has been previously written to. It is read only. When this bit is a ‘1’, this indicates that the CPU_SCR1 register has been written to and is now locked. When this bit is a ‘0’, the register has not been written to since the last reset event. The System Status and Control Register 1 (CPU_SCR1) is used to convey the status and control of events related to internal resets and watchdog reset. Bit 7: IRESS. The Internal Reset Status bit is a read only bit that may be used to determine if the booting process occurred more than once. Bit 2: ECO EX. The ECO Exists bit serves as a flag to the hardware, to indicate that an external crystal oscillator exists in the system. Just after boot, it may be written only once to a value of ‘1’ (crystal exists) or ‘0’ (crystal does not exist). If the bit is ‘0’, a switch-over to the ECO is locked out by hardware. If the bit is ‘1’, hardware allows the firmware to freely switch between the ECO and ILO. It should be written as early as possible after a Power On Reset (POR) or External Reset (XRES) event, where it is assumed that program execution integrity is high. When this bit is set, it indicates that the SROM SWBootReset code was executed more than once. If this bit is not set, the SWBootReset was executed only once. In either case, the SWBootReset code will not allow execution from code stored in Flash until the M8C Core is in a safe operating mode with respect to supply voltage and Flash operation. There is no need for concern when this bit is set. It is provided for systems which may be sensitive to boot time, so that they can determine if the normal one-pass boot time was exceeded. For more information on the SWBootReest code see the Supervisory ROM (SROM) chapter on page 49. Bit 0: IRAMDIS. The Initialize RAM Disable bit is a control bit that is readable and writeable. The default value for this bit is ‘0’, which indicates that the maximum amount of SRAM should be initialized on watchdog reset to a value of 00h. When the bit is ‘1’, the minimum amount of SRAM is initialized after a watchdog reset. For more information on this bit, see the “SROM Function Descriptions” on page 50. Bit 4: SLIMO. When set, the Slow IMO bit allows the active power dissipation of the PSoC device to be reduced by slowing down the IMO from 24 MHz to 6 MHz. The IMO trim value must also be changed when SLIMO is set (see “Engaging Slow IMO” on page 81). When not in external clocking mode, the IMO is the source for SYSCLK; therefore, when the speed of the IMO changes, so will SYSCLK. 8.3.2 Address 1,E2h OSC_CR2 Register Name OSC_CR2 Bit 7 PLLGAIN Bit 6 Bit 5 Bit 4 Bit 3 SLP_EXTE ND The Oscillator Control Register 2 (OSC_CR2) is used to configure various features of internal clock sources and clock nets. 82 For additional information, refer to the CPU_SCR1 register on page 216. WDR32_SE Bit 2 EXTCLKEN Bit 1 Bit 0 Access RSVD SYSCLKX2 DIS RW : 00 Bit 7: PLLGAIN. This is the only bit in the OSC_CR2 register that directly influences the PLL. When set, this bit keeps the PLL in Low Gain mode. If this bit is held low, the lock time is less than 10 ms. If this bit is held high, the lock time is CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Internal Main Oscillator (IMO) on the order of 50 ms. After lock is achieved, it is recommended that this bit be forced high to decrease the jitter on the output. If longer lock time is tolerable, the PLLGAIN bit can be held high all the time. Bit 4: SLP_EXTEND. This bit allows for extended sleep intervals, up to 16s. Bit 3: WDR32_SE. If an external 32 kHz crystal is used, this bit allows a choice between the ECO or the ILO as the source of the watchdog timer and sleep timer Bit 2: EXTCLKEN. When the EXTCLKEN bit is set, the external clock becomes the source for the internal clock tree, SYSCLK, which drives most PSoC device clocking functions. All external and internal signals, including the 32-kHz clock, whether derived from the Internal Low Speed 8.3.3 Address 1,E8h Oscillator (ILO) or the crystal oscillator, are synchronized to this clock source. If an external clock is enabled, PLL mode should be off. The external clock input is located on port P1[4]. When using this input, the pin drive mode should be set to High-Z (not High-Z analog). Bit 1: RSVD. Reserved bit - This bit should always be 0. Bit 0: SYSCLKX2DIS. When SYSCLKX2DIS is set, the IMO’s doubler is disabled. This will result in a reduction of overall device power, on the order of 1 mA. It is advised that any application that does not require this doubled clock should have it turned off. For additional information, refer to the OSC_CR2 register on page 298. IMO_TR Register Name Bit 7 Bit 6 Bit 5 Bit 4 IMO_TR Bit 3 Bit 2 Bit 1 Bit 0 Trim[7:0] Access RW : 00 The Internal Main Oscillator Trim Register (IMO_TR) is used to manually center the oscillator’s output to a target frequency. value for operation in this range. For operation between these voltage ranges, user code can interpolate the best value using both available factory trim values. The PSoC device specific value for 5-V operation is loaded into the Internal Main Oscillator Trim register (IMO_TR) at boot time. The Internal Main Oscillator will operate within specified tolerance over a voltage range of 4.75 V to 5.25 V, with no modification of this register. If the PSoC device is operated at a lower voltage, user code must modify the contents of this register. For operation in the voltage range of 3.3 V ± 0.3 V, this is accomplished with a Table Read command to the Supervisory ROM, which will supply a trim It is strongly recommended that the user not alter the register value, unless Slow IMO mode is used. 8.3.4 Address 1,EFh Bits 7 to 0: Trim[7:0]. These bits are used to trim the Internal Main Oscillator. A larger value in this register will increase the speed of the oscillator. For additional information, refer to the IMO_TR register on page 303. IMO_TR1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 IMO_TR1 Bit 1 Bit 0 CATA_Trim[1:0] The Internal Main Oscillator Trim 1 Register (IMO_TR1) is used to tune CATA current. ‘00’ is for largest CATA current (default value). Bits 1 to 0: CATA_Trim[1:0]. These bits are used to tune CATA current. ‘11’ is for smallest CATA current. Access RW : 0 ... For additional information, refer to the IMO_TR1 register on page 307. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 83 Internal Main Oscillator (IMO) 84 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 9. Internal Low Speed Oscillator (ILO) This chapter briefly explains the Internal Low Speed Oscillator (ILO) and its associated register. The Internal Low Speed Oscillator produces a 32 kHz clock. For a quick reference of all PSoC® registers in address order, refer to the Register Details chapter on page 125. 9.1 Architectural Description The Internal Low Speed Oscillator (ILO) is an oscillator with a nominal frequency of 32 kHz. It is used to generate Sleep Wakeup interrupts and watchdog resets. This oscillator can also be used as a clocking source for the digital PSoC blocks. 9.2 The oscillator operates in three modes: normal power, low power, and off. The Normal Power mode consumes more current to produce a more accurate frequency. The Low Power mode is always used when the part is in a power down (sleep) state. Register Definitions The following register is associated with the Internal Low Speed Oscillator (ILO). The register description has an associated register table showing the bit structure. The bits in the table that are grayed out are reserved bits and are not detailed in the register description that follows. Note that reserved bits should always be written with a value of ‘0’. 9.2.1 ILO_TR Register Address Name 1,E9h ILO_TR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bias Trim[1:0] The Internal Low Speed Oscillator Trim Register (ILO_TR) sets the adjustment for the internal low speed oscillator. The device specific value, placed in the trim bits of this register at boot time, is based on factory testing. It is strongly recommended that the user not alter the values in the register. Bits 5 and 4: Bias Trim[1:0]. These two bits are used to set the bias current in the PTAT Current Source. Bit 5 gets inverted, so that a medium bias is selected when both bits are ‘0’. The bias current is set according to Table 9-1. Bit 1 Bit 0 Freq Trim[3:0] Access RW : 00 Table 9-1. Bias Current in PTAT Bias Current Bias Trim [1:0] Medium Bias 00b Maximum Bias 01b Minimum Bias 10b Reserved 11b Bits 3 to 0: Freq Trim[3:0]. These four bits are used to trim the frequency. Bit 0 is the LSb and bit 3 is the MSb. Bit 3 gets inverted inside the register. For additional information, refer to the ILO_TR register on page 304. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 85 Internal Low Speed Oscillator (ILO) 86 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 10. External Crystal Oscillator (ECO) This chapter briefly explains the External Crystal Oscillator (ECO) and its associated registers. The 32.768 kHz external crystal oscillator circuit allows the user to replace the internal low speed oscillator with a more precise time source at low cost and low power. For a complete table of the External Crystal Oscillator registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC® registers in address order, refer to the Register Details chapter on page 125. 10.1 Architectural Description The External Crystal Oscillator (ECO) circuit uses an inexpensive watch crystal and two small value capacitors as external components, with all other components being on the PSoC device. The crystal oscillator may be configured to provide a reference to the Internal Main Oscillator (IMO) in PLL mode, for generating a 24 MHz system clock. Figure 10-1. State Transition Between ECO and ILO Operation The XTALIn and XTALOut pins support connection of a 32.768 kHz watch crystal. To use the external crystal, bit 7 of the Oscillator Control 0 register (OSC_CR0) must be set (the default is off). The only external components needed are the crystal and the two capacitors that connect to Vdd. Note that transitions between the internal and external oscillator domains may produce glitches on the clock bus. Set OSC_CR0[7] to activate the ECO, then on the next Sleep interrupt, ECO becomes the 32.768 kHz source. During the process of activating the ECO, there must be a hold-off period before using it as the 32.768 kHz source. This hold-off period is partially implemented in hardware using the sleep timer. Firmware must set up a sleep period of one second (maximum ECO settling time), and then enable the ECO in the OSC_CR0 register. At the one second time-out (the sleep interrupt), the switch is made by hardware to the ECO. If the ECO is subsequently deactivated, the Internal Low Speed Oscillator (ILO) will again be activated and the switch is made back to the ILO immediately. The ECO Exists bit (ECO EX, bit 2 in the CPU_SCR1 register) is used to control whether the switch-over is allowed or locked. This is a write once bit. It is written early in code execution after a Power On Reset (POR) or external reset (XRES) event. A ‘1’ in this bit indicates to the hardware that a crystal exists in the system, and firmware is allowed to switch back and forth between ECO and ILO operation. If the bit is ‘0’, switch-over to the ECO is locked out. The ECO Exists Written bit (ECO EXW, bit 3 in the CPU_SCR1 register) is read only and is set on the first write to this register. When this bit is ‘1’, it indicates that the state of ECO EX is locked. This is illustrated in Figure 10-1. Transitions allowed only if write once "ECO Exists" register bit is set. (Default POR State) ECO Inactive ILO Active ECO Active ILO Inactive Clear OSC_CR0[7] to immediately revert back to ILO as 32 kHz source. (User has stated that ECO is in use.) The firmware steps involved in switching between the Internal Low Speed Oscillator (ILO) to the 32.768 kHz External Crystal Oscillator (ECO) are as follows. 1. At reset, the PSoC device begins operation, using the ILO. 2. Set the ECO EX bit to allow crystal operation. 3. Select a sleep interval of one second, using bits[4:3] in the Oscillator Control 0 register (OSC_CR0), as the oscillator stabilization interval. 4. Enable the ECO by setting bit [7] in Oscillator Control 0 register (OSC_CR0) to ‘1’. 5. The ECO becomes the selected source at the end of the one-second interval on the edge created by the Sleep Interrupt logic. The one-second interval gives the oscillator time to stabilize before it becomes the active source. The sleep interrupt need not be enabled for the switchover to occur. Reset the sleep timer (if this does not interfere with any ongoing real-time clock operation), to guarantee the interval length. Note that the ILO continues to run until the oscillator is automatically switched over by the sleep timer interrupt. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 87 External Crystal Oscillator (ECO) 6. It is strongly advised to wait the one-second stabilization period prior to engaging the PLL mode to lock the IMO frequency to the ECO frequency. Note 1 The ILO switches back instantaneously by writing the 32 kHz Select Control bit to ‘0’. Note 2 If the proper settings are selected in PSoC Designer, these steps are automatically done in boot.asm. Note 3 Transitions between oscillator domains may produce glitches on the 32 kHz clock bus. Functions that require accuracy on the 32 kHz clock should be enabled after the transition in oscillator domains. 10.1.1 ECO External Components The external component connections and selections of the External Crystal Oscillator are illustrated in Figure 10-2. ■ Crystal – 32.768 kHz watch crystal such as Epson C002RX. ■ Capacitors – C1, C2 use NPO ceramic caps. Use the following equation if you do not employ PLL mode. C1 = C2 = 25 pF – (Package Capacitance) – (Board Parasitic Capacitance) An error of 1 pF in C1 and C2 gives about a 3 ppm error in frequency. Figure 10-2. 20-Pin PSoC Example of the ECO External Connections Vdd C3 Vss ® PSoC P1[1] P1[0] Vss Vdd Vdd C1 C2 X1 Refer to the PSoC devices’ data sheets, in the packaging chapter, for typical package capacitances on crystal pins. 88 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F External Crystal Oscillator (ECO) 10.2 Register Definitions The following registers are associated with the External Crystal Oscillator and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are reserved bits and are not detailed in the register descriptions. Note that reserved bits should always be written with a value of ‘0’. For a complete table of external crystal oscillator registers, refer to the “Summary Table of the Core Registers” on page 36. 10.2.1 Address x,FEh CPU_SCR1 Register Name Bit 7 CPU_SCR1 IRESS Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SLIMO ECO EXW ECO EX Bit 1 Bit 0 Access IRAMDIS # : 00 LEGEND x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. # Access is bit specific. Refer to the Register Details chapter on page 125 for additional information. The System Status and Control Register 1 (CPU_SCR1) is used to convey the status and control of events related to internal resets and watchdog reset. Bit 7: IRESS. The Internal Reset Status bit is a read only bit that may be used to determine if the booting process occurred more than once. When this bit is set, it indicates that the SROM SWBootReset code was executed more than once. If this bit is not set, the SWBootReset was executed only once. In either case, the SWBootReset code will not allow execution from code stored in Flash until the M8C Core is in a safe operating mode with respect to supply voltage and Flash operation. There is no need for concern when this bit is set. It is provided for systems which may be sensitive to boot time, so that they can determine if the normal one-pass boot time was exceeded. For more information on the SWBootReest code see the Supervisory ROM (SROM) chapter on page 49. Bit 4: SLIMO. When set, the Slow IMO bit allows the active power dissipation of the PSoC device to be reduced by slowing down the IMO from 24 MHz to 6 MHz. The IMO trim value must also be changed when SLIMO is set (see “Engaging Slow IMO” on page 81). When not in external clocking mode, the IMO is the source for SYSCLK; therefore, when the speed of the IMO changes, so will SYSCLK. Bit 3: ECO EXW. The ECO Exists Written bit is used as a status bit to indicate that the ECO EX bit has been previously written to. It is read only. When this bit is a ‘1’, this indicates that the CPU_SCR1 register has been written to and is now locked. When this bit is a ‘0’, the register has not been written to since the last reset event. Bit 2: ECO EX. The ECO Exists bit serves as a flag to the hardware, to indicate that an external crystal oscillator exists in the system. Just after boot, it may be written only once to a value of ‘1’ (crystal exists) or ‘0’ (crystal does not exist). If the bit is ‘0’, a switch-over to the ECO is locked out by hardware. If the bit is ‘1’, hardware allows the firmware to freely switch between the ECO and ILO. It should be written as early as possible after a Power On Reset (POR) or External Reset (XRES) event, where it is assumed that program execution integrity is high. Bit 0: IRAMDIS. The Initialize RAM Disable bit is a control bit that is readable and writeable. The default value for this bit is ‘0’, which indicates that the maximum amount of SRAM should be initialized on watchdog reset to a value of 00h. When the bit is ‘1’, the minimum amount of SRAM is initialized after a watchdog reset. For more information on this bit, see the “SROM Function Descriptions” on page 50. For additional information, refer to the CPU_SCR1 register on page 216. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 89 External Crystal Oscillator (ECO) 10.2.2 Address 1,E0h OSC_CR0 Register Name OSC_CR0 Bit 7 Bit 6 Bit 5 32k Select PLL Mode No Buzz The Oscillator Control Register 0 (OSC_CR0) is used to configure various features of internal clock sources and clock nets. Bit 7: 32k Select. By default, the 32 kHz clock source is the Internal Low Speed Oscillator (ILO). Optionally, the 32.768 kHz External Crystal Oscillator (ECO) may be selected. Bit 6: PLL Mode. This is the only bit in the OSC_CR0 register that directly influences the Phase Locked Loop (PLL). When set, this bit enables the PLL. The EXTCLKEN bit in the OSC_CR2 register should be set low during PLL operation. For information on the PLL, refer to the Phase-Locked Loop (PLL) chapter on page 93. Bit 5: No Buzz. Normally, when the Sleep bit is set in the CPU_SCR register, all PSoC device systems are powered down, including the bandgap reference. However, to facilitate the detection of POR and LVD events at a rate higher than the sleep interval, the bandgap circuit is powered up periodically for about 60 s at the Sleep System Duty Cycle (set in ECO_TR), which is independent of the sleep interval and typically higher. When the No Buzz bit is set, the Sleep System Duty Cycle value is overridden and the bandgap circuit is forced to be on during sleep. This results in a faster response to an LVD or POR event (continuous detection as opposed to periodic detection), at the expense of higher average sleep current. Bits 4 and 3: Sleep[1:0]. The available sleep interval selections are shown in Table 10-1. It must be remembered that when the ILO is the selected 32 kHz clock source, sleep intervals are approximate. Table 10-1. Sleep Interval Selections Sleep Interval Sleep Timer OSC_CR2[4] OSC_CR0[4:3] Clocks Sleep Period (nominal) Watchdog Period (nominal) 0 00b (default) 64 1.95 ms 6 ms 0 01b 512 15.6 ms 47 ms 0 10b 4,096 125 ms 375 ms 0 11b 32,768 1 sec 3 sec 1 00b (default) 65,536 2 sec 6 sec 1 01b 131,072 4 sec 12 sec 1 10b 262,144 8 sec 24 sec 1 11b 524,288 16 sec 48 sec Bit 4 Bit 3 Sleep[1:0] Bit 2 Bit 1 Bit 0 CPU Speed[2:0] Access RW : 00 The reset value for the CPU Speed bits is zero; therefore, the default CPU speed is one-eighth of the clock source. The Internal Main Oscillator (IMO) is the default clock source for the CPU speed circuit; therefore, the default CPU speed is 3 MHz. The CPU frequency is changed with a write to the OSC_CR0 register. There are eight frequencies generated from a power-of-2 divide circuit, which are selected by a 3bit code. At any given time, the CPU 8-to-1 clock mux is selecting one of the available frequencies, which is resynchronized to the 24 MHz master clock at the output. Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24 MHz operating requirements apply. An example of this scenario is a device that is configured to use an external clock, which is supplying a frequency of 20 MHz. If the CPU speed register’s value is 0b011, the CPU clock will be 20 MHz. Therefore, the supply voltage requirements for the device are the same as if the part was operating at 24 MHz off of the IMO. The operating voltage requirements are not relaxed until the CPU speed is at 12 MHz or less. Table 10-2. OSC_CR0[2:0] Bits: CPU Speed Bits Internal Main Oscillator External Clock 000b 3 MHz EXTCLK/ 8 001b 6 MHz EXTCLK/ 4 010b 12 MHz EXTCLK/ 2 011b 24 MHz EXTCLK/ 1 100b 1.5 MHz EXTCLK/ 16 101b 750 kHz EXTCLK/ 32 110b 187.5 kHz EXTCLK/ 128 111b 93.7 kHz EXTCLK/ 256 For additional information, refer to the OSC_CR0 register on page 296. Bits 2 to 0: CPU Speed[2:0]. The PSoC M8C may operate over a range of CPU clock speeds (see Table 10-2), allowing the M8C’s performance and power requirements to be tailored to the application. 90 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F External Crystal Oscillator (ECO) 10.2.3 Address 1,E2h OSC_CR2 Register Name OSC_CR2 Bit 7 Bit 6 Bit 5 Bit 4 PLLGAIN Bit 7: PLLGAIN. This is the only bit in the OSC_CR2 register that directly influences the PLL. When set, this bit keeps the PLL in a Low Gain mode. If this bit is held low, the lock time is less than 10 ms. If this bit is held high, the lock time is on the order of 50 ms. After lock is achieved, it is recommended that this bit be forced high to decrease the jitter on the output. If longer lock time is tolerable, the PLLGAIN bit can be held high all the time. Bit 0 Access RSVD SYSCLKX2 DIS RW : 00 Bit 0: SYSCLKX2DIS. When set, the Internal Main Oscillator’s doubler is disabled. This results in a reduction of overall device power, on the order of 1 mA. It is advised that any application that does not require this doubled clock should have it turned off. Bit 3: WDR32_SE. If an external 32 kHz crystal is used, this bit allows a choice between the ECO or the ILO as the source of the watchdog timer and sleep timer Address EXTCLKEN Bit 1 Bit 1: RSVD. Reserved bit - This bit should always be 0. Bit 4: SLP_EXTEND. This bit allows for extended sleep intervals, up to 16s. 1,EBh WDR32_SE Bit 2 Bit 2: EXTCLKEN. When the EXTCLKEN bit is set, the external clock becomes the source for the internal clock tree, SYSCLK, which drives most PSoC device clocking functions. All external and internal signals, including the 32 kHz clock, whether derived from the internal low speed oscillator (ILO) or the crystal oscillator, are synchronized to this clock source. If an external clock is enabled, PLL mode should be off. The external clock input is located on port P1[4]. When using this input, the pin drive mode should be set to High-Z (not High-Z analog). The Oscillator Control Register 2 (OSC_CR2) is used to configure various features of internal clock sources and clock nets. 10.2.4 Bit 3 SLP_EXTE ND For additional information, refer to the OSC_CR2 register on page 298. ECO_TR Register Name ECO_TR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PSSDC[1:0] Bit 1 Bit 0 Access RW : 00 The External Crystal Oscillator Trim Register (ECO_TR) sets the adjustment for the 32.768 kHz External Crystal Oscillator. The device specific value placed in this register at boot time is based on factory testing. This register does not adjust the frequency of the external crystal oscillator. It is strongly recommended that the user not alter the register value. Bits 7 and 6: PSSDC[1:0]. These bits are used to set the sleep duty cycle. These bits should not be altered. For additional information, refer to the ECO_TR register on page 306. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 91 External Crystal Oscillator (ECO) 92 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 11. Phase-Locked Loop (PLL) This chapter presents the Phase-Locked Loop (PLL) and its associated registers. For a complete table of the PLL registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC® registers in address order, refer to the Register Details chapter on page 125. 11.1 Architectural Description A Phase-Locked Loop (PLL) function generates the system clock with crystal accuracy. It is designed to provide a 23.986 MHz oscillator, when utilized with an external 32.768 kHz crystal. Although the PLL tracks crystal accuracy, it requires time to lock onto the reference frequency when first starting. The length of time depends on the PLLGAIN controlled by bit 7 of the OSC_CR2 register. If this bit is held low, the lock time is less than 10 ms. If this bit is held high, the lock time is on the order of 50 ms. After lock is achieved, it is recommended that this bit be forced high to decrease the jitter on the output. If longer lock time is tolerable, the PLLGAIN bit can be held high all the time. After the 32.768 kHz External Crystal Oscillator (ECO) has been selected and enabled, the following procedure should 11.2 be followed to enable the PLL and allow for proper frequency lock. ■ Select a CPU frequency of 3 MHz or less. ■ Enable the PLL. ■ Wait between 10 and 50 ms, depending on bit 7 of the OSC_CR2 register. ■ Set the CPU to a faster frequency, if desired. To do this, write the CPU Speed[2:0] bits in the OSC_CR0 register. The CPU frequency will immediately change when these bits are set. Note If the proper settings are selected in PSoC Designer™, these steps are automatically done in boot.asm. Register Definitions The following registers are associated with the Phase Locked Loop (PLL) and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are reserved bits and are not detailed in the register descriptions. Note that reserved bits should always be written with a value of ‘0’. For a complete table of the PLL registers, refer to the “Summary Table of the Core Registers” on page 36. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 93 Phase-Locked Loop (PLL) 11.2.1 Address 1,E0h OSC_CR0 Register Name OSC_CR0 Bit 7 Bit 6 Bit 5 32k Select PLL Mode No Buzz The Oscillator Control Register 0 (OSC_CR0) is used to configure various features of internal clock sources and clock nets. Bit 7: 32k Select. By default, the 32 kHz clock source is the Internal Low Speed Oscillator (ILO). Optionally, the 32.768 kHz External Crystal Oscillator (ECO) may be selected. Bit 6: PLL Mode. This is the only bit in the OSC_CR0 register that directly influences the Phase Locked Loop (PLL). When set, this bit enables the PLL. The EXTCLKEN bit in the OSC_CR2 register should be set low during PLL operation. Bit 5: No Buzz. Normally, when the Sleep bit is set in the CPU_SCR register, all PSoC device systems are powered down, including the bandgap reference. However, to facilitate the detection of POR and LVD events at a rate higher than the sleep interval, the bandgap circuit is powered up periodically for about 60 s at the Sleep System Duty Cycle (set in ECO_TR), which is independent of the sleep interval and typically higher. When the No Buzz bit is set, the Sleep System Duty Cycle value is overridden and the bandgap circuit is forced to be on during sleep. This results in a faster response to an LVD or POR event (continuous detection as opposed to periodic detection), at the expense of slightly higher average sleep current. Bit 4 Bit 3 Bit 2 Sleep[1:0] Bit 1 Bit 0 CPU Speed[2:0] Access RW : 00 The reset value for the CPU Speed bits is zero; therefore, the default CPU speed is one-eighth of the clock source. The Internal Main Oscillator (IMO) is the default clock source for the CPU speed circuit; therefore, the default CPU speed is 3 MHz. The CPU frequency is changed with a write to the OSC_CR0 register. There are eight frequencies generated from a power-of-2 divide circuit, which are selected by a 3bit code. At any given time, the CPU 8-to-1 clock mux is selecting one of the available frequencies, which is resynchronized to the 24 MHz master clock at the output. Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24 MHz operating requirements apply. An example of this scenario is a device that is configured to use an external clock, which is supplying a frequency of 20 MHz. If the CPU speed register’s value is 0b011, the CPU clock will be 20 MHz. Therefore, the supply voltage requirements for the device are the same as if the part was operating at 24 MHz off of the IMO. The operating voltage requirements are not relaxed until the CPU speed is at 12 MHz or less. Some devices support the slow IMO option, as discussed in the IMO chapter in the “Architectural Description” on page 81. This offers an option to lower both system and CPU clock speed to save power. Bits 4 and 3: Sleep[1:0]. The available sleep interval selections are shown in Table 11-1. It must be remembered that when the ILO is the selected 32 kHz clock source, sleep intervals are approximate. An automatic protection mechanism is available for systems that need to run at peak CPU clock speed but cannot guarantee a high enough supply voltage for that clock speed. See the LVDTBEN bit in the “VLT_CR Register” on page 523 for more information. Table 11-1. Sleep Interval Selections Table 11-2. OSC_CR0[2:0] Bits: CPU Speed OSC_CR2[4] Sleep Interval Sleep Timer OSC_CR0[4:3] Clocks Sleep Period (nominal) Watchdog Period (nominal) 0 00b (default) 64 1.95 ms 6 ms 0 01b 512 15.6 ms 47 ms 0 10b 4,096 125 ms 375 ms 0 11b 32,768 1 sec 3 sec 1 00b (default) 65,536 2 sec 6 sec 1 01b 131,072 4 sec 12 sec 1 10b 262,144 8 sec 24 sec 1 11b 524,288 16 sec 48 sec Bits 2 to 0: CPU Speed[2:0]. The PSoC M8C may operate over a range of CPU clock speeds (see Table 11-2), allowing the M8C’s performance and power requirements to be tailored to the application. 94 Bits 6 MHz Internal Main Oscillator * 24 MHz Internal Main Oscillator External Clock 000b 750 kHz 3 MHz EXTCLK/ 8 001b 1.5 MHz 6 MHz EXTCLK/ 4 010b 3 MHz 12 MHz EXTCLK/ 2 011b 6 MHz 24 MHz EXTCLK/ 1 100b 375 kHz 1.5 MHz EXTCLK/ 16 101b 187.5 kHz 750 kHz EXTCLK/ 32 110b 93.7 kHz 187.5 kHz EXTCLK/ 128 111b 46.9 kHz 93.7 kHz EXTCLK/ 256 * For PSoC devices that support the slow IMO option, see the “Architectural Description” on page 81. For additional information, refer to the OSC_CR0 register on page 296. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Phase-Locked Loop (PLL) 11.2.2 Address 1,E2h OSC_CR2 Register Name OSC_CR2 Bit 7 PLLGAIN Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SLP_EXTE ND WDR32_SE EXTCLKEN RSVD SYSCLKX2 DIS RW : 00 The Oscillator Control Register 2 (OSC_CR2) is used to configure various features of internal clock sources and clock nets. Bit 7: PLLGAIN. This is the only bit in the OSC_CR2 register that directly influences the PLL. When set, this bit keeps the PLL in Low Gain mode. If this bit is held low, the lock time is less than 10 ms. If this bit is held high, the lock time is on the order of 50 ms. After lock is achieved, it is recommended that this bit be forced high to decrease the jitter on the output. If longer lock time is tolerable, the PLLGAIN bit can be held high all the time. Bit 4: SLP_EXTEND. This bit allows for extended sleep intervals, up to 16s. Bit 3: WDR32_SE. If an external 32 kHz crystal is used, this bit allows a choice between the ECO or the ILO as the source of the watchdog timer and sleep timer Bit 2: EXTCLKEN. When the EXTCLKEN bit is set, the external clock becomes the source for the internal clock tree, SYSCLK, which drives most PSoC device clocking functions. All external and internal signals, including the 32 kHz clock, whether derived from the Internal Low Speed Oscillator (ILO) or the crystal oscillator, are synchronized to this clock source. If an external clock is enabled, PLL mode should be off. The external clock input is located on port P1[4]. When using this input, the pin drive mode should be set to High-Z (not High-Z analog). Bit 1: RSVD. Reserved bit - This bit should always be 0. Bit 0: SYSCLKX2DIS. When SYSCLKX2DIS is set, the IMO’s doubler is disabled. This will result in a reduction of overall device power, on the order of 1 mA. It is advised that any application that does not require this doubled clock should have it turned off. During emulation with the In-Circuit Emulator (ICE), the IMO’s doubler is always active regardless of the status of SYSCLKX2DIS. For additional information, refer to the OSC_CR2 register on page 298. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 95 Phase-Locked Loop (PLL) 96 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 12. Sleep and Watchdog This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep and Watchdog registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC® registers in address order, refer to the Register Details chapter on page 125. 12.1 Architectural Description Device components that are involved in Sleep and Watchdog operation are the selected 32 kHz clock (external crystal or internal), the sleep timer, the Sleep bit in the CPU_SCR0 register, the sleep circuit (to sequence going into and coming out of sleep), the bandgap refresh circuit (to periodically refresh the reference voltage during sleep), and the watchdog timer. The goal of Sleep operation is to reduce average power consumption as much as possible. The system has a sleep state that can be initiated under firmware control. In this state, the CPU is stopped at an instruction boundary and the 24/48 MHz oscillator (IMO), the Flash memory module, and bandgap voltage reference are powered down. The only blocks that remain in operation are the 32 kHz oscillator (external crystal or internal), PSoC blocks clocked from the 32 kHz clock selection, and the supply voltage monitor circuit. Analog PSoC blocks have individual power down settings that are controlled by firmware, independently of the sleep state. Continuous time analog blocks may remain in operation, because they do not require a clock source. Typically, switched capacitor analog blocks will not operate, because the internal sources of clocking for these blocks are stopped. The system can only wake up from sleep as a result of an interrupt or reset event. The sleep timer can provide periodic interrupts to allow the system to wake up, poll peripherals, or do real-time functions, and then go to sleep again. The GPIO (pin) interrupt, supply monitor interrupt, analog column interrupts, and timers clocked externally or from the 32 kHz clock are examples of asynchronous interrupts that can also be used to wake the system up. The Watchdog Timer (WDT) circuit is designed to assert a hardware reset to the device after a pre-programmed interval, unless it is periodically serviced in firmware. In the event that an unexpected execution path is taken through the code, this functionality serves to reboot the system. It can also restart the system from the CPU halt state. When the WDT is enabled, it can only be disabled by an External Reset (XRES) or a Power On Reset (POR). A WDT reset will leave the WDT enabled. Therefore, if the WDT is used in an application, all code (including initialization code) must be written as though the WDT is enabled. 12.1.1 32 kHz Clock Selection By default, the 32 kHz clock source is the Internal Low Speed Oscillator (ILO). Optionally, the 32.768 kHz External Crystal Oscillator (ECO) may be activated. This selection is made in bit 7 of the OSC_CR0 register. Selecting the ECO as the source for the 32 kHz clock allows the sleep timer and sleep interrupt to be used in real-time clock applications. Regardless of the clock source selected, the 32 kHz clock plays a key role in sleep functionality. It runs continuously and is used to sequence system wakeup. It is also used to periodically refresh the bandgap voltage during sleep. Refer to the External Crystal Oscillator (ECO) chapter on page 87, for details on activating an external crystal oscillator. 12.1.2 Sleep Timer The sleep timer is a 15-bit up counter clocked by the currently selected 32 kHz clock source, either the ILO or ECO. This timer is always enabled. The exception to this is within an ICE (in-circuit emulator) in debugger mode and when the Stop bit in the CPU_SCR0 is set; the sleep timer is disabled, so that the user will not get continual watchdog resets when a breakpoint is hit in the debugger environment. If the associated sleep timer interrupt is enabled, a periodic interrupt to the CPU is generated based on the sleep interval selected from the OSC_CR0 register. The sleep timer functionality does not need to be directly associated with the sleep state. It can be used as a general purpose timer interrupt regardless of sleep state. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 97 Sleep and Watchdog The reset state of the sleep timer is a count value of all zeros. There are two ways to reset the sleep timer. Any hardware reset, (that is, POR, XRES, or Watchdog Reset (WDR) will reset the sleep timer. There is also a method that allows the user to reset the sleep timer in firmware. A write of 38h to the RES_WDT register clears the sleep timer. Note Any write to the RES_WDT register also clears the watchdog timer. Clearing the sleep timer may be done at anytime to synchronize the sleep timer operation to CPU processing. A good example of this is after POR. The CPU hold-off, due to voltage ramp and others, may be significant. In addition, a significant amount of program initialization may be required. However, the sleep timer starts counting immediately after POR and will be at an arbitrary count when user code begins execution. In this case, it may be desirable to clear the sleep timer before enabling the sleep interrupt initially, to ensure that the first sleep period is a full interval. 12.2 Application Description The following are notes regarding sleep as it relates to firmware and application issues. Note 1 If an interrupt is pending, enabled, and scheduled to be taken at the instruction boundary after the write to the sleep bit, the system will not go to sleep. The instruction will still execute, but it will not be able to set the SLEEP bit in the CPU_SCR0 register. Instead, the interrupt will be taken and the effect of the sleep instruction is ignored. Note 2 The Global Interrupt Enable (CPU_F register) does not need to be enabled to wake the system out of sleep state. Individual interrupt enables, as set in the interrupt mask registers, are sufficient. If the Global Interrupt Enable is not set, the CPU will not service the ISR associated with that interrupt. However, the system will wake up and continue executing instructions from the point at which it went to sleep. In this case, the user must manually clear the pending interrupt or subsequently enable the Global Interrupt Enable bit and let the CPU take the ISR. If a pending interrupt is not cleared, it will be continuously asserted. Although the sleep bit may be written and the sleep sequence executed as soon as the device enters Sleep mode, the Sleep bit is cleared by the pending interrupt and Sleep mode is exited immediately. 98 Note 3 On wakeup, the instruction immediately after the sleep instruction is executed before the interrupt service routine (if enabled). The instruction after the sleep instruction is pre-fetched, before the system actually goes to sleep. Therefore, when an interrupt occurs to wake the system up, the pre-fetched instruction is executed and then the interrupt service routine is executed. (If the Global Interrupt Enable is not set, instruction execution will just continue where it left off before sleep.) Note 4 If PLL mode is enabled, CPU frequency must be reduced to 3 MHz before going to sleep. The PLL will overshoot as it attempts to re-lock after wakeup; therefore, the CPU frequency must be relatively low. It is recommended to wait 10 ms after wakeup, before normal CPU operating frequency may be restored. Note 5 Analog power must be turned off by firmware before going to sleep, to achieve the smallest sleep current. The system sleep state does not control the analog array. There are individual power controls for each analog block and global power controls in the reference block. These power controls must be manipulated by firmware. Note 6 If the Global Interrupt Enable bit is disabled, it can be safely enabled just before the instruction that writes the sleep bit. It is usually undesirable to get an interrupt on the instruction boundary, just before writing the sleep bit. This means that on the return from interrupt, the sleep command will be executed, possibly bypassing any firmware preparations that must be made to go to sleep. To prevent this, disable interrupts before preparations are made. After sleep preparations, enable global interrupts and write the sleep bit with the two consecutive instructions as follows. and f,~01h // disable global interrupts // (prepare for sleep, could // be many instructions) or f,01h // enable global interrupts mov reg[ffh],08h // Set the sleep bit Due to the timing of the Global Interrupt Enable instruction, it is not possible for an interrupt to occur immediately after that instruction. The earliest the interrupt can occur is after the next instruction (write to the Sleep bit) has been executed. Therefore, if an interrupt is pending, the sleep instruction is executed; but as described in Note 1, the sleep instruction will be ignored. The first instruction executed after the ISR is the instruction after sleep. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Sleep and Watchdog 12.3 Register Definitions The following registers are associated with Sleep and Watchdog and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are reserved bits and are not detailed in the register descriptions. Note that reserved bits should always be written with a value of ‘0’. For a complete table of the Sleep and Watchdog registers, refer to the “Summary Table of the Core Registers” on page 36. 12.3.1 INT_MSK0 Register Address 0,E0h Name 4 Cols. 2 Cols. INT_MSK0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor VC3 Sleep GPIO Analog 1 Analog 0 V Monitor Depending on your PSoC device’s characteristics, only certain bits are accessible to be read or written in the analog column dependent INT_MSK0 register. (Refer to the table titled “CY8C28xxx Device Characteristics” on page 24.) In the table, the analog column numbers are listed to the right in the Address column. Address 0,E3h RW : 00 Bits 7 and 5 to 0. The INT_MSK0 register holds bits that are used by several different resources. For a full discussion of the INT_MSK0 register, see the Interrupt Controller chapter on page 65. The Interrupt Mask Register 0 (INT_MSK0) is used to enable the individual sources’ ability to create pending interrupts. 12.3.2 Access Bit 6: Sleep. This bit controls the sleep interrupt enable. For additional information, refer to the INT_MSK0 register on page 208. RES_WDT Register Name Bit 7 Bit 6 Bit 5 RES_WDT The Reset Watchdog Timer Register (RES_WDT) is used to clear the watchdog timer (a write of any value) and clear both the watchdog timer and the sleep timer (a write of 38h). Bits 7 to 0: WDSL_Clear[7:0]. The Watchdog Timer (WDT) write-only register is designed to timeout at three rollover events of the sleep timer. Therefore, if only the WDT is cleared, the next Watchdog Reset (WDR) will occur anywhere from two to three times the current sleep interval setting. If the sleep timer is near the beginning of its count, the watchdog timeout will be closer to three times. However, if Bit 4 Bit 3 Bit 2 WDSL_Clear[7:0] Bit 1 Bit 0 Access W : 00 the sleep timer is very close to its terminal count, the watchdog timeout will be closer to two times. To ensure a full three times timeout, both the WDT and the sleep timer may be cleared. In applications that need a real-time clock, and thus cannot reset the sleep timer when clearing the WDT, the duty cycle at which the WDT must be cleared should be no greater than two times the sleep interval. For additional information, refer to the RES_WDT register on page 211. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 99 Sleep and Watchdog 12.3.3 Address x,FEh CPU_SCR1 Register Name Bit 7 CPU_SCR1 IRESS Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SLIMO ECO EXW ECO EX Bit 1 Bit 0 Access IRAMDIS # : 00 LEGEND x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. # Access is bit specific. Refer to the Register Details chapter on page 125 for additional information. The System Status and Control Register 1 (CPU_SCR1) is used to convey the status and control of events related to internal resets and watchdog reset. Bit 7: IRESS. The Internal Reset Status bit is a read only bit that may be used to determine if the booting process occurred more than once. When this bit is set, it indicates that the SROM SWBootReset code was executed more than once. If this bit is not set, the SWBootReset was executed only once. In either case, the SWBootReset code will not allow execution from code stored in Flash until the M8C Core is in a safe operating mode with respect to supply voltage and Flash operation. There is no need for concern when this bit is set. It is provided for systems which may be sensitive to boot time, so that they can determine if the normal one-pass boot time was exceeded. For more information on the SWBootReest code see the Supervisory ROM (SROM) chapter on page 49. Bit 4: SLIMO. When set, the Slow IMO bit allows the active power dissipation of the PSoC device to be reduced by slowing down the IMO from 24 MHz to 6 MHz. The IMO trim value must also be changed when SLIMO is set (see “Engaging Slow IMO” on page 81). When not in external clocking mode, the IMO is the source for SYSCLK; therefore, when the speed of the IMO changes, so will SYSCLK. 100 Bit 3: ECO EXW. The ECO Exists Written bit is used as a status bit to indicate that the ECO EX bit has been previously written to. It is read only. When this bit is a ‘1’, this indicates that the CPU_SCR1 register has been written to and is now locked. When this bit is a ‘0’, the register has not been written to since the last reset event. Bit 2: ECO EX. The ECO Exists bit serves as a flag to the hardware, to indicate that an external crystal oscillator exists in the system. Just after boot, it may be written only once to a value of ‘1’ (crystal exists) or ‘0’ (crystal does not exist). If the bit is ‘0’, a switch-over to the ECO is locked out by hardware. If the bit is ‘1’, hardware allows the firmware to freely switch between the ECO and ILO. It should be written as early as possible after a Power On Reset (POR) or External Reset (XRES) event, where it is assumed that program execution integrity is high. Bit 0: IRAMDIS. The Initialize RAM Disable bit is a control bit that is readable and writeable. The default value for this bit is ‘0’, which indicates that the maximum amount of SRAM should be initialized on watchdog reset to a value of 00h. When the bit is ‘1’, the minimum amount of SRAM is initialized after a watchdog reset. For more information on this bit, see the “SROM Function Descriptions” on page 50. For additional information, refer to the CPU_SCR1 register on page 216. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Sleep and Watchdog 12.3.4 Address x,FFh CPU_SCR0 Register Name Bit 7 CPU_SCR0 GIES Bit 6 Bit 5 Bit 4 Bit 3 WDRS PORS Sleep Bit 2 Bit 1 Bit 0 Access STOP # : XX LEGEND X The value for power on reset is unknown. x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. # Access is bit specific. Refer to the Register Details chapter on page 125 for additional information. The System Status and Control Register 0 (CPU_SCR0) is used to convey the status and control of events for various functions of a PSoC device. Bit 7: GIES. The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged. The GIES bit is a legacy bit which was used to provide the ability to read the GIE bit of the CPU_F register. However, the CPU_F register is now readable. When this bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn, indicates that the microprocessor will service interrupts. Bit 5: WDRS. The WatchDog Reset Status bit may not be set. It is normally ‘0’ and automatically set whenever a watchdog reset occurs. The bit is readable and clearable by writing a zero to its bit position in the CPU_SCR0 register. Bit 4: PORS. The Power On Reset Status (PORS) bit, which is the watchdog enable bit, is set automatically by a POR or External Reset (XRES). If the bit is cleared by user code, the watchdog timer is enabled. When cleared, the only way to reset the PORS bit is to go through a POR or XRES. Thus, there is no way to disable the watchdog timer, other than to go through a POR or XRES. Bit 3: Sleep. The Sleep bit is used to enter Low Power Sleep mode when set. To wake up the system, this register bit is cleared asynchronously by any enabled interrupt. There are two special features of this register bit that ensures proper Sleep operation. First, the write to set the register bit is blocked, if an interrupt is about to be taken on that instruction boundary (immediately after the write). Second, there is a hardware interlock to ensure that, when set, the sleep bit may not be cleared by an incoming interrupt until the sleep circuit has finished performing the sleep sequence and the system-wide power down signal has been asserted. This prevents the sleep circuit from being interrupted in the middle of the process of system power down, possibly leaving the system in an indeterminate state. Bit 0: STOP. The STOP bit is readable and writeable. When set, the PSoC M8C will stop executing code until a reset event occurs. This can be either a POR, WDR, or XRES. If an application wants to stop code execution until a reset, the preferred method is to use the HALT instruction rather than a register write to this bit. For additional information, refer to the CPU_SCR0 register on page 217. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 101 Sleep and Watchdog 12.3.5 Address 1,E0h OSC_CR0 Register Name OSC_CR0 Bit 7 Bit 6 Bit 5 32k Select PLL Mode No Buzz The Oscillator Control Register 0 (OSC_CR0) is used to configure various features of internal clock sources and clock nets. Bit 7: 32k Select. By default, the 32 kHz clock source is the Internal Low Speed Oscillator (ILO). Optionally, the 32.768 kHz External Crystal Oscillator (ECO) may be selected. Bit 6: PLL Mode. This is the only bit in the OSC_CR0 register that directly influences the Phase Locked Loop (PLL). When set, this bit enables the PLL. The EXTCLKEN bit in the OSC_CR2 register should be set low during PLL operation. For information on the PLL, refer to the Phase-Locked Loop (PLL) chapter on page 93. Bit 5: No Buzz. Normally, when the Sleep bit is set in the CPU_SCR register, all PSoC device systems are powered down, including the bandgap reference. However, to facilitate the detection of POR and LVD events at a rate higher than the sleep interval, the bandgap circuit is powered up periodically for about 60 s at the Sleep System Duty Cycle (set in ECO_TR), which is independent of the sleep interval and typically higher. When the No Buzz bit is set, the Sleep System Duty Cycle value is overridden and the bandgap circuit is forced to be on during sleep. This results in a faster response to an LVD or POR event (continuous detection as opposed to periodic detection), at the expense of slightly higher average sleep current. Bits 4 and 3: Sleep[1:0]. The available sleep interval selections are shown in Table 12-1. The accuracy of the sleep intervals are dependent on the accuracy of the oscillator used. Table 12-1. Sleep Interval Selections Sleep Interval OSC_CR2[4] OSC_CR0[4:3] Sleep Timer Clocks Sleep Period (nominal) Watchdog Period (nominal) 0 00b (default) 64 1.95 ms 0 01b 512 15.6 ms 47 ms 0 10b 4,096 125 ms 375 ms Bit 4 Bit 3 Sleep[1:0] Bit 2 Bit 1 Bit 0 CPU Speed[2:0] Access RW : 00 The reset value for the CPU Speed bits is zero; therefore, the default CPU speed is one-eighth of the clock source. The Internal Main Oscillator (IMO) is the default clock source for the CPU speed circuit; therefore, the default CPU speed is 3 MHz. The CPU frequency is changed with a write to the OSC_CR0 register. There are eight frequencies generated from a power-of-2 divide circuit, which are selected by a 3bit code. At any given time, the CPU 8-to-1 clock mux is selecting one of the available frequencies, which is resynchronized to the 24 MHz master clock at the output. Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24 MHz operating requirements apply. An example of this scenario is a device that is configured to use an external clock, which is supplying a frequency of 20 MHz. If the CPU speed register’s value is 011b, the CPU clock will be 20 MHz. Therefore, the supply voltage requirements for the device are the same as if the part was operating at 24 MHz off of the IMO. The operating voltage requirements are not relaxed until the CPU speed is at 12 MHz or less. Table 12-2. OSC_CR0[2:0] Bits: CPU Speed Bits Internal Main Oscillator External Clock 000b 3 MHz EXTCLK/ 8 001b 6 MHz EXTCLK/ 4 010b 12 MHz EXTCLK/ 2 011b 24 MHz EXTCLK/ 1 100b 1.5 MHz EXTCLK/ 16 101b 750 kHz EXTCLK/ 32 110b 187.5 kHz EXTCLK/ 128 111b 93.7 kHz EXTCLK/ 256 For additional information, refer to the OSC_CR0 register on page 296. 6 ms 0 11b 32,768 1 sec 3 sec 1 00b (default) 65,536 2 sec 6 sec 1 01b 131,072 4 sec 12 sec 1 10b 262,144 8 sec 24 sec 1 11b 524,288 16 sec 48 sec Bits 2 to 0: CPU Speed[2:0]. The PSoC M8C may operate over a range of CPU clock speeds (see Table 12-2), allowing the M8C’s performance and power requirements to be tailored to the application. 102 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Sleep and Watchdog 12.3.6 Address 1,E2h OSC_CR2 Register Name OSC_CR2 Bit 7 Bit 6 Bit 5 Bit 4 PLLGAIN Bit 7: PLLGAIN. This is the only bit in the OSC_CR2 register that directly influences the PLL. When set, this bit keeps the PLL in a Low Gain mode. If this bit is held low, the lock time is less than 10 ms. If this bit is held high, the lock time is on the order of 50 ms. After lock is achieved, it is recommended that this bit be forced high to decrease the jitter on the output. If longer lock time is tolerable, the PLLGAIN bit can be held high all the time. Bit 0 Access RSVD SYSCLKX2 DIS RW : 00 Bit 0: SYSCLKX2DIS. When set, the Internal Main Oscillator’s doubler is disabled. This results in a reduction of overall device power, on the order of 1 mA. It is advised that any application that does not require this doubled clock should have it turned off. Bit 3: WDR32_SE. If an external 32 kHz crystal is used, this bit allows a choice between the ECO or the ILO as the source of the watchdog timer and sleep timer Address EXTCLKEN Bit 1 Bit 1: RSVD. Reserved bit - This bit should always be 0. Bit 4: SLP_EXTEND. This bit allows for extended sleep intervals, up to 16s. 1,E9h WDR32_SE Bit 2 Bit 2: EXTCLKEN. When the EXTCLKEN bit is set, the external clock becomes the source for the internal clock tree, SYSCLK, which drives most PSoC device clocking functions. All external and internal signals, including the 32 kHz clock, whether derived from the internal low speed oscillator (ILO) or the crystal oscillator, are synchronized to this clock source. If an external clock is enabled, PLL mode should be off. The external clock input is located on port P1[4]. When using this input, the pin drive mode should be set to High-Z (not High-Z analog). The Oscillator Control Register 2 (OSC_CR2) is used to configure various features of internal clock sources and clock nets. 12.3.7 Bit 3 SLP_EXTE ND For additional information, refer to the OSC_CR2 register on page 298. ILO_TR Register Name ILO_TR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bias Trim[1:0] The Internal Low Speed Oscillator Trim Register (ILO_TR) sets the adjustment for the internal low speed oscillator. The device specific value, placed in the trim bits of this register at boot time, is based on factory testing. It is strongly recommended that the user not alter the register value. Bits 5 and 4: Bias Trim[1:0]. These two bits are used to set the bias current in the PTAT Current Source. Bit 5 gets inverted, so that a medium bias is selected when both bits are ‘0’. The bias current is set according to Table 12-3. Bit 1 Bit 0 Freq Trim[3:0] Access RW : 00 Table 12-3. Bias Current in PTAT Bias Current Bias Trim [1:0] Medium Bias 00b Maximum Bias 01b Minimum Bias 10b Not needed * 11b * About 15% higher than the minimum bias. Bits 3 to 0: Freq Trim[3:0]. These four bits are used to trim the frequency. Bit 0 is the LSb and bit 3 is the MSb. Bit 3 gets inverted inside the register. For additional information, refer to the ILO_TR register on page 304. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 103 Sleep and Watchdog 12.3.8 Address 1,EBh ECO_TR Register Name ECO_TR Bit 7 Bit 6 Bit 5 PSSDC[1:0] The External Crystal Oscillator Trim Register (ECO_TR) sets the adjustment for the 32.768 kHz external crystal oscillator. The value placed in this register is based on factory testing. This register does not adjust the frequency of the external crystal oscillator. It is strongly recommended that the user not alter the register value. 12.4 12.4.1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access RW : 00 Bits 7 and 6: PSSDC[1:0]. These bits are used to set the sleep duty cycle. These bits should not be altered. For additional information, refer to the ECO_TR register on page 306. Timing Diagrams Sleep Sequence The Sleep bit, in the CPU_SCR0 register, is an input into the sleep logic circuit. This circuit is designed to sequence the device into and out of the hardware sleep state. The hardware sequence to put the device to sleep is shown in Figure 12-1 and is defined as follows. 1. Firmware sets the SLEEP bit in the CPU_SCR0 register. The Bus Request (BRQ) signal to the CPU is immediately asserted: This is a request by the system to halt CPU operation at an instruction boundary. 2. The CPU issues a Bus Request Acknowledge (BRA) on the following positive edge of the CPU clock. 3. The sleep logic waits for the following negative edge of the CPU clock and then asserts a system-wide Power Down (PD) signal. In Figure 12-1, the CPU is halted and the system-wide power down signal is asserted. The system-wide PD signal controls three major circuit blocks: the Flash memory module, the Internal Main Oscillator (24/48 MHz oscillator that is also called the IMO), and the bandgap voltage reference. These circuits transition into a zero power state. The only operational circuits on the PSoC device are the ILO (or optional ECO), the bandgap refresh circuit, and the supply voltage monitor circuit. Note that the system sleep state does not apply to the analog array. Power down settings for individual analog blocks and references must be done in firmware, prior to executing the sleep instruction. 104 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Sleep and Watchdog Figure 12-1. Sleep Sequence Firmware write to the SLEEP bit causes an immediate BRQ. CPU captures BRQ on next CPUCLK edge. CPU responds with a BRA. On the falling edge of CPUCLK, PD is asserted. The 24/48 MHz system clock is halted; the Flash and bandgap are powered down. CPUCLK IOW SLEEP BRQ BRA PD 12.4.2 Wakeup Sequence When asleep, the only event that can wake the system up is an interrupt. The Global Interrupt Enable of the CPU flag register does not need to be set. Any unmasked interrupt will wake the system up. It is optional for the CPU to actually take the interrupt after the wakeup sequence. The wakeup sequence is synchronized to the 32 kHz clock for purposes of sequencing a startup delay, to allow the Flash memory module enough time to power up before the CPU asserts the first read access. Another reason for the delay is to allow the IMO, bandgap, and LVD/POR circuits time to settle before actually being used in the system. As shown in Figure 12-2, the wake up sequence is as follows. 1. The wakeup interrupt occurs and is synchronized by the negative edge of the 32 kHz clock. 2. At the following positive edge of the 32 kHz clock, the system-wide PD signal is negated. The Flash memory module, IMO, and bandgap any POR/LVD circuits are all powered up to a normal operating state. 3. At the next positive edge of the 32 kHz clock, the values of the bandgap are settled and sampled. 4. At the following negative edge of the 32 kHz clock (after about 15 s, nominal). The values of the POR/LVD signals have settled and are sampled. The BRQ signal is negated by the sleep logic circuit. On the following CPU clock, BRA is negated by the CPU and instruction execution resumes. The wakeup times (interrupt to CPU operational) will range from two to three 32 kHz cycles or 61 to 92 s (nominal). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 105 Sleep and Watchdog Figure 12-2. Wakeup Sequence Sleep timer or GPIO interrupt occurs. Interrupt is double sampled by 32K clock and PD is negated to system. CPU is restarted after 75 s (nominal). CLK32K INT LVD/PPOR is valid SLEEP PD BANDGAP LVD/PPOR ENABLE POR/LVD/ BANDGAP SAMPLE BANDGAP SAMPLE LVD/POR CPUCLK/ 24 Mhz (Not to Scale) BRQ BRA CPU 106 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Sleep and Watchdog 12.4.3 Bandgap Refresh 12.4.4 During normal operation, the bandgap circuit provides a voltage reference (VRef) to the system, for use in the analog blocks, Flash, and low voltage detect (LVD) circuitry. Normally, the bandgap output is connected directly to the VRef signal. However, during sleep, the bandgap reference generator block and LVD circuits are completely powered down. The bandgap and LVD blocks are periodically re-enabled during sleep, to monitor for low voltage conditions. This is accomplished by turning on the bandgap periodically, allowing it time to start up for a full 32 kHz clock period, and connecting it to VRef to refresh the reference voltage for the following 32 kHz clock period as shown in Figure 12-3. During the second 32 kHz clock period of the refresh cycle, the LVD circuit is allowed to settle during the high time of the 32 kHz clock. During the low period of the second 32 kHz clock, the LVD interrupt is allowed to occur. Figure 12-3. Bandgap Refresh Operation Bandgap is turned on, but not yet connected to VRef. Bandgap output is connected to VRef. Voltage is refreshed. Bandgap is powered down until next refresh cycle. CLK32K Band Gap VRef VRef is slowly leaking to ground. Low voltage monitors are active during CLK32K low. Watchdog Timer On device boot up, the Watchdog Timer (WDT) is initially disabled. The PORS bit in the system control register controls the enabling of the WDT. On boot, the PORS bit is initially set to '1', indicating that either a POR or XRES event has occurred. The WDT is enabled by clearing the PORS bit. After this bit is cleared and the watchdog timer is enabled, it cannot be subsequently disabled. (The PORS bit cannot be set to '1' in firmware; it can only be cleared.) The only way to disable the Watchdog function, after it is enabled, is through a subsequent POR or XRES. Although the WDT is disabled during the first time through initialization code after a POR or XRES, all code should be written as if it is enabled (that is, the WDT should be cleared periodically). This is because, in the initialization code after a WDR event, the watchdog timer is enabled so all code must be aware of this. The watchdog timer is three counts of the sleep timer interrupt output. The watchdog interval is three times the selected sleep timer interval. The available selections for the watchdog interval are shown in Table 12-1. When the sleep timer interrupt is asserted, the watchdog timer increments. When the counter reaches three, a terminal count is asserted. This terminal count is registered by the 32 kHz clock. Therefore, the WDR (Watchdog Reset) signal will go high after the following edge of the 32 kHz clock and be held asserted for one cycle (30 s nominal). The flip-flop that registers the WDT terminal count is not reset by the WDR signal when it is asserted, but is reset by all other resets. This timing is shown in Figure 12-4. Figure 12-4. Watchdog Reset The rate at which the refresh occurs is related to the 32 kHz clock and controlled by the Power System Sleep Duty Cycle (PSSDC), bits [7:6] of the ECO_TR register). Table 12-4 enumerates the available selections. The default setting (256 sleep timer counts) is applicable for many applications, giving a typical average device current under 5 A. CLK32K SLEEP INT WD COUNT 2 3 0 WD RESET (WDR) Table 12-4. Power System Sleep Duty Cycle Selections PSSDC Sleep Timer Counts Period (Nominal) 00b (default) 256 8 ms 01b 1024 31.2 ms 10b 64 2 ms 11b 16 500 s When enabled, the WDT must be periodically cleared in firmware. This is accomplished with a write to the RES_WDT register. This write is data independent, so any write will clear the watchdog timer. (Note that a write of 38h will also clear the sleep timer.) If for any reason the firmware fails to clear the WDT within the selected interval, the circuit will assert WDR to the device. WDR is equivalent in effect to any other reset. All internal registers are set to their reset state, see the table titled “Details of Functionality for Various Resets” on page 518. An important aspect to remember about WDT resets is that RAM initialization can be disabled (IRAMDIS in the CPU_SCR1 register). In this case, the SRAM contents are unaffected; so that when a WDR occurs, program variables are persistent through this reset. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 107 Sleep and Watchdog In practical application, it is important to know that the watchdog timer interval can be anywhere between two and three times the sleep timer interval. The only way to guarantee that the WDT interval is a full three times that of the sleep interval is to clear the sleep timer (write 38h) when clearing the WDT register. However, this is not possible in applications that use the sleep timer as a real-time clock. In the case where firmware clears the WDT register without clearing the sleep timer, this can occur at any point in a given sleep timer interval. If it occurs just before the terminal count of a sleep timer interval, the resulting WDT interval will be just over two times that of the sleep timer interval. 12.5 Power Consumption Sleep mode power consumption consists of the items in the following tables. In Table 12-5, the typical block currents shown do not represent maximums. These currents do not include any analog block currents that may be on during Sleep mode. Table 12-5. Continuous Currents IPOR 1 A ICLK32K (ILO/ECO) 1 A While the CLK32K can be turned off in Sleep mode, this mode is not useful because it makes it impossible to restart unless an imprecise power on reset (IPOR) occurs. (The Sleep bit can not be cleared without CLK32K.) During the sleep mode buzz, the bandgap is on for two cycles and the LVD circuitry is on for one cycle. Time-averaged currents from periodic sleep mode ‘buzz’, with periodic count of N, are listed in Table 12-6. Table 12-6. Time-Averaged Currents IBG (Bandgap) (2/N) * 60 A ILVD (LVD comparators) (2/N) * 50 A Table 12-7 lists example currents for N=256 and N=1024. Device leakage currents add to the totals in the table. Table 12-7. Example Currents N = 256 N = 1024 IPOR 1 1 CLK32K 1 1 IBG 0.46 0.12 ILVD 0.4 0.1 Total 2.9 A 2.2 A 108 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Section C: Register Reference The Register Reference section discusses the registers of the PSoC® device. It lists all the registers in mapping tables, in address order. For easy reference, each register is linked to the page of a detailed description located in the next chapter. This section encompasses the following chapter: ■ Register Details on page 125 Register General Conventions Register Mapping Tables The register conventions specific to this section and the Register Details chapter are listed in the following table. The PSoC device has a total register address space of 512 bytes. The register space is also referred to as I/O space and is broken into two parts. The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set, the user is said to be in the “extended” address space or the “configuration” registers. Register Conventions Convention Description Empty, grayed-out table cell Illustrates a reserved bit or group of bits. ‘x’ before the comma in an address Indicates the register exists in register bank 1 and register bank 2. ‘x’ in a register name Indicates that there are multiple instances/address ranges of the same register. R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Refer to the individual PSoC device data sheets for devicespecific register mapping information. Register Naming Conventions The register naming convention specific to this section for arrays of PSoC blocks and their registers is: <Prefix>mn<Suffix> where m = row index, n = column index Therefore, ASD13CR3 is a register for an analog PSoC block in row 1 column 3. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 109 CY8C28x03 Register Maps Register Map Bank 0 Table: User Space IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 171 172 173 174 175 176 177 178 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F CPU_SCR1 CPU_SCR0 Page CUR_PP STK_PP Access 153 154 155 155 155 155 MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) RW RW RW RW RW RW 197 Name RW 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Page SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 Access I2C1_DR # W RW # # W RW # # W RW # # W RW # Addr (0,Hex) 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Page 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (0,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 DCC13CR0 Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW 189 190 RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # 191 192 193 194 195 197 198 199 201 203 204 206 207 208 209 210 211 195 198 W W R R RW RW RW RW 171 172 173 174 175 176 177 178 RL 214 # # 216 217 Gray fields are reserved. # Access is bit specific. 110 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Register Map Bank 1 Table: Configuration Space RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU RW RW RW RW RW RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 271 272 273 274 275 276 277 278 279 280 281 282 283 284 284 285 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR BDG_TR ECO_TR CPU_F FLS_PR1 CPU_SCR1 CPU_SCR0 Page 247 248 259 260 Access RW RW RW RW Addr (1,Hex) 194 155 155 155 155 GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name RW RW RW RW RW SADC_TSCMPL SADC_TSCMPH Page SADC_TSCR0 SADC_TSCR1 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 Access I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name Gray fields are reserved. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Page 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW RW RW 286 287 288 289 RW RW RW RW RW RW RW R 293 294 295 296 297 298 299 300 RW RW RW RW 303 304 305 306 I 214 RW 308 # # 216 217 # Access is bit specific. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 111 CY8C28x13 Register Maps Register Map Bank 0 Table: User Space 171 172 173 174 175 176 177 178 179 180 181 182 184 186 187 188 179 180 181 182 184 RDI1RO0 RDI1RO1 RDI1DSM BD BE BF RW RW RW 186 187 188 Page W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access 153 154 155 155 155 155 MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 DEC0_DH DEC0_DL DEC1_DH DEC1_DL Addr (0,Hex) RW RW RW RW RW RW 146 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW 189 190 RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W 191 192 193 194 195 197 198 199 201 203 204 206 207 208 209 210 211 RW RW W W R R RW RW RW RW 212 213 171 172 173 174 175 176 177 178 RL 214 DAC1_D0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC RW 215 DAC0_D1 CPU_SCR1 CPU_SCR0 FD FE FF RW # # 215 216 217 Name 7D 7E 7F RW Page 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 Access 132 133 134 # W RW # # W RW # # W RW # # W RW # Addr (0,Hex) W RW # 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C Name 3D 3E 3F SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Page DCC13DR1 DCC13DR2 DCC13CR0 AMUX_CFG Access Page 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # Name Addr (0,Hex) 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 Name RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM CUR_PP STK_PP RC RC RC RC 169 170 169 170 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F Gray fields are reserved. # Access is bit specific. 0Corresponds to right port. 1Corresponds to left port. 112 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Register Map Bank 1 Table: Configuration Space ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE00CR1 ACE00CR2 ASE10CR0 DEC0_CR0 DEC_CR3 DEC1_CR0 DEC_CR5 RW 246 RW RW RW RW 155 155 155 155 RW RW RW 247 248 249 RW RW RW 250 251 252 RW RW RW 253 254 255 RW RW RW 256 257 258 GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW RW 262 263 263 RW RW RW 264 265 266 RW RW RW 256 257 258 RW RW 267 268 RW 267 RW 270 RW RW RW RW RW RW RW RW RW RW RW RW # RW 271 272 273 274 275 276 277 278 279 280 281 282 283 284 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 285 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_ CR DEC1_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_MODE IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 CPU_F FLS_PR1 IDAC_CR0 CPU_SCR1 CPU_SCR0 Page ACE_CMP_CR0 ACE_CMP_CR1 ACE01CR1 ACE01CR2 ASE11CR0 259 260 261 Access ACE_AMX_IN ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 RW RW RW Addr (1,Hex) ACE_AMD_CR0 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name SADC_TSCR0 SADC_TSCR1 SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Page TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 Access AMUX_CFG1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name Gray fields are reserved. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Page 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW RW RW RW RW 286 287 288 289 290 290 RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW 291 291 291 291 292 293 294 295 296 297 298 299 300 301 301 302 303 304 305 306 291 291 RL 214 RW 308 RW # # 309 216 217 # Access is bit specific. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 113 CY8C28x23 Register Maps Register Map Bank 0 Table: User Space 155 155 155 155 156 157 159 160 156 157 159 160 DEC0_DH DEC0_DL DEC1_DH DEC1_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM RW RW RW RW RW RW RW RW 165 166 167 168 161 162 163 164 CUR_PP STK_PP RC RC RC RC 169 170 169 170 W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 171 172 173 174 175 176 177 178 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F CPU_SCR1 CPU_SCR0 Page RW RW RW RW RW RW RW RW RW RW RW RW 145 146 147 148 149 150 151 197 161 162 163 164 165 166 167 168 Access RW RW RW RW # # RW RW RW RW RW RW RW RW RW RW Addr (0,Hex) ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACC00CR3 ACC00CR0 ACC00CR1 ACC00CR2 ACC01CR3 ACC01CR0 ACC01CR1 ACC01CR2 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Page AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 Access 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 # W RW # # W RW # # W RW # # W RW # Addr (0,Hex) # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Page 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (0,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 DCC13CR0 Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW 189 190 RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW 191 192 193 194 195 197 198 199 201 203 204 206 207 208 209 210 211 195 198 212 213 171 172 173 174 175 176 177 178 I 214 # # 216 217 Gray fields are reserved. # Access is bit specific. 114 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Register Map Bank 1 Table: Configuration Space 236 237 238 239 240 RW RW 242 243 RW 245 RW RW RW RW RW 194 155 155 155 155 GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM 267 268 RW 267 RW 270 RW RW RW RW RW RW RW RW 271 272 273 274 275 276 277 278 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_ CR DEC1_CR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR BDG_TR ECO_TR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 284 284 285 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 CPU_F FLS_PR1 CPU_SCR1 CPU_SCR0 Page RW RW RW RW RW RW RW Access DEC_CR5 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 DEC1_CR0 Name CLK_CR2 DEC0_CR0 DEC_CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Page AMD_CR1 ALT_CR0 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 Access CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name Gray fields are reserved. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Page 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW RW RW RW RW 286 287 288 289 290 290 RW RW RW RW RW RW RW R 293 294 295 296 297 298 299 300 RW RW RW RW 303 304 305 306 RL 214 RW 308 # # 216 217 # Access is bit specific. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 115 CY8C28x33 Register Maps Register Map Bank 0 Table: User Space 145 146 147 148 149 150 151 RW RW RW RW RW RW RW RW RW RW RW RW RW RW 153 154 155 155 155 155 156 157 159 160 156 157 159 160 Page RW RW RW RW # # RW Access 161 162 163 164 165 166 167 168 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM RW RW RW RW RW RW RW RW 165 166 167 168 161 162 163 164 CUR_PP STK_PP RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 169 170 169 170 169 170 169 170 171 172 173 174 175 176 177 178 179 180 181 182 184 186 187 188 179 180 181 182 184 RDI1RO0 RDI1RO1 RDI1DSM BD BE BF RW RW RW 186 187 188 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Addr (0,Hex) 7D 7E 7F RW RW RW RW RW RW RW RW DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW 189 190 RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W 191 192 193 194 195 197 198 199 201 203 204 206 207 208 209 210 211 RW RW W W R R RW RW RW RW 212 213 171 172 173 174 175 176 177 178 I 214 DAC1_D0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC RW 215 DAC0_D1 CPU_SCR1 CPU_SCR0 FD FE FF RW # # 215 216 217 Name 132 133 134 Page W RW # 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 Access 3D 3E 3F # W RW # # W RW # # W RW # # W RW # Addr (0,Hex) DCC13DR1 DCC13DR2 DCC13CR0 SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACC00CR3 ACC00CR0 ACC00CR1 ACC00CR2 ACC01CR3 ACC01CR0 ACC01CR1 ACC01CR2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C Name AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 Page 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 Access Page # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # Addr (0,Hex) Access DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Name Addr (0,Hex) 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 Name RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F Gray fields are reserved. # Access is bit specific. 0Corresponds to right port. 1Corresponds to left port. 116 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Register Map Bank 1 Table: Configuration Space ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE00CR1 ACE00CR2 ASE10CR0 DEC0_CR0 DEC_CR3 DEC1_CR0 DEC_CR4 DEC2_CR0 DEC_CR5 DEC3_CR0 RW RW RW RW RW 236 237 238 239 240 RW RW 242 243 RW RW 245 246 RW RW RW RW 155 155 155 155 RW RW RW 247 248 249 RW RW RW 250 251 252 RW RW RW 253 254 255 RW RW RW 256 257 258 GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW RW 262 263 263 RW RW RW 264 265 266 RW RW RW 256 257 258 RW RW 267 268 RW RW 267 269 RW RW 267 270 RW 267 RW RW RW RW RW RW RW RW RW RW RW RW # RW 271 272 273 274 275 276 277 278 279 280 281 282 283 284 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 285 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_ CR DEC1_CR DEC2 CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_MODE IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 CPU_F FLS_PR1 IDAC_CR0 CPU_SCR1 CPU_SCR0 Page ACE_AMD_CR0 ACE01CR1 ACE01CR2 ASE11CR0 259 260 261 Access SADC_TSCR0 SADC_TSCR1 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 RW RW RW Addr (1,Hex) TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name CLK_CR2 AMUX_CFG1 SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Page AMD_CR1 ALT_CR0 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 Access CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name Gray fields are reserved. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Page 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW 286 287 288 289 290 290 290 290 291 291 291 291 292 293 294 295 296 297 298 299 300 301 301 302 303 304 305 306 291 291 RL 214 RW 308 RW # # 309 216 217 # Access is bit specific. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 117 CY8C28x43 Register Maps Register Map Bank 0 Table: User Space RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F CPU_SCR1 CPU_SCR0 Page 153 154 155 155 155 155 156 157 159 160 156 157 159 160 156 157 159 160 156 157 159 160 161 162 163 164 165 166 167 168 161 162 163 164 165 166 167 168 165 166 167 168 161 162 163 164 165 166 167 168 161 162 163 164 169 170 169 170 169 170 169 170 171 172 173 174 175 176 177 178 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (0,Hex) 145 146 147 148 149 150 151 197 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACC00CR3 ACC00CR0 ACC00CR1 ACC00CR2 ACC01CR3 ACC01CR0 ACC01CR1 ACC01CR2 ACC02CR3 ACC02CR0 ACC02CR1 ACC02CR2 ACC03CR3 ACC03CR0 ACC03CR1 ACC03CR2 RW RW RW RW # # RW RW ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM Page AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 Access 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 # W RW # # W RW # # W RW # # W RW # Addr (0,Hex) # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Page 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (0,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 DCC13CR0 Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW 189 190 RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW 191 192 193 194 195 197 198 199 201 203 204 206 207 208 209 210 211 195 198 212 213 171 172 173 174 175 176 177 178 I 214 # # 216 217 Gray fields are reserved. # Access is bit specific. 118 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Register Map Bank 1 Table: Configuration Space DEC3_CR0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 236 237 238 239 240 241 242 243 244 245 246 194 155 155 155 155 RW RW 247 248 GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW 267 268 RW RW 267 269 RW RW 267 270 RW 267 RW RW RW RW RW RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 271 272 273 274 275 276 277 278 279 280 281 282 283 284 284 285 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_ CR DEC1_CR DEC2 CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 CPU_F FLS_PR1 CPU_SCR1 CPU_SCR0 Page DEC2_CR0 DEC_CR5 259 260 Access DEC1_CR0 DEC_CR4 RW RW Addr (1,Hex) DEC0_CR0 DEC_CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name SADC_TSCMPL SADC_TSCMPH Page SADC_TSCR0 SADC_TSCR1 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 Access CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name Gray fields are reserved. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Page 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW RW RW RW RW RW RW RW RW RW RW 286 287 288 289 290 290 290 290 291 291 291 291 RW RW RW RW RW RW RW R 293 294 295 296 297 298 299 300 RW RW RW RW RW RW 303 304 305 306 291 291 RL 214 RW 308 # # 216 217 # Access is bit specific. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 119 CY8C28x45 Register Maps Register Map Bank 0 Table: User Space W RW # 132 133 134 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 161 162 163 164 165 166 167 168 161 162 163 164 165 166 167 168 165 166 167 168 161 162 163 164 165 166 167 168 161 162 163 164 169 170 169 170 169 170 169 170 171 172 173 174 175 176 177 178 179 180 181 182 184 186 187 188 179 180 181 182 184 RW RW RW RW # # RW RW 145 146 147 148 149 150 151 197 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACC03CR0 ACC03CR1 ACC03CR2 7D 7E 7F RW RW RW 157 159 160 RDI1RO0 RDI1RO1 RDI1DSM BD BE BF RW RW RW 186 187 188 Page 3D 3E 3F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC Access DCC13DR1 DCC13DR2 DCC13CR0 153 154 155 155 155 155 156 157 159 160 156 157 159 160 156 157 159 160 156 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 Addr (0,Hex) 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW 189 190 RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW 191 192 193 194 195 197 198 199 201 203 204 206 207 208 209 210 211 195 198 212 213 171 172 173 174 175 176 177 178 I 214 DAC1_D0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC RW 215 DAC0_D1 CPU_SCR1 CPU_SCR0 FD FE FF RW # # 215 216 217 Name AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Page 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # Addr (0,Hex) Page # W RW # # W RW # # W RW # # W RW # SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACC00CR3 ACC00CR0 ACC00CR1 ACC00CR2 ACC01CR3 ACC01CR0 ACC01CR1 ACC01CR2 ACC02CR3 ACC02CR0 ACC02CR1 ACC02CR2 ACC03CR3 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C Name Access Page Addr (0,Hex) Access DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Name Addr (0,Hex) 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 Name RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F Gray fields are reserved. # Access is bit specific. 0Corresponds to right port. 1Corresponds to left port. 120 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Register Map Bank 1 Table: Configuration Space ACE_ALT_CR0 ACE_ABF_CR0 ACE00CR1 ACE00CR2 ASE10CR0 DEC0_CR0 DEC_CR3 DEC1_CR0 DEC_CR4 DEC2_CR0 DEC_CR5 DEC3_CR0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 236 237 238 239 240 241 242 243 244 245 246 194 155 155 155 155 RW RW RW 247 248 249 RW RW RW 250 251 252 RW RW RW 253 254 255 RW RW RW 256 257 258 GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW RW 262 263 263 RW RW RW 264 265 266 RW RW RW 256 257 258 RW RW 267 268 RW RW 267 269 RW RW 267 270 RW 267 RW RW RW RW RW RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 271 272 273 274 275 276 277 278 279 280 281 282 283 284 284 285 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_ CR DEC1_CR DEC2 CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_MODE IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 IMO_TR1 CPU_F FLS_PR1 IDAC_CR0 CPU_SCR1 CPU_SCR0 Page ACE_CMP_GI_EN ACE01CR1 ACE01CR2 ASE11CR0 259 260 261 Access ACE_CMP_CR0 ACE_CMP_CR1 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 RW RW RW Addr (1,Hex) ACE_AMX_IN ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name ACE_AMD_CR0 SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Page SADC_TSCR0 SADC_TSCR1 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 Access CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name Gray fields are reserved. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Page 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW 286 287 288 289 290 290 290 290 291 291 291 291 292 293 294 295 296 297 298 299 300 301 301 302 303 304 305 306 291 291 RW 291 RL 214 RW 308 RW # # 309 216 217 # Access is bit specific. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 121 CY8C28x52 Register Maps Register Map Bank 0 Table: User Space 157 159 160 RDI1RO0 RDI1RO1 RDI1DSM BD BE BF RW RW RW 186 187 188 DAC0_D1 CPU_SCR1 CPU_SCR0 FD FE FF AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 RW RW RW RW # # RW 145 146 147 148 149 150 151 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACC00CR3 ACC00CR0 ACC00CR1 ACC00CR2 ACC01CR3 ACC01CR0 ACC01CR1 ACC01CR2 ACC02CR3 ACC02CR0 ACC02CR1 ACC02CR2 ACC03CR3 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACC03CR0 ACC03CR1 ACC03CR2 7D 7E 7F RW RW RW CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F Page DAC1_D0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC Access 161 162 163 164 165 166 167 168 161 162 163 164 165 166 167 168 165 166 167 168 161 162 163 164 165 166 167 168 161 162 163 164 169 170 169 170 169 170 169 170 171 172 173 174 175 176 177 178 179 180 181 182 184 186 187 188 179 180 181 182 184 Addr (0,Hex) Page RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Access 132 133 134 Addr (0,Hex) W RW # 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 Name 3D 3E 3F 155 155 155 155 156 157 159 160 156 157 159 160 156 157 159 160 156 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 Page DCC13DR1 DCC13DR2 DCC13CR0 Access Page 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 132 133 134 131 Addr (0,Hex) Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # Name Addr (0,Hex) 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 127 128 129 130 Name RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 RW RW 189 190 RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W 191 192 193 194 195 197 198 199 201 203 204 206 207 208 209 210 211 RW RW W W R R RW RW RW RW 212 213 171 172 173 174 175 176 177 178 I 214 RW 215 RW # # 215 216 217 Gray fields are reserved. # Access is bit specific. 0Corresponds to right port. 1Corresponds to left port. 122 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Register Map Bank 1 Table: Configuration Space ACE_ALT_CR0 ACE_ABF_CR0 ACE00CR1 ACE00CR2 ASE10CR0 DEC0_CR0 DEC_CR3 DEC1_CR0 DEC_CR4 DEC2_CR0 DEC_CR5 DEC3_CR0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 236 237 238 239 240 241 242 243 244 245 246 194 155 155 155 155 RW RW RW 247 248 249 RW RW RW 250 251 252 RW RW RW 253 254 255 RW RW RW 256 257 258 GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW RW 262 263 263 RW RW RW 264 265 266 RW RW RW 256 257 258 RW RW 267 268 RW RW 267 269 RW RW 267 270 RW 267 RW RW RW RW RW RW RW RW RW RW RW RW # RW 271 272 273 274 275 276 277 278 279 280 281 282 283 284 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 285 179 180 181 182 184 186 187 188 179 180 181 182 184 186 187 188 RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_ CR DEC1_CR DEC2 CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_MODE IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 CPU_F FLS_PR1 IDAC_CR0 CPU_SCR1 CPU_SCR0 Page ACE_CMP_GI_EN ACE01CR1 ACE01CR2 ASE11CR0 259 260 261 Access ACE_CMP_CR0 ACE_CMP_CR1 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 RW RW RW Addr (1,Hex) ACE_AMX_IN ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name ACE_AMD_CR0 SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Page SADC_TSCR0 SADC_TSCR1 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 Access CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 222 224 226 228 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name Gray fields are reserved. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Page 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 218 219 220 221 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) Page 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Name Access DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW 179 180 181 182 184 186 187 188 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW 286 287 288 289 290 290 290 290 291 291 291 291 292 293 294 295 296 297 298 299 300 301 301 302 303 304 305 306 291 291 RL 214 RW 308 RW # # 309 216 217 # Access is bit specific. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 123 124 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 13. Register Details This chapter is a reference for all the PSoC® device registers in address order, for Bank 0 and Bank 1. The most detailed descriptions of the PSoC registers are in the Register Definitions section of each chapter. The registers that are in both banks are incorporated with the Bank 0 registers, designated with an ‘x’, rather than a ‘0’ preceding the comma in the address. Bank 0 registers are listed first and begin on page 127. Bank 1 registers are listed second and begin on page 218. A condensed view of all the registers is shown in the “Register Map Bank 0 Table: User Space” on page 120 and the “Register Map Bank 1 Table: Configuration Space” on page 121. 13.1 Maneuvering Around the Registers For ease-of-use, this chapter has been formatted so that there is one register per page, although some registers use two pages. On each page, from top to bottom, there are four sections: 1. Register name and address (from lowest to highest). 2. Register table showing the bit organization, with reserved bits grayed out. 3. Written description of register specifics or links to additional register information. 4. Detailed register bit descriptions. Note that some registers are directly related to the digital and analog functions; therefore, these registers might have more than one register table (number 2 above). This is due to the fact that the PSoC devices have different digital row and analog column characteristics which use different bits in the same register. To find out the number of digital rows and analog columns your PSoC device has, refer to the following table. Digital I/O Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Regular Analog Blocks Limited Analog Blocks CY8C28xxx Device Characteristics CY8C28403 24 3 12 8 0 0 0 0 CY8C28413 24 3 12 24 0 0 0 4 CY8C28513 40 3 12 40 0 0 0 4 CY8C28623 44 3 12 10 2 2 6 0 CY8C28433 24 3 12 24 2 2 6 4 CY8C28533 40 3 12 40 2 2 6 4 CY8C28243 16 3 12 16 4 4 12 0 CY8C28643 44 3 12 44 4 4 12 0 CY8C28445 24 3 12 24 4 4 12 4 CY8C28545 40 3 12 40 4 4 12 4 CY8C28645 44 3 12 44 4 4 12 4 CY8C28452 24 2 8 24 4 4 12 4 CY8C28xxx Part Number CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 125 Register Details Use the register tables, in addition to the detailed register bit descriptions, to determine which bits are reserved for some smaller PSoC devices. Reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. Register Conventions The following table lists the register conventions that are specific to this chapter. Register Conventions Convention Example Description ‘x’ in a register name ACCxxCR1 Multiple instances/address ranges of the same register R R : 00 Read register or bit(s) W W : 00 Write register or bit(s) L RL : 00 Logical register or bit(s) C RC : 00 Clearable register or bit(s) 00 RW : 00 Reset value is 0x00 or 00h XX RW : XX Register is not reset 0, 0,04h Register is in bank 0 1, 1,23h Register is in bank 1 x, x,F7h Register exists in register bank 0 and register bank 1 2L 2L Column Register bit table designation for PSoC devices with two column limited functionality Empty, grayed-out table cell 13.1.1 Reserved bit or group of bits, unless otherwise stated Register Naming Conventions There are a few register naming conventions used in this manual to abbreviate repetitious register information by using a lower case ‘x’ in the register name. The convention to interpret these register names is as follows. ■ For all registers, an ‘x’ before the comma in the address field indicates that the register can be accessed or written to no matter what bank is used. For example, the M8C flag register’s (CPU_F) address is ‘x,F7h’ meaning it is located in bank 0 and bank 1 at F7h. ■ For digital block registers, the first ‘x’ in some register names represents either “B” for basic or “C” for communication. For rows of digital PSoC blocks and their registers, the second ‘x’ set represents <Prefix>mn<Suffix>, where m = row index, n = column index. Therefore, DCC32CR0 (written DxCxxCR0) is a digital communication register for a digital PSoC block in row 3 column 2. ■ For digital row registers, the ‘x’ in the digital register’s name represents the digital row index. For example, if the RDIxIS register name encompasses four registers, there is one for each digital row index and unique address (RDI0IS, RDI1IS, RDI2IS, and RDI3IS). ■ For analog column registers, the naming convention for the switched capacitor and continuous time registers and their arrays of PSoC blocks is <Prefix>mn<Suffix>, where m = row index, n = column index. Therefore, ASC21CR2 (written ASCxxCR2) is a register for an analog PSoC block in row 2 column 1 126 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Register Details 13.2 Bank 0 Registers The following registers are all in bank 0 and are listed in address order. An ‘x’ before the comma in the register’s address indicates that the register can be accessed independent of the XIO bit in the CPU_F register. Registers that are in both Bank 0 and Bank 1 are listed in address order in Bank 0. For example, the RDIxLT1 register has an address of x,B4h and is in both Bank 0 and Bank 1. 13.2.1 PRTxDR Port Data Register Individual Register Names and Addresses: PRT0DR : 0,00h PRT4DR : 0,10h 0,00h PRT1DR : 0,04h PRT5DR : 0,14h 7 6 PRT2DR : 0,08h 5 4 PRT3DR : 0,0Ch 3 Access : POR RW : 00 Bit Name Data[7:0] 2 1 0 This register allows for write or read access of the current logical equivalent of the voltage on the pin. For Port 5, the upper nibble of this register returns the last data bus value when read and should be masked off prior to using this information. Note For devices with less than 5 ports, the extra registers can be used as temp registers. For additional information, refer to the “Register Definitions” on page 76 in the GPIO chapter. Bit Name Description 7:0 Data[7:0] Write value to port or read value from port. Reads return the state of the pin, not the value in the PRTxDR register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 127 PRTxIE 0,01h 13.2.2 PRTxIE Port Interrupt Enable Register Individual Register Names and Addresses: PRT0IE : 0,01h PRT4IE : 0,11h 0,01h PRT1IE : 0,05h PRT5IE : 0,15h 7 6 PRT2IE : 0,09h 5 4 PRT3IE : 0,0Dh 3 2 1 0 RW : 00 Access : POR Interrupt Enables[7:0] Bit Name This register is used to enable or disable the interrupt enable internal to the GPIO block. For Port 5, the upper nibble of this register returns the last data bus value when read and should be masked off prior to using this information. For additional information, refer to the “Register Definitions” on page 76 in the GPIO chapter. Bit Name Description 7:0 Interrupt Enables[7:0] A bit set in this register will enable the corresponding port pin interrupt. 0 Port pin interrupt disabled for the corresponding pin. 1 Port pin interrupt enabled for the corresponding pin. 128 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F PRTxGS 0,02h 13.2.3 PRTxGS Port Global Select Register Individual Register Names and Addresses: PRT0GS : 0,02h PRT4GS : 0,12h 0,02h PRT1GS : 0,06h PRT5GS : 0,16h 7 6 PRT2GS : 0,0Ah 5 4 PRT3GS : 0,0Eh 3 2 1 0 RW : 00 Access : POR Global Select[7:0] Bit Name This register is used to select the block for connection to global inputs or outputs. For Port 5, the upper nibble of this register returns the last data bus value when read and should be masked off prior to using this information. For additional information, refer to the “Register Definitions” on page 76 in the GPIO chapter. Bit Name Description 7:0 Global Select[7:0] A bit set in this register connects the corresponding port pin to an internal global bus. This connection is used to input or output digital signals to or from the digital blocks. 0 Global function disabled. The pin value is determined by the PRTxDR bit value and port configuration registers. 1 Global function enabled. Direction depends on mode bits for the pin (registers PRTxDM0, PRTxDM1, and PRTxDM2). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 129 PRTxDM2 0,03h 13.2.4 PRTxDM2 Port Drive Mode Bit 2 Register Individual Register Names and Addresses: PRT0DM2 : 0,03h PRT4DM2 : 0,13h 0,03h PRT1DM2 : 0,07h PRT5DM2 : 0,17h 7 6 PRT2DM2 : 0,0Bh 5 4 PRT3DM2 : 0,0Fh 3 2 1 0 RW : FFh Access : POR Drive Mode 2[7:0] Bit Name This register is one of three registers whose combined value determines the unique Drive mode of each bit in a GPIO port. In this register, there are eight possible drive modes for each port pin. Three mode bits are required to select one of these modes, and these three bits are spread into three different registers (the PRTxDM0 register on page 218, the PRTxDM1 register on page 219, and the PRTxDM2 register). The bit position of the affected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the three drive mode register bits that control the Drive mode for that pin (for example: PRT0DM0[2], PRT0DM1[2], and PRT0DM2[2]). The three bits from the three registers are treated as a group. These are referred to as DM2, DM1, and DM0, or together as DM[2:0]. All Drive mode bits are shown in the sub-table below ([210] refers to the combination (in order) of bits in a given bit position); however, this register only controls the most significant bit (MSb) of the Drive mode. For Port 5, the upper nibble of this register returns the last data bus value when read and should be masked off prior to using this information. For additional information, refer to the “Register Definitions” on page 76 in the GPIO chapter. Bit Name Description 7:0 Drive Mode 2[7:0] Bit 2 of the Drive mode, for each pin of an 8-bit GPIO port. [210] 000b 001b 010b 011b 100b 101b 110b Pin Output High Strong Strong High-Z Resistive Slow + strong Slow + strong High-Z Pin Output Low Resistive Strong High-Z Strong High-Z Slow + strong High-Z 111b High-Z Slow + strong Notes Digital input enabled. Reset state. Digital input disabled for zero power. I2C Compatible mode. Note A bold digit, in the table, signifies that the digit is used in this register. 130 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxDR0 0,20h 13.2.5 DxCxxDR0 Digital Basic/Communication Type C Block Data Register 0 Individual Register Names and Addresses: DBC00DR0 : 0,20h DBC10DR0 : 0,30h DBC20DR0 : 0,40h 0,20h DBC01DR0 : 0,24h DBC11DR0 : 0,34h DBC21DR0 : 0,44h 7 6 DCC02DR0 : 0,28h DCC12DR0 : 0,38h DCC22DR0 : 0,48h 5 4 DCC03DR0 : 0,2Ch DCC13DR0 : 0,3Ch DCC23DR0 : 0,4Ch 3 2 1 0 R : 00 Access : POR Data[7:0] Bit Name This register is the data register for a digital block. The use of this register is dependent on which function is selected for its block. This selection is made in the FN[2:0] bits of the DxCxxFN register on page 222. (For the Timer, Counter, Dead Band, CRCPRS, PWMDBL, and DSM functions, a read of the DxCxxDR0 register returns 00h and transfers DxCxxDR0 to DxCxxDR2.) The naming convention for the digital basic/communication and control registers is as follows. The first ‘x’ in the digital register’s name represents either “B” for basic or “C” for communication. For rows of digital PSoC blocks and their registers, the second ‘x’ set represents <Prefix>mn<Suffix>, where m=row index, n=column index. Therefore, DBC21DR0 is a digital basic register for a digital PSoC block in row 2 column 1. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:0 Data[7:0] Data for selected function. Block Function Timer Counter Dead Band PWMDBL CRCPRS SPIM SPIS TXUART RXUART DSM Register Function Count Value Count Value Count Value Count Value LFSR * Shifter Shifter Shifter Shifter Difference DCC Only No No No No No Yes Yes Yes Yes Yes * Linear Feedback Shift Register (LFSR) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 131 DxCxxDR1 0,21h 13.2.6 DxCxxDR1 Digital Basic/Communication Type C Block Data Register 1 Individual Register Names and Addresses: DBC00DR1 : 0,21h DBC10DR1 : 0,31h DBC20DR1 : 0,41h 0,21h DBC01DR1 : 0,25h DBC11DR1 : 0,35h DBC21DR1 : 0,45h 7 6 DCC02DR1 : 0,29h DCC12DR1 : 0,39h DCC22DR1 : 0,49h 5 4 3 DCC03DR1 : 0,2Dh DCC13DR1 : 0,3Dh DCC23DR1 : 0,4Dh 2 1 0 W : 00 Access : POR Data[7:0] Bit Name This register is the data register for a digital block. The use of this register is dependent on which function is selected for its block. This selection is made in the FN[2:0] bits of the DxCxxFN register on page 222. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:0 Data[7:0] Data for selected function. Block Function Timer Counter Dead Band PWMDBL CRCPRS SPIM SPIS TXUART RXUART DSM 132 Register Function Period Period Period Period Polynomial TX Buffer TX Buffer TX Buffer Not applicable Initial Phase DCC Only No No No No No Yes Yes Yes Yes Yes CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxDR2 0,22h 13.2.7 DxCxxDR2 Digital Basic/Communication Type C Block Data Register 2 Individual Register Names and Addresses: DBC00DR2 : 0,22h DBC10DR2 : 0,32h DBC20DR2 : 0,42h 0,22h DBC01DR2 : 0,26h DBC11DR2 : 0,36h DBC21DR2 : 0,46h 7 6 DCC02DR2 : 0,2Ah DCC12DR2 : 0,3Ah DCC22DR2 : 0,4Ah 5 4 DCC03DR2 : 0,2Eh DCC13DR2 : 0,3Eh DCC23DR2 : 0,4Eh 3 Access : POR RW : 00 Bit Name Data[7:0] 2 1 0 This register is the data register for a digital block. The use of this register is dependent on which function is selected for its block. This selection is made in the FN[2:0] bits of the DxCxxFN register on page 222. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. * If the block is configured as SPIM, SPIS, or RXUART, this register is read only. Bit Name 7:0 Data[7:0] Description Data for selected function. Block Function Timer Counter Dead Band PMWDBL CRCPRS SPIM SPIS TXUART RXUART DMS Register Function Capture/Compare Compare Buffer Compare Seed/Residue RX Buffer RX Buffer Not applicable RX Buffer Density Value DCC Only No No No No No Yes Yes Yes Yes Yes CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 133 DxCxxCR0 (Timer Control:000) 0,23h 13.2.8 DxCxxCR0 (Timer Control:000) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DBC00CR0 : 0,23h DBC10CR0 : 0,33h DBC20CR0 : 0,43h 0,23h DBC01CR0 : 0,27h DBC11CR0 : 0,37h DBC21CR0 : 0,47h 7 6 Access : POR Bit Name DCC02CR0 : 0,2Bh DCC12CR0 : 0,3Bh DCC22CR0 : 0,4Bh 5 4 3 DCC03CR0 : 0,2Fh DCC13CR0 : 0,3Fh DCC23CR0 : 0,4Fh 2 1 0 RW : 0000 RW : 0 RW : 0 RW : 0 RW : 0 KILL[3:0] NPS TC Pulse Width Capture Int Enable This register is the Control register for a timer, if the DxCxxFN register is configured as a ‘000’. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 KILL[3:0] Select signal for kill function 0000b Low 0001b High 0010b BC 0011b VC3 0100b RI[0] 0101b RI[1] 0110b RI[2] 0111b RI[3] 1000b RO[0] 1001b RO[1] 1010b RO[2] 1011b RO[3] 1100b ACMP[0] 1101b ACMP[1] 1110b ACMP[2] 1111b ACMP[3] 3 NPS Negative phase selection. The comparison output will be updated only when block clock is 0. 2 TC Pulse Width Primary output 0 Terminal Count pulse width is one-half a block clock. Supports a period value of 00h. 1 Terminal Count pulse width is one full block clock. 1 Capture Int 0 1 Interrupt is selected with Mode bit 0 in the Function (DxCxxFN) register. Block interrupt is caused by a hardware capture event (overrides Mode bit 0 selection). 0 Enable 0 1 Timer is not enabled. Timer is enabled. 134 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxCR0 (Counter Control:001) 0,23h 13.2.9 DxCxxCR0 (Counter Control:001) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DBC00CR0: 0,23h DBC10CR0: 0,33h DBC20CR0: 0,43h 0,23h DBC01CR0: 0,27h DBC11CR0: 0,37h DBC21CR0: 0,47h 7 6 Access : POR Bit Name DCC02CR0: 0,2Bh DCC12CR0: 0,3Bh DCC22CR0: 0,4Bh 5 4 DCC03CR0: 0,2Fh DCC13CR0: 0,3Fh DCC23CR0: 0,4Fh 3 2 RW : 0000 RW : 0 RW : 0 KILL[3:0] NPS 1 0 RW : 0 RW : 0 DR2BufEN Enable This register is the Control register for a counter, if the DxCxxFN register is configured as a ‘001’. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 KILL[3:0] Same meaning as in Timer function. 3 NPS Same meaning as in Timer function. 1 DR2BufEn 1 Enable DR2 update buffer; that is, update DR2 only at TC when function is running. 0 Enable 0 1 Counter is not enabled. Counter is enabled. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 135 DxCxxCR0 (Dead Band Control:100) 0,23h 13.2.10 DxCxxCR0 (Dead Band Control:100) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DBC00CR0: 0,23h DBC10CR0: 0,33h DBC20CR0: 0,43h 0,23h DBC01CR0: 0,27h DBC11CR0: 0,37h DBC21CR0: 0,47h 7 6 DCC02CR0: 0,2Bh DCC12CR0: 0,3Bh DCC22CR0: 0,4Bh 5 4 3 Access : POR Bit Name DCC03CR0: 0,2Fh DCC13CR0: 0,3Fh DCC23CR0: 0,4Fh 2 1 0 RW : 0 RW : 0 RW : 0 Bit Bang Clock Bit Bang Mode Enable This register is the Control register for a dead band, if the DxCxxFN register is configured as ‘100’. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 2 Bit Bang Clock When Bit Bang mode is enabled, the output of this register bit is substituted for the PWM reference. This register may be toggled by user firmware to generate PHI1 and PH2 output clocks with the programmed dead time. 1 Bit Bang Mode 0 1 Dead Band Generator uses the previous block primary output as the input reference. Dead Band Generator uses the Bit Bang Clock register as the input reference. 0 Enable 0 1 Dead Band Generator is not enabled. Dead Band Generator is enabled. 136 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxCR0 (CRCPRS Control:010) 0,23h 13.2.11 DxCxxCR0 (CRCPRS Control:010) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DBC00CR0: 0,23h DBC10CR0: 0,33h DBC20CR0: 0,43h 0,23h DBC01CR0: 0,27h DBC11CR0: 0,37h DBC21CR0: 0,47h 7 6 5 Access : POR Bit Name DCC02CR0: 0,2Bh DCC12CR0: 0,3Bh DCC22CR0: 0,4Bh 4 3 DCC03CR0: 0,2Fh DCC13CR0: 0,3Fh DCC23CR0: 0,4Fh 2 1 0 RW : 0000 RW : 0 RW : 0 RW : 0 KILL[3:0] Shift Mode Pass Mode Enable This register is the Control register for a CRCPRS, if the DxCxxFN register is configured as a ‘010’. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 KILL[3:0] Same as Timer function. 2 Shift Mode Forces CRCPRS forward bus to zero to complete shift function. 0 Normal CRC/PRS operation 1 Shift register operation 1 Pass Mode If selected, the DATA input selection is driven directly to the primary output and the block interrupt output. The CLK input selection is driven directly to the auxiliary output. 0 Normal CRC/PRS outputs. 1 Outputs are overridden. 0 Enable 0 1 CRC/PRS is not enabled. CRC/PRS is enabled. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 137 DxCxxCR0 (PWMDBL Control:011) 0,23h 13.2.12 DxCxxCR0 (PWMDBL Control:011) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DBC00CR0: 0,23h DBC10CR0: 0,33h DBC20CR0: 0,43h 0,23h DBC01CR0: 0,27h DBC11CR0: 0,37h DBC21CR0: 0,47h 7 6 5 DCC02CR0: 0,2Bh DCC12CR0: 0,3Bh DCC22CR0: 0,4Bh 4 3 DCC03CR0: 0,2Fh DCC13CR0: 0,3Fh DCC23CR0: 0,4Fh 2 1 0 Access : POR RW : 0000 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name START[3:0] NPS KILL_INT SWT Enable This register is the Control register for a PWMDBL, if the DxCxxFN register is configured as a ‘011’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 START[3:0] PPG (programmable pulse generator) means the output pulse number is programmable. The pulse number at each trigger is specified by a 4 bit multi-shot value. When SWT is 0 in PPG mode: 0000b Low 0001b High 0010b BC 0011b VC3 0100b RI[0] 0101b RI[1] 0110b RI[2] 0111b RI[3] 1000b RO[0] 1001b RO[1] 1010b RO[2] 1011b RO[3] 1100b ACMP[0] 1101b ACMP[1] 1110b ACMP[2] 1111b ACMP[3] When the shot is ongoing, the new trigger (rising edge of 'START') has no effect. It will launch a new shot when START stays high at the end of the shot. 3 NPS Negative Phase Select. 0 Disables negative phase select. No delay for compare output to become low. 1 Enable negative phase select. Compare output will delay one half cycle to become low. Note The PWMDBL function does not support NPS mode when integrated dead band function is enabled. 2 KILL_INT 0 1 KILL is not interrupt source. The interrupt follows the rising edge for primary output. Set to select KILL as interrupt; it has highest priority. (continued on next page) 138 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxCR0 (PWMDBL Control:011) 0,23h 13.2.12 DxCxxCR0 (PWMDBL Control:011) (continued) 1 SWT 0 Disables software trigger mode. 1 Enables software trigger mode. If SWT is set to ‘1’, writing Enable (bit 0) to ‘1’ software will start PPG mode. If SWT is cleared to ‘0’, PWMDBL will wait for the rising edge of START to trigger PPG. 0 Enable 0 Disables PWMDBL function. 1 Enables PWMDBL function. The primary digital block output is a comparison output (< or <=); the auxiliary digital block output is the reversed version. They support dead band. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 139 DCCxxCR0 (SPIM Control:0-110) 0,2Bh 13.2.13 DCCxxCR0 (SPIM Control:0-110) Digital Communication Type C Block Control Register 0 Individual Register Names and Addresses: DCC02CR0: 0,2Bh DCC22CR0: 0,4Bh DCC03CR0: 0,2Fh DCC23CR0: 0,4Fh DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh 7 6 5 4 3 2 1 0 RW : 0 R:0 R:0 R:1 R:0 RW : 0 RW : 0 RW : 0 LSb First Overrun SPI Complete TX Reg Empty RX Reg Full Clock Phase Clock Polarity Enable Access : POR Bit Name 0,2Bh This register is the Control register for a SPIM, if the DxCxxFN register is configured as a ‘110’. The LSb First, Clock Phase, and Clock Polarity bits are configuration bits and should never be changed when the block is enabled. They can be set at the same time that the block is enabled. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7 LSb First This bit should not be changed during an SPI transfer. 0 Data is shifted out MSb first. 1 Data is shifted out LSb first. 6 Overrun 0 1 No overrun has occurred. Overrun has occurred. Indicates that a new byte is received and loaded into the RX Buffer before the previous one is read. It is cleared on a read of this (CR0) register. 5 SPI Complete 0 1 Indicates that a byte may still be in the process of shifting out, or no transmission is active. Indicates that a byte is shifted out and all associated clocks are generated. It is cleared on a read of this (CR0) register. Optional interrupt. 4 TX Reg Empty Reset state and the state when the block is disabled is ‘1’. 0 Indicates that a byte is currently buffered in the TX register. 1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer (DR1) register. This is the default interrupt. This status is initially asserted on block enable; however, the TX Reg Empty interrupt will occur only after the first data byte is written and transferred into the shifter. 3 RX Reg Full 0 1 RX register is empty. A byte is received and loaded into the RX register. It is cleared on a read of the RX Buffer (DR2) register. 2 Clock Phase 0 1 Data is latched on the leading clock edge. Data changes on the trailing edge (Modes 0, 1). Data changes on the leading clock edge. Data is latched on the trailing edge (Modes 2, 3). 1 Clock Polarity 0 1 Non-inverted, clock idles low (Modes 0, 2). Inverted, clock idles high (Modes 1, 3). 0 Enable 0 1 SPI Master is not enabled. SPI Master is enabled. 140 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DCCxxCR0 (SPIS Control:1-110) 0,2Bh 13.2.14 DCCxxCR0 (SPIS Control:1-110) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DCC02CR0: 0,2Bh DCC22CR0: 0,4Bh DCC03CR0: 0,2Fh DCC23CR0: 0,4Fh DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh 7 6 5 4 3 2 1 0 RW : 0 R:0 R:0 R:1 R:0 RW : 0 RW : 0 RW : 0 LSb First Overrun SPI Complete TX Reg Empty RX Reg Full Clock Phase Clock Polarity Enable Access : POR Bit Name 0,2Bh This register is the Control register for a SPIS, if the DxCxxFN register is configured as a ‘110’. The LSb First, Clock Phase, and Clock Polarity bits are configuration bits and should never be changed when the block is enabled. They can be set at the same time that the block is enabled. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7 LSb First This bit should not be changed during an SPI transfer. 0 Data is shifted out MSb first. 1 Data is shifted out LSb first. 6 Overrun 0 1 No overrun has occurred. Overrun has occurred. Indicates that a new byte is received and loaded into the RX Buffer before the previous one is read. It is cleared on a read of this (CR0) register. 5 SPI Complete 0 1 Indicates that a byte may still be in the process of shifting out, or no transmission is active. Indicates that a byte is shifted out and all associated clocks are generated. It is cleared on a read of this (CR0) register. Optional interrupt. 4 TX Reg Empty Reset state and the state when the block is disabled is ‘1’. 0 Indicates that a byte is currently buffered in the TX register. 1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer (DR1) register. This is the default interrupt. This status is initially asserted on block enable; however, the TX Reg Empty interrupt will occur only after the first data byte is written and transferred into the shifter. 3 RX Reg Full 0 1 RX register is empty. A byte is received and loaded into the RX register. It is cleared on a read of the RX Buffer (DR2) register. 2 Clock Phase 0 1 Data is latched on the leading clock edge. Data changes on the trailing edge (Modes 0, 1). Data changes on the leading clock edge. Data is latched on the trailing edge (Modes 2, 3). 1 Clock Polarity 0 1 Non-inverted, clock idles low (Modes 0, 2). Inverted, clock idles high (Modes 1, 3). 0 Enable 0 1 SPI Slave is not enabled. SPI Slave is enabled. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 141 DxCxxCR0 (DSM Control:111) 0,23h 13.2.15 DxCxxCR0 (DSM Control:111) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DBC00CR0: 0,23h DBC10CR0: 0,33h DBC20CR0: 0,43h 0,23h DBC01CR0: 0,27h DBC11CR0: 0,37h DBC21CR0: 0,47h 7 6 5 4 3 DCC03CR0: 0,2Fh DCC13CR0: 0,3Fh DCC23CR0: 0,4Fh 2 1 0 RW : 0000 RW : 0 KILL_SEL[3:0] Enable Access : POR Bit Name DCC02CR0: 0,2Bh DCC12CR0: 0,3Bh DCC22CR0: 0,4Bh This register is the Control register for a DSM, if the DxCxxFN register is configured as a ‘111’. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’.For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 KILL_SEL[3:0] Used to select KILL signal source 0000b Low 0001b High 0010b BC 0011b VC3 0100b RI[0] 0101b RI[1] 0110b RI[2] 0111b RI[3] 1000b RO[0] 1001b RO[1] 1010b RO[2] 1011b RO[3] 1100b ACMP[0] 1101b ACMP[1] 1110b ACMP[2] 1111b ACMP[3] 0 Enable 0 1 142 Enables DSM function. When enabled, the DSM starts working. Disables DSM function. When disabled, DSM output is low and it stops working. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DCCxxCR0 (UART Transmitter Control) 0,2Bh 13.2.16 DCCxxCR0 (UART Transmitter Control) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DCC02CR0: 0,2Bh DCC22CR0: 0,4Bh 0,2Bh DCC03CR0: 0,2Fh DCC23CR0: 0,4Fh 7 6 Access : POR Bit Name DCC12CR0: 0,3Bh 3 DCC13CR0: 0,3Fh 5 4 2 1 0 R:0 R:1 RW : 0 RW : 0 RW : 0 TX Complete TX Reg Empty Parity Type Parity Enable Enable This register is the Control register for a UART transmitter, if the DxCxxFN register is configured as a ‘101’. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. For the Receive mode definition, refer to DCCxxCR0 (UART Receiver Control) register on page 144. Bit Name Description 5 TX Complete 0 1 4 TX Reg Empty Reset state and the state when the block is disabled is ‘1’. 0 Indicates that a byte is currently buffered in the TX register. 1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer register. This is the default interrupt. TX Reg Empty interrupt will occur only after the first data byte is written and transferred into the shifter. 2 Parity Type 0 1 Even parity Odd parity 1 Parity Enable 0 1 Parity is not enabled. Parity is enabled, frame includes parity bit. 0 Enable 0 1 Serial Transmitter is not enabled. Serial Transmitter is enabled. Indicates that a byte may still be in the process of shifting out. Indicates that a byte is shifted out and all associated framing bits are generated. Optional interrupt. Cleared on a read of this (CR0) register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 143 DCCxxCR0 (UART Receiver Control) 0,2Bh 13.2.17 DCCxxCR0 (UART Receiver Control) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: DCC02CR0: 0,2Bh DCC22CR0: 0,4Bh DCC03CR0: 0,2Fh DCC23CR0: 0,4Fh DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh 7 6 5 4 3 2 1 0 R:0 R:0 R:0 R:0 R:0 RW : 0 RW : 0 RW : 0 Parity Error Overrun Framing Error RX Active RX Reg Full Parity Type Parity Enable Enable Access : POR Bit Name 0,2Bh This register is the Control register for a UART receiver, if the DxCxxFN register is configured as a ‘101’. Refer to the DxCxxDR0 register on page 131 for naming convention and digital row availability information. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. For the transmit mode definition, refer to section DCCxxCR0 (UART Transmitter Control) register on page 143. Bit Name Description 7 Parity Error 0 1 Indicates that no parity error has occurred. Valid when RX Reg Full is set, indicating that a parity error has occurred in the received byte and cleared on a read of this (CR0) register. 6 Overrun 0 1 Indicates that no overrun has occurred. Valid when RX Reg Full is set, indicating that the byte in the RX Buffer register has not been read before the next byte is loaded. It is cleared on a read of this (CR0) register. 5 Framing Error 0 1 Indicates no framing error has occurred. Valid when RX Reg Full is set, indicating that a framing error has occurred (a logic 0 was sampled at the STOP bit, instead of the expected logic 1). It is cleared on a read of this (CR0) register. 4 RX Active 0 1 Indicates that no reception is in progress. Indicates that a reception is in progress. It is set by the detection of a START bit and cleared at the sampling of the STOP bit. 3 RX Reg Full 0 1 Indicates that the RX Buffer register is empty. Indicates that a byte is received and transferred to the RX Buffer (DR2) register. This bit is cleared when the RX Buffer register (DR2) is read by the CPU. Interrupt source. 2 Parity Type 0 1 Even parity Odd parity 1 Parity Enable 0 1 Parity is not enabled. Parity is enabled, frame includes parity bit. 0 Enable 0 1 Serial Receiver is not enabled. Serial Receiver is enabled. 144 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F AMX_IN 0,60h 13.2.18 AMX_IN Analog Input Select Register Individual Register Names and Addresses: 0,60h AMX_IN: 0,60h 7 Access : POR Bit Name 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 ACI3[1:0] ACI2[1:0] ACI1[1:0] ACI0[1:0] This register controls the analog muxes that feed signals in from port pins into the analog column. For additional information, refer to the “Register Definitions” on page 419 in the Analog Input Configuration chapter. Bits Name Description 7:6 ACI3[1:0] Selects the Analog Column Mux 3. 00b ACM3 P0[0] 01b ACM3 P0[2] 10b ACM3 P0[4] 11b ACM3 P0[6] 5:4 ACI2[1:0] Selects the Analog Column Mux 2. 00b ACM2 P0[1] 01b ACM2 P0[3] 10b ACM2 P0[5] 11b ACM2 P0[7] 3:2 ACI1[1:0] Selects the Analog Column Mux 1. For 1 column, these are even inputs. 00b ACM1 P0[0] 01b ACM1 P0[2] 10b ACM1 P0[4] 11b ACM1 P0[6] 1:0 ACI0[1:0] Selects the Analog Column Mux 0. For 1 column, these are odd inputs. 00b ACM0 P0[1] 01b ACM0 P0[3] 10b ACM0 P0[5] 11b ACM0 P0[7] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 145 AMUX_CFG 0,61h 13.2.19 AMUX_CFG Analog Mux Configuration Register Individual Register Names and Addresses: 0,61h AMUX_CFG : 0,61h Access : POR Bit Name 7 6 RW : 0 RW : 0 5 RW : 0 4 3 RW : 0 2 1 RW : 0 0 ABusMux1 ABusMux0 INTCAP[1:0] MUXCLK0[2:0] EN0 This register is used to configure the clocked pre-charge mode of the analog multiplexer system. Note The analog mux bus is not available in the CY8C28x03 and CY8C28x33. For additional information, refer to the “Register Definitions” on page 528 in the I/O Analog Multiplexer chapter. Bits Name Description 7 ABusMux1 0 1 Set column 1 input to column 1 mux output (selects among P0[6,4,2,0]) Set column 1 input to the analog mux bus. If the bus is configured as two nets, the analog mux bus right net connects to column 1. 6 ABusMux0 0 1 Set column 0 input to column 0 mux output (selects among P0[7,5,3,1]). Set column 0 input to the analog mux bus. If the bus is configured as two nets, the analog mux bus left net connects to column 0. 5:4 INTCAP[1:0] Selects pins for static operation, even when the precharge clock is selected with MUXCLKx[2:0]. 00b Both P0[7] and P0[5] are in normal precharge configuration. 01b P0[5] pin selected for static mode only. 10b P0[7] pin selected for static mode only. 11b Both P0[7] and P0[5] are selected for static mode only. 3:1 MUXCLK0[2:0] Selects a precharge clock source for analog mux bus left (AMuxBus0) connections. It can be suppressed by bit 4 in the AMUX_CLK register. 000b Precharge clock is off, no switching. 001b VC1 010b VC2 011b Row0 Broadcast 100b Analog column 0clock* 101b Analog column 2 clock* 110b Analog column 4 clock 111b Reserved * The analog column clock selection is a 1x version of the clock, such as before the divide by four. 0 146 EN0 0 1 Disable MUXCLK output Enable MUXCLK output CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CLK_CR3 0,62h 13.2.20 CLK_CR3 Analog Clock Source Control Register 3 Individual Register Names and Addresses: 0,62h CLK_CR3: 0,62h 7 6 5 4 3 2 1 0 RW : 0 Access : POR SYSDIR[3:0] Bit Name The Analog Clock Source Control Register 3 (CLK_CR3) is used to select the clock source for an individual analog column. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 3:0 SYSDIR[3:0] 0 1 Associated ACC column's clock source is determined by setting of CLK_CR0. Associated ACC column's clock source is SYSCLK. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 147 ARF_CR 0,63h 13.2.21 ARF_CR Analog Reference Control Register Individual Register Names and Addresses: 0,63h ARF_CR: 0,63h 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 0 RW : 0 RW : 0 HBE REF[2:0] PWR[2:0] 0 This register is used to configure various features of the configurable analog references. In the table, note that the reserved bit is a gray table cell and is not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 422 in the Analog Reference chapter. Bits Name Description 6 HBE Bias level control for opamps. 0 Low bias mode for analog array 1 High bias mode for analog array 5:3 REF[2:0] Analog Array Reference Control (values with respect to Vss). These three bits select the sources for analog ground (AGND), the high reference (RefHi), and the low reference (RefLo). The following table applies to 4 and 2 column PSoC devices: AGND RefHi 000b Vdd/2 Vdd/2 + Bandgap 001b P2[4] P2[4] + P2[6] 010b Vdd/2 Vdd/2 + Vdd/2 011b 2 x Bandgap 2 x Bandgap + Bandgap 100b 2 x Bandgap 2 x Bandgap + P2[6] 101b P2[4] P2[4] + Bandgap 110b Bandgap Bandgap + Bandgap 111b 1.6 x Bandgap 1.6 x Bandgap + 1.6 x Bandgap 2:0 PWR[2:0] Analog Array Power Control 000b 001b 010b 011b 100b 101b 110b 111b 148 RefLo Vdd/2 – Bandgap P2[4] – P2[6] Vdd/2 – Vdd/2 2 x Bandgap – Bandgap 2 x Bandgap – P2[6] P2[4] – Bandgap Bandgap – Bandgap 1.6 x Bandgap – 1.6 x Bandgap Reference Off Low Medium High Off Low Medium High CT Block Off On On On Off On On On SC Blocks Off Off Off Off Off On On On CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CMP_CR0 0,64h 13.2.22 CMP_CR0 Analog Comparator Bus Control Register 0 Individual Register Names and Addresses: 0,64h CMP_CR0: 0,64h 7 Access : POR Bit Name 6 5 4 3 2 1 R:0 RW : 0 COMP[3:0] AINT[3:0] 0 This register is used to poll the analog column comparator bus states and select column interrupts. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 7 COMP[3] Comparator bus state for column 3. This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the CLDISx bits in the CMP_CR1 register). If the comparator latch disable bits are set, then this bit is transparent to the comparator bus in the analog array. 6 COMP[2] Comparator bus state for column 2. This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the CLDISx bits in the CMP_CR1 register). If the comparator latch disable bits are set, then this bit is transparent to the comparator bus in the analog array. 5 COMP[1] Comparator bus state for column 1. This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the CLDISx bits in the CMP_CR1 register). If the comparator latch disable bits are set, then this bit is transparent to the comparator bus in the analog array. 4 COMP[0] Comparator bus state for column 0. This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the CLDISx bits in the CMP_CR1 register). If the comparator latch disable bits are set, then this bit is transparent to the comparator bus in the analog array. 3 AINT[3] Controls the selection of the analog comparator interrupt for column 3. 0 The comparator data bit from the column is the input to the interrupt controller. 1 The falling edge of PHI2 for the column is the input to the interrupt controller. 2 AINT[2] Controls the selection of the analog comparator interrupt for column 2. 0 The comparator data bit from the column is the input to the interrupt controller. 1 The falling edge of PHI2 for the column is the input to the interrupt controller. 1 AINT[1] Controls the selection of the analog comparator interrupt for column 1. 0 The comparator data bit from the column is the input to the interrupt controller. 1 The falling edge of PHI2 for the column is the input to the interrupt controller. In 2 column limited analog PSoC devices, this bit selects the terminal count for the dedicated incremental PWM as the interrupt source. 0 AINT[0] Controls the selection of the analog comparator interrupt for column 0. 0 The comparator data bit from the column is the input to the interrupt controller. 1 The falling edge of PHI2 for the column is the input to the interrupt controller. In 2 column limited analog PSoC devices, this bit selects the terminal count for the dedicated incremental PWM as the interrupt source. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 149 ASY_CR 0,65h 13.2.23 ASY_CR Analog Synchronization Control Register Individual Register Names and Addresses: 0,65h ASY_CR: 0,65h 4, 2 COLUMN 7 Access : POR Bit Name 6 5 4 3 2 1 0 W:0 RW : 0 RW : 0 RW : 0 SARCNT[2:0] SARSIGN SARCOL[1:0] SYNCEN This register is used to control SAR operation, except for the SYNCEN bit which is associated with analog register write stalling. Note This does not refer to the dedicated SAR10 ADC Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 6:4 SARCNT[2:0] Initial SAR count. This field is initialized to the number of SAR bits to process. Note Any write to the SARCNT bits, other than ‘0’, will result in a modification of the read back of any analog register in the analog array. These bits must always be zero, except for SAR processing. 3 SARSIGN This bit adjusts the SAR comparator based on the type of block addressed. In a DAC configuration with more than one analog block (more than 6 bits), this bit should be set to ‘0’ when processing the most significant block. It should be set to ‘1’ when processing the least significant block., because the least significant block is an inverting input to the most significant block. 2:1 SARCOL[1:0] The selected column corresponds with the position of the SAR comparator block. Note that the comparator and DAC can be in the same block. 00b Analog Column 0 is the source for SAR comparator. 01b Analog Column 1 is the source for SAR comparator. 10b Analog Column 2 is the source for SAR comparator. 11b Analog Column 3 is the source for SAR comparator. 0 SYNCEN Set to ‘1’, will stall the CPU until the rising edge of PHI1, if a write to a register within an analog Switch Cap block takes place. 0 CPU stalling disabled. 1 CPU stalling enabled. 150 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CMP_CR1 0,66h 13.2.24 CMP_CR1 Analog Comparator Bus Control Register 1 Individual Register Names and Addresses: 0,66h CMP_CR1: 0,66h 4 COLUMN 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 CLDIS[3] CLDIS[2] CLDIS[1] CLDIS[0] CLK1X[3] CLK1X[2] CLK1X[1] CLK1X[0] Access : POR Bit Name This register is used to override the analog column comparator synchronization, or select direct column clock synchronization. By default, the analog comparator bus is synchronized by the column clock and driven to the digital comparator bus for use in the digital array and the interrupt controller. The CLDIS bits are used to bypass the synchronization. This bypass mode can be used in power down operation to wake the device out of sleep, as a result of an analog column interrupt. Most devices update the comparator bus on the rising edge of PHI2. The CY8C28xxx PSoC devices have the option to synchronize using PHI2 or, when the CLK1X bits are set for a given column, 1X rising edge column clock sync is enabled. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 7 CLDIS[3] Controls the comparator output latch, column 3. 0 Comparator bus synchronization is enabled. 1 Comparator bus synchronization is disabled. 6 CLDIS[2] Controls the comparator output latch, column 2. 0 Comparator bus synchronization is enabled. 1 Comparator bus synchronization is disabled. 5 CLDIS[1] Controls the comparator output latch, column 1. 0 Comparator bus synchronization is enabled. 1 Comparator bus synchronization is disabled. 4 CLDIS[0] Controls the comparator output latch, column 0. 0 Comparator bus synchronization is enabled. 1 Comparator bus synchronization is disabled. 3 CLK1X[3] Controls the digital comparator bus 3 synchronization clock. 0 Comparator bit is synchronized by rising edge of PHI2. 1 Comparator bit is synchronized directly by selected column clock. (This clock is not divided by 4.) 2 CLK1X[2] Controls the digital comparator bus 2 synchronization clock. 0 Comparator bit is synchronized by rising edge of PHI2. 1 Comparator bit is synchronized directly by selected column clock. (This clock is not divided by 4.) 1 CLK1X[1] Controls the digital comparator bus 1 synchronization clock. 0 Comparator bit is synchronized by rising edge of PHI2. 1 Comparator bit is synchronized directly by selected column clock. (This clock is not divided by 4.) (continued on next page) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 151 CMP_CR1 0,66h 13.2.24 0 152 CMP_CR1 (continued) CLK1X[0] Controls the digital comparator bus 0 synchronization clock. 0 Comparator bit is synchronized by rising edge of PHI2. 1 Comparator bit is synchronized directly by selected column clock. (This clock is not divided by 4.) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F SADC_DH 0,6Ah 13.2.25 SADC_DH SAR ADC Data High Register Individual Register Names and Addresses: 0,6Ah SADC_DH : 0,6Ah 7 6 5 4 3 2 1 0 R : 00 Access : POR Data High [7:0] Bit Name The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, see “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7:0 Data High [7:0] The high byte of ADC data. Only the two least significant bits are valid when in right-justified mode. The ADC can be treated as an 8-bit ADC if you only read this byte of ADC data in left-justified mode. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 153 SADC_DL 0,6Bh 13.2.26 SADC_DL SAR ADC Data Low Register Individual Register Names and Addresses: 0,6Bh SADC_DL : 0,6Bh 7 6 5 4 3 2 1 0 R : 00 Access : POR Data Low [7:0] Bit Name The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, see “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7:0 Data Low [7:0] The low byte of ADC data. It contains the least significant 8 bits of the 10-bit sample in right-justified data format. In left-justified data format only the bits [1:0] are valid to hold the least significant 2 bits of the 10-bit sample. 154 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F TMP_DRx x,6Ch 13.2.27 TMP_DRx Temporary Data Register Individual Register Names and Addresses: TMP_DR0 : x,6Ch x,6Ch TMP_DR1 : x,6Dh 7 6 TMP_DR2 : x,6Eh 5 4 TMP_DR3 : x,6Fh 3 Access : POR RW : 00 Bit Name Data[7:0] 2 1 0 This register is used to enhance the performance in multiple SRAM page PSoC devices. For additional information, refer to the “Register Definitions” on page 60 in the RAM Paging chapter. Bit Name Description 7:0 Data[7:0] General purpose register space. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 155 ACCxxCR3 0,70h 13.2.28 ACCxxCR3 Analog Continuous Time Type C Block Control Register 3 Individual Register Names and Addresses: ACC00CR3 : 0,70h 0,70h ACC01CR3 : 0,74h 7 6 Access : POR Bit Name ACC02CR3 : 0,78h ACC03CR3 : 0,7Ch 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 AGND_PD RTopMux1 LPCMPEN CMOUT INSAMP EXGAIN This register is one of four registers used to configure a type C continuous time PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n=column index; therefore, ACC01CR3 is a register for an analog PSoC block in row 0 column 1. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 426 in the Continuous Time Block chapter. Bits Name Description 5 AGND_PD Used to power down AGND buffer in CT block. 0 AGND buffer in CT block enabled 1 AGND buffer in CT block disabled 4 RTopMux1 0 1 RTop to Vdd or opamp's output depending on ACCxxCR0 bit 2. RTop to RefHi. 3 LPCMPEN 0 1 Low power comparator is disabled. Low power comparator is enabled. 2 CMOUT 0 1 No connection to column output. Connect Common mode to column output. 1 INSAMP 0 1 Normal mode Connect amplifiers across column to form an Instrumentation Amp. 0 EXGAIN 0 1 Standard Gain mode High Gain mode (see the ACCxxCR0 register on page 157.) 156 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACCxxCR0 0,71h 13.2.29 ACCxxCR0 Analog Continuous Time Type C Block Control Register 0 Individual Register Names and Addresses: ACC00CR0 : 0,71h 0,71h ACC01CR0 : 0,75h 7 Access : POR Bit Name 6 ACC02CR0 : 0,79h 5 4 ACC03CR0 : 0,7Dh 3 2 RW : 0 RW : 0 RW : 0 1 RW : 0 0 RTapMux[3:0] Gain RTopMux RBotMux[1:0] This register is one of four registers used to configure a type C continuous time PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ACC01CR0 is a register for an analog PSoC block in row 0 column 1. For additional information, refer to the “Register Definitions” on page 426 in the Continuous Time Block chapter. Bits Name Description 7:4 RTapMux[3:0] Encoding for selecting one of 18 resistor taps. The four bits of RTapMux[3:0] allow selection of 16 taps. The two additional tap selections are provided using ACCxxCR3 bit 0, EXGAIN. The EXGAIN bit only affects the RTapMux values 0000b and 0001b. RTap 0000b 0001b 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b EXGAIN 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rf 47 46 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 Ri 1 2 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 Loss 0.0208 0.0417 0.0625 0.1250 0.1875 0.2500 0.3125 0.3750 0.4375 0.5000 0.5625 0.6250 0.6875 0.7500 0.8125 0.8750 0.9375 1.0000 3 Gain Select gain or loss configuration for output tap. 0 Loss 1 Gain 2 RTopMux Encoding for feedback resistor select. 0 RTop to Vdd 1 RTop to opamp’s output Gain 48.000 24.000 16.000 8.000 5.333 4.000 3.200 2.667 2.286 2.000 1.778 1.600 1.455 1.333 1.231 1.143 1.067 1.000 (continued on next page) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 157 ACCxxCR0 0,71h 13.2.29 1:0 ACCxxCR0 (continued) RBotMux[1:0] Encoding for feedback resistor select. Bits [1:0] are overridden if bit 1 of the ACCxxCR3 register is set. In that case, the bottom of the resistor string is connected across columns. Note that available mux inputs vary by individual PSoC block. In the following table, only columns ACC00 and ACC01 are used by the 2 column analog PSoC blocks and all columns are used by the 4 column analog PSoC blocks. 00b 01b 10b 11b 158 ACC00 ACC01 AGND Vss ASC10 ACC01 ACC00 AGND Vss ASD11 ACC02 ACC03 AGND Vss ASC12 ACC03 ACC02 AGND Vss ASD13 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACCxxCR1 0,72h 13.2.30 ACCxxCR1 Analog Continuous Time Type C Block Control Register 1 Individual Register Names and Addresses: ACC00CR1 : 0,72h Access : POR Bit Name 0,72h ACC01CR1 : 0,76h ACC02CR1 : 0,7Ah 5 4 ACC03CR1 : 0,7Eh 7 6 RW : 0 RW : 0 RW : 0 3 2 RW : 0 1 AnalogBus CompBus NMux[2:0] PMux[2:0] 0 This register is one of four registers used to configure a type C continuous time PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ACC01CR1 is a register for an analog PSoC block in row 0 column 1. For additional information, refer to the “Register Definitions” on page 426 in the Continuous Time Block chapter. Bits Name Description 7 AnalogBus Enable output to the analog bus. 0 Disable output to analog column bus. 1 Enable output to analog column bus. 6 CompBus Enable output to the comparator bus. 0 Disable output to comparator bus. 1 Enable output to comparator bus. 5:3 NMux[2:0] Encoding for negative input select. Note that available mux inputs vary by individual PSoC block. In this table, only columns ACC00 and ACC01 are used by the 2 column analog PSoC blocks and all columns are used by the 4 column analog PSoC blocks. ACC00 ACC01 ACC02 ACC03 000b ACC01 ACC00 ACC03 ACC02 001b AGND AGND AGND AGND 010b RefLo RefLo RefLo RefLo 011b RefHi RefHi RefHi RefHi 100b 101b 110b 111b FB# ASC10 ASD11 Port Inputs FB# ASD11 ASC10 Port Inputs FB# ASC12 ASD13 Port Inputs FB# ASD13 ASC12 Port Inputs # Feedback point from tap of the feedback resistor as defined by corresponding CR0 bits [7:4] and CR3 bit 0. 2:0 PMux[2:0] Encoding for positive input select. Note that available mux inputs vary by individual PSoC block. The following table is used by the 4 column analog PSoC blocks. ACC00 ACC01 ACC02 ACC03 000b RefLo ACC02 ACC01 RefLo 001b Port Inputs Port Inputs Port Inputs Port Inputs 010b ACC01 ACC00 ACC03 ACC02 011b AGND AGND AGND AGND 100b ASC10 ASD11 ASC12 ASD13 101b ASD11 ASC10 ASD13 ASC12 110b ABUS0 ABUS1 ABUS2 ABUS3 111b FB# FB# FB# FB# # Feedback point from tap of the feedback resistor as defined by corresponding CR0 bits [7:4] and CR3 bit 0. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 159 ACCxxCR2 0,73h 13.2.31 ACCxxCR2 Analog Continuous Time Type C Block Control Register 2 Individual Register Names and Addresses: ACC00CR2 : 0,73h 0,73h ACC01CR2 : 0,77h ACC02CR2 : 0,7Bh ACC03CR2 : 0,7Fh 7 6 5 4 Access : POR RW : 0 RW : 0 RW : 0 RW : 0 3 RW : 0 2 1 RW : 0 0 Bit Name CPhase CLatch CompCap TMUXEN TestMux[1:0] PWR[1:0] This register is one of four registers used to configure a type C continuous time PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ACC01CR2 is a register for an analog PSoC block in row 0 column 1. For additional information, refer to the “Register Definitions” on page 426 in the Continuous Time Block chapter. Bits Name Description 7 CPhase 0 1 Comparator Control latch is transparent on PHI1. Comparator Control latch is transparent on PHI2. 6 CLatch 0 1 Comparator Control latch is always transparent. Comparator Control latch is active. 5 CompCap 0 1 Comparator Mode Opamp Mode 4 TMUXEN Test Mux 0 Disabled 1 Enabled 3:2 TestMux[1:0] Select block bypass mode. Note that available mux inputs vary by individual PSoC block and TMUXEN must be set. In the following table, column ACC01 is used by the one column PSoC blocks, columns ACC00 and ACC01 are used by the 2 column PSoC blocks, and all columns are used by the 4 column PSoC blocks. ACC00 ACC01 ACC02 ACC03 00b Positive Input to ABUS0 ABUS1 ABUS2 ABUS3 01b AGND to ABUS0 ABUS1 ABUS2 ABUS3 10b RefLo to ABUS0 ABUS1 ABUS2 ABUS3 11b RefHi to ABUS0 ABUS1 ABUS2 ABUS3 1:0 PWR[1:0] Encoding for selecting one of four power levels. High Bias mode doubles the power at each of these settings. See bit 6 in the ARF_CR register on page 148. 00b Off 01b Low 10b Medium 11b High 160 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ASCxxCR0 0,80h 13.2.32 ASCxxCR0 Analog Switch Cap Type C Block Control Register 0 Individual Register Names and Addresses: ASC10CR0 : 0,80h Access : POR 0,80h ASC12CR0 : 0,88h ASC21CR0 : 0,94h 7 6 5 RW : 0 RW : 0 RW : 0 RW : 00 FCap ClockPhase ASign ACap[4:0] Bit Name 4 3 ASC23CR0 : 0,9Ch 2 1 0 This register is one of four registers used to configure a type C switch capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ASC12CR0 is a register for an analog PSoC block in row 1 column 2. For additional information, refer to the “Register Definitions” on page 434 in the Switched Capacitor Block chapter. Bits Name Description 7 FCap F Capacitor value selection bit. 0 16 capacitor units 1 32 capacitor units 6 ClockPhase The ClockPhase controls the clock phase of the comparator within the switched cap blocks, as well as the clock phase of the switches. 0 Switch phasing is Internal PHI1 = External PHI1. Comparator Capture Point Event is triggered by Falling PHI2 and Comparator Output Point Event is triggered by Rising PHI1. 1 Switch phasing is Internal PHI1 = External PHI2. Comparator Capture Point Event is triggered by Falling PHI1 and Comparator Output Point Event is triggered by Rising PHI2. 5 ASign 0 1 4:0 ACap[4:0] Binary encoding for 32 possible capacitor sizes for capacitor ACap. Input sampled on Internal PHI1. Reference Input sampled on Internal PHI2. Positive gain. Input sampled on Internal PHI2. Reference Input sampled on Internal PHI1. Negative gain. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 161 ASCxxCR1 0,81h 13.2.33 ASCxxCR1 Analog Switch Cap Type C Block Control Register 1 Individual Register Names and Addresses: ASC10CR1 : 0,81h ASC12CR1 : 0,89h 7 Access : POR Bit Name 0,81h 6 ASC21CR1 : 0,95h 5 4 3 ASC23CR1 : 0,9Dh 2 RW : 0 RW : 00 ACMux[2:0] BCap[4:0] 1 0 This register is one of four registers used to configure a type C switch capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m=row index, n=column index; therefore, ASC12CR1 is a register for an analog PSoC block in row 1 column 2. For additional information, refer to the “Register Definitions” on page 434 in the Switched Capacitor Block chapter. Bits Name Description 7:5 ACMux[2:0] Encoding to select A and C inputs. (Note that available mux inputs vary by individual PSoC block. For 4 Column Analog PSoC Blocks: ASC10 ASC21 ASC12 ASC23 A Inputs C Inputs A Inputs C Inputs A Inputs C Inputs A Inputs C Inputs 000b ACC00 ACC00 ASD11 ASD11 ACC02 ACC02 ASD13 ASD13 001b ASD11 ACC00 ASD20 ASD11 ASD13 ACC02 ASD22 ASD13 010b RefHi ACC00 RefHi ASD11 RefHi ACC02 RefHi ASD13 011b ASD20 ACC00 Vtemp ASD11 ASD22 ACC02 ABUS3 ASD13 100b ACC01 ASD20 ASC10 ASD11 ACC03 ASD22 ASC12 ASD13 101b ACC00 ASD20 ASD20 ASD11 ACC02 ASD22 ASD22 ASD13 110b ASD11 ASD20 ABUS1 ASD11 ASD13 ASD22 ABUS3 ASD13 111b P2[1] ASD20 ASD22 ASD11 ASD11 ASD22 P2[2] ASD13 4:0 BCap[4:0] Binary encoding for 32 possible capacitor sizes of the capacitor BCap. 162 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ASCxxCR2 0,82h 13.2.34 ASCxxCR2 Analog Switch Cap Type C Block Control Register 2 Individual Register Names and Addresses: ASC10CR2 : 0,82h ASC12CR2 : 0,8Ah ASC21CR2 : 0,96h 4 3 ASC23CR2 : 0,9Eh 7 6 5 RW : 0 RW : 0 RW : 0 RW : 00 AnalogBus CompBus AutoZero CCap[4:0] Access : POR Bit Name 0,82h 2 1 0 This register is one of four registers used to configure a type C switch capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ASC12CR2 is a register for an analog PSoC block in row 1 column 2. For additional information, refer to the “Register Definitions” on page 434 in the Switched Capacitor Block chapter. Bits Name Description 7 AnalogBus Enable output to the analog bus. Note that ClockPhase in the ASCxxCR0 register on page 161, bit 6, also affects this bit: Sample + Hold mode is allowed only if ClockPhase = 0. 0 Disable output to analog column bus. 1 Enable output to analog column bus. 6 CompBus Enable output to the comparator bus. 0 Disable output to comparator bus. 1 Enable output to comparator bus. 5 AutoZero Bit for controlling gated switches. 0 Shorting switch is not active. Input cap branches shorted to opamp input. 1 Shorting switch is enabled during Internal PHI1. Input cap branches shorted to analog ground during Internal PHI1 and to opamp input during Internal PHI2. 4:0 CCap[4:0] Binary encoding for 32 possible capacitor sizes of the capacitor CCap. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 163 ASCxxCR3 0,83h 13.2.35 ASCxxCR3 Analog Switch Cap Type C Block Control Register 3 Individual Register Names and Addresses: ASC10CR3 : 0,83h 0,83h ASC12CR3 : 0,8Bh 7 Access : POR Bit Name 6 ASC21CR3 : 0,97h ASC23CR3 : 0,9Fh 5 4 RW : 0 RW : 0 RW : 0 3 RW : 0 2 1 RW : 0 0 ARefMux[1:0] FSW1 FSW0 BMuxSC[1:0] PWR[1:0] This register is one of four registers used to configure a type C switch capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ASC12CR3 is a register for an analog PSoC block in row 1 column 2. For additional information, refer to the “Register Definitions” on page 434 in the Switched Capacitor Block chapter. Bits Name Description 7:6 ARefMux[1:0] Encoding for selecting reference input. 00b Analog ground is selected. 01b RefHi input selected. 10b RefLo input selected. 11b Reference selection is driven by the comparator. (When output comparator node is set high, the input is set to RefHi. When set low, the input is set to RefLo.) 5 FSW1 Bit for controlling the FSW1 switch. 0 Switch is disabled. 1 If the FSW1 bit is set to ‘1’, the state of the switch is determined by the AutoZero bit. If the AutoZero bit is ‘0’, the switch is enabled at all times. If the AutoZero bit is ‘1’, the switch is enabled only when the Internal PHI2 is high. 4 FSW0 Bit for controlling the FSW0 switch. 0 Switch is disabled. 1 Switch is enabled when PHI1 is high. 3:2 BMuxSC[1:0] Encoding for selecting B inputs. Note that the available mux inputs vary by individual PSoC block. For 4 Column Analog PSoC Blocks: ASC10 ASC21 ASC12 ASC23 00b ACC00 ASD11 ACC02 ASD13 01b ASD11 ASD20 ASD13 ASD22 10b P2[3] ASD22 ASD11 P2[0] 11b ASD20 TrefGND ASD22 ABUS3 1:0 PWR[1:0] Encoding for selecting one of four power levels. 00b Off 10b Medium 01b Low 11b High 164 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ASDxxCR0 0,84h 13.2.36 ASDxxCR0 Analog Switch Cap Type D Block Control Register 0 Individual Register Names and Addresses: ASD11CR0 : 0,84h Access : POR 0,84h ASD13CR0 : 0,8Ch ASD20CR0 : 0,90h 7 6 5 RW : 0 RW : 0 RW : 0 RW : 00 FCap ClockPhase ASign ACap[4:0] Bit Name 4 3 ASD22CR0 : 0,98h 2 1 0 This register is one of four registers used to configure a type D switch capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m=row index, n=column index; therefore, ASD13CR0 is a register for an analog PSoC block in row 1 column 3. For additional information, refer to the “Register Definitions” on page 434 in the Switched Capacitor Block chapter. Bits Name Description 7 FCap F Capacitor value selection bit. 0 16 capacitor units 1 32 capacitor units 6 ClockPhase The ClockPhase controls the clock phase of the comparator within the switched cap blocks, as well as the clock phase of the switches. 0 Switch phasing is Internal PHI1 = External PHI1. Comparator Capture Point Event is triggered by Falling PHI2 and Comparator Output Point Event is triggered by Rising PHI1. 1 Switch phasing is Internal PHI1 = External PHI2. Comparator Capture Point Event is triggered by Falling PHI1 and Comparator Output Point Event is triggered by Rising PHI2. 5 ASign 0 1 4:0 ACap[4:0] Binary encoding for 32 possible capacitor sizes for capacitor ACap. Input sampled on Internal PHI1. Reference Input sampled on Internal PHI2. Positive gain. Input sampled on Internal PHI2. Reference Input sampled on Internal PHI1. Negative gain. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 165 ASDxxCR1 0,85h 13.2.37 ASDxxCR1 Analog Switch Cap Type D Block Control Register 1 Individual Register Names and Addresses: ASD11CR1 : 0,85h ASD13CR1 : 0,8Dh 7 Access : POR Bit Name 0,85h 6 ASD20CR1 : 0,91h 5 4 3 ASD22CR1 : 0,99h 2 RW : 0 RW : 00 AMux[2:0] BCap[4:0] 1 0 This register is one of four registers used to configure a type D switch capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ASD13CR1 is a register for an analog PSoC block in row 1 column 3. For additional information, refer to the “Register Definitions” on page 434 in the Switched Capacitor Block chapter. Bits Name Description 7:5 AMux[2:0] Encoding for selecting A and C inputs for C Type blocks and A inputs for D Type blocks. (Note that available mux inputs vary by individual PSoC block.) ASD20 ASD11 ASD22 ASD13 000b ASC10 ACC01 ASC12 ACC03 001b P2[1] ASC12 ASC21 P2[2] 010b ASC21 ASC10 ASC23 ASC12 011b ABUS0 ASC21 ABUS2 ASC23 100b RefHi RefHi RefHi RefHi 101b ASD11 ACC00 ASD13 ACC02 110b Reserved Reserved Reserved Reserved 111b Reserved Reserved Reserved Reserved 4:0 BCap[4:0] Binary encoding for 32 possible capacitor sizes for capacitor BCap. 166 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ASDxxCR2 0,86h 13.2.38 ASDxxCR2 Analog Switch Cap Type D Block Control Register 2 Individual Register Names and Addresses: ASD11CR2 : 0,86h ASD13CR2 : 0,8Eh ASD20CR2 : 0,92h 4 3 ASD22CR2 : 0,9Ah 7 6 5 RW : 0 RW : 0 RW : 0 RW : 00 AnalogBus CompBus AutoZero CCap[4:0] Access : POR Bit Name 0,86h 2 1 0 This register is one of four registers used to configure a type D switch capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ASD13CR2 is a register for an analog PSoC block in row 1 column 3. For additional information, refer to the “Register Definitions” on page 434 in the Switched Capacitor Block chapter. Bits Name Description 7 AnalogBus Enable output to the analog bus. Note that ClockPhase in ASDxxCR0 register, bit 6, also affect this bit: Sample + Hold mode is allowed only if ClockPhase = 0. 0 Disable output to analog column bus. 1 Enable output to analog column bus. 6 CompBus Enable output to the comparator bus. 0 Disable output to comparator bus. 1 Enable output to comparator bus. 5 AutoZero Bit for controlling the AutoZero switch. 0 Shorting switch is not active. Input cap branches shorted to opamp input. 1 Shorting switch is enabled during Internal PHI1. Input cap branches shorted to analog ground during Internal PHI1 and to opamp input during Internal PHI2. 4:0 CCap[4:0] Binary encoding for 32 possible capacitor sizes for capacitor CCap. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 167 ASDxxCR3 0,87h 13.2.39 ASDxxCR3 Analog Switch Cap Type D Block Control Register 3 Individual Register Names and Addresses: ASD11CR3 : 0,87h ASD13CR3 : 0,8Fh 7 6 ASD20CR3 : 0,93h ASD22CR3 : 0,9Bh 5 4 3 2 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 ARefMux[1:0] FSW1 FSW0 BSW BMuxSD PWR[1:0] Access : POR Bit Name 0,87h 1 0 This register is one of four registers used to configure a type D switch capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index, n = column index; therefore, ASD13CR3 is a register for an analog PSoC block in row 1 column 3. For additional information, refer to the “Register Definitions” on page 434 in the Switched Capacitor Block chapter. Bits Name Description 7:6 ARefMux[1:0] Encoding for selecting reference input. 00b Analog ground is selected. 01b RefHi input selected. (This is usually the high reference.) 10b RefLo input selected. (This is usually the low reference.) 11b Reference selection is driven by the comparator. (When output comparator node is set high, the input is set to RefHi. When set low, the input is set to RefLo.) 5 FSW1 Bit for controlling gated switches. 0 Switch is disabled. 1 If the FSW1 bit is set to ‘1’, the state of the switch is determined by the AutoZero bit. If the AutoZero bit is ‘0’, the switch is enabled at all times. If the AutoZero bit is ‘1’, the switch is enabled only when the Internal PHI2 is high. 4 FSW0 Bits for controlling gated switches. 0 Switch is disabled. 1 Switch is enabled when PHI1 is high. 3 BSW Enable switching in branch. 0 B branch is a continuous time path. 1 B branch is switched with Internal PHI2 sampling. 2 BMuxSD Encoding for selecting B inputs. (Note that the available mux inputs vary by individual PSoC block.) In the following table, only columns ASD20 and ASD11 are used by the 2 column analog PSoC blocks and all columns are used by the 4 column analog PSoC blocks. ASD20 ASD11 ASD22 ASD13 0 ASD11 ACC00 ASD13 ACC02 1 ASC10 ACC01 ASC12 ACC03 1:0 PWR[1:0] Encoding for selecting one of four power levels. 00b Off 10b Medium 01b Low 11b High 168 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DECx_DH 0,A0h 13.2.40 DECx_DH Decimator Data High Register Individual Register Names and Addresses: DEC0_DH : 0,A0h 0,A0h DEC1_DH : 0,A2h 7 DEC2_DH : 0,A4h 6 5 4 DEC3_DH : 0,A6h 3 2 1 0 RC : XX Access : POR Data High Byte[7:0] Bit Name This register is a dual purpose register and is used to read the high byte of the decimator’s output or clear the decimator. Note that the CY8C28x03 does not have a decimator, and that the CY8C28x13 and CY8C28x23 only have two decimators. When a hardware reset occurs, the internal state of the decimator is reset, but the output data registers (DECx_DH and DECx_DL) are not. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bit Name Description 7:0 Data High Byte[7:0] Read Write Returns the high byte of the decimator. Clears the 16-bit accumulator values for one of the decimators. Either the DECx_DH or DECx_DL register may be written to clear the accumulators (that is, it is not necessary to write both). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 169 DECx_DL 0,A1h 13.2.41 DECx_DL Decimator Data Low Register Individual Register Names and Addresses: DEC0_DL : 0,A1h 0,A1h DEC1_DL : 0,A3h 7 DEC2_DL : 0,A5h 6 5 4 DEC3_DL : 0,A7h 3 2 1 0 RC : XX Access : POR Data Low Byte[7:0] Bit Name This register is a dual purpose register and is used to read the low byte of the decimator’s output or clear the decimator. When a hardware reset occurs, the internal state of the Decimator is reset, but the output data registers (DECx_DH and DECx_DL) are not. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bit Name Description 7:0 Data Low Byte[7:0] Read Write 170 Returns the low byte of the decimator. Clears the 16-bit accumulator values for one of the decimators. Either the DECx_DH or DECx_DL register may be written to clear the accumulators (that is, it is not necessary to write both). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F MULx_X 0,A8h 13.2.42 MULx_X Multiply Input X Register Individual Register Names and Addresses: MUL1_X : 0,A8h 0,A8h MUL0_X : 0,E8h 7 6 5 4 3 2 1 0 W : XX Access : POR Data[7:0] Bit Name This register is one of two multiplicand registers for the signed 8-bit multiplier in the PSoC MAC. This register is for 2 MAC block PSoC devices only. For additional information, refer to the “Register Definitions” on page 478 in the Multiply Accumulate chapter. Bit Name Description 7:0 Data[7:0] X multiplicand for MAC 8-bit multiplier. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 171 MULx_Y 0,A9h 13.2.43 MULx_Y Multiply Input Y Register Individual Register Names and Addresses: MUL1_Y : 0,A9h 0,A9h MUL0_Y : 0,E9h 7 6 5 4 3 2 1 0 W : XX Access : POR Data[7:0] Bit Name This register is one of two multiplicand registers for the signed 8-bit multiplier in the PSoC MAC. This register is for 2 MAC block PSoC devices only. For additional information, refer to the “Register Definitions” on page 478 in the Multiply Accumulate chapter. Bit Name Description 7:0 Data[7:0] Y multiplicand for MAC 8-bit multiplier. 172 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F MULx_DH 0,AAh 13.2.44 MULx_DH Multiply Result High Byte Register Individual Register Names and Addresses: MUL1_DH : 0,AAh 0,AAh MUL0_DH : 0,EAh 7 6 5 4 3 2 1 0 R : XX Access : POR Data[7:0] Bit Name This register holds the most significant byte of the 16-bit product. This register is for 2 MAC block PSoC devices only. For additional information, refer to the “Register Definitions” on page 478 in the Multiply Accumulate chapter. Bit Name Description 7:0 Data[7:0] High byte of MAC multiplier 16-bit product. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 173 MULx_DL 0,ABh 13.2.45 MULx_DL Multiply Result Low Byte Register Individual Register Names and Addresses: MUL1_DL : 0,ABh 0,ABh MUL0_DL : 0,EBh 7 6 5 4 3 2 1 0 R : XX Access : POR Data[7:0] Bit Name This register holds the least significant byte of the 16-bit product. This register is for 2 MAC block PSoC devices only. For additional information, refer to the “Register Definitions” on page 478 in the Multiply Accumulate chapter. Bit Name Description 7:0 Data[7:0] Low byte of MAC multiplier 16-bit product. 174 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F MACx_X/ACCx_DR1 0,ACh 13.2.46 MACx_X/ACCx_DR1 Accumulator Data Register 1 Individual Register Names and Addresses: MAC1_X/ACC1_DR1 : 0,ACh 7 0,ACh MAC0_X/ACC0_DR1 : 0,ECh 6 5 4 3 Access : POR RW : 00 Bit Name Data[7:0] 2 1 0 This is the multiply accumulate X register and the second byte of the accumulated value. This register is only for PSoC devices with two MAC blocks. For additional information, refer to the “Register Definitions” on page 478 in the Multiply Accumulate chapter. Bit Name Description 7:0 Data[7:0] Read Returns the second byte of the 32-bit accumulated value. The second byte is next to the least significant byte for the accumulated value. Write X multiplicand for the MAC 16-bit multiply and 32-bit accumulator. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 175 MACx_Y/ACCx_DR0 0,ADh 13.2.47 MACx_Y/ACCx_DR0 Accumulator Data Register 0 Individual Register Names and Addresses: MAC1_Y/ACC1_DR0 : 0,ADh 7 0,ADh MAC0_Y/ACC0_DR0 : 0,EDh 6 5 4 3 Access : POR RW : 00 Bit Name Data[7:0] 2 1 0 This is the multiply accumulate Y register and the first byte of the accumulated value. This register is only for PSoC devices with two MAC blocks.For additional information, refer to the “Register Definitions” on page 478 in the Multiply Accumulate chapter. Bit Name Description 7:0 Data[7:0] Read Returns the first byte of the 32-bit accumulated value. The first byte is the least significant byte for the accumulated value. Write Y multiplicand for the MAC 16-bit multiply and 32-bit accumulate. 176 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F MACx_CL0/ACCx_DR3 0,AEh 13.2.48 MACx_CL0/ACCx_DR3 Accumulator Data Register 3 Individual Register Names and Addresses: MAC1_CL0/ACC1_DR3 : 0,AEh 7 0,AEh MAC0_CL0/ACC0_DR3 : 0,EEh 6 5 4 3 Access : POR RW : 00 Bit Name Data[7:0] 2 1 0 This is an accumulator clear register and the fourth byte of the accumulated value. This register is for 2 MAC block PSoC devices only. For additional information, refer to the “Register Definitions” on page 478 in the Multiply Accumulate chapter. Bit Name Description 7:0 Data[7:0] Read Returns the fourth byte of the 32-bit accumulated value. The fourth byte is the most significant byte (MSB) for the accumulated value. Write Writing any value to this address will clear all four bytes of the Accumulator. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 177 MACx_CL1/ACCx_DR2 0,AFh 13.2.49 MACx_CL1/ACCx_DR2 Accumulator Data Register 2 Individual Register Names and Addresses: MAC1_CL1/ACC1_DR2 : 0,AFh 7 0,AFh MAC0_CL1/ACC0_DR2 : 0,EFh 6 5 4 3 Access : POR RW : 00 Bit Name Data[7:0] 2 1 0 This is an accumulator clear register and the third byte of the accumulated value. This register is only for PSoC devices with two MAC blocks. For additional information, refer to the “Register Definitions” on page 478 in the Multiply Accumulate chapter. Bit Name Description 7:0 Data[7:0] Read Returns the third byte of the 32-bit accumulated value. The third byte is the next to most significant byte for the accumulated value. Write Writing any value to this address will clear all four bytes of the Accumulator. 178 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RDIxRI x,B0h 13.2.50 RDIxRI Row Digital Interconnect Row Input Register Individual Register Names and Addresses: RDI0RI : x,B0h x,B0h RDI1RI : x,B8h 7 6 RDI2RI : x,C0h 5 4 3 2 1 0 Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] This register is used to control the input mux that determines which global inputs will drive the row inputs. The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. For additional information, refer to the “Register Definitions” on page 329 in the Row Digital Interconnect chapter. Bit Name Description 7:6 RI3[1:0] Select source for row input 3. 00b GIE[3] 01b GIE[7] 10b GIO[3] 11b GIO[7] 5:4 RI2[1:0] Select source for row input 2. 00b GIE[2] 01b GIE[6] 10b GIO[2] 11b GIO[6] 3:2 RI1[1:0] Select source for row input 1. 00b GIE[1] 01b GIE[5] 10b GIO[1] 11b GIO[5] 1:0 RI0[1:0] Select source for row input 0. 00b GIE[0] 01b GIE[4] 10b GIO[0] 11b GIO[4] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 179 RDIxSYN x,B1h 13.2.51 RDIxSYN Row Digital Interconnect Synchronization Register Individual Register Names and Addresses: RDI0SYN : x,B1h x,B1h RDI1SYN : x,B9h 7 6 RDI2SYN : x,C1h 3 2 1 0 Access : POR 5 4 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name RI3SYN RI2SYN RI1SYN RI0SYN This register is used to control the input synchronization. The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 329 in the Row Digital Interconnect chapter. Bit Name Description 3 RI3SYN 0 1 Row input 3 is synchronized to the SYSCLK system clock. Row input 3 is passed without synchronization. 2 RI2SYN 0 1 Row input 2 is synchronized to the SYSCLK system clock. Row input 2 is passed without synchronization. 1 RI1SYN 0 1 Row input 1 is synchronized to the SYSCLK system clock. Row input 1 is passed without synchronization. 0 RI0SYN 0 1 Row input 0 is synchronized to the SYSCLK system clock. Row input 0 is passed without synchronization. 180 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RDIxIS x,B2h 13.2.52 RDIxIS Row Digital Interconnect Input Select Register Individual Register Names and Addresses: RDI0IS : x,B2h x,B2h RDI1IS : x,BAh 7 RDI2IS : x,C2h 6 5 Access : POR Bit Name 3 2 1 0 RW : 0 4 RW : 0 RW : 0 RW : 0 RW : 0 BCSEL[1:0] IS3 IS2 IS1 IS0 This register is used to configure the inputs to the digital row LUTS and select a broadcast driver from another row if present. The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 329 in the Row Digital Interconnect chapter. Bit Name Description 5:4 BCSEL[1:0] When the BCSEL value is equal to the row number, the tri-state buffer that drives the row broadcast net from the input select mux is disabled, so that one of the row’s blocks may drive the local row broadcast net. 00b Row 0 drives row broadcast net. 01b Row 1 drives row broadcast net. 10b Row 2 drives row broadcast net. Reserved for 2 row PSoC devices. 11b Row 3 drives row broadcast net. Reserved for 2 row PSoC devices. 3 IS3 0 1 The ‘A’ input of LUT3 is RO[3]. The ‘A’ input of LUT3 is RI[3]. 2 IS2 0 1 The ‘A’ input of LUT2 is RO[2]. The ‘A’ input of LUT2 is RI[2]. 1 IS1 0 1 The ‘A’ input of LUT1 is RO[1]. The ‘A’ input of LUT1 is RI[1]. 0 IS0 0 1 The ‘A’ input of LUT0 is RO[0]. The ‘A’ input of LUT0 is RI[0]. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 181 RDIxLT0 x,B3h 13.2.53 RDIxLT0 Row Digital Interconnect Logic Table Register 0 Individual Register Names and Addresses: RDI0LT0 : x,B3h x,B3h RDI1LT0 : x,BBh 7 Access : POR Bit Name 6 RDI2LT0 : x,C3h 5 4 3 2 1 RW : 0 RW : 0 LUT1[3:0] LUT0[3:0] 0 This register is used to select the logic function of the digital row LUTS. The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. For additional information, refer to the “Register Definitions” on page 329 in the Row Digital Interconnect chapter. Bit Name Description 7:4 LUT1[3:0] Select logic function for LUT1. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE (continued on next page) 182 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RDIxLT0 x,B3h 13.2.53 3:0 RDIxLT0 (continued) LUT0[3:0] Select logic function for LUT0. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 183 RDIxLT1 x,B4h 13.2.54 RDIxLT1 Row Digital Interconnect Logic Table Register 1 Individual Register Names and Addresses: RDI0LT1 : x,B4h x,B4h RDI1LT1 : x,BCh 7 Access : POR Bit Name 6 RDI2LT1 : x,C4h 5 4 3 2 1 RW : 0 RW : 0 LUT3[3:0] LUT2[3:0] 0 This register is used to select the logic function of the digital row LUTS. The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. For additional information, refer to the “Register Definitions” on page 329 in the Row Digital Interconnect chapter. Bit Name Description 7:4 LUT3[3:0] Select logic function for LUT3. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE (continued on next page) 184 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RDIxLT1 x,B4h 13.2.54 3:0 RDIxLT1 (continued) LUT2[3:0] Select logic function for LUT2. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 185 RDIxRO0 x,B5h 13.2.55 RDIxRO0 Row Digital Interconnect Row Output Register 0 Individual Register Names and Addresses: RDI0RO0 : x,B5h RDI1RO0 : x,BDh RDI2RO0 : x,C5h 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN Access : POR Bit Name x,B5h This register is used to select the global nets that the row outputs drive. The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. For additional information, refer to the “Register Definitions” on page 329 in the Row Digital Interconnect chapter. Bit Name Description 7 GOO5EN 0 1 Disable Row’s LUT1 output to global output. Enable Row’s LUT1 output to GOO[5]. 6 GOO1EN 0 1 Disable Row’s LUT1 output to global output. Enable Row’s LUT1 output to GOO[1]. 5 GOE5EN 0 1 Disable Row’s LUT1 output to global output. Enable Row’s LUT1 output to GOE[5]. 4 GOE1EN 0 1 Disable Row’s LUT1 output to global output. Enable Row’s LUT1 output to GOE[1]. 3 GOO4EN 0 1 Disable Row’s LUT0 output to global output. Enable Row’s LUT0 output to GOO[4]. 2 GOO0EN 0 1 Disable Row’s LUT0 output to global output. Enable Row’s LUT0 output to GOO[0]. 1 GOE4EN 0 1 Disable Row’s LUT0 output to global output. Enable Row’s LUT0 output to GOE[4]. 0 GOE0EN 0 1 Disable Row’s LUT0 output to global output. Enable Row’s LUT0 output to GOE[0]. 186 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RDIxRO1 x,B6h 13.2.56 RDIxRO1 Row Digital Interconnect Row Output Register 1 Individual Register Names and Addresses: RDI0RO1 : x,B6h RDI1RO1 : x,BEh RDI2RO1 : x,C6h 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN Access : POR Bit Name x,B6h This register is used to select the global nets that the row outputs drive. The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. For additional information, refer to the “Register Definitions” on page 329 in the Row Digital Interconnect chapter. Bit Name Description 7 GOO7EN 0 1 Disable Row’s LUT3 output to global output. Enable Row’s LUT3 output to GOO[7]. 6 GOO3EN 0 1 Disable Row’s LUT3 output to global output. Enable Row’s LUT3 output to GOO[3]. 5 GOE7EN 0 1 Disable Row’s LUT3 output to global output. Enable Row’s LUT3 output to GOE[7]. 4 GOE3EN 0 1 Disable Row’s LUT3 output to global output. Enable Row’s LUT3 output to GOE[3]. 3 GOO6EN 0 1 Disable Row’s LUT2 output to global output. Enable Row’s LUT2 output to GOO[6]. 2 GOO2EN 0 1 Disable Row’s LUT2 output to global output. Enable Row’s LUT2 output to GOO[2]. 1 GOE6EN 0 1 Disable Row’s LUT2 output to global output. Enable Row’s LUT2 output to GOE[6]. 0 GOE2EN 0 1 Disable Row’s LUT2 output to global output. Enable Row’s LUT2 output to GOE[2]. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 187 RDIxDSM x,B7h 13.2.57 RDIxDSM Row Digital Interconnect Delta Sigma Modulator Function Select Register Individual Register Names and Addresses: RDI0DSM : x,B7h x,B7h RDI1DSM : x,BFh 7 Access : POR Bit Name 6 RDI2DSM : x,C7h 5 4 3 2 1 RW : 0000 RW : 0000 AVG_SEL[3:0] AVG_EN[3:0] 0 The Row Digital Interconnect Delta Sigma Modulator Register (RDIxDSM) is used to select the Delta Sigma Modulator function on the row outputs. The ‘x’ in the digital register’s name represents the digital row index. Depending on the digital row characteristics of your PSoC device (see the table titled “PSoC Device Characteristics” on page 311), some addresses may not be available. For additional information, refer to the “Register Definitions” on page 329 in the Row Digital Interconnect chapter. Bit Name Description 7:4 AVG_SEL[3:0] Selects digital block output as average-control signal. 0000b DBC00 0001b DBC01 0010b DCC02 0011b DCC03 0100b DBC10 0101b DBC11 0110b DCC12 0111b DCC13 1000b DBC20 1001b DBC21 1010b DCC22 1011b DCC23 1100b low 1101b low 1110b low 1111b low 3:0 AVG_EN[3:0] Enables average function on corresponding RO channel. AVG_EN[0] 0 Disable. 1 Enables average output on ROW[0] output. AVG_EN[1] 0 Disable. 1 Enables average output on ROW[1] output. AVG_EN[2] 0 Disable. 1 Enables average output on ROW[2] output. AVG_EN[3] 0 Disable. 1 Enables average output on ROW[3] output. 188 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CUR_PP 0,D0h 13.2.58 CUR_PP Current Page Pointer Register Individual Register Names and Addresses: 0,D0h CUR_PP: 0,D0h 7 6 5 4 3 2 1 0 RW : 0 Access : POR Page Bits[2:0] Bit Name This register is used to set the effective SRAM page for normal memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 60 in the RAM Paging chapter. Bit Name Description 2:0 Page Bits[2:0] These bits determine which SRAM Page is used for generic SRAM access. See the RAM Paging chapter on page 57 for more information. 000b 001b 010b 011b 100b 101b 110b 111b SRAM Page 0 SRAM Page 1 SRAM Page 2 SRAM Page 3 SRAM Page 4 SRAM Page 5 SRAM Page 6 SRAM Page 7 Note A value beyond the available SRAM for a specific PSoC device, should not be set. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 189 STK_PP 0,D1h 13.2.59 STK_PP Stack Page Pointer Register Individual Register Names and Addresses: 0,D1h STK_PP: 0,D1h 7 6 5 4 3 2 1 0 RW : 0 Access : POR Page Bits[2:0] Bit Name This register is used to set the effective SRAM page for stack memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 60 in the RAM Paging chapter. Bit Name Description 2:0 Page Bits[2:0] These bits determine which SRAM Page is used to hold the stack. See the RAM Paging chapter on page 57 for more information. 000b 001b 010b 011b 100b 101b 110b 111b SRAM Page 0 SRAM Page 1 SRAM Page 2 SRAM Page 3 SRAM Page 4 SRAM Page 5 SRAM Page 6 SRAM Page 7 Note A value beyond the available SRAM for a specific PSoC device, should not be set. 190 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F IDX_PP 0,D3h 13.2.60 IDX_PP Indexed Memory Access Page Pointer Register Individual Register Names and Addresses: 0,D3h IDX_PP: 0,D3h 7 6 5 4 3 2 1 0 RW : 0 Access : POR Page Bits[2:0] Bit Name This register is used to set the effective SRAM page for indexed memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 60 in the RAM Paging chapter. Bit Name Description 2:0 Page Bits[2:0] These bits determine which SRAM Page an indexed memory access operates on. See the “Register Definitions” on page 60 for more information on when this register is active. 000b 001b 010b 011b 100b 101b 110b 111b SRAM Page 0 SRAM Page 1 SRAM Page 2 SRAM Page 3 SRAM Page 4 SRAM Page 5 SRAM Page 6 SRAM Page 7 Note A value beyond the available SRAM for a specific PSoC device, should not be set. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 191 MVR_PP 0,D4h 13.2.61 MVR_PP MVI Read Page Pointer Register Individual Register Names and Addresses: 0,D4h MVR_PP: 0,D4h 7 6 5 4 3 2 1 0 RW : 0 Access : POR Page Bits[2:0] Bit Name This register is used to set the effective SRAM page for MVI read memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 60 in the RAM Paging chapter. Bit Name Description 2:0 Page Bits[2:0] These bits determine which SRAM Page a MVI Read instruction operates on. 000b 001b 010b 011b 100b 101b 110b 111b SRAM Page 0 SRAM Page 1 SRAM Page 2 SRAM Page 3 SRAM Page 4 SRAM Page 5 SRAM Page 6 SRAM Page 7 Note A value beyond the available SRAM for a specific PSoC device, should not be set. 192 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F MVW_PP 0,D5h 13.2.62 MVW_PP MVI Write Page Pointer Register Individual Register Names and Addresses: 0,D5h MVW_PP: 0,D5h 7 6 5 4 3 2 1 0 RW : 0 Access : POR Page Bits[2:0] Bit Name This register is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 60 in the RAM Paging chapter. Bit Name Description 2:0 Page Bits[2:0] These bits determine which SRAM Page a MVI Write instruction operates on. 000b 001b 010b 011b 100b 101b 110b 111b SRAM Page 0 SRAM Page 1 SRAM Page 2 SRAM Page 3 SRAM Page 4 SRAM Page 5 SRAM Page 6 SRAM Page 7 Note A value beyond the available SRAM for a specific PSoC device, should not be set. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 193 I2Cx_CFG 0,D6h 13.2.63 I2Cx_CFG I2C Configuration Register Individual Register Names and Addresses: I2C0_CFG : 0,D6h I2C1_CFG 7 0,D6h : 1,6Bh 6 5 4 1 0 Access : POR RW : 0 RW : 0 RW : 0 3 RW : 0 2 RW : 0 RW : 0 Bit Name PSelect Bus Error IE Stop IE Clock Rate[1:0] Enable Master Enable Slave This register is used to set the basic operating modes, baud rate, and selection of interrupts. Note that the second I2C block is available in the CY8C28x03, CY8C28x23, CY8C28x43, and CY8C28x45 PSoC devices only. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 497 in the I2C chapter. Bit Name Description 6 PSelect I2C Pin Select I2C1 0 P1[2] and P1[6] 1 P3[0] and P3[2] I2C0 P1[7] and P1[5] P1[1] and P1[0] Note Read the I2C chapter for a discussion of the side effects of choosing the P1[0] and P1[1] pair of pins. 5 Bus Error IE Bus Error Interrupt Enable 0 Disabled 1 Enabled. An interrupt is generated on the detection of a Bus Error. 4 Stop IE Stop Interrupt Enable 0 Disabled 1 Enabled. An interrupt is generated on the detection of a Stop Condition. 3:2 Clock Rate[1:0] 00b 01b 10b 11b 1 Enable Master Writing a ‘0’ to both the Enable Master and Enable Slave bits will hold the I2C hardware in reset. 0 Disabled 1 Enabled 0 Enable Slave Writing a ‘0’ to both the Enable Master and Enable Slave bits will hold the I2C hardware in reset. 0 Disabled 1 Enabled 194 100K Standard Mode 400K Fast Mode 50K Standard Mode Reserved CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F I2Cx_SCR 0,D7h 13.2.64 I2Cx_SCR I2C Status and Control Register Individual Register Names and Addresses: 0,D7h I2C0_SCR : 0,E4h : 0,D7h 7 6 5 4 3 2 1 0 RC : 0 RC : 0 RC : 0 RW : 0 RC : 0 RW : 0 RC : 0 RC : 0 Bus Error Lost Arb Stop Status ACK Address Transmit LRB Byte Complete Access : POR Bit Name I2C1_SCR This register is used by both master and slave to control the flow of data bytes and to keep track of the bus state during a transfer. Bits in this register are held in reset until one of the enable bits in I2C_CFG is set. Note that the second I2C block is available in the CY8C28x03, CY8C28x23, CY8C28x43, and CY8C28x45 PSoC devices only. For additional information, refer to the “Register Definitions” on page 497 in the I2C chapter. Bit Name Description 7 Bus Error 0 1 6 Lost Arb 0 1 5 Stop Status 0 1 This status bit must be cleared by firmware by writing a ‘0’ to the bit position. It is never cleared by the hardware. A misplaced Start or Stop condition was detected. This bit is set immediately on lost arbitration; however, it does not cause an interrupt. This status may be checked after the following Byte Complete interrupt. Any Start detect or a write to the Start or Restart generate bits (I2C_MSCR register), when operating in Master mode, will also clear the bit. Lost Arbitration This status bit must be cleared by firmware with write of ‘0’ to the bit position. It is never cleared by the hardware. A Stop condition was detected. 4 ACK Acknowledge Out. This bit is automatically cleared by hardware on a Byte Complete event. 0 NAK the last received byte. 1 ACK the last received byte 3 Address 0 1 2 Transmit Transmit bit is set by firmware to define the direction of the byte transfer. Any Start detect or a write to the Start or Restart generate bits, when operating in Master mode, will also clear the bit. 0 Receive mode 1 Transmit mode 1 LRB Last Received Bit. The value of the ninth bit in a Transmit sequence, which is the acknowledge bit from the receiver. Any Start detect or a write to the Start or Restart generate bits, when operating in Master mode, will also clear the bit. 0 Last transmitted byte was ACKed by the receiver. 1 Last transmitted byte was NAKed by the receiver. This status bit must be cleared by firmware with write of ‘0’ to the bit position. The received byte is a slave address. (continued on next page) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 195 I2Cx_SCR 0,D7h 13.2.64 0 I2Cx_SCR (continued) Byte Complete Transmit/Receive Mode: 0 No completed transmit/receive since last cleared by firmware. Any Start detect or a write to the Start or Restart generate bits, when operating in Master mode, will also clear the bit. Transmit Mode: 1 Eight bits of data have been transmitted and an ACK or NAK has been received. Receive Mode: 1 Eight bits of data have been received. 196 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F I2Cx_DR 0,D8h 13.2.65 I2Cx_DR I2C Data Register Individual Register Names and Addresses: 0,D8h I2C1_DR : 0,67h I2C0_DR : 0,D8h 7 6 5 4 3 Access : POR RW : 00 Bit Name Data[7:0] 2 1 0 This register provides read/write access to the Shift register. Note that the second I2C block is available in the CY8C28x03, CY8C28x23, CY8C28x43, and CY8C28x45 PSoC devices only. This register is read only for received data and write only for transmitted data. For additional information, refer to the “Register Definitions” on page 497 in the I2C chapter. Bit Name Description 7:0 Data[7:0] Read received data or write data to transmit. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 197 I2Cx_MSCR 0,D9h 13.2.66 I2Cx_MSCR I2C Master Status and Control Register Individual Register Names and Addresses: I2C0_MSCR : 0,D9h 7 0,D9h I2C1_MSCR : 0,E5h 6 5 Access : POR Bit Name 4 3 2 1 0 R:0 R:0 RW : 0 RW : 0 Bus Busy Master Mode Restart Gen Start Gen This register implements I2C framing controls and provides Bus Busy status. Note that the second I2C block is available in the CY8C28x03, CY8C28x23, CY8C28x43, and CY8C28x45 PSoC devices only. Bits in this register are held in reset until one of the enable bits in I2C_CFG is set. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 497 in the I2C chapter. Bit Name Description 3 Bus Busy This bit is set to the following. 0 When a Stop condition is detected (from any bus master). 1 When a Start condition is detected (from any bus master). 2 Master Mode This bit is set/cleared by hardware when the device is operating as a master. 0 Stop condition detected, generated by this device. 1 Start condition detected, generated by this device. 1 Restart Gen This bit is cleared by hardware when the Restart generation is complete. 0 Restart generation complete. 1 Generate a Restart condition. 0 Start Gen This bit is cleared by hardware when the Start generation is complete. 0 Start generation complete. 1 198 Generate a Start condition and send a byte (address) to the I2C bus, if bus is not busy. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F INT_CLR0 0,DAh 13.2.67 INT_CLR0 Interrupt Clear Register 0 Individual Register Names and Addresses: 0,DAh INT_CLR0: 0,DAh Access : POR Bit Name 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor This register is used to enable the individual interrupt sources’ ability to clear posted interrupts. When bits in this register are read, a ‘1’ will be returned for every bit position that has a corresponding posted interrupt. When bits in this register are written with a ‘0’ and ENSWINT is not set, posted interrupts will be cleared at the corresponding bit positions. If there was not a posted interrupt, there is no effect. When bits in this register are written with a ‘1’ and ENSWINT is set, an interrupt is posted in the interrupt controller. Note that the ENSWINT bit is in the INT_MSK3 register on page 206. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 7 VC3 Read 0 No posted interrupt for Variable Clock 3. Read 1 Posted interrupt present for Variable Clock 3. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for Variable Clock 3. 6 Sleep Read 0 No posted interrupt for sleep timer. Read 1 Posted interrupt present for sleep timer. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for sleep timer. 5 GPIO Read 0 No posted interrupt for general purpose inputs and outputs (pins). Read 1 Posted interrupt present for GPIO (pins). Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for general purpose inputs and outputs (pins). 4 Analog 3 Read 0 No posted interrupt for analog columns. Read 1 Posted interrupt present for analog columns Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for analog columns. continued on next page) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 199 INT_CLR0 0,DAh 13.2.67 INT_CLR0 (continued) 3 Analog 2 Read 0 No posted interrupt for analog columns. Read 1 Posted interrupt present for analog columns Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for analog columns. 2 Analog 1 Read 0 No posted interrupt for analog columns. Read 1 Posted interrupt present for analog columns Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for analog columns. 1 Analog 0 Read 0 No posted interrupt for analog columns. Read 1 Posted interrupt present for analog columns Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for analog columns. 0 V Monitor Read 0 No posted interrupt for supply voltage monitor. Read 1 Posted interrupt present for supply voltage monitor. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for supply voltage monitor. 200 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F INT_CLR1 0,DBh 13.2.68 INT_CLR1 Interrupt Clear Register 1 Individual Register Names and Addresses: 0,DBh INT_CLR1: 0,DBh 4, 2 Rows 7 6 5 4 3 2 1 0 Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCC13 DCC12 DBC11 DBC10 DCC03 DCC02 DBC01 DBC00 This register is used to clear posted interrupts for digital blocks or generate interrupts. When bits in this register are read, a ‘1’ will be returned for every bit position that has a corresponding posted interrupt. When bits in this register are written with a ‘0’ and ENSWINT is not set, posted interrupts will be cleared at the corresponding bit positions. If there was not a posted interrupt, there is no effect. When bits in this register are written with a ‘1’ and ENSWINT is set, an interrupt is posted in the interrupt controller. Note that the ENSWINT bit is in the INT_MSK3 register on page 206. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 7 DCC13 Digital Communications Block type B, row 1, position 3. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 6 DCC12 Digital Communications Block type B, row 1, position 2. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 5 DBC11 Digital Basic Block type B, row 1, position 1. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. (continued on next page) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 201 INT_CLR1 0,DBh 13.2.68 INT_CLR1 (continued) 4 DBC10 Digital Basic Block type B, row 1, position 0. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 3 DCC03 Digital Communications Block type B, row 0, position 3. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 2 DCC02 Digital Communications Block type B, row 0, position 2. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 1 DBC01 Digital Basic Block type B, row 0, position 1. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 0 DBC00 Digital Basic Block type B, row 0, position 0. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 202 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F INT_CLR2 0,DCh 13.2.69 INT_CLR2 Interrupt Clear Register 2 Individual Register Names and Addresses: 0,DCh INT_CLR2: 0,DCh 3 2 1 0 Access : POR 7 6 5 4 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCC23 DCC22 DBC21 DBC20 This register is used to enable the individual interrupt sources’ ability to clear posted interrupts for digital blocks. When bits in this register are read, a ‘1’ will be returned for every bit position that has a corresponding posted interrupt. When bits in this register are written with a ‘0’ and ENSWINT is not set, posted interrupts will be cleared at the corresponding bit positions. If there was not a posted interrupt, there is no effect. When bits in this register are written with a ‘1’ and ENSWINT is set, an interrupt is posted in the interrupt controller. Note that the ENSWINT bit is in the INT_MSK3 register on page 206. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 3 DCC23 Digital Communications Block type B, row 2, position 3. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 2 DCC22 Digital Communications Block type B, row 2, position 2. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 1 DBC21 Digital Basic Block type B, row 2, position 1. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. 0 DBC20 Digital Basic Block type B, row 2, position 0. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 203 INT_CLR3 0,DDh 13.2.70 INT_CLR3 Interrupt Clear Register 3 Individual Register Names and Addresses: 0,DDh INT_CLR3: 0,DDh 7 Access : POR Bit Name 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Analog 5 Analog 4 RTC SARADC I2C1 I2C0 This register is used to enable the individual interrupt sources’ ability to clear posted interrupts for analog column 5/4, RTC, SARADC and I2Cs. When bits in this register are read, a ‘1’ will be returned for every bit position that has a corresponding posted interrupt. When bits in this register are written with a ‘0’ and ENSWINT is cleared, any posted interrupt will be cleared. If there was not a posted interrupt, there is no effect. When bits in this register are written with a ‘1’ and ENSWINT is set, an interrupt is posted in the interrupt controller. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 5 Analog 5 Read 0 No posted interrupt for analog column 5. Read 1 Posted interrupt present for analog column 5. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for analog column 5. 4 Analog 4 Read 0 No posted interrupt for analog column 4. Read 1 Posted interrupt present for analog column 4. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for analog column 4. 3 RTC Read 0 No posted interrupt for RTC. Read 1 Posted interrupt present for RTC. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for RTC. 2 SARADC Read 0 No posted interrupt for SARADC. Read 1 Posted interrupt present for SARADC. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for SARADC. (continued on next page) 204 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F INT_CLR3 0,DDh 13.2.70 INT_CLR3 (continued) 1 I2C1 Read 0 No posted interrupt for I2C1. Read 1 Posted interrupt present for I2C1. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for I2C1. 0 I2C0 Read 0 No posted interrupt for I2C0. Read 1 Posted interrupt present for I2C0. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for I2C0. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 205 INT_MSK3 0,DEh 13.2.71 INT_MSK3 Interrupt Mask Register 3 Individual Register Names and Addresses: 0,DEh INT_MSK3: 0,DEh 5 4 3 2 1 0 RW : 0 7 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 ENSWINT Analog 5 Analog 4 RTC SARADC I2C1 I2C0 Access : POR Bit Name 6 This register is used to enable the individual sources’ ability to create pending interrupts. When an interrupt is masked off, the mask bit is ‘0’. The interrupt will still post in the interrupt controller. Therefore, clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 7 ENSWINT 0 1 Disable software interrupts. Enable software interrupts. 5 Analog 5 0 1 Mask Analog 5 interrupt Unmask Analog 5 interrupt 4 Analog 4 0 1 Mask Analog 4 interrupt Unmask Analog 4 interrupt 3 RTC 0 1 Mask RTC interrupt Unmask RTC interrupt 2 SARADC 0 1 Mask SARADC interrupt Unmask SARADC interrupt 1 I2C1 0 1 Mask I2C1 interrupt Unmask I2C1 interrupt 0 I2C0 0 1 Mask I2C0 interrupt Unmask I2C0 interrupt 206 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F INT_MSK2 0,DFh 13.2.72 INT_MSK2 Interrupt Mask Register 2 Individual Register Names and Addresses: 0,DFh INT_MSK2: 0,DFh 3 2 1 0 Access : POR 7 6 5 4 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCC23 DCC22 DBC21 DBC20 This register is used to enable the individual sources’ ability to create pending interrupts for digital blocks. When an interrupt is masked off in this register, the mask bit is ‘0’. The interrupt will still post in the interrupt controller. Therefore, clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 3 DCC23 0 1 Mask Digital Communication Block, row 2, position 3 interrupt. Unmask Digital Communication Block, row 2, position 3 interrupt. 2 DCC22 0 1 Mask Digital Communication Block, row 2, position 2 interrupt. Unmask Digital Communication Block, row 2, position 2 interrupt. 1 DBC21 0 1 Mask Digital Basic Block, row 2, position 1 interrupt. Unmask Digital Basic Block, row 2, position 1 interrupt. 0 DBC20 0 1 Mask Digital Basic Block, row 2, position 0 interrupt. Unmask Digital Basic Block, row 2, position 0 interrupt. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 207 INT_MSK0 0,E0h 13.2.73 INT_MSK0 Interrupt Mask Register 0 Individual Register Names and Addresses: 0,E0h INT_MSK0: 0,E0h Access : POR 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor Bit Name This register is used to enable the individual sources’ ability to create pending interrupts. This register is used to enable the individual sources’ ability to create pending interrupts. When an interrupt is masked off, the mask bit is ‘0’. The interrupt will still post in the interrupt controller. Therefore, clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 7 VC3 0 1 Mask VC3 interrupt. Unmask VC3 interrupt. 6 Sleep 0 1 Mask sleep interrupt. Unmask sleep interrupt. 5 GPIO 0 1 Mask GPIO interrupt. Unmask GPIO interrupt. 4 Analog 3 0 1 Mask analog interrupt, column 3. Unmask analog interrupt. 3 Analog 2 0 1 Mask analog interrupt, column 2. Unmask analog interrupt. 2 Analog 1 0 1 Mask analog interrupt, column 1. Unmask analog interrupt. 1 Analog 0 0 1 Mask analog interrupt, column 0. Unmask analog interrupt. 0 V Monitor 0 1 Mask voltage monitor interrupt. Unmask voltage monitor interrupt. 208 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F INT_MSK1 0,E1h 13.2.74 INT_MSK1 Interrupt Mask Register 1 Individual Register Names and Addresses: 0,E1h INT_MSK1: 0,E1h 7 6 5 4 3 2 1 0 Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCC13 DCC12 DBC11 DBC10 DCC03 DCC02 DBC01 DBC00 This register is used to enable the individual sources’ ability to create pending interrupts for digital blocks. When an interrupt is masked off, the mask bit is ‘0’. The interrupt will still post in the interrupt controller. Therefore, clearing the mask bit only prevents a posted interrupt from becoming a pending interrupt. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 7 DCC13 0 1 Mask Digital Communication Block, row 1, position 3 interrupt. Unmask Digital Communication Block, row 1, position 3 interrupt. 6 DCC12 0 1 Mask Digital Communication Block, row 1, position 2 interrupt. Unmask Digital Communication Block, row 1, position 2 interrupt. 5 DBC11 0 1 Mask Digital Basic Block, row 1, position 1interrupt. Unmask Digital Basic Block, row 1, position 1 interrupt. 4 DBC10 0 1 Mask Digital Basic Block, row 1, position 0 interrupt. Unmask Digital Basic Block, row 1, position 0 interrupt. 3 DCC03 0 1 Mask Digital Communication Block, row 0, position 3 off. Unmask Digital Communication Block, row 0, position 3. 2 DCC02 0 1 Mask Digital Communication Block, row 0, position 2 off. Unmask Digital Communication Block, row 0, position 2. 1 DBC01 0 1 Mask Digital Basic Block, row 0, position 1 off. Unmask Digital Basic Block, row 0, position 1. 0 DBC00 0 1 Mask Digital Basic Block, row 0, position 0 off. Unmask Digital Basic Block, row 0, position 0. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 209 INT_VC 0,E2h 13.2.75 INT_VC Interrupt Vector Clear Register Individual Register Names and Addresses: 0,E2h INT_VC: 0,E2h 7 6 5 4 3 2 1 0 RC : 00 Access : POR Pending Interrupt[7:0] Bit Name This register returns the next pending interrupt and clears all pending interrupts when written. For additional information, refer to the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 7:0 Pending Interrupt[7:0] Read Write 210 Returns vector for highest priority pending interrupt. Clears all pending and posted interrupts. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RES_WDT 0,E3h 13.2.76 RES_WDT Reset Watchdog Timer Register Individual Register Names and Addresses: 0,E3h RES_WDT: 0,E3h 7 6 5 4 3 2 1 0 W : 00 Access : POR WDSL_Clear[7:0] Bit Name This register is used to clear the watchdog timer and clear both the watchdog timer and the sleep timer. For additional information, refer to the “Register Definitions” on page 99 in the Sleep and Watchdog chapter. Bit Name Description 7:0 WDSL_Clear[7:0] Any write clears the watchdog timer. A write of 38h clears both the watchdog and sleep timers. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 211 DEC_CR0 0,E6h 13.2.77 DEC_CR0 Decimator Global Control Register 0 Individual Register Names and Addresses: 0,E6h DEC_CR0: 0,E6h 7 6 5 ACC_IGEN[3:0] Bit Name 4 3 2 1 0 RW : 00 Access : POR ICLKS[0] ACE_IGEN[1:0] DCLKS[0] This register contains control bits for selecting the incremental gate enable signal and for selecting the decimator output latch signal. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bits Name Description 7:4 ACC_IGEN[3:0] Incremental Gate Enable. Selects on a column basis which comparator outputs will be gated with the digital block source selected in ICLKS[3:0] 0001b Analog Column 0 0010b Analog Column 1 0100b Analog Column 2 1000b Analog Column 3 3 ICLKS[0] Incremental Gate Source. Along with ICLKS3, ICLKS2, ICLKS1 in the DEC_CR1 register, this bit selects one of the digital blocks in the device. The bit value for a digital block number that does not exist in a specific PSoC should be considered reserved. 0000b Digital block 02 1000b Digital block 22 0001b Digital block 12 1001b Digital block 32 0010b Digital block 01 1010b Digital block 21 0011b Digital block 11 1011b Digital block 31 0100b Digital block 00 1100b Digital block 20 0101b Digital block 10 1101b Digital block 30 0110b Digital block 03 1110b Digital block 23 0111b Digital block 13 1111b Digital block 33 2:1 ACE_IGEN[1:0] Incremental Gate Enable. Selects on a Type E column basis which Type E comparator outputs will be gated with the Digital block source selected in ICLKS[3:0] 01 Analog Type E column 0 10 Analog Type E column 1 0 DCLKS[0] Decimator Latch Select. Along with DCLKS3, DCLKS2, and DCLKS1 in the DEC_CR1 register, this bit selects any one of the digital blocks in the device. 0000b Digital block 02 1000b Digital block 22 0001b Digital block 12 1001b Digital block 32 0010b Digital block 01 1010b Digital block 21 0011b Digital block 11 1011b Digital block 31 0100b Digital block 00 1100b Digital block 20 0101b Digital block 10 1101b Digital block 30 0110b Digital block 03 1110b Digital block 23 0111b Digital block 13 1111b Digital block 33 Note If the decimation rate bits in DECx_CR are set then this setting is overwritten 212 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DEC_CR1 0,E7h 13.2.78 DEC_CR1 Decimator Global Control Register 1 Individual Register Names and Addresses: 0,E7h DEC_CR1: 0,E7h 7 6 5 4 IDEC Bit Name 3 2 1 0 ICLKS[1] DCLKS[3] DCLKS[2] DCLKS[1] RW : 00 Access : POR ICLKS[3] ICLKS[2] This register is used to configure the incremental gate enable signal, and the decimator output latch. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bits Name Description 6 IDEC Invert the Digital Block Latch Control (selected by DCLKS3, DCLKS2, DCLKS1, and DCLKS0). 0 Non-Inverted 1 Inverted 5:3 ICLKS[3:1] Incremental Gate Source. Along with ICLKS[0] in DEC_CR0, selects any one of the digital blocks in the device to gate the output of a analog column comparator If the IGEN bit for that column is set in DEC_CR0. The bit value for a digital block that does not exist should be considered reserved. 0000b Digital block 02 1000b Digital block 22 0001b Digital block 12 1001b Digital block 32 0010b Digital block 01 1010b Digital block 21 0011b Digital block 11 1011b Digital block 31 0100b Digital block 00 1100b Digital block 20 0101b Digital block 10 1101b Digital block 30 0110b Digital block 03 1110b Digital block 23 0111b Digital block 13 1111b Digital block 33 2:0 DCLKS[3:1] Decimator Latch Select. Along with DCLKS0 in DEC_CR0, selects any one of the digital blocks in the device, as the source for the decimator output latch. The bit value for a digital block that does not exist should be considered reserved. 0000b Digital block 02 1000b Digital block 22 0001b Digital block 12 1001b Digital block 32 0010b Digital block 01 1010b Digital block 21 0011b Digital block 11 1011b Digital block 31 0100b Digital block 00 1100b Digital block 20 0101b Digital block 10 1101b Digital block 30 0110b Digital block 03 1110b Digital block 23 0111b Digital block 13 1111b Digital block 33 Note If the decimation rate bits in DECx_CR are set, then this setting is overwritten. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 213 CPU_F x,F7h 13.2.79 CPU_F M8C Flag Register Individual Register Names and Addresses: x,F7h CPU_F: x,F7h 7 Access : POR Bit Name 2 1 0 RL : 0 6 5 RL : 0 4 3 RL : 0 RL : 0 RL : 0 PgMode[1:0] XIO Carry Zero GIE This register provides read access to the M8C flags. The AND f, expr; OR f, expr; and XOR f, expr flag instructions can be used to modify this register. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 48 in the M8C chapter and the “Register Definitions” on page 68 in the Interrupt Controller chapter. Bit Name Description 7:6 PgMode[1:0] 00b 01b 10b 11b Direct Address mode and Indexed Address mode operands are referred to RAM Page 0, regardless of the values of CUR_PP and IDX_PP. Note that this condition prevails on entry to an Interrupt Service Routine when the CPU_F register is cleared. Direct Address mode instructions are referred to page 0. Indexed Address mode instructions are referred to the RAM page specified by the stack page pointer, STK_PP. Direct Address mode instructions are referred to the RAM page specified by the current page pointer, CUR_PP. Indexed Address mode instructions are referred to the RAM page specified by the index page pointer, IDX_PP. Direct Address mode instructions are referred to the RAM page specified by the current page pointer, CUR_PP. Indexed Address mode instructions are referred to the RAM page specified by the stack page pointer, STK_PP. 4 XIO 0 1 2 Carry Set by the M8C CPU Core to indicate whether there has been a carry in the previous logical/arithmetic operation. 0 No carry 1 Carry 1 Zero Set by the M8C CPU Core to indicate whether there has been a zero result in the previous logical/ arithmetic operation. 0 Not equal to zero 1 Equal to zero 0 GIE 0 1 214 Normal register address space Extended register address space. Primarily used for configuration. M8C will not process any interrupts. Interrupt processing enabled. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F IDACx_D 0,FCh 13.2.80 IDACx_D IDAC Data Register Individual Register Names and Addresses: IDAC1_D : 0,FCh IDAC0_D 7 0,FCh : 0,FDh 6 5 4 3 2 1 0 RW : 00 Access : POR IDACx Bit Name This register specifies the 8-bit multiplying factor that determines the output DAC current. For additional information, refer to the “Register Definitions” on page 528 in the I/O Analog Multiplexer chapter. Bits Name Description 7:0 IDACx This 8-bit value selects the number of current units that combine to form the DAC current. This current then drives the analog mux bus when DAC mode is enabled in the IDAC_CRx register. For example, a setting of 80h means that the charging current will be 128 current units. The current unit size depends on the range setting in the IDAC_CRx register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 215 CPU_SCR1 x,FEh 13.2.81 CPU_SCR1 System Status and Control Register 1 Individual Register Names and Addresses: x,FEh CPU_SCR1: x,FEh 4 3 2 R:0 7 RW : 0 R:0 RW : 0 RW : 0 IRESS SLIMO ECO EXW ECO EX IRAMDIS Access : POR Bit Name 6 5 1 0 This register is used to convey the status and control of events related to internal resets and watchdog reset. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 54 in the SROM chapter or “Register Definitions” on page 89 of the External Crystal Oscillator (ECO) chapter. Bit Name Description 7 IRESS This bit is read only. 0 Boot phase only executed once. 1 Boot phase occurred multiple times. 4 SLIMO Reduces frequency of the internal main oscillator (IMO). 0 IMO produces 24 MHz 1 Slow IMO (6 MHz) 3 ECO EXW ECO Exists Written. 1 The ECO Exists Written bit has been written with a ‘1’ or ‘0’ and is now locked. 0 The ECO Exists Written bit has never been written in User mode. 2 ECO EX ECO Exists (write once – see the explanation in “Register Definitions” on page 99). 1 ECO operation exists (set/reset OSC_CR[7] to enable/disable). 0 ECO operation does not exist. 32 kHz clock source is locked to operate from the ILO. 0 IRAMDIS 0 1 216 SRAM is initialized to 00h after POR, XRES, and WDR. Addresses 03h to D7h of SRAM Page 0 are not modified by WDR. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CPU_SCR0 x,FFh 13.2.82 CPU_SCR0 System Status and Control Register 0 Individual Register Names and Addresses: x,FFh CPU_SCR0: x,FFh 5 4 3 Access : POR R:0 7 6 RC : 0 RC : 1 RW : 0 2 1 RW : 0 0 Bit Name GIES WDRS PORS Sleep STOP This register is used to convey the status and control of events for various functions of a PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 99 in the Sleep and Watchdog chapter. Bit Name Description 7 GIES Global interrupt enable status. It is recommended that the user read the Global Interrupt Enable Flag bit from the CPU_F register on page 214. This bit is Read Only for GIES. Its use is discouraged, as the Flag register is now readable at address x,F7h (read only). 5 WDRS Watchdog Reset Status. This bit may not be set by user code; however, it may be cleared by writing it with a ‘0’. 0 No Watchdog Reset has occurred. 1 Watchdog Reset has occurred. 4 PORS Power On Reset Status. This bit may not be set by user code; however, it may be cleared by writing it with a ‘0’. 0 Power On Reset has not occurred and watchdog timer is enabled. 1 Will be set after external reset or Power On Reset. 3 Sleep Set by the user to enable the CPU sleep state. CPU will remain in Sleep mode until any interrupt is pending. 0 Normal operation 1 Sleep 0 STOP 0 1 M8C is free to execute code. M8C is halted. Can only be cleared by POR, XRES, or WDR. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 217 PRTxDM0 1,00h 13.3 Bank 1 Registers The following registers are all in bank 1 and are listed in address order. Registers that are in both Bank 0 and Bank 1 are listed in address order in the section titled “Bank 0 Registers” on page 127. 13.3.1 PRTxDM0 Port Drive Mode Bit Register 0 Individual Register Names and Addresses: PRT0DM0 : 1,00h PRT4DM0 : 1,10h 1,00h PRT1DM0 : 1,04h PRT5DM0 : 1,14h 7 6 PRT2DM0 : 1,08h 5 4 PRT3DM0 : 1,0Ch 3 2 1 0 RW : 0 Access : POR Drive Mode 0[7:0] Bit Name This register is one of three registers whose combined value determines the unique Drive mode of each bit in a GPIO port. In register PRTxDM0 there are eight possible drive modes for each port pin. Three mode bits are required to select one of these modes, and these three bits are spread into three different registers (PRTxDM0, “PRTxDM1” on page 219, and “PRTxDM2” on page 130). The bit position of the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the three Drive Mode register bits that control the Drive mode for that pin (for example, Bit[2] in PRT0DM0, bit[2] in PRT0DM1, and bit[2] in PRT0DM2). The three bits from the three registers are treated as a group. These are referred to as DM2, DM1, and DM0, or together as DM[2:0]. All Drive mode bits are shown in the sub-table below ([210] refers to the combination (in order) of bits in a given bit position); however, this register only controls the least significant bit (LSb) of the Drive mode. For Port 5, the upper nibble of this register will return the last data bus value when read and should be masked off prior to using this information. For additional information, refer to the “Register Definitions” on page 76 in the GPIO chapter. Bit Name Description 7:0 Drive Mode 0[7:0] Bit 0 of the Drive mode, for each of 8-port pins, for a GPIO port. [210] 000b 001b 010b 011b 100b 101b 110b Pin Output High Strong Strong High-Z Resistive Slow + strong Slow + strong High-Z Pin Output Low Resistive Strong High-Z Strong High-Z Slow + strong High-Z 111b High-Z Slow + strong Notes Digital input enabled. Reset state. Digital input disabled for zero power. I2C Compatible mode. Note A bold digit, in the table, signifies that the digit is used in this register. 218 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F PRTxDM1 1,01h 13.3.2 PRTxDM1 Port Drive Mode Bit Register 1 Individual Register Names and Addresses: PRT0DM1 : 1,01h PRT4DM1 : 1,11h 1,01h PRT1DM1 : 1,05h PRT5DM1 : 1,15h 7 6 PRT2DM1 : 1,09h 5 4 PRT3DM1 : 1,0Dh 3 2 1 0 RW : FFh Access : POR Drive Mode 1[7:0] Bit Name This register is one of three registers whose combined value determines the unique Drive mode of each bit in a GPIO port. In register PRTxDM1 there are eight possible drive modes for each port pin. Three mode bits are required to select one of these modes, and these three bits are spread into three different registers (“PRTxDM0” on page 218, PRTxDM1, and “PRTxDM2” on page 130). The bit position of the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the three Drive Mode register bits that control the Drive mode for that pin (for example, Bit[2] in PRT0DM0, bit[2] in PRT0DM1, and bit[2] in PRT0DM2). The three bits from the three registers are treated as a group. These are referred to as DM2, DM1, and DM0, or together as DM[2:0]. All Drive mode bits are shown in the sub-table below ([210] refers to the combination (in order) of bits in a given bit position); however, this register only controls the middle bit of the Drive mode. For Port 5, the upper nibble of this register will return the last data bus value when read and should be masked off prior to using this information. For additional information, refer to the “Register Definitions” on page 76 in the GPIO chapter. Bit Name Description 7:0 Drive Mode 1[7:0] Bit 1 of the Drive mode, for each of 8-port pins, for a GPIO port. [210] 000b 001b 010b 011b 100b 101b 110b Pin Output High Strong Strong High-Z Resistive Slow + strong Slow + strong High-Z Pin Output Low Resistive Strong High-Z Strong High-Z Slow + strong High-Z 111b High-Z Slow + strong Notes Digital input enabled. Reset state. Digital input disabled for zero power. I2C Compatible mode. Note A bold digit, in the table, signifies that the digit is used in this register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 219 PRTxIC0 1,02h 13.3.3 PRTxIC0 Port Interrupt Control Register 0 Individual Register Names and Addresses: PRT0IC0 : 1,02h PRT4IC0 : 1,12h 1,02h PRT1IC0 : 1,06h PRT5IC0 : 1,16h 7 6 PRT2IC0 : 1,0Ah 5 4 PRT3IC0 : 1,0Eh 3 2 1 0 RW : 00 Access : POR Interrupt Control 0[7:0] Bit Name This register is one of two registers whose combined value determine the unique Interrupt mode of each bit in a GPIO port. In register PRTxIC0 there are four possible interrupt modes for each port pin. Two mode bits are required to select one of these modes and these two bits are spread into two different registers (PRTxIC0 and “PRTxIC1” on page 221). The bit position of the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the interrupt control register bits that control the Interrupt mode for that pin (for example, Bit[2] in PRT0IC0 and bit[2] in PRT0IC1). The two bits from the two registers are treated as a group. In the sub-table below, “[0]” refers to the combination (in order) of bits in a given position, one bit from PRTxIC1 and one bit from PRTxIC0. For Port 5, the upper nibble of this register will return the last data bus value when read and should be masked off prior to using this information. For additional information, refer to the “Register Definitions” on page 76 in the GPIO chapter. Bit Name Description 7:0 Interrupt Control 0[7:0] [10] 00b 01b 10b 11b ‘ Interrupt Type Disabled Low High Change from last read Note A bold digit, in the table, signifies that the digit is used in this register. 220 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F PRTxIC1 1,03h 13.3.4 PRTxIC1 Port Interrupt Control Register 1 Individual Register Names and Addresses: PRT0IC1 : 1,03h PRT4IC1 : 1,13h 1,03h PRT1IC1 : 1,07h PRT5IC1 : 1,17h 7 6 PRT2IC1 : 1,0Bh 5 4 PRT3IC1 : 1,0Fh 3 2 1 0 RW : 00 Access : POR Interrupt Control 1[7:0] Bit Name This register is one of two registers whose combined value determine the unique Interrupt mode of each bit in a GPIO port. In register PRTxIC1 there are four possible interrupt modes for each port pin. Two mode bits are required to select one of these modes and these two bits are spread into two different registers (“PRTxIC0” on page 220 and PRTxIC1). The bit position of the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the interrupt control register bits that control the Interrupt mode for that pin (for example, Bit[2] in PRT0IC0 and bit[2] in PRT0IC1). The two bits from the two registers are treated as a group. In the sub-table below, “[1]” refers to the combination (in order) of bits in a given position, one bit from PRTxIC1 and one bit from PRTxIC0. For Port 5, the upper nibble of this register will return the last data bus value when read and should be masked off prior to using this information. For additional information, refer to the “Register Definitions” on page 76 in the GPIO chapter. Bit Name Description 7:0 Interrupt Control 1[7:0] [10] 00b 01b 10b 11b ‘ Interrupt Type Disabled Low High Change from last read Note A bold digit, in the table, signifies that the digit is used in this register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 221 DxCxxFN 1,20h 13.3.5 DxCxxFN Digital Basic/Communications Type C Block Function Register Individual Register Names and Addresses: DBC00FN : 1,20h DBC10FN : 1,30h DBC20FN : 1,40h DBC01FN : 1,24h DBC11FN : 1,34h DBC21FN : 1,44h DCC02FN : 1,28h DCC12FN : 1,38h DCC22FN : 1,48h 4 DCC03FN : 1,2Ch DCC13FN : 1,3Ch DCC23FN : 1,4Ch 7 6 5 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Data Invert BCEN End Single Mode[1:0] Function[2:0] Access : POR Bit Name 1,20h 3 2 1 0 This register contains the primary Mode and Function bits that determine the function of the block. Before changing any of the configuration registers (DxCxxFN, DxCxxIN, and DxCxxOU), disable the corresponding digital block by setting bit 0 in the CR0 or DxCxxCR0 register to ‘0’. The values in the DxCxxFN register should not be changed while the block is enabled. After all configuration changes are made, enable the block by setting bit 0 in the DxCxxCR0 register to ‘1’. The naming convention for this register is as follows. The first ‘x’ in the digital register’s name represents either “B” for basic or “C” for communication. For rows of digital PSoC blocks and their registers, the second ‘x’ set represents <Prefix>mn<Suffix>, where m = row index, n = column index. Therefore, DCC12FN is a digital communication register for a digital PSoC block in row 1 column 2. Depending on the digital row characteristics of your PSoC device, some addresses may not be available. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7 Data Invert 0 1 6 BCEN Enable Primary Function Output to drive the broadcast net. 0 Disable 1 Enable 5 End Single 0 1 4:3 Mode[1:0] These bits are function dependent and are described by function as follows. Timer or Counter: Mode[0] signifies the interrupt type. 0 Interrupt on Terminal Count 1 Interrupt on Compare True Mode[1] signifies the compare type. 0 Compare on Less Than or Equal 1 Compare on Less Than CRCPRS: Mode[1:0] are encoded as the Compare Type. 00b Compare on Equal 01b Compare on Less Than or Equal 10b Reserved 11b Compare on Less Than Data input is non-inverted. Data input is inverted. Block is not the end of a chained function or the function is not chainable. Block is the end of a chained function or a standalone block in a chainable function. (continued on next page) 222 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxFN 1,20h 13.3.5 4:3 (cont.) DxCxxFN (continued) PWMDBL Same as Dead Band that follows: Dead Band: Mode[1:0] are encoded as the Kill Type. 00b Synchronous Restart KILL mode 01b Disable KILL mode 10b Asynchronous KILL mode 11b Reserved UART: Mode[0] signifies the Direction. 0 Receiver 1 Transmitter Mode[1] signifies the Interrupt Type. 0 Interrupt on TX Reg Empty 1 Interrupt on TX Complete SPI: Mode[0] signifies the Type. 0 Master 1 Slave Mode[1] signifies the Interrupt Type. 0 Interrupt on TX Reg Empty 1 Interrupt on SPI Complete DSM DSM Kill Mode 0 “KILL Async” Mode 1 “KILL Disable” Mode DSM Multiplication Mode 0 Density Multiplier for Single Reference 1 Density Multiplier for Bipolar Reference (Mode[0]) 2:0 Function[2:0] 000b 001b 010b 011b 100b 101b 110b 111b Timer (chainable) Counter (chainable) CRCPRS (chainable) PWMDBL Dead Band UART (DCCxx blocks only) SPI (DCCxx blocks only) DSM CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 223 DxCxxIN 1,21h 13.3.6 DxCxxIN Digital Basic/Communications Type C Block Input Register Individual Register Names and Addresses: DBC00IN : 1,21h DBC10IN : 1,31h DBC20IN : 1,41h 1,21h DBC01IN : 1,25h DBC11IN : 1,35h DBC21IN : 1,45h 7 Access : POR Bit Name 6 DCC02IN : 1,29h DCC12IN : 1,39h DCC22IN : 1,49h 5 4 DCC03IN : 1,2Dh DCC13IN : 1,3Dh DCC23IN : 1,4Dh 3 2 1 RW : 0 RW : 0 Data Input[3:0] Clock Input[3:0] 0 These registers are used to select the data and clock inputs. Before changing any of the configuration registers (DxCxxFN, DxCxxIN, and DxCxxOU), disable the corresponding digital block by setting bit 0 in the CR0 or DxCxxCR0 register to ‘0’. The values in this register should not be changed while the block is enabled. After all configuration changes are made, enable the block by setting bit 0 in the CR0 register to ‘1’. The naming convention for this register is as follows. The first ‘x’ in the digital register’s name represents either “B” for basic or “C” for communication. For rows of digital PSoC blocks and their registers, the second ‘x’ set represents <Prefix>mn<Suffix>, where m = row index, n = column index. Therefore, DCC12IN is a digital communication register for a digital PSoC block in row 1 column 2. Depending on the digital row characteristics of your PSoC device, some addresses may not be available. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 Data Input[3:0] 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Low (0) High (1) Row broadcast net Chain function to previous block (low (0) in block DBC00IN) Analog column comparator 0 Analog column comparator 1 Analog column comparator 2 Analog column comparator 3 Row output 0 Row output 1 Row output 2 Row output 3 Row input 0 Row input 1 Row input 2 Row input 3 (continued on next page) 224 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxIN 1,21h 13.3.6 3:0 DxCxxIN (continued) Clock Input[3:0] 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Clock disabled (low) VC3 Row broadcast net Previous block primary output (low for DBC00) SYSCLKX2 VC1 VC2 CLK32K Row output 0 Row output 1 Row output 2 Row output 3 Row input 0 Row input 1 Row input 2 Row input 3 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 225 DxCxxOU 1,22h 13.3.7 DxCxxOU Digital Basic/Communications Type C Block Output Register Individual Register Names and Addresses: DBC00OU : 1,22h DBC10OU : 1,32h DBC20OU : 1,42h 1,22h DBC01OU : 1,26h DBC11OU : 1,36h DBC21OU : 1,46h 7 Access : POR Bit Name 6 DCC02OU : 1,2Ah DCC12OU : 1,3Ah DCC22OU : 1,4Ah 5 4 3 DCC03OU : 1,2Eh DCC13OU : 1,3Eh DCC23OU : 1,4Eh 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] This register is used to control the connection of digital block outputs to the available row interconnect and control clock resynchronization. Before changing any of the configuration registers (DxCxxFN, DxCxxIN, and DxCxxOU), disable the corresponding digital block by setting bit 0 in the CR0 or DxCxxCR0 register to ‘0’. The values in this register should not be changed while the block is enabled. After all configuration changes are made, enable the block by setting bit 0 in the DxCxxCR0 register to ‘1’. The naming convention for this register is as follows. The first ‘x’ in the digital register’s name represents either “B” for basic or “C” for communication. For rows of digital PSoC blocks and their registers, the second ‘x’ set represents <Prefix>mn<Suffix>, where m = row index, n = column index. Therefore, DBC12OU is a digital basic register for a digital PSoC block in row 1 column 2. Depending on the digital row characteristics of your PSoC device, some addresses may not be available. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:6 AUXCLK 00b 01b 10b 11b 5 AUXEN Auxiliary I/O Enable (function dependent) No sync Synchronize Synchronize SYSCLK 16-to-1 clock mux output Output of 16-to-1 clock mux to SYSCLK Output of 16-to-1 clock mux to SYSCLKX2 Directly connect SYSCLK to block clock input All Functions except SPI Slave: Enable Auxiliary Output Driver 0 Disabled 1 Enabled SPI Slave: Input Source for SS_ 0 Row Input [3:0], as selected by the AUX IO Select bits 1 Force SS_ Active 4:3 AUX IO Select[1:0] Auxiliary I/O Select Function Output (function dependent) All Functions except SPI Slave: Row Output Select 00b Row Output 0 01b Row Output 1 10b Row Output 2 11b Row Output 3 SPI Slave Source for SS_ Input if AUXEN =0. 00b Row Input 0 01b Row Input 1 10b Row Input 2 11b Row Input 3 (continued on next page) 226 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxOU 1,22h 13.3.7 DxCxxOU (continued) 4:3 (cont.) AUX IO Select[1:0] SPI Slave Source for SS_ Input if AUXEN =1. 00b Force SS_ Active 01b Reserved 10b Reserved 11b Reserved 2 OUTEN Enable Primary Function Output Driver 0 Disabled 1 Enabled 1:0 Output Select[1:0] Row Output Select for Primary Function Output 00b Row Output 0 01b Row Output 1 10b Row Output 2 11b Row Output 3 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 227 DxCxxCR1 (Timer Control:000) 1,23h 13.3.8 DxCxxCR1 (Timer Control:000) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: DBC00CR1 : 1,23h DBC10CR1 : 1,33h DBC20CR1 : 1,43h 1,23h DBC01CR1 : 1,27h DBC11CR1 : 1,37h DBC21CR1 : 1,47h 7 6 5 DCC02CR1 : 1,2Bh DCC12CR1 : 1,3Bh DCC22CR1 : 1,4Bh 4 3 DCC03CR1 : 1,2Fh DCC13CR1 : 1,3Fh DCC23CR1 : 1,4Fh 2 1 0 Access : POR RW : 0000 RW : 0 RW : 00 RW : 0 Bit Name Multi-Shot KILL_INV KILL_MD[1:0] KILL_INT This register is the second Control register for a Timer, if the DxCxxFN register is configured as a ‘000’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 Multi-Shot == 0 Multi-Shot > 0 No Multi-shot function, and function will run repeatedly. Multi-shot number. 3 KILL_INV 0 1 2:1 KILL_MD[1:0] KILL mode. 0Xb NO KILL mode. 10b "Kill Sync" mode: When the kill signal is asserted the DR0 Register is reloaded on every block clock. The multi-shot counter is reloaded on the first rising edge of the block clock after the kill signal is deasserted. This is also when the down counter starts counting again. When the kill signal is asserted both digital block outputs are held low. 11b "Kill Disable" mode: The block is immediately disabled when the kill signal is asserted. Both block outputs are held low. The block must be restarted in firmware. 0 KILL_INT 0 1 228 Normal Kill signal Invert Kill signal Kill signal is not interrupt source Kill signal is interrupt source and has highest priority CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxCR1 (Counter Control:001) 1,23h 13.3.9 DxCxxCR1 (Counter Control:001) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: DBC00CR1 : 1,23h DBC10CR1 : 1,33h DBC20CR1 : 1,43h 1,23h DBC01CR1 : 1,27h DBC11CR1 : 1,37h DBC21CR1 : 1,47h 7 6 5 DCC02CR1 : 1,2Bh DCC12CR1 : 1,3Bh DCC22CR1 : 1,4Bh 4 3 DCC03CR1 : 1,2Fh DCC13CR1 : 1,3Fh DCC23CR1 : 1,4Fh 2 1 0 Access : POR RW : 0000 RW : 0 RW : 00 RW : 0 Bit Name Multi-Shot KILL_INV KILL_MD[1:0] KILL_INT This register is the second Control register for a Counter, if the DxCxxFN register is configured as a ‘001’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 Multi-Shot Has same meaning as in Timer. 3 KILL_INV Same as Timer. 2:1 KILL_MD[1:0] Same as Timer. 0 KILL_INT Same as Timer. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 229 DxCxxCR1 (CRCPRS Control:010) 1,23h 13.3.10 DxCxxCR1 (CRCPRS Control:010) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: DBC00CR1 : 1,23h DBC10CR1 : 1,33h DBC20CR1 : 1,43h 1,23h DBC01CR1 : 1,27h DBC11CR1 : 1,37h DBC21CR1 : 1,47h 7 6 5 DCC02CR1 : 1,2Bh DCC12CR1 : 1,3Bh DCC22CR1 : 1,4Bh 4 3 DCC03CR1 : 1,2Fh DCC13CR1 : 1,3Fh DCC23CR1 : 1,4Fh 2 1 0 Access : POR RW : 0000 RW : 0 RW : 00 RW : 0 Bit Name Multi-Shot KILL_INV KILL_MD[1:0] KILL_INT This register is the second Control register for a CRCPRS, if the DxCxxFN register is configured as a ‘010’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 Multi-Shot Has same meaning as in Timer. 3 KILL_INV Same as Timer. 2:1 KILL_MD[1:0] Same as Timer. 0 KILL_INT Same as Timer. 230 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxCR1 (PWMDBL Control:011) 1,23h 13.3.11 DxCxxCR1 (PWMDBL Control:011) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: DBC00CR1 : 1,23h DBC10CR1 : 1,33h DBC20CR1 : 1,43h 1,23h DBC01CR1 : 1,27h DBC11CR1 : 1,37h DBC21CR1 : 1,47h 7 6 5 DCC02CR1 : 1,2Bh DCC12CR1 : 1,3Bh DCC22CR1 : 1,4Bh 4 3 DCC03CR1 : 1,2Fh DCC13CR1 : 1,3Fh DCC23CR1 : 1,4Fh 2 1 Access : POR RW : 0000 RW : 0 RW : 000 Bit Name Multi-Shot STARTINV DBW[2:0] 0 This register is the second Control register for a PWMDBL, if the DxCxxFN register is configured as a ‘011’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7:4 Multi-Shot Has same meaning as in Timer. 0 means the function is not in PPG mode. Otherwise the function is in PPG mode and the iteration time by one trigger is specified by these 4 multi-shot bits. 3 STARTINV 0 1 2:0 DBW[2:0] Dead Band Width: 000b No Dead Band 010b 2 BLKCLK Dead Band 100b 8 BLKCLK Dead Band 110b 32 BLKCLK Dead Band Normal Start signal Invert Start signal 001b 011b 101b 111b 1 BLKCLK Dead Band 4 BLKCLK Dead Band 16 BLKCLK Dead Band 64 BLKCLK Dead Band CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 231 DxCxxCR1 (Dead Band Control:100) 1,23h 13.3.12 DxCxxCR1 (Dead Band Control:100) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: DBC00CR1 : 1,23h DBC10CR1 : 1,33h DBC20CR1 : 1,43h 1,23h DBC01CR1 : 1,27h DBC11CR1 : 1,37h DBC21CR1 : 1,47h 7 6 5 DCC02CR1 : 1,2Bh DCC12CR1 : 1,3Bh DCC22CR1 : 1,4Bh 4 3 DCC03CR1 : 1,2Fh DCC13CR1 : 1,3Fh DCC23CR1 : 1,4Fh 2 1 0 RW : 0 Access : POR KILL_INT Bit Name This register is the second Control register for a Dead Band Generator, if the DxCxxFN register is configured as a ‘100’. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 0 KILL_INT 0 1 232 Kill signal is not interrupt source. Kill signal is interrupt source, and has highest priority. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxCR1 (SPIM Control:0-110) 1,23h 13.3.13 DxCxxCR1 (SPIM Control:0-110) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: DBC00CR1 : 1,23h DBC10CR1 : 1,33h DBC20CR1 : 1,43h 1,23h DBC01CR1 : 1,27h DBC11CR1 : 1,37h DBC21CR1 : 1,47h 5 DCC02CR1 : 1,2Bh DCC12CR1 : 1,3Bh DCC22CR1 : 1,4Bh 4 3 DCC03CR1 : 1,2Fh DCC13CR1 : 1,3Fh DCC23CR1 : 1,4Fh 7 6 Access : POR RW : 0 RW : 0 RW : 00000 2 Bit Name Chain LSB SPI Length 1 0 This register is the second Control register for a SPIM, if the DxCxxFN register is configured as a ‘110’. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7 Chain 0 1 6 LSB 0 Block is MSB in SPI chain. 1 Block is LSB in SPI chain. Note Bit 7 must be set to use this bit. 4:0 SPI Length Specifies the SPI length in chain mode. Block is not part of an SPI chain. Block is in an SPI chain CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 233 DxCxxCR1 (SPIS Control:0-110) 1,23h 13.3.14 DxCxxCR1 (SPIS Control:0-110) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: DBC00CR1 : 1,23h DBC10CR1 : 1,33h DBC20CR1 : 1,43h 1,23h DBC01CR1 : 1,27h DBC11CR1 : 1,37h DBC21CR1 : 1,47h 5 DCC02CR1 : 1,2Bh DCC12CR1 : 1,3Bh DCC22CR1 : 1,4Bh 4 3 DCC03CR1 : 1,2Fh DCC13CR1 : 1,3Fh DCC23CR1 : 1,4Fh 7 6 2 Access : POR RW : 0 RW : 0 RW : 00000 Bit Name Chain LSB SPI Length 1 0 This register is the second Control register for a SPIS, if the DxCxxFN register is configured as a ‘110’. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 7 Chain 0 1 6 LSB 0 Block is MSB in SPI chain. 1 Block is LSB in SPI chain. Note Bit 7 must be set to use this bit 4:0 SPI Length Specifies the SPI length in chain mode. 234 Block is not part of an SPI chain. Block is in an SPI chain. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DxCxxCR1 (DSM Control:111) 1,23h 13.3.15 DxCxxCR1 (DSM Control:111) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: DBC00CR1 : 1,23h DBC10CR1 : 1,33h DBC20CR1 : 1,43h 1,23h DBC01CR1 : 1,27h DBC11CR1 : 1,37h DBC21CR1 : 1,47h 7 6 5 DCC02CR1 : 1,2Bh DCC12CR1 : 1,3Bh DCC22CR1 : 1,4Bh 4 Access : POR Bit Name 3 DCC03CR1 : 1,2Fh DCC13CR1 : 1,3Fh DCC23CR1 : 1,4Fh 2 1 0 RW : 0 RW : 0 KILL_INV KILL_INT This register is the second Control register for a DSM, if the DxCxxFN register is configured as a ‘111’. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 348 in the Digital Blocks chapter. Bit Name Description 3 KILL_INV 0 1 Do not invert Kill signal. Invert Kill signal. 0 KILL_INT 0 1 Select CO as interrupt. Select KILL as interrupt. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 235 CLK_CR0 1,60h 13.3.16 CLK_CR0 Analog Column Clock Control Register 0 Individual Register Names and Addresses: 1,60h CLK_CR0: 1,60h 7 6 Bit Name 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 AColumn3[1:0] AColumn2[1:0] AColumn1[1:0] AColumn0[1:0] Access : POR This register is used to select the clock source for an individual analog column. Each column has two bits that select the column clock input source. The resulting column clock frequency is the selected input clock frequency divided by four. For additional information, refer to the “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 7:6 AColumn3[1:0] Clock selection for column 3. 00b Variable Clock 1 (VC1) 01b Variable Clock 2 (VC2) 10b Analog Clock 0 (ACLK0) 11b Analog Clock 1 (ACLK1) 5:4 AColumn2[1:0] Clock selection for column 2. 00b Variable Clock 1 (VC1) 01b Variable Clock 2 (VC2) 10b Analog Clock 0 (ACLK0) 11b Analog Clock 1 (ACLK1) 3:2 AColumn1[1:0] Clock selection for column 1. 00b Variable Clock 1 (VC1) 01b Variable Clock 2 (VC2) 10b Analog Clock 0 (ACLK0) 11b Analog Clock 1 (ACLK1) 1:0 AColumn0[1:0] Clock selection for column 0. 00b Variable Clock 1 (VC1) 01b Variable Clock 2 (VC2) 10b Analog Clock 0 (ACLK0) 11b Analog Clock 1 (ACLK1) 236 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CLK_CR1 1,61h 13.3.17 CLK_CR1 Analog Clock Source Control Register 1 Individual Register Names and Addresses: 1,61h CLK_CR1: 1,61h 7 6 5 4 3 2 1 Access : POR RW : 0 RW : 0 RW : 0 Bit Name SHDIS ACLK1[2:0] ACLK0[2:0] 0 This register is used to select the clock source for an individual analog column. There are two ranges of Digital PSoC blocks shown. The range is set by bits ACLK0R and ACLK1R in register CLK_CR2. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 6 SHDIS Sample and hold disable. 0 Enabled 1 Disabled 5:3 ACLK1[2:0] Select the clocking source for Analog Clock 1. 000b Digital Basic Block 00 or 20 001b Digital Basic Block 01 or 21 010b Digital Communication Block 02 or 22 011b Digital Communication Block 03 or 23 100b Digital Basic Block 10 101b Digital Basic Block 11 110b Digital Communication Block 12 111b Digital Communication Block 13 Note Selection determined by setting of ACLK1R. 2:0 ACLK0[2:0] Select the clocking source for Analog Clock 0. 000b Digital Basic Block 00 or 20 001b Digital Basic Block 01 or 21 010b Digital Communication Block 02 or 22 011b Digital Communication Block 03 or 23 100b Digital Basic Block 10 101b Digital Basic Block 11 110b Digital Communication Block 12 111b Digital Communication Block 13 Note Selection determined by setting of ACLK1R. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 237 ABF_CR0 1,62h 13.3.18 ABF_CR0 Analog Output Buffer Control Register 0 Individual Register Names and Addresses: 1,62h ABF_CR0: 1,62h Access : POR Bit Name 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 ACol1Mux ACol2Mux ABUF1EN ABUF2EN ABUF0EN ABUF3EN Bypass PWR This register controls analog input muxes from Port 0. For additional information, see “Register Definitions” on page 419 in the Analog Input Configuration chapter. Bits Name Description 7 ACol1Mux 0 1 Set column 1 input to column 1 input mux output. (1 Column: selects among P0[6,4,2,0]) Set column 1 input to column 0 input mux output. (1 Column: selects among P0[7,5,3,1]) 6 ACol2Mux 0 1 Set column 2 input to column 2 input mux output. (1 Column: selects among P0[7,5,3,1]) Set column 2 input to column 3 input mux output. (1 Column: selects among P0[6,4,2,0]) 5 ABUF1EN Enables the analog output buffer for Analog Column 1 (Pin P0[5]). 0 Disable analog output buffer. 1 Enable analog output buffer. 4 ABUF2EN Enables the analog output buffer for Analog Column 2 (Pin P0[4]). 0 Disable analog output buffer. 1 Enable analog output buffer. 3 ABUF0EN Enables the analog output buffer for Analog Column 0 (Pin P0[3]). 0 Disable analog output buffer. 1 Enable analog output buffer. 2 ABUF3EN Enables the analog output buffer for Analog Column 3 (Pin P0[2]). 0 Disable analog output buffer. 1 Enable analog output buffer. 1 Bypass Connects the positive input of the amplifier(s) directly to the output(s). Amplifiers must be disabled when in Bypass mode. 0 Disable 1 Enable 0 PWR Determines power level of all output buffers. 0 Low output power 1 High output power 238 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F AMD_CR0 1,63h 13.3.19 AMD_CR0 Analog Modulation Control Register 0 Individual Register Names and Addresses: 1,63h AMD_CR0: 1,63h 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 0 RW : 0 AMOD2[2:0] AMOD0[2:0] 0 This register is used to select the modulator bits used with each column. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 6:4 AMOD2[2:0] Analog modulation control signal selection for column 2. 000b Zero (off) 001b Global Output Bus, even bus bit 1 (GOE[1]) 010b Global Output Bus, even bus bit 0 (GOE[0]) 011b Row 0 Broadcast Bus 100b Analog Column Comparator 0 101b Analog Column Comparator 1 110b Analog Column Comparator 2 111b Analog Column Comparator 3 2:0 AMOD0[2:0] Analog modulation control signal selection for column 0. 000b Zero (off) 001b Global Output Bus, even bus bit 1 (GOE[1]) 010b Global Output Bus, even bus bit 0 (GOE[0]) 011b Row 0 Broadcast Bus 100b Analog Column Comparator 0 101b Analog Column Comparator 1 110b Analog Column Comparator 2 111b Analog Column Comparator 3 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 239 CMP_GO_EN 1,64h 13.3.20 CMP_GO_EN Comparator Bus to Global Outputs Enable Register Individual Register Names and Addresses: 1,64h CMP_GO_EN: 1,64h 7 6 3 2 Access : POR RW : 0 RW : 0 5 RW : 0 4 RW : 0 RW : 0 1 RW : 0 0 Bit Name GOO5 GOO1 SEL1[1:0] GOO4 GOO0 SEL0[1:0] This register controls options for driving the analog comparator bus and column clock to the global bus. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 7 GOO5 Drives the selected column 1 signal to GOO5. 0 No connection to GOO5 from column 1 1 Column 1 drives GOO5 6 GOO1 Drives the selected column 1 signal to GOO1. 0 No connection to GOO1 from column 1 1 Column 1 drives GOO1 5:4 SEL1[1:0] Selects the column 1 signal to output. 00b Comparator bus output 01b PHI1 column clock 10b PHI2 column clock 11b Selected column clock direct (1X) 3 GOO4 Drives the selected column 0 signal to GOO4. 0 No connection to GOO4 from column 0 1 Column 0 drives GOO4 2 GOO0 Drives the selected column 0 signal to GOO0. 0 No connection to GOO0 from column 0 1 Column 0 drives GOO0 1:0 SEL0[1:0] Selects the column 0 signal to output. 00b Comparator bus output 01b PHI1 column clock 10b PHI2 column clock 11b Selected column clock direct (1X) 240 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CMP_GO_EN1 1,65h 13.3.21 CMP_GO_EN1 Comparator Bus to Global Outputs Enable Register 1 Individual Register Names and Addresses: 1,65h CMP_GO_EN1: 1,65h 7 6 3 2 Access : POR RW : 0 RW : 0 5 RW : 0 4 RW : 0 RW : 0 1 RW : 0 0 Bit Name GOO7 GOO3 SEL3[1:0] GOO6 GOO2 SEL2[1:0] This register controls options for driving the analog comparator bus and column clock to the global bus. It is only used by the CY8C28x43, CY8C28x45, and CY8C28x52 PSoC devices. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 7 GOO7 Drives the selected column 3 signal to GOO7. 0 No connection to GOO7 from column 3 1 Column 3 drives GOO7 6 GOO3 Drives the selected column 3 signal to GOO3. 0 No connection to GOO3 from column 3 1 Column 3 drives GOO3 5:4 SEL3[1:0] Selects the column 3 signal to output. 00b Comparator bus output. 01b PHI1 column clock. 10b PHI2 column clock. 11b PHI1 unsynchronized comparator bus. 3 GOO6 Drives the selected column 2 signal to GOO6. 0 No connection to GOO6 from column 2 1 Column 2 drives GOO6 2 GOO2 Drives the selected column 2 signal to GOO2. 0 No connection to GOO2 from column 2 1 Column 2 drives GOO2 1:0 SEL2[1:0] Selects the column 2 signal to output. 00b Comparator bus output. 01b PHI1 column clock. 10b PHI2 column clock. 11b PHI1 unsynchronized comparator bus. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 241 AMD_CR1 1,66h 13.3.22 AMD_CR1 Analog Modulation Control Register 1 Individual Register Names and Addresses: 1,66h AMD_CR1: 1,66h 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 0 RW : 0 AMOD3[2:0] AMOD1[2:0] 0 This register is used to select the modulator bits used with each column. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 6:4 AMOD3[2:0] Analog modulation control signal selection for column 3. 000b Zero (off) 001b Global Output Bus, even bus bit 1 (GOE[1]) 010b Global Output Bus, even bus bit 0 (GOE[0]) 011b Row 0 Broadcast Bus 100b Analog Column Comparator 0 101b Analog Column Comparator 1 110b Analog Column Comparator 2 111b Analog Column Comparator 3 2:0 AMOD1[2:0] Analog modulation control signal selection for column 1. 000b Zero (off) 001b Global Output Bus, even bus bit 1 (GOE[1]) 010b Global Output Bus, even bus bit 0 (GOE[0]) 011b Row 0 Broadcast Bus 100b Analog Column Comparator 0 101b Analog Column Comparator 1 110b Analog Column Comparator 2 111b Analog Column Comparator 3 242 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ALT_CR0 1,67h 13.3.23 ALT_CR0 Analog LUT Control Register 0 Individual Register Names and Addresses: 1,67h ALT_CR0: 1,67h 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 0 RW : 0 LUT1[3:0] LUT0[3:0] 0 This register is used to select the logic function. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 7:4 LUT1[3:0] Select 1 of 16 logic functions for output of comparator bus 1. For a 1 column device, LUT input B = 0. 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 3:0 LUT0[3:0] Function FALSE A AND B A AND B A A AND B B A XOR B A OR B A NOR B A XNOR B B A OR B A A OR B A NAND B TRUE Select 1 of 16 logic functions for output of comparator bus 0. 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Function FALSE A AND B A AND B A A AND B B A XOR B A OR B A NOR B A XNOR B B A OR B A A OR B A NAND B TRUE CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 243 ALT_CR1 1,68h 13.3.24 ALT_CR1 Analog LUT Control Register 1 Individual Register Names and Addresses: 1,68h ALT_CR1: 1,68h 4 COLUMN Access : POR Bit Name 7 6 5 4 3 2 1 RW : 0 RW : 0 LUT3[3:0] LUT2[3:0] 0 This register is used to select the logic function performed by the LUT for each analog column. This register is for 4 column PSoC devices only. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 7:4 LUT3[3:0] Select 1 of 16 logic functions for output of comparator bus 3. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE 3:0 LUT2[3:0] Select 1 of 16 logic functions for output of comparator bus 2. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE 244 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F CLK_CR2 1,69h 13.3.25 CLK_CR2 Analog Clock Source Control Register 2 Individual Register Names and Addresses: 1,69h CLK_CR2: 1,69h 4 COLUMN 7 6 Access : POR Bit Name 5 4 3 2 1 0 RW : 0 RW : 0 ACLK1R ACLK0R This register, in conjunction with the CLK_CR1 and CLK_CR0 registers, selects a digital block as a source for analog column clocking. This register is for 4 column PSoC devices only. These bits extend the range of the Digital PSoC blocks that may be selected for the analog clock source in CLK_CR1 from eight to 16. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 400 in the Analog Interface chapter. Bits Name Description 3 ACLK1R Analog Clock 1 Selection Range 0 Select Digital PSoC Block, from row 0 and 1 (00-13). 1 Select Digital PSoC Block, from row 2 and 3 (20-33). 0 ACLK0R Analog Clock 0 Selection Range 0 Select Digital PSoC Block, from row 0 and 1 (00-13). 1 Select Digital PSoC Block, from row 2 and 3 (20-33). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 245 AMUX_CFG1 1,6Ah 13.3.26 AMUX_CFG1 Analog Mux Config Register 1 Individual Register Names and Addresses: 1,6Ah AMUX_CFG1: 1,6Ah Access : POR Bit Name 7 6 5 4 RW : 0 RW : 0 RW : 0 RW : 0 3 RW : 0 2 1 RW : 0 0 ABusMux3 ABusMux2 ACol3Mux ACol0Mux MUXCLK1[2:0] EN1 This register controls the inputs to the analog column muxes. For additional information, refer to the “Register Definitions” on page 528 in the I/O Analog Multiplexer chapter. Bits Name 7 ABusMux3 6 5 Description 0 1 Select analog column 3 input to analog column 3 Input Select mux output. Select analog column 3 input to the analog mux bus right. 0 1 Select analog column 2 input to analog column 2 Input Select mux output. Select analog column 2 input to the analog mux bus left. 0 Select analog column 3 input to analog column 3 input mux output. (Selects among P0[6,4,2,0].) Select analog column 3 input to analog column 2 input mux output. (Selects among P0[7,5,3,1].) ABusMux2 ACol3Mux 1 4 ACol0Mux 0 1 Select analog column 0 input to analog column 0 input mux output. (Selects among P0[7,5,3,1].) Select analog column 0 input to analog column 1 input mux output. (Selects among P0[6,4,2,0].) 3:1 MUXCLK1[2:0] Selects a precharge clock source for analog mux bus right (AMuxBus1) connections. It can be suppressed by bit 5 in AMUX_CLK register. 000b Precharge clock is off; no switching. 001b VC1 010b VC2 011b Row1 Broadcast 100b Analog column 1 clock 101b Analog column 3 clock 110b Analog column 5 clock 111b Reserved 0 EN1 0 1 246 Disable MUXCLK Right output. Enable MUXCLK Right output. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F SADC_TSCR0 1,71h 13.3.27 SADC_TSCR0 SAR ADC Trigger Source Control Register 0 Individual Register Names and Addresses: 1,71h SADC_TSCR0: 1,71h 7 6 3 2 1 0 RW : 0000 5 RW : 0 RW : 0 RW : 0 RW : 0 TS_INCMP_SEL[3:0] INCMP_INV INCMP_EN CMPH_EN CMPL_EN Access : POR Bit Name 4 This register controls the selection for an external trigger source. The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, refer to the “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7:4 TS_INCMP_SEL Indicates the external source (GIE[7:0) or internal source (ACC_ACMP[3:0] or ACE_ACMP[1:0]). 0000b to 0111b Select GIE[0:7]. 1000b to 1011b Select ACC_ACMP[0:3]. 1100b to 1101b Select ACE_ACMP[0:1]. 1110b to 1111b Reserved. 3 INCMP_INV 1 Use inverted version of INCMP 2 INCMP_EN 1 Enable INCMP trigger source 1 CMPH_EN 1 Enable high channel trigger source 0 CMPL_EN 1 Enable low channel trigger source Note Enable both CMPH_EN and CMPL_EN to use 16-bit trigger source. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 247 SADC_TSCR1 1,72h 13.3.28 SADC_TSCR1 SAR ADC Trigger Source Control Register 1 Individual Register Names and Addresses: 1,72h SADC_TSCR1: 1,72h 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 000 RW : 000 TS_CMPH_SEL[2:0] TS_CMPL_SEL[2:0] 0 This register controls the selection of digital blocks for high and low channel comparison. The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, refer to the “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 6:4 TS_CMPH_SEL[2:0] Selects a digital block's DR0 register to compare against SADC_TSCMPH. When the comparison is equal an ADC sample is triggered. 000b DBB00 001b DBB01 010b DCB02 011b DCB03 100b DBB10 101b DBB11 110b DCB12 111b DCB13 2:0 TS_CMPL_SEL[2:0] Selects a digital block's DR0 register to compare against SADC_TSCMPL. When the comparison is equal an ADC sample is triggered. 000b DBB00 001b DBB01 010b DCB02 011b DCB03 100b DBB10 101b DBB11 110b DCB12 111b DCB13 248 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACE_AMD_CR0 1,73h 13.3.29 ACE_AMD_CR0 Analog Type-E Modulation Control Register 0 Individual Register Names and Addresses: 1,73h ACE_AMD_CR0: 1,73h 2L* Column 7 6 5 4 3 2 1 0 RW : 0 Access : POR AMOD4[3:0] Bit Name * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is used to select the modulator bits used for analog column 4. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 3:0 AMOD4[3:0] Analog modulation control signal selection for column 4. 0000b Zero (off) 0001b Global Output Bus, even bus bit 1 (GOE[1]) 0010b Global Output Bus, even bus bit 0 (GOE[0]) 0011b Row 0 Broadcast Bus 0100b Analog Column Comparator 4 0101b Analog Column Comparator 5 0110b Analog Column Comparator 0 0111b Analog Column Comparator 1 1000b Reserved (Zero) 1001b Row 1 Broadcast Bus 1010b Row 1 Broadcast Bus 1011b Reserved (High) 1100b Analog Column Comparator 4, single synchronized 1101b Analog Column Comparator 5, single synchronized 1110b Analog Column Comparator 2 1111b Analog Column Comparator 3 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 249 ACE_AMX_IN 1,75h 13.3.30 ACE_AMX_IN Analog Type-E Input Select Register Individual Register Names and Addresses: 1,75h ACE_AMX_IN: 1,75h 2L* Column 7 6 5 4 Access : POR Bit Name 3 2 1 0 RW : 0 RW : 0 ACI5[1:0] ACI4[1:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register controls the analog muxes that feed signals in from port pins into the analog column 5/4. Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 3:2 ACI5[1:0] Selects the Analog Column Mux 5. 00b ACM5 P0[0] 01b ACM5 P0[2] 10b ACM5 P0[4] 11b ACM5 P0[6] 1:0 ACI4[1:0] Selects the Analog Column Mux 4. 00b ACM4 P0[1] 01b ACM4 P0[3] 10b ACM4 P0[5] 11b ACM4 P0[7] 250 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACE_CMP_CR0 1,76h 13.3.31 ACE_CMP_CR0 Analog Type-E Comparator Bus 0 Register Individual Register Names and Addresses: 1,76h ACE_CMP_CR0: 1,76h 2L* Column 7 6 Access : POR Bit Name 5 4 3 2 1 0 R:0 RW : 0 COMP[5:4] AINT[5:4] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is used to poll the analog 5/4 column comparator bits and select column interrupts. Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 5 COMP[5] Comparator bus state for column 5. This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the CLDISx bits in the ACE_CMP_CR1 register). If the comparator latch disable bits are set, then this bit is transparent to the comparator bus in the analog array. 4 COMP[4] Comparator bus state for column 4. This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the CLDISx bits in the ACE_CMP_CR1 register). If the comparator latch disable bits are set, then this bit is transparent to the comparator bus in the analog array. 1 AINT[5] Controls the selection of the analog comparator interrupt for column 5. 0 The comparator data bit from the column is the input to the interrupt controller. 1 The terminal count for the dedicated incremental PWM is the interrupt source. 0 AINT[4] Controls the selection of the analog comparator interrupt for column 4. 0 The comparator data bit from the column is the input to the interrupt controller. 1 The terminal count for the dedicated incremental PWM is the interrupt source. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 251 ACE_CMP_CR1 1,77h 13.3.32 ACE_CMP_CR1 Analog Type-E Comparator Bus 1 Register Individual Register Names and Addresses: 1,77h ACE_CMP_CR1: 1,77h 2L* Column Access : POR Bit Name 7 6 5 4 RW : 0 RW : 0 CLDIS[5 CLDIS[4] 3 2 1 0 * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is used to override the analog column comparator synchronization for analog columns 4 and 5. By default, the analog comparator bus is synchronized by the column clock and driven to the digital comparator bus for use in the digital array and the interrupt controller. The CLDIS bits are used to bypass the synchronization. This bypass mode can be used in power down operation to wake the device out of sleep, as a result of an analog column interrupt. Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 5 CLDIS[5] Controls the comparator output latch, column 5. 0 Comparator bus synchronization is enabled. 1 Comparator bus synchronization is disabled. 4 CLDIS[4] Controls the comparator output latch, column 4. 0 Comparator bus synchronization is enabled. 1 Comparator bus synchronization is disabled. 252 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACE_CMP_GI_EN 1,79h 13.3.33 ACE_CMP_GI_EN Analog Type-E Columns Compare Bus to Global Inputs Control Register Individual Register Names and Addresses: 1,79h ACE_CMP_GI_EN : 1,79h 2L* Column Access : POR 7 6 3 2 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 GIO5 GIO1 SEL4[1:0] GIO4 GIO0 SEL5[1:0] Bit Name 5 4 1 0 * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register controls options for driving the analog comparator bus and column clock to the global bus. For additional information, refer to the “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 7 GIO5 Drives the selected column 5 signal to GIO5. 0 No connection to GIO5 from column 5 1 Column 5 drives GIO5 6 GIO1 Drives the selected column 5 signal to GIO1. 0 No connection to GIO1 from column 5 1 Column 5 drives GIO1 5:4 SEL5[1:0] Selects the column 5 signal to output. 00b Comparator bus output 01b Column clock 10b Comparator output after single sync 11b Column clock gated with the synchronized comparator bus 3 GIO4 Drives the selected column 4 signal to GIO4. 0 No connection to GIO4 from column 4 1 Column 4 drives GIO4 2 GIO0 Drives the selected column 4 signal to GIO0. 0 No connection to GIO0 from column 4 1 Column 4 drives GIO0 1:0 SEL4[1:0] Selects the column 4 signal to output. 00b Comparator bus output 01b Column clock 10b ADC PWM output 11b Column clock gated with the synchronized comparator bus CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 253 ACE_ALT_CR0 1,7Ah 13.3.34 ACE_ALT_CR0 Analog Type-E LUT Control Register 0 Individual Register Names and Addresses: 1,7Ah ACE_ALT_CR0: 1,7Ah 2L* Column Access : POR Bit Name 7 6 5 4 3 2 1 RW : 0 RW : 0 LUT5[3:0] LUT4[3:0] 0 * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is used to select the logic function. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 7:4 LUT5[3:0] Select 1 of 16 logic functions for output of comparator bus 5. LUT input B = 0. Function 0000b FALSE 0011b A 1100b A 1111b TRUE 3:0 LUT4[3:0] Select 1 of 16 logic functions for output of comparator bus 4. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b A 0100b A AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b B 1011b A OR B 1100b A 1101b A OR B 1110b A NAND B 1111b TRUE 254 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACE_ABF_CR0 1,7Bh 13.3.35 ACE_ABF_CR0 Analog Type-E Output Buffer Control Register 0 Individual Register Names and Addresses: 1,7Bh ACE_ABF_CR0: 1,7Bh 2L* Column Access : POR Bit Name 7 6 RW : 0 RW : 0 ACE1Mux ACE0Mux 5 4 3 2 1 0 * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register controls analog input muxes from Port 0. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 7 ACE1Mux 0 1 Set analog column 5 input to analog column 5 input mux output. (P0[6,4,2,0]) Set analog column 5 input to analog column 4 input mux output. (P0[7,5,3,1]) 6 ACE0Mux 0 1 Set analog column 4 input to analog column 4 input mux output (P0[7,5,3,1]). Set analog column 4 input to analog column 5 input mux output (P0[6,4,2,0]). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 255 ACExxCR1 1,7Dh 13.3.36 ACExxCR1 Analog Continuous Time Type E Block Control Register 1 Individual Register Names and Addresses: ACE00CR1 : 1,7Dh 2L* Column Access : POR Bit Name 1,7Dh ACE01CR1 : 1,8Dh 7 6 5 4 3 2 1 RW : 0 RW : 0 RW : 0 CompBus NMux[2:0] PMux[2:0] 0 * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is one of two registers used to configure the type E continuous time PSoC block. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 6 CompBus Enable output to the comparator bus. The comparator bus is always driven from the CT block. 0 Disable output to comparator bus. 1 Enable output to comparator bus. 5:3 NMux[2:0] Encoding for negative input select. Note that available mux inputs vary by individual PSoC block. ACE00 ACE01 000b ACE01 ACE00 001b VBG VBG 010b Reserved Reserved 011b Muxbus0 Muxbus1 Chip-wide analog mux bus. 100b 101b 110b 111b FB# ASE10 ASE11 Port Inputs(AC4) FB# ASE11 ASE10 Port Inputs (AC5) # Feedback. Gain = 1, configuration only. 2:0 256 PMux[2:0] Encoding for positive input select. Note that available mux inputs vary by individual PSoC block. ACE00 ACE01 000b Reserved VTEMP 001b Port Inputs (AC4 Port Inputs (AC5) 010b ACE01 ACE00 011b VBG VBG 100b ASE10 ASE11 101b ASE11 ASE10 110b Reserved Reserved 111b Muxbus0 Muxbus1 Chip-wide analog mux bus. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACExxCR2 1,7Eh 13.3.37 ACExxCR2 Analog Continuous Time Type E Block Control Register 2 Individual Register Names and Addresses: ACE00CR2 : 1,7Eh 2L* Column 1,7Eh ACE01CR2 : 1,8Eh 7 6 5 4 3 2 Access : POR Bit Name 1 0 RW : 0 RW : 0 FullRange PWR * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is one of two registers used to configure the type E continuous time PSoC block. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 1 FullRange 0 1 Input range includes Vss but not Vdd. Rail-to-rail input range, with approximately 10 A additional cell current. 0 PWR 0 1 Powers off both the CT and SC blocks in the column. Enables the column’s analog blocks. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 257 ASExxCR0 1,7Fh 13.3.38 ASExxCR0 Analog Switch Cap Type E Block Control Register 0 Individual Register Names and Addresses: ASE10CR0 : 1,7Fh 2L* Column Access : POR 1,7Fh ASE11CR0 : 1,8Fh 7 6 5 4 3 2 1 0 RW : 0 FVal Bit Name * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is used to configure a type E switched capacitor PSoC block. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 7 FVal F Capacitor value selection bit. 0 Slower integration in the SC block (higher accuracy) 1 Faster integration (lower accuracy) 258 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F SADC_TSCMPL 1,81h 13.3.39 SADC_TSCMPL SAR ADC Trigger Source Compare Low Register Individual Register Names and Addresses: 1,81h SADC_TSCMPL: 1,81h 7 6 5 4 3 2 1 0 RW : 00 Access : POR TS_CMPL[7:0] Bit Name This byte contains the low channel comparison value. This value is compared against the DR0 register of the digital block chosen in TS_CMPL_SEL. When the comparison is true, an ADC conversion is triggered. Note SADC_TSCMPL and SADC_TSCMPH can be combined to form a 16-bit comparison. The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, refer to the “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7:0 TS_CMPL The compare value of low channel. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 259 SADC_TSCMPH 1,82h 13.3.40 SADC_TSCMPH SAR ADC Trigger Source Compare High Register Individual Register Names and Addresses: 1,82h SADC_TSCMPH: 1,82h 7 6 5 4 3 2 1 0 RW : 00 Access : POR TS_CMPH[7:0] Bit Name This byte contains the high channel comparison value. This value is compared against the DR0 register of the digital block chosen in TS_CMPH_SEL. When the comparison is true, an ADC conversion is triggered. Note SADC_TSCMPL and SADC_TSCMPH can be combined to form a 16-bit comparison. The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, refer to the “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7:0 TS_CMPH The compare value of high channel. 260 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACE_AMD_CR1 1,83h 13.3.41 ACE_AMD_CR1 Analog Type-E Modulation Control Register 1 Individual Register Names and Addresses: 1,83h ACE_AMD_CR1: 1,83h 2L* Column 7 6 5 4 3 2 1 0 RW : 0 Access : POR AMOD5[3:0] Bit Name * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is used to select the modulator bits used with analog column 5. Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 3:0 AMOD5[3:0] Analog modulation control signal selection for column 5. 0000b Zero (off) 0001b Global Output Bus, even bus bit 1 (GOE[1]) 0010b Global Output Bus, even bus bit 0 (GOE[0]) 0011b Row 0 Broadcast Bus 0100b Analog Column Comparator 4 0101b Analog Column Comparator 5 0110b Analog Column Comparator 0 0111b Analog Column Comparator 1 1000b Reserved (Zero) 1001b Row 1 Broadcast Bus 1010b Row 2 Broadcast Bus 1011b Reserved (High) 1100b Analog Column Comparator 4, single synchronized 1101b Analog Column Comparator 5, single synchronized 1110b Analog Column Comparator 2 1111b Analog Column Comparator 3 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 261 ACE_PWM_CR 1,85h 13.3.42 ACE_PWM_CR ADC PWM Control Register Individual Register Names and Addresses: 1,85h ACE_PWM_CR: 1,85h 2L* Column 7 6 5 Access : POR Bit Name 4 3 2 1 0 RW : 0 RW : 0 RW : 0 HIGH[2:0] LOW[1:0] PWMEN * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register controls the parameters for the dedicated ADC PWM. This PWM signal can be selected to gate one or more comparator bus signals (as enabled by bits 7:4 of the DEL_CR0 register). In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. When the HIGH[2:0] bits are configured with a value other than zero, this PWM source overrides the digital block sources for gating as defined by ICLKS3, ICLKS2, ICLKS1, and ICLKS0 in the DEC_CR0 and DEC_CR1 registers. Bits Name Description 5:3 HIGH[2:0] 000b 001b 010b 011b 100b 101b 110b 111b The dedicated PWM is not in use. The gating signal reverts to a digital block output as selected by the ICLKS bits in the DEC_CR0 and DEC_CR1 registers. High time is 1 VC3 period. High time is 2 VC3 periods. High time is 4 VC3 periods. High time is 8 VC3 periods. High time is 16 VC3 periods. Reserved Reserved 2:1 LOW[1:0] 00b 01b 10b 11b No PWM low time, only the terminal count is generated. Low time is 1 VC3 period. Low time is 2 VC3 periods. Low time is 3 VC3 periods. 0 PWMEN 0 1 Disable the dedicated PWM. Enable the dedicated PWM. 262 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACE_ADCx_CR 1,86h 13.3.43 ACE_ADCx_CR ADC Column 0 and Column 1 Configuration Register Individual Register Names and Addresses: ACE_ADC0_CR : 1,86h 2L* Column Access : POR Bit Name 7 1,86h ACE_ADC1_CR : 1,87h 6 5 R:0 RW : 0 CMPST LOREN 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 SHEN CBSRC AUTO ADCEN * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register controls the single slope ADC in each column. ACE_ADC0_CR is the ADC column 0 configuration register and ACE_ADC1_CR is the ADC column 1 configuration register. Reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bit Name Description 7 CMPST This bit is the state of the comparator at the end of an ADC conversion period (as defined by the falling edge of the gating PWM). It is read only. 0 The comparator tripped during the previous conversion ramp. 1 The comparator did not trip during the previous conversion ramp. 6 LOREN This bit controls an approximate 4-to-1 range on the ADC current source. 0 Normal current range 1 Low current range 5 SHEN Sample and Hold Enable. The sample and hold function is only applicable to the PMUX (positive) comparator input. 0 Disabled 1 Enabled 3 CBSRC Digital Comparator Bus Source. There are two possible sources for the digital comparator bus in conjunction with ADC operation. 0 Digital comparator bus is driven with synchronized and gated analog comparator output. Implements a Counter Enable interface. 1 Digital comparator bus is driven with the selected PWM terminal count. Implements a Timer Capture interface. 2 AUTO Auto ADC Mode. The bit allows for a periodic signal to control ADC sequencing. 0 Auto mode off. 1 Auto mode on. Set this bit for ADC operation. The voltage ramp generator and sample and hold circuitry are controlled by the selected PWM signal (digital block or dedicated PWM). 0 ADCEN Enable. Configures the ADC for operation, power up. 0 Disabled, Powered Down. 1 Enabled CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 263 ACE_CLK_CR0 1,89h 13.3.44 ACE_CLK_CR0 Analog Type-E Column Clock Control Register 0 Individual Register Names and Addresses: 1,89h ACE_CLK_CR0: 1,89h 2L* Column 7 6 5 4 3 2 Bit Name 1 0 RW : 0 RW : 0 AColumn5[1:0] AColumn4[1:0] Access : POR * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is used to select the clock source for an individual analog column. Each column has two bits that select the column clock input source. The resulting column clock frequency is the selected input clock frequency divided by the ACE_CLK_CR3 register. Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 3:2 AColumn5[1:0] Clock selection for column 5. 00b Variable Clock 1 (VC1) 01b Variable Clock 2 (VC2) 10b Analog Clock 4 (ACLK4) 11b Analog Clock 5 (ACLK5) 1:0 AColumn4[1:0] Clock selection for column 4. 00b Variable Clock 1 (VC1) 01b Variable Clock 2 (VC2) 10b Analog Clock 4 (ACLK4) 11b Analog Clock 5 (ACLK4) 264 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ACE_CLK_CR1 1,8Ah 13.3.45 ACE_CLK_CR1 Analog Type E Columns Clock Control Register 1 Individual Register Names and Addresses: 1,8Ah ACE_CLK_CR1 : 1,8Ah 2L* Column 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 0 RW : 0 ACLK5[3:0] ACLK4[3:0] 0 * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register is used to select the clock source for an individual analog column. Each nibble is used to form 16:1 MUX to select 1 out of 16 dig row output for Type-E column clocks. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 7:4 ACLK5[3:0] Select the clocking source for Analog Clock 5 0000b Digital Basic Block 00 0001b Digital Basic Block 01 0010b Digital Communication Block 02 0011b Digital Communication Block 03 0100b Digital Basic Block 10 0101b Digital Basic Block 11 0110b Digital Communication Block 12 0111b Digital Communication Block 13 1000b Digital Basic Block 20 1001b Digital Basic Block 21 1010b Digital Communication Block 22 1011b Digital Communication Block 23 1100b Reserved 1101b Reserved 1110b Reserved 1111b Reserved 3:0 ACLK4[3:0] Select the clocking source for Analog Clock 4 0000b Digital Basic Block 00 0001b Digital Basic Block 01 0010b Digital Communication Block 02 0011b Digital Communication Block 03 0100b Digital Basic Block 10 0101b Digital Basic Block 11 0110b Digital Communication Block 12 0111b Digital Communication Block 13 1000b Digital Basic Block 20 1001b Digital Basic Block 21 1010b Digital Communication Block 22 1011b Digital Communication Block 23 1100b Reserved 1101b Reserved 1110b Reserved 1111b Reserved CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 265 ACE_CLK_CR3 1,8Bh 13.3.46 ACE_CLK_CR3 Analog Clock Source Control Register 3 Individual Register Names and Addresses: 1,8Bh ACE_CLK_CR3: 1,8Bh 2L* Column 7 6 5 4 3 2 1 0 Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name SYS5 DIVCLK5[1:0] SYS4 DIVCLK4[1:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. This register controls additional options for analog column clock generation. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 6 SYS5 0 1 Column 5 clock selection is controlled by ACE_CLK_CR0. Column 5 clock selection is SYSCLK direct. 5:4 DIVCLK5[1:0] 00b 01b 10b 11b No divide on selected column 5 clock. Divide by 2 on selected column 5 clock. Divide by 4 on selected column 5 clock. Divide by 8 on selected column 5 clock. 2 SYS4 0 1 Column 4 clock selection is controlled by ACE_CLK_CR0. Column 4 clock selection is SYSCLK direct. 1:0 DIVCLK4[1:0] 00b 01b 10b 11b No divide on selected column 4 clock. Divide by 2 on selected column 4 clock. Divide by 4 on selected column 4 clock. Divide by 8 on selected column 4 clock. 266 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DECx_CR0 1,91h 13.3.47 DECx_CR0 Decimator Control Register 0 Individual Register Names and Addresses: DEC0_CR0 : 1,91h 1,91h DEC1_CR0 : 1,95h 7 6 5 4 3 DEC3_CR0 : 1,9Dh 2 1 0 RW : 00 Access : POR POL Bit Name DEC2_CR0 : 1,99h GOOO GOOE DATA_IN[2:0] This register controls the data inputs for the decimator. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bits Name Description 7 POL 0 1 Do not invert the decimator data input. Invert the decimator data input. 6 GOOO 1 Enables the related decimator data input to be output to Global Digital Output Odd Bus. Decimator # GOO Bus Bit 0 Output to GOO[1] 1 Output to GOO[3] 2 Output to GOO[5] 3 Output to GOO[7] 5 GOOE 1 Enables the related decimator data input to be output to Global Digital Output Even Bus. Decimator # GOO Bus Bit 0 output to GOO[0] 1 output to GOO[2] 2 output to GOO[4] 3 output to GOO[6] 2:0 DATA_IN[2:0] Used to select one decimator data input from among the following sources. The 'x' in the following entries is the corresponding decimator number. 000b ACCx_CMPO, the corresponding analog column compare bus output. 001b BCROWx, the corresponding Broadcast net from digital blocks. Note that it is fixed 'HIGH' for decimator 3. 010b The compare bus output of analog column 4 (Type-E column). 011b The compare bus output of analog column 5 (Type-E column). 100b ROW0LUTx, the corresponding LUT output from digital row 0. 101b ROW1LUTx, the corresponding LUT output from digital row 1. 110b ROW2LUTx, the corresponding LUT output from digital row 2. 111b LOW (reserved) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 267 DEC_CR3 1,92h 13.3.48 DEC_CR3 Decimator Global Control Register 3 Individual Register Names and Addresses: 1,92h DEC_CR3: 1,92h 7 6 5 4 DEC1_EN Bit Name 3 2 1 0 RW : 00 Access : POR CLK_IN1[2:0] DEC0_EN CLK_IN0[2:0] This register controls decimator enabling and clock selection. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bits Name Description 7 DEC1_EN 1 6:4 CLK_IN1[2:0] Select one of the following sources as decimator 1 clock 000b VC1 001b VC2 010b CLKA4 (from analog column 4) 011b CLKA5 (from analog column 5) 100b VC3 101b Preselected clock source (from digital block primary outputs). See DEC_CR5. 110b Reserved 111b LOW (Reserved) 3 DEC0_EN 1 2:0 CLK_IN0[2:0] Selects one of the following sources as decimator 0 clock 000b VC1 001b VC2 010b CLKA4 (from analog column 4) 011b CLKA5 (from analog column 5) 100b VC3 101b Preselected clock source (from digital block primary outputs). See DEC_CR5. 110b Reserved 111b LOW (Reserved) Enables decimator 1 Enables decimator 0 Note The input clock frequency must be less than 24 MHz. 268 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F DEC_CR4 1,96h 13.3.49 DEC_CR4 Decimator Global Control Register 4 Individual Register Names and Addresses: 1,96h DEC_CR4: 1,96h 7 6 5 DEC3_EN Bit Name 4 3 2 1 0 RW : 00 Access : POR CLK_IN3[2:0] DEC2_EN CLK_IN2[2:0] This register controls decimator enabling and clock selection. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bits Name Description 7 DEC3_EN 1 6:4 CLK_IN3[2:0] Selects one as decimator 3 clock from among the following sources 000b VC1 001b VC2 010b CLKA4 (from analog column 4) 011b CLKA5 (from analog column 5) 100b VC3 101b Preselected clock source (from digital block primary outputs). See DEC_CR5. 110b Reserved 111b LOW (Reserved) 3 DEC2_EN 1 2:0 CLK_IN2[2:0] Selects one as decimator 2 clock from among the following sources 000b VC1 001b VC2 010b CLKA4 (from analog column 4) 011b CLKA5 (from analog column 5) 100b VC3 101b Preselected clock source (from digital block primary outputs). See DEC_CR5. 110b Reserved 111b LOW (Reserved) Enable decimator 3 Enable decimator 2 Note The input clock frequency must be less than 24 MHz. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 269 DEC_CR5 1,9Ah 13.3.50 DEC_CR5 Decimator Global Control Register 5 Individual Register Names and Addresses: 1,9Ah DEC_CR5: 1,9Ah 7 6 5 4 3 2 1 0 RW : 00 Access : POR DSCLK[3:0] Bit Name In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bits Name Description 3:0 DSCLK[3:0] Indicate which digital block's primary output is selected as a decimator clock source. Note LOW is selected when DSCLK is greater than 1011b. 0000b DBC00 0001b DBC01 0010b DCC02 0011b DCC03 0100b DCB10 0101b DCB11 0110b DCC12 0111b DCC13 1000b DCC20 1001b DCC21 1010b DCC22 1011b DCC23 1100b Reserved 1101b Reserved 1110b Reserved 1111b Reserved 270 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F GDI_O_IN_CR 1,A0h 13.3.51 GDI_O_IN_CR Global Digital Interconnect Odd Inputs Control Register Individual Register Names and Addresses: 1,A0h GDI_O_IN_CR: 1,A0h 7 6 5 GDIOICR[7] Bit Name 4 3 2 1 0 GDIOICR[3] GDIOICR[2] GDIOICR[1] GDIOICR[0] RW : 00 Access : POR GDIOICR[6] GDIOICR[5] GDIOICR[4] This register allows a global input net to drive its corresponding next global output net. Note that the corresponding bit in GDI_O_IN must be set. For additional information, refer to the “Register Definitions” on page 322 in the Global Digital Interconnect chapter. Bit Name Description 7 GDIOICR[7] 0 GIO[7] drives GOO[7] 1 GIO[6] drives GOO[7] Note These selections are only valid if bit 7 is set to ‘1’ in the GDI_O_IN register. 6 GDIOICR[6] 0 GIO[6] drives GOO[6] 1 GIO[5] drives GOO[6] Note These selections are only valid if bit 6 is set to ‘1’ in the GDI_O_IN register. 5 GDIOICR[5] 0 GIO[5] drives GOO[5] 1 GIO[4] drives GOO[5] Note These selections are only valid if bit 5 is set to ‘1’ in the GDI_O_IN register. 4 GDIOICR[4] 0 GIO[4] drives GOO[4] 1 GIO[3] drives GOO[4] Note These selections are only valid if bit 4 is set to ‘1’ in the GDI_O_IN register. 3 GDIOICR[3] 0 GIO[3] drives GOO[3] 1 GIO[2] drives GOO[3] when bit 3 is 1 in GDI_O_IN register. Note These selections are only valid if bit 3 is set to ‘1’ in the GDI_O_IN register. 2 GDIOICR[2] 0 GIO[2] drives GOO[2] 1 GIO[1] drives GOO[2] Note These selections are only valid if bit 2 is set to ‘1’ in the GDI_O_IN register. 1 GDIOICR[1] 0 GIO[1] drives GOO[1] 1 GIO[0] drives GOO[1] Note These selections are only valid if bit 1 is set to ‘1’ in the GDI_O_IN register. 0 GDIOICR[0] 0 GIO[0] drives GOO[0] 1 GIO[7] drives GOO[0] Note These selections are only valid if bit 0 is set to ‘1’ in the GDI_O_IN register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 271 GDI_E_IN_CR 1,A1h 13.3.52 GDI_E_IN_CR Global Digital Interconnect Even Inputs Control Register Individual Register Names and Addresses: 1,A1h GDI_E_IN_CR: 1,A1h 7 6 5 GDIEICR[7] Bit Name 4 3 2 1 0 GDIEICR[3] GDIEICR[2] GDIEICR[1] GDIEICR[0] RW : 00 Access : POR GDIEICR[6] GDIEICR[5] GDIEICR[4] This register allows a global input net to drive its corresponding next global output net. Note that the corresponding bit in GDI_E_IN must be set. For additional information, refer to the “Register Definitions” on page 322 in the Global Digital Interconnect chapter. Bit Name Description 7 GDIEICR[7] 0 GIE[7] drives GOE[7] 1 GIE[6] drives GOE[7] Note These selections are only valid if bit 7 is set to ‘1’ in the GDI_E_IN register. 6 GDIEICR[6] 0 GIE[6] drives GOE[6] 1 GIE[5] drives GOE[6] Note These selections are only valid if bit 6 is set to ‘1’ in the GDI_E_IN register. 5 GDIEICR[5] 0 GIE[5] drives GOE[5] 1 GIE[4] drives GOE[5] Note These selections are only valid if bit 5 is set to ‘1’ in the GDI_E_IN register. 4 GDIEICR[4] 0 GIE[4] drives GOE[4] 1 GIE[3] drives GOE[4] Note These selections are only valid if bit 4 is set to ‘1’ in the GDI_E_IN register. 3 GDIEICR[3] 0 GIE[3] drives GOE[3] 1 GIE[2] drives GOE[3] Note These selections are only valid if bit 3 is set to ‘1’ in the GDI_E_IN register. 2 GDIEICR[2] 0 GIE[2] drives GOE[2] 1 GIE[1] drives GOE[2] Note These selections are only valid if bit 2 is set to ‘1’ in the GDI_E_IN register. 1 GDIEICR[1] 0 GIE[1] drives GOE[1] 1 GIE[0] drives GOE[1] Note These selections are only valid if bit 1 is set to ‘1’ in the GDI_E_IN register. 0 GDIEICR[0] 0 GIE[0] drives GOE[0] 1 GIE[7] drives GOE[0] Note These selections are only valid if bit 0 is set to ‘1’ in the GDI_E_IN register. 272 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F GDI_O_OU_CR 1,A2h 13.3.53 GDI_O_OU_CR Global Digital Interconnect Odd Outputs Control Register Individual Register Names and Addresses: 1,A2h GDI_O_OU_CR: 1,A2h 7 6 5 Bit Name 4 3 2 1 0 GDIOOCR[3] GDIOOCR[2] GDIOOCR[1] GDIOOCR[0] RW : 00 Access : POR GDIOOCR[7] GDIOOCR[6] GDIOOCR[5] GDIOOCR[4] This register allows a global output net to drive its corresponding next global input net. Note that corresponding bit in GDI_O_OU must be set. For additional information, refer to the “Register Definitions” on page 322 in the Global Digital Interconnect chapter. Bit Name Description 7 GDIOOCR[7] 0 GOO[7] drives GIO[7] 1 GOO[6] drives GIO[7] Note These selections are only valid if bit 7 is set to ‘1’ in the GDI_O_OU register. 6 GDIOOCR[6] 0 GOO[6] drives GIO[6] 1 GOO[5] drives GIO[6] Note These selections are only valid if bit 6 is set to ‘1’ in the GDI_O_OU register. 5 GDIOOCR[5] 0 GOO[5] drives GIO[5] 1 GOO[4] drives GIO[5] Note These selections are only valid if bit 5 is set to ‘1’ in the GDI_O_OU register. 4 GDIOOCR[4] 0 GOO[4] drives GIO[4] 1 GOO[3] drives GIO[4] Note These selections are only valid if bit 4 is set to ‘1’ in the GDI_O_OU register. 3 GDIOOCR[3] 0 GOO[3] drives GIO[3] 1 GOO[2] drives GIO[3] Note These selections are only valid if bit 3 is set to ‘1’ in the GDI_O_OU register. 2 GDIOOCR[2] 0 GOO[2] drives GIO[2] 1 GOO[1] drives GIO[2] Note These selections are only valid if bit 2 is set to ‘1’ in the GDI_O_OU register. 1 GDIOOCR[1] 0 GOO[1] drives GIO[1] 1 GOO[0] drives GIO[1] Note These selections are only valid if bit 1 is set to ‘1’ in the GDI_O_OU register. 0 GDIOOCR[0] 0 GOO[0] drives GIO[0] 1 GOO[7] drives GIO[0] Note These selections are only valid if bit 0 is set to ‘1’ in the GDI_O_OU register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 273 GDI_E_OU_CR 1,A3h 13.3.54 GDI_E_OU_CR Global Digital Interconnect Even Outputs Control Register Individual Register Names and Addresses: 1,A3h GDI_E_OU_CR: 1,A3h 7 6 5 Bit Name 4 3 2 1 0 GDIEOCR[3] GDIEOCR[2] GDIEOCR[1] GDIEOCR[0] RW : 00 Access : POR GDIEOCR[7] GDIEOCR[6] GDIEOCR[5] GDIEOCR[4] This register allows a global output net to drive its corresponding next global input net. Note that corresponding bit in GDI_E_OU must be set. For additional information, refer to the “Register Definitions” on page 322 in the Global Digital Interconnect chapter. Bit Name Description 7 GDEOICR[7] 0 GOE[7] drives GIE[7] 1 GOE[6] drives GIE[7] Note These selections are only valid if bit 7 is set to ‘1’ in the GDI_E_OU register. 6 GDEOICR[6] 0 GOE[6] drives GIE[6] 1 GOE[5] drives GIE[6] Note These selections are only valid if bit 6 is set to ‘1’ in the GDI_E_OU register. 5 GDEOICR[5] 0 GOE[5] drives GIE[5] 1 GOE[4] drives GIE[5] Note These selections are only valid if bit 5 is set to ‘1’ in the GDI_E_OU register. 4 GDEOICR[4] 0 GOE[4] drives GIE[4] 1 GOE[3] drives GIE[4] Note These selections are only valid if bit 4 is set to ‘1’ in the GDI_E_OU register. 3 GDEOICR[3] 0 GOE[3] drives GIE[3] 1 GOE[2] drives GIE[3] Note These selections are only valid if bit 3 is set to ‘1’ in the GDI_E_OU register. 2 GDEOICR[2] 0 GOE[2] drives GIE[2] 1 GOE[1] drives GIE[2] Note These selections are only valid if bit 2 is set to ‘1’ in the GDI_E_OU register. 1 GDEOICR[1] 0 GOE[1] drives GIE[1] 1 GOE[0] drives GIE[1] Note These selections are only valid if bit 1 is set to ‘1’ in the GDI_E_OU register. 0 GDEOICR[0] 0 GOE[0] drives GIE[0] 1 GOE[7] drives GIE[0] Note These selections are only valid if bit 0 is set to ‘1’ in the GDI_E_OU register. 274 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RTC_H 1,A4h 13.3.55 RTC_H Real Time Clock Hours Register Individual Register Names and Addresses: 1,A4h RTC_H: 1,A4h 7 6 5 4 3 2 1 Access : POR RW : 00 RW : 0000 Bit Name HR1[1:0] HR0[3:0] 0 This register is used to read and write the current hour value in BCD format. Writing to this register will reset count 65536 to all zeros. (Will be displayed as “XY”; the legal range is from 00 to 23.) In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 534 in the Real Time Clock chapter. Bit Name Description 5:4 HR1[1:0] Hour time decal number; BCD code. 3:0 HR0[3:0] Hour time units number; BCD code. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 275 RTC_M 1,A5h 13.3.56 RTC_M Real Time Clock Minutes Register Individual Register Names and Addresses: 1,A5h RTC_M: 1,A5h 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 00 RW : 0000 MIN1[2:0] MIN0[3:0] 0 This register is used to read and write the current minute value in BCD format. Writing to this register will reset count 65536 to all zeros. (Will be displayed as “XY”; the legal range is from 00 to 59.) In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 534 in the Real Time Clock chapter. Bit Name Description 6:4 MIN1[2:0] Minute time decal number; BCD code. 3:0 MIN0[3:0] Minute time units number; BCD code. 276 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F RTC_S 1,A6h 13.3.57 RTC_S Real Time Clock Seconds Register Individual Register Names and Addresses: 1,A6h RTC_S: 1,A6h 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 00 RW : 0000 SEC1[2:0] SEC0[3:0] 0 This register is used to read and write the current second value in BCD format. Writing to this register will reset count 65536 to all zeros. (Will be displayed as “XY”; the legal range is from 00 to 59.) In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 534 in the Real Time Clock chapter. Bit Name Description 6:4 SEC1[2:0] Second time decal number; BCD code. 3:0 SEC0[3:0] Second time units number; BCD code. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 277 RTC_CR 1,A7h 13.3.58 RTC_CR Real Time Clock Control Register Individual Register Names and Addresses: 1,A7h RTC_CR: 1,A7h 5 4 1 0 Access : POR 7 6 RW : 0 RW : 0 3 RW : 00 2 RW : 0 RW : 0 Bit Name INT_EN CLKSE INT_SEL[1:0] SYNCRD_EN RTC_EN This register controls the RTC. For additional information, see “Register Definitions” on page 534 in the Real Time Clock chapter. Bit Name Description 5 INT_EN 0 1 4 CLKSE 0 CLK32S 1 VC1 If VC1 is selected, the RTC module acts as a fixed period interrupt source. 3:2 INT_SEL[1:0] Interrupt Select 00b Interrupt per second 01b Interrupt per minute 10b Interrupt per hour 11b Interrupt per day 1 SYNCRD_EN 0 1 RTC_M/RTC_S are read directly from their registers without buffering. RTC_M/RTC_S reads data from its data buffer. The data is latched from the real register when RTC_H is read. 0 RTC_EN 0 1 Disable RTC function Enable RTC function 278 Disable interrupt Enable interrupt CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F SADC_CR0 1,A8h 13.3.59 SADC_CR0 SAR ADC Control Register 0 Individual Register Names and Addresses: 1,A8h SADC_CR0: 1,A8h 7 6 5 Access : POR Bit Name 2 1 0 RW : 0000 4 3 RW : 0 RW : 0 RW : 0 ADC_CHS[3:0] READY Start/ONGOING ADCEN This register controls the input selection for the SAR ADC, and contains status and enable bits. The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 6:3 ADC_CHS[3:0] Channel selection 0000b P0.0 0010b P0.2 0100b P0.4 0110b P0.6 1000b ACC00 1010b ACC02 1100b Muxbus0 1110b Vbg 0001b 0011b 0101b 0001b 1001b 1011b 1101b 1111b P0.1 P0.3 P0.5 P0.7 ACC01 ACC03 Muxbus1 Reserved 2 READY 1 There is new data that has never been read. 1 Start/ONGOING Reading a ‘1’ means the A-D conversion started, and is not finished yet. Writing ‘1’ to it in SW trigger mode triggers a new conversion. 0 ADC_EN Enable ADC function. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 279 SADC_CR1 1,A9h 13.3.60 SADC_CR1 SAR ADC Control Register 1 Individual Register Names and Addresses: 1,A9h SADC_CR1: 1,A9h 7 Access : POR Bit Name 6 5 4 3 2 1 0 RW : 00 RW : 00 RW : 000 RW : 0 CVTMD[1:0] TIGSEL[1:0] CLKSEL[2:0] ALIGN_EN This register contains control bit for the 10-bit SAR ADC. The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, see “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7:6 CVTMD[1:0] The conversion mode 00b The default mode that only the extra cycle for 6th bit conversion 01b The extra cycle for 6th bit conversion with add-on weak Vref buffer 10b The extra cycle for 7th bit conversion with add-on weak Vref buffer 11b The extra cycle for 1st bit conversion with add-on weak Vref buffer 5:4 TIGSEL[1:0] Auto-trigger source selection 00b TGL 01b TGH 10b TG16BIT 11b TGINCMP 3:1 CLKSEL[3:0] ADC Clock Selection 000b /2 001b /4 010b /6 011b /8 100b /12 101b /16 110b /32 111b /64 0 ALIGN_EN ‘1’ to enable auto-align function. The ADC will be driven by outside-block trigger signal. Refer to bit[5:4] of this register and SADC_TSCRx (1,71 and 1,72) and SADC_TSCMPL/H (1,81 and 1,82). Note When both ALIGN_EN and FREERUN are zero, the ADC is in software trigger mode; that is, if you write 1 to START bit of SADC_CR0, it triggers one time A-D-C. 280 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F SADC_CR2 1,AAh 13.3.61 SADC_CR2 SAR ADC Control Register 2 Individual Register Names and Addresses: 1,AAh SADC_CR2: 1,AAh 7 6 5 4 3 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 REFSEL BUFEN VDBEN VDB_CLK FREERUN Access : POR Bit Name 2 1 0 The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, see “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7 REFSEL 0 1 Selects Vdd as reference. Selects external Vref other than Vdd. See EXTREF in SADC_CR4. 6 BUFEN 0 1 Bypass Vref buffer. Enable Vref buffer. 5 VDBEN 1 Enable voltage doubler in ADC comparator. 4 VDB_CLK 0 1 Select SYSCLK/4 as VDB clock. Select SYSLCK as VDB clock. 3 FREERUN 1 ADC in FREERUN mode if ADC is not in auto-align mode. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 281 SADC_CR3 1,ABh 13.3.62 SADC_CR3 SAR ADC Control Register 3 Individual Register Names and Addresses: 1,ABh SADC_CR3: 1,ABh 7 6 5 4 3 2 1 Access : POR RW : 0 RW : 0 Bit Name LALIGN ADC_TRIM0[2:0] 0 The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7 LALIGN 1 2:0 ADC_TRIM0[2:0] Sent to ADC comparator block directly. 282 Set left-justified data format. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F SADC_CR4 1,ACh 13.3.63 SADC_CR4 SAR ADC Control Register 4 Individual Register Names and Addresses: 1,ACh SADC_CR4: 1,ACh 7 6 5 4 3 2 1 0 RW : 0 Access : POR EXTREF Bit Name The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, see “Register Definitions” on page 541 in the 10-Bit SAR ADC Controller chapter. Bit Name Description 7 EXTREF 0 1 Selects REFHI as reference input Selects externally supplied reference voltage on P2[6] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 283 I2Cx_ADDR 1,ADh 13.3.64 I2Cx_ADDR I2C Address Register Individual Register Names and Addresses: I2C0_ADDR : 1,ADh 7 Access : POR Bit Name 1,ADh I2C1_ADDR 6 5 : 1,AEh 4 3 RW:0 RW : 000000 HwAddrEn Addr[6:0] 2 1 0 The I2C address register is used to configure the hardware address automatic comparison feature so that the microcontroller will not be disturbed by an unwanted slave request. When HwAddrEn is enabled, the 7-bit address should be stored in Addr[6:0]; there is an interrupt only when the received address matches the stored address. The hardware address automatic compare feature is available in slave only mode; master/slave mode is not supported. Note that the second I2C block is available in the CY8C28x03, CY8C28x23, CY8C28x43, and CY8C28x45 PSoC devices only. For additional information, see “Register Definitions” on page 497 in the I2C chapter. Bit Name Description 7 HwAddrEn 1 Enable hardware address comparison feature. Only supports 7-bit address. When you enable the hardware address comparison feature, I2C block will not support the special sys- 0 6:0 284 Addr tem address definition which is listed in I2C V2.1 spec, section 10 (for example: general call address, CBUS address, 10-bit slave address, and so on). Disable hardware address comparison feature. Slave Address bits hold the slave's own device address. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F AMUX_CLK 1,AFh 13.3.65 AMUX_CLK Analog Mux Clock Register Individual Register Names and Addresses: 1,AFh AMUX_CLK: 1,AFh 2 Column 7 Access : POR Bit Name 6 5 4 RW : 0 RW : 0 3 RW : 0 2 1 RW : 0 0 CLKTOR CLKTOL CLK1SYNC[1:0] CLK0SYNC[1:0] This register is used to adjust the phase of the clock to the analog mux bus. This register is only used by the CY8C28xxx PSoC devices. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 528 in the I/O Analog Multiplexer chapter. Bits Name 5 CLKTOR Description 0 Select MUXCLK1 as clock to drive right side Amuxbus1's IOMUX. 1 Select MUXCLK0 as clock to drive right side Amuxbus1's IOMUX. This bit is only available in the CY8C28xxx PSoC device. 4 CLKTOL 0 Select MUXCLK0 as clock to drive left side Amuxbus0's IOMUX. 1 Select MUXCLK1 as clock to drive left side Amuxbus0's IOMUX. This bit is only available in the CY8C28xxx PSoC device. 3:2 CLK1SYNC[1:0] Synchronizes the right side MUXCLK (MUXCLK1). The right side MUXCLK that drives switching on the analog mux right (Amuxbus1) can be synchronized to one of four phases, as listed. These settings can be used to optimize noise performance by varying the analog mux sampling point relative to the system clock. 00b Synchronize to SYSCLK rising edge. 01b Synchronize to delayed (approximately 5 ns) SYSCLK rising edge. 10b Synchronize to SYSCLK falling edge. 11b Synchronize to early (approximately 5 ns) SYSCLK rising edge. These bits are only available in the CY8C28xxx PSoC device. 1:0 CLK0SYNC[1:0] Synchronizes the left side MUXCLK (MUXCLK0). The left side MUXCLK that drives switching on the analog mux left (Amuxbus0) can be synchronized to one of four phases, as listed. These settings can be used to optimize noise performance by varying the analog mux sampling point relative to the system clock. 00b Synchronize to SYSCLK rising edge. 01b Synchronize to delayed (approximately 5 ns) SYSCLK rising edge. 10b Synchronize to SYSCLK falling edge. 11b Synchronize to early (approximately 5 ns) SYSCLK rising edge. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 285 GDI_O_IN 1,D0h 13.3.66 GDI_O_IN Global Digital Interconnect Odd Inputs Register Individual Register Names and Addresses: 1,D0h GDI_O_IN: 1,D0h Access : POR Bit Name 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 GIONOUT7 GIONOUT6 GIONOUT5 GIONOUT4 GIONOUT3 GIONOUT2 GIONOUT1 GIONOUT0 This register is used to configure a global input to drive a global output. For additional information, refer to the “Register Definitions” on page 322 in the Global Digital Interconnect chapter. Bit Name Description 7 GIONOUT7 0 1 No connection between GIO[7]/GIO[6] to GOO[7] Allow GIO[7]/GIO[6] to drive GOO[7] depending on the setting in GDI_O_IN_CR. 6 GIONOUT6 0 1 No connection between GIO[6]/GIO[5] to GOO[6] Allow GIO[6]/GIO[5] to drive GOO[6] depending on the setting in GDI_O_IN_CR. 5 GIONOUT5 0 1 No connection between GIO[5]/GIO[4] to GOO[5] Allow GIO[5]/GIO[4] to drive GOO[5] depending on the setting in GDI_O_IN_CR. 4 GIONOUT4 0 1 No connection between GIO[4]/GIO[3] to GOO[4] Allow GIO[4]/GIO[3] to drive GOO[4] depending on the setting in GDI_O_IN_CR. 3 GIONOUT3 0 1 No connection between GIO[3]/GIO[2] to GOO[3] Allow GIO[3]/GIO[2] to drive GOO[3] depending on the setting in GDI_O_IN_CR. 2 GIONOUT2 0 1 No connection between GIO[2]/GIO[1] to GOO[2] Allow GIO[2]/GIO[1] to drive GOO[2] depending on the setting in GDI_O_IN_CR. 1 GIONOUT1 0 1 No connection between GIO[1]/GIO[0] to GOO[1] Allow GIO[1]/GIO[0] to drive GOO[1] depending on the setting in GDI_O_IN_CR. 0 GIONOUT0 0 1 No connection between GIO[0]/GIO[7] to GOO[0] Allow GIO[0]/GIO[7] to drive GOO[0] depending on the setting in GDI_O_IN_CR. 286 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F GDI_E_IN 1,D1h 13.3.67 GDI_E_IN Global Digital Interconnect Even Inputs Register Individual Register Names and Addresses: 1,D1h GDI_E_IN: 1,D1h Access : POR Bit Name 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 GIENOUT7 GIENOUT6 GIENOUT5 GIENOUT4 GIENOUT3 GIENOUT2 GIENOUT1 GIENOUT0 This register is used to configure a global input to drive a global output. For additional information, refer to the “Register Definitions” on page 322 in the Global Digital Interconnect chapter. Bit Name Description 7 GIENOUT7 0 1 No connection between GIE[7]/GIE[6] to GOE[7] Allow GIE[7]/GIE[6] to drive GOE[7] depending on the setting in GDI_E_IN_CR. 6 GIENOUT6 0 1 No connection between GIE[6]/GIE[5] to GOE[6] Allow GIE[6]/GIE[5] to drive GOE[6] depending on the setting in GDI_E_IN_CR. 5 GIENOUT5 0 1 No connection between GIE[5]/GIE[4] to GOE[5] Allow GIE[5]/GIE[4] to drive GOE[5] depending on the setting in GDI_E_IN_CR. 4 GIENOUT4 0 1 No connection between GIE[4]/GIE[3] to GOE[4] Allow GIE[4]/GIE[3] to drive GOE[4] depending on the setting in GDI_E_IN_CR. 3 GIENOUT3 0 1 No connection between GIE[3]/GIE[2] to GOE[3] Allow GIE[3]/GIE[2] to drive GOE[3] depending on the setting in GDI_E_IN_CR. 2 GIENOUT2 0 1 No connection between GIE[2]/GIE[1] to GOE[2] Allow GIE[2]/GIE[1] to drive GOE[2] depending on the setting in GDI_E_IN_CR. 1 GIENOUT1 0 1 No connection between GIE[1]/GIE[0] to GOE[1] Allow GIE[1]/GIE[0] to drive GOE[1] depending on the setting in GDI_E_IN_CR. 0 GIENOUT0 0 1 No connection between GIE[0]/GIE[7] to GOE[0] Allow GIE[0]/GIE[7] to drive GOE[0] depending on the setting in GDI_E_IN_CR. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 287 GDI_O_OU 1,D2h 13.3.68 GDI_O_OU Global Digital Interconnect Odd Outputs Register Individual Register Names and Addresses: 1,D2h GDI_O_OU: 1,D2h Access : POR Bit Name 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 This register is used to configure a global output to drive a global input. For additional information, refer to the “Register Definitions” on page 322 in the Global Digital Interconnect chapter. Bit Name Description 7 GOOUTIN7 0 1 No connection between GIO[7]/GIO[6] to GOO[7] Allow GOO[7]/GOO[6] to drive GIO[7] depending on the setting in GDI_O_OU_CR. 6 GOOUTIN6 0 1 No connection between GIO[6]/GIO[5] to GOO[6] Allow GOO[6]/GOO[5] to drive GIO[6] depending on the setting in GDI_O_OU_CR. 5 GOOUTIN5 0 1 No connection between GIO[0]/GIO[4] to GOO[5] Allow GOO[5]/GOO[4] to drive GIO[5] depending on the setting in GDI_O_OU_CR. 4 GOOUTIN4 0 1 No connection between GIO[4]/GIxO[3] to GOO[4] Allow GOO[4]/GOO[3] to drive GIO[4] depending on the setting in GDI_O_OU_CR. 3 GOOUTIN3 0 1 No connection between GIO[3]/GIO[2] to GOO[3] Allow GOO[3]/GOO[2] to drive GIO[3] depending on the setting in GDI_O_OU_CR. 2 GOOUTIN2 0 1 No connection between GIO[2]/GIO[1] to GOO[2] Allow GOO[2]/GOO[1] to drive GIO[2] depending on the setting in GDI_O_OU_CR. 1 GOOUTIN1 0 1 No connection between GIO[1]/GIO[0] to GOO[1] Allow GOO[1]/GOO[0] to drive GIO[1] depending on the setting in GDI_O_OU_CR. 0 GOOUTIN0 0 1 No connection between GIO[0]/GIO[7] to GOO[0] Allow GOO[0]/GOO[7] to drive GIO[0] depending on the setting in GDI_O_OU_CR. 288 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F GDI_E_OU 1,D3h 13.3.69 GDI_E_OU Global Digital Interconnect Even Outputs Register Individual Register Names and Addresses: 1,D3h GDI_E_OU: 1,D3h Access : POR Bit Name 7 6 5 4 3 2 1 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 GOEUTIN7 GOEUTIN6 GOEUTIN5 GOEUTIN4 GOEUTIN3 GOEUTIN2 GOEUTIN1 GOEUTIN0 This register is used to configure a global output to drive a global input. For additional information, refer to the “Register Definitions” on page 322 in the Global Digital Interconnect chapter. Bit Name Description 7 GOEUTIN7 0 1 No connection between GIE[7]/GIE[6] to GOE[7] Allow GOE[7]/GOE[6] to drive GIE[7 depending on the setting in GDI_E_OU_CR. 6 GOEUTIN6 0 1 No connection between GIE[6]/GIE[5] to GOE[6] Allow GOE[6]/GOE[5] to drive GIE[6] depending on the setting in GDI_E_OU_CR. 5 GOEUTIN5 0 1 No connection between GIE[0]/GIE[4] to GOE[5] Allow GOE[5]/GOE[4] to drive GIE[5] depending on the setting in GDI_E_OU_CR. 4 GOEUTIN4 0 1 No connection between GIE[4]/GIE[3] to GOE[4] Allow GOE[4]/GOE[3] to drive GIE[4] depending on the setting in GDI_E_OU_CR. 3 GOEUTIN3 0 1 No connection between GIE[3]/GIE[2] to GOE[3] Allow GOE[3]/GOE[2] to drive GIE[3] depending on the setting in GDI_E_OU_CR. 2 GOEUTIN2 0 1 No connection between GIE[2]/GIE[1] to GOE[2] Allow GOE[2]/GOE[1] to drive GIE[2] depending on the setting in GDI_E_OU_CR. 1 GOEUTIN1 0 1 No connection between GIE[1]/GIE[0] to GOE[1] Allow GOE[1]/GOE[0] to drive GIE[1] depending on the setting in GDI_E_OU_CR. 0 GOEUTIN0 0 1 No connection between GIE[0]/GIE[7] to GOE[0] Allow GOE[0]/GOE[7] to drive GIE[0] depending on the setting in GDI_E_OU_CR. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 289 DECx_CR 1,D4h 13.3.70 DECx_CR Decimator Type 2 Control Register Individual Register Names and Addresses: DEC0_CR : 1,D4h 1,D4h DEC1_CR : 1,D5h 7 Access : POR Bit Name 6 DEC2_CR : 1,D6h 5 4 3 DEC3_CR : 1,D7h 2 1 RW : 0 RW : 0 RW : 0 RW : 0 Mode[1:0] Data Out Shift[1:0] Data Format Decimation Rate[2:0] 0 This register is used to configure the decimators before use. This register is only available for the CY8C28xxx PSoC devices with type 2 decimator blocks. For additional information, refer to the “Register Definitions” on page 488 in the Decimator chapter. Bits Name Description 7:6 Mode[1:0] 00b 01b 10b 11b Compatibility mode (old UM works) Incremental mode Full algorithm Reserved 5:4 Data Out Shift[1:0] 00b 01b 10b 11b No shift One shift Two shifts Four shifts 3 Data Format Controls how the input data stream is interpreted by the integrator. 0 A 0/1 input is interpreted as -1/+1. 1 A 0/1 input is interpreted as 0/+1. 2:0 Decimation Rate[2:0] 000b Off 001b 32 010b 50 011b 64 100b 125 101b 128 110b 250 111b 256 Note If this is set to anything other than Off, the digital block selected by DCLKS will be ignored. 290 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F MUX_CRx 1,D8h 13.3.71 MUX_CRx Analog Mux Port Bit Enables Register Individual Register Names and Addresses: MUX_CR0 : 1,D8h MUX_CR4 : 1,ECh 1,D8h MUX_CR1 : 1,D9h MUX_CR5 : 1,EDh 7 6 MUX_CR2 : 1,DAh 5 4 MUX_CR3 : 1,DBh 3 2 1 0 RW : 00 Access : POR ENABLE[7:0] Bit Name This register is used to control the connection between the analog mux bus and the corresponding pin. Port 3 and the upper 4 bits of the MUX_CR3 register are reserved and will return zeros when read. For additional information, refer to the “Register Definitions” on page 528 in the I/O Analog Multiplexer chapter. Bits Name Description 7:0 ENABLE[7:0] Each bit controls the connection between the analog mux bus and the corresponding port pin. For example, MUX_CR2[3] controls the connection to bit 3 in Port 2. Any number of pins may be connected at the same time. Note that if a precharge clock is selected in the AMUX_CFG register, the connection to the mux bus will be switched on and off under hardware control. 0 No connection between port pin and analog mux bus. 1 Connect port pin to analog mux bus. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 291 IDAC_CR1 1,DCh 13.3.72 IDAC_CR1 IDAC Control Register 1 Individual Register Names and Addresses: 1,DCh IDAC_CR1 : 1,DCh Access : POR Bit Name 7 6 5 RW : 0 RW : 0 RW : 00 4 3 RW : 1000 2 1 RW : 0 0 EN1 MuxClkGE1 ICEN IDAC_TRIM Double_Current This register contains the control bits for the IDAC current that drives the analog mux bus and for selecting the split configuration. For additional information, refer to the “Register Definitions” on page 528 in the I/O Analog Multiplexer chapter. Bits Name Description 7 EN1 0 1 Disables right IDAC (IDAC1). Enables right IDAC (IDAC1). 6 MuxClkGE1 0 1 Disables driving right side MUXCLK (MUXCLK1) to GOO[7]. Enables driving right side MUXCLK (MUXCLK1) to GOO[7]. 5 ICEN 0 Disables this feature: both IDAC will be controlled by their own registers, including data and output on/off registers. Enables this feature: both IDAC0 and IDAC1 will use the IDAC0_D register for IDAC current setting when their output enable signal is high, and it will automatically switch to use IDAC1_D register for IDAC setting when their output enable signal is low. 1 4:1 IDAC_TRIM[3:0] These signals go to PLL block and are used to trim IUNIT32 current output. The default value is 1000b (ideally it is 10 µA). Each step will change the current approximately by 3%. 0 Double_Current This bit is used for IDAC current range control; it will four different IDAC current range. Double_Current IDAC_CR0[3].IRANGE 0 (default) 0 (default) 1 0 0 1 1 1 292 combine with IDAC_CR0[3].IRANGE to define Current Range Reserved Maximum 91.03 µA Maximum 318.75 µA Maximum 637.5 µA CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F OSC_GO_EN 1,DDh 13.3.73 OSC_GO_EN Oscillator to Global Outputs Enable Register Individual Register Names and Addresses: 1,DDh OSC_GO_EN: 1,DDh 7 6 5 4 3 2 1 0 Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name SLPINT VC3 VC2 VC1 SYSCLKX2 SYSCLK CLK24M CLK32K This register is used to enable tri-state buffers that connect specific system clocks to specific global output even nets. For additional information, refer to the “Register Definitions” on page 469 in the Digital Clocks chapter. Bit Name Description 7 SLPINT 0 1 The sleep interrupt is not driven onto a global net. The sleep interrupt is driven onto GOE[7]. 6 VC3 0 1 The VC3 clock is not driven onto a global net The VC3 clock is driven onto GOE[6] 5 VC2 0 1 The VC2 clock is not driven onto a global net The VC2 clock is driven onto GOE[5] 4 VC1 0 1 The VC1 clock is not driven onto a global net The VC1 clock is driven onto GOE[4] 3 SYSCLKX2 0 1 The 2 times system clock is not driven onto a global net The 2 times system clock is driven onto GOE[3] 2 SYSCLK 0 1 The system clock is not driven onto a global net The system clock is driven onto GOE[2] 1 CLK24M 0 1 The 24 MHz clock is not driven onto a global net The 24 MHz system clock is driven onto GOE[1] 0 CLK32K 0 1 The 32 kHz clock is not driven onto a global net The 32 kHz system clock is driven onto GOE[0] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 293 OSC_CR4 1,DEh 13.3.74 OSC_CR4 Oscillator Control Register 4 Individual Register Names and Addresses: 1,DEh OSC_CR4: 1,DEh 7 6 5 4 3 2 1 0 RW : 0 Access : POR VC3 Input Select[1:0] Bit Name This register selects the input clock to variable clock 3 (VC3). In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 469 in the Digital Clocks chapter. Bit Name Description 1:0 VC3 Input Select[1:0] Selects the clocking source for the VC3 Clock Divider. 00b SYSCLK 01b VC1 10b VC2 11b SYSCLKX2 294 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F OSC_CR3 1,DFh 13.3.75 OSC_CR3 Oscillator Control Register 3 Individual Register Names and Addresses: 1,DFh OSC_CR3: 1,DFh 7 6 5 4 3 2 1 0 RW : 00 Access : POR VC3 Divider[7:0] Bit Name This register selects the divider value for variable clock 3 (VC3). The output frequency of the VC3 Clock Divider is the input frequency divided by the value in this register, plus one. For example, if this register contains 07h, the clock frequency output from the VC3 Clock Divider will be one eighth the input frequency. For additional information, refer to the “Register Definitions” on page 469 in the Digital Clocks chapter. Bit Name Description 7:0 VC3 Divider[7:0] Refer to the OSC_CR4 register. 0000 0000b Input Clock 0000 0001b Input Clock / 2 0000 0010b Input Clock / 3 0000 0011b Input Clock / 4 ... ... 1111 1100b Input Clock / 253 1111 1101b Input Clock / 254 1111 1110b Input Clock / 255 1111 1111b Input Clock / 256 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 295 OSC_CR0 1,E0h 13.3.76 OSC_CR0 Oscillator Control Register 0 Individual Register Names and Addresses: 1,E0h OSC_CR0: 1,E0h 7 6 5 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] Access : POR Bit Name 4 3 2 1 0 This register is used to configure various features of internal clock sources and clock nets. For additional information, refer to the “Register Definitions” on page 469 in the Digital Clocks chapter. Bit Name Description 7 32k Select 0 1 Internal low precision 32 kHz oscillator External crystal 32.768 kHz oscillator 6 PLL Mode 0 1 Disabled Enabled. Internal main oscillator is frequency locked to External Crystal Oscillator. 5 No Buzz 0 1 BUZZ bandgap during power down. Bandgap is always powered even during sleep. 4:3 Sleep[1:0] Sleep Interval when SLP_EXTEND=0 00b 1.95 ms (512 Hz) 01b 15.6 ms (64 Hz) 10b 125 ms (8 Hz) 11b 1s (1 Hz) Sleep Interval when SLP_EXTEND=1 00b 2s (1/2 Hz) 01b 4s (1/4 Hz) 10b 8s (1/8 Hz) 11b 16s (1/16 Hz) 2:0 CPU Speed[2:0] These bits set the CPU clock speed, based on the system clock (SYSCLK). SYSCLK is 24 MHz by default, but it can optionally be set to 6 MHz on some PSoC devices (see the “Architectural Description” on page 81), or driven from an external clock. 000b 001b 010b 011b 100b 101b 110b 111b 296 6 MHz IMO 750 kHz 1.5 MHz 3 MHz 6 MHz 375 kHz 187.5 kHz 46.9 kHz 23.4 kHz 24 MHz IMO 3 MHz 6 MHz 12 MHz 24 MHz 1.5 MHz 750 kHz 187.5 kHz 93.7 kHz External Clock EXTCLK / 8 EXTCLK / 4 EXTCLK / 2 EXTCLK / 1 EXTCLK / 16 EXTCLK / 32 EXTCLK / 128 EXTCLK / 256 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F OSC_CR1 1,E1h 13.3.77 OSC_CR1 Oscillator Control Register 1 Individual Register Names and Addresses: 1,E1h OSC_CR1: 1,E1h 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 0 RW : 0 VC1 Divider[3:0] VC2 Divider[3:0] 0 This register selects the divider value for variable clocks 1 and 2 (VC1 and VC2). For additional information, refer to the “Register Definitions” on page 469 in the Digital Clocks chapter. Bit Name 7:4 VC1 Divider[3:0] 3:0 Description 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Internal Main Oscillator 24 MHz 12 MHz 8 MHz 6 MHz 4.8 MHz 4 MHz 3.43 MHz 3 MHz 2.67 MHz 2.40 MHz 2.18 MHz 2.00 MHz 1.85 MHz 1.71 MHz 1.6 MHz 1.5 MHz External Clock EXTCLK / 1 EXTCLK / 2 EXTCLK / 3 EXTCLK / 4 EXTCLK / 5 EXTCLK / 6 EXTCLK / 7 EXTCLK / 8 EXTCLK / 9 EXTCLK / 10 EXTCLK / 11 EXTCLK / 12 EXTCLK / 13 EXTCLK / 14 EXTCLK / 15 EXTCLK / 16 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Internal Main Oscillator (24 / (OSC_CR1[7:4]+1)) / 1 (24 / (OSC_CR1[7:4]+1)) / 2 (24 / (OSC_CR1[7:4]+1)) / 3 (24 / (OSC_CR1[7:4]+1)) / 4 (24 / (OSC_CR1[7:4]+1)) / 5 (24 / (OSC_CR1[7:4]+1)) / 6 (24 / (OSC_CR1[7:4]+1)) / 7 (24 / (OSC_CR1[7:4]+1)) / 8 (24 / (OSC_CR1[7:4]+1)) / 9 (24 / (OSC_CR1[7:4]+1)) / 10 (24 / (OSC_CR1[7:4]+1)) / 11 (24 / (OSC_CR1[7:4]+1)) / 12 (24 / (OSC_CR1[7:4]+1)) / 13 (24 / (OSC_CR1[7:4]+1)) / 14 (24 / (OSC_CR1[7:4]+1)) / 15 (24 / (OSC_CR1[7:4]+1)) / 16 External Clock (EXTCLK / (OSC_CR1[7:4]+1)) / 1 (EXTCLK / (OSC_CR1[7:4]+1)) / 2 (EXTCLK / (OSC_CR1[7:4]+1)) / 3 (EXTCLK / (OSC_CR1[7:4]+1)) / 4 (EXTCLK / (OSC_CR1[7:4]+1)) / 5 (EXTCLK / (OSC_CR1[7:4]+1)) / 6 (EXTCLK / (OSC_CR1[7:4]+1)) / 7 (EXTCLK / (OSC_CR1[7:4]+1)) / 8 (EXTCLK / (OSC_CR1[7:4]+1)) / 9 (EXTCLK / (OSC_CR1[7:4]+1)) / 10 (EXTCLK / (OSC_CR1[7:4]+1)) / 11 (EXTCLK / (OSC_CR1[7:4]+1)) / 12 (EXTCLK / (OSC_CR1[7:4]+1)) / 13 (EXTCLK / (OSC_CR1[7:4]+1)) / 14 (EXTCLK / (OSC_CR1[7:4]+1)) / 15 (EXTCLK / (OSC_CR1[7:4]+1)) / 16 VC2 Divider[3:0] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 297 OSC_CR2 1,E2h 13.3.78 OSC_CR2 Oscillator Control Register 2 Individual Register Names and Addresses: 1,E2h OSC_CR2: 1,E2h 4 3 2 1 0 RW : 0 7 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 PLLGAIN SLP_EXTEND WDR32_SE EXTCLKEN RSVD SYSCLKX2DIS Access : POR Bit Name 6 5 This register is used to configure various features of internal clock sources and clock nets. In OCD mode (OCDM = 1), bits [1:0] have no effect. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 469 in the Digital Clocks chapter. Bit Name Description 7 PLLGAIN Phase-locked loop gain. 0 Recommended value, normal gain. 1 Reduced gain to make PLL more tolerant to noisy or jittery crystal input. 4 SLP_EXTEND Extend sleep timer period. SLP_EXTEND = 0 OSC_CR0 register. SLEEP[1:0] 00b 2 ms 01b 16 ms 10b 128 ms 11b 1s SLP_EXTEND = 1 OSC_CR0 register, SLEEP[1:0] 00b 2s 01b 4s 10b 8s 11b 16s 3 WDR32_SE Watchdog clock source selection. 0 The same 32 kHz clock source as system setting, default mode. 1 Uses internal 32 kHz oscillator as clock source, even if external 32 kHz clock source is enabled. 2 EXTCLKEN External clock mode enable. 0 Disabled. Operate from internal main oscillator. 1 Enabled. Operate from clock supplied at port P1[4]. 1 RSVD Reserved bit. This bit should always be 0. 0 SYSCLKX2DIS 48 MHz clock source disable. 0 Enabled. If enabled, system clock net is forced on. 1 Disabled for power reduction. 298 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F VLT_CR 1,E3h 13.3.79 VLT_CR Voltage Monitor Control Register Individual Register Names and Addresses: 1,E3h VLT_CR: 1,E3h 7 Access : POR 6 5 4 3 2 1 RW : 0 RW : 0 RW : 0 RW : 0 SMP PORLEV[1:0] LVDTBEN VM[2:0] Bit Name 0 This register is used to set the trip points for POR, LVD, and the supply pump. Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 523 in the POR and LVD chapter. Bit Name Description 7 SMP Switch Mode Pump disable for those PSoC devices with this feature. 0 SMP enabled. 1 SMP disabled. 5:4 PORLEV[1:0] Sets the POR level per the DC electrical specifications in the PSoC device data sheet. 00b POR level for 2.4 V or 3 V operation (refer to the PSoC device data sheet) 01b POR level for 3.0 V or 4.5 V operation (refer to the PSoC device data sheet) 10b POR level for 4.75 V operation 11b Reserved 3 LVDTBEN Enables reset of CPU speed register by LVD comparator output. 0 Disables CPU speed throttle-back. 1 Enables CPU speed throttle-back. 2:0 VM[2:0] Sets the LVD and pump levels per the DC electrical specifications in the PSoC device data sheet, for those PSoC devices with this feature. 000b Lowest voltage setting 001b 010b . 011b . 100b . 101b 110b 111b Highest voltage setting CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 299 VLT_CMP 1,E4h 13.3.80 VLT_CMP Voltage Monitor Comparators Register Individual Register Names and Addresses: 1,E4h VLT_CMP: 1,E4h 7 6 5 4 Access : POR Bit Name 3 2 1 0 R:0 R:0 R:0 PUMP LVD PPOR This register is used to read the state of internal supply voltage monitors. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 523 in the POR and LVD chapter. Bit Name Description 2 PUMP Read state of pump comparator. 0 Vdd is above trip point. 1 Vdd is below trip point. 1 LVD Reads state of LVD comparator. 0 Vdd is above LVD trip point. 1 Vdd is below LVD trip point. 0 PPOR Reads state of Precision POR comparator (only useful with PPOR reset disabled, with PORLEV[1:0] in VLT_CR register set to 11b). 0 Vdd is above PPOR trip voltage. 1 Vdd is below PPOR trip voltage. 300 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F ADCx_TR 1,E5h 13.3.81 ADCx_TR Type E ADC Trim Register Individual Register Names and Addresses: ADC0_TR : 1,E5h 2L* Column 1,E5h ADC1_TR : 1,E6h 7 6 5 4 3 2 1 0 RW : 00 Access : POR CAPVAL_[7:0] Bit Name * This table shows the two column limited functionality of the CY8C28xxx PSoC devices for this register. This register controls a combination of capacitor and current values that determine the slope of the ADC voltage ramp. ADC0_TR is the ADC column 0 trim register and ADC1_TR is the ADC column 1 trim register. For additional information, refer to the “Register Definitions” on page 452 in the Two Column Limited Analog System chapter. Bits Name Description 7:0 CAPVAL_[7:0] Controls, in binary weighted segments, the capacitor trim for ADC and general analog operation. This trim has a 16-1 range. By default (0000b), all capacitors are switched into the circuit, which is the maximum capacitance. 0 Switches that binary weighted capacitor segment into the circuit (more capacitance). 1 Switches that binary weighted capacitor segment out of the circuit (less capacitance). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 301 IDAC_MODE 1,E7h 13.3.82 IDAC_MODE IDAC Mode Control Register Individual Register Names and Addresses: 1,E7h IDAC_MODE: 1,E7h 7 Access : POR 6 5 RW : 00 4 3 RW : 00 IDAC1_MD[3:0] Bit Name 2 1 RW : 00 0 RW : 00 IDAC0_MD[3:0] This register controls the selection of the IDAC ON/OFF Control. For additional information, refer to the “Register Definitions” on page 528 in the I/O Analog Multiplexer chapter. Bit Name Description 7:1 IDACx_MD[3:0] Select the signal to control IDAC ON/OFF. 0000b Always ON 0001b Reserved 0010b Reserved 0011b Reserved 0100b DECD[0], Decimator 0 data input 0101b DECD[1], Decimator 1 data input 0110b DECD[2], Decimator 2 data input 0111b DECD[3], Decimator 3 data input 1000b ACC_CMP[0], ACC 0 compare bus 1001b ACC_CMP[1], ACC 1 compare bus 1010b ACC_CMP[2], ACC 2 compare bus 1011b ACC_CMP[3], ACC 3 compare bus 1100b Reserved 1101b Reserved 1110b ACE_CMPFF[0], ACE 0 compare bus 1111b ACE_CMPFF[1], ACE 1 compare bus 302 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F IMO_TR 1,E8h 13.3.83 IMO_TR Internal Main Oscillator Trim Register Individual Register Names and Addresses: 1,E8h IMO_TR: 1,E8h 7 6 5 4 3 2 1 0 W : 00 Access : POR Trim[7:0] Bit Name This register is used to manually center the oscillator’s output to a target frequency. It is strongly recommended that the user not alter this register’s values. The value in this register should not be changed. For additional information, refer to the “Register Definitions” on page 82 in the Internal Main Oscillator chapter. Bit Name Description 7:0 Trim[7:0] The value of this register is used to trim the Internal Main Oscillator. Its value is set to the best value for the device during boot. The value of these bits should not be changed. 0000 0000b Lowest frequency setting 0000 0001b ... ... 0111 1111b 1000 0000b Design center setting 1000 0001b ... ... 1111 1110b 1111 1111b Highest frequency setting CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 303 ILO_TR 1,E9h 13.3.84 ILO_TR Internal Low Speed Oscillator Trim Register Individual Register Names and Addresses: 1,E9h ILO_TR: 1,E9h 7 6 Access : POR Bit Name 5 4 3 2 1 RW : 0 RW : 0 Bias Trim[1:0] Freq Trim[3:0] 0 This register sets the adjustment for the Internal Low Speed Oscillator (ILO). It is strongly recommended that the user not alter this register’s values. The trim bits are set to factory specifications and should not be changed. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 85 in the Internal Low Speed Oscillator chapter. Bit Name Description 5:4 Bias Trim[1:0] The value of this register is used to trim the Internal Low Speed Oscillator. Its value is set to the device specific, best value during boot. The value of these bits should not be changed. 00b Medium bias 01b Maximum bias (recommended) 10b Minimum bias 11b Intermediate Bias * * About 15% higher than the minimum bias. 3:0 Freq Trim[3:0] The value of this register is used to trim the Internal Low Speed Oscillator. Its value is set to the device specific, best value during boot. The value of these bits should not be changed. 304 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F BDG_TR 1,EAh 13.3.85 BDG_TR Bandgap Trim Register Individual Register Names and Addresses: 1,EAh BDG_TR: 1,EAh 7 Access : POR Bit Name 6 5 4 3 2 1 RW : 0 RW : 01 RW : 8h AGNDBYP TC[1:0] V[3:0] 0 This register is used to adjust the bandgap and add an RC filter to AGND. Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 511 in the Internal Voltage Reference chapter. Bit Name Description 6 AGNDBYP If set, an external bypass capacitor on AGND may be connected to Port 2[4]. 0 Disable 1 Enable 5:4 TC[1:0] The value of these bits is used to trim the temperature coefficient. Their value is set to the best value for the device during boot. The value of these bits should not be changed. 3:0 V[3:0] The value of these bits is used to trim the bandgap reference. Their value is set to the best value for the device during boot. The value of these bits should not be changed. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 305 ECO_TR 1,EBh 13.3.86 ECO_TR External Crystal Oscillator Trim Register Individual Register Names and Addresses: 1,EBh ECO_TR: 1,EBh 7 Access : POR 6 5 4 3 2 1 0 RW : 0 PSSDC[1:0] Bit Name This register sets the adjustment for the 32.768 kHz External Crystal Oscillator. The value in this register should not be changed. The value is used to trim the 32.768 kHz external crystal oscillator and is set to the device specific, best value during boot. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 89 in the External Crystal Oscillator (ECO) chapter. Bit Name Description 7:6 PSSDC[1:0] Sleep duty cycle. Controls the ratios (in numbers of 32.768 kHz clock periods) of “on” time versus “off” time for PORLVD, Bandgap reference, and pspump. These bits should not be changed. 00b 1 / 128 01b 1 / 512 10b 1 / 32 11b 1/8 306 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F IMO_TR1 1,EFh 13.3.87 IMO_TR1 Internal Main Oscillator Trim Register 1 Individual Register Names and Addresses: 1,EFh IMO_TR1: 1,EFh 7 6 5 4 3 2 1 0 RW : 0 Access : POR CATA_Trim[1:0] Bit Name This register is used to tune CATA current. For additional information, refer to the “Register Definitions” on page 82 in the Internal Main Oscillator chapter. Bit Name Description 1:0 CATA_Trim[1:0] These bits are used to tune CATA current. 00b Largest CATA current (reset value) ... ... 11b Smallest CATA current CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 307 FLS_PR1 1,FAh 13.3.88 FLS_PR1 Flash Program Register 1 Individual Register Names and Addresses: 1,FAh FLS_PR1: 1,FAh 7 6 5 4 3 2 1 0 RW : 0 Access : POR Bank Bit Name This register is used to specify which Flash bank should be used for SROM operations. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the Supervisory ROM (SROM) chapter on page 49. Bit Name Description 0 Bank Selects the active Flash bank for supervisory operations. No affect in User mode. 0 Flash Bank 0 1 Flash Bank 1 308 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F IDAC_CR0 1,FDh 13.3.89 IDAC_CR0 IDAC Control Register 0 Individual Register Names and Addresses: 1,FDh IDAC_CR0 : 1,FDh Access : POR Bit Name 7 6 RW : 0 RW : 0 5 RW : 0 4 RW : 0 3 2 RW : 0 1 RW : 0 0 SplitMux MuxClkGE0 OSCMD1[1:0] IRANGE OSCMD0[1:0] EN0 This register contains the control bits for the IDAC current that drives the analog mux bus and for selecting the split configuration for the CY8C28xxx PSoC devices. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the “Register Definitions” on page 528 in the I/ O Analog Multiplexer chapter. Bits Name Description 7 SplitMux Configures the analog mux bus Left side connects to odd pins (P0[1], P5[5]) and right side connects to even pins (P0[2], P5[6]) with one exception: P0[7] is a right side pin. 0 Split analog mux bus: left side pins connect to Analog Mux Bus Left (Muxbus0) and right side pins connect to Analog Mux Bus Right (Muxbus1). 1 Single analog mux bus. 6 MuxClkGE0 Global enable connection for MUXCLK0. 0 Analog mux bus clock not connected to global. 1 Connect analog mux bus clock to global GOO[6]. 5:4 OSCMD1[1:0] When set, these bits enable the analog mux bus right (Muxbus1) to reset to Vss whenever the comparator trip point is reached. 3 IRANGE Sets the DAC range. Note that the value for the unit current is found in the PSoC data sheet. 0 Low range 1 High range (16 times low range) 2:1 OSCMD0[1:0] When set, these bits enable the analog mux bus left (Muxbus0) to reset to Vss whenever the comparator trip point is reached. 00b No automatic reset. 01b Reset whenever GOO[4] is high. 10b Reset whenever GOO[5] is high. 11b Reset whenever either GOO[4] or GOO[5] is high. 0 EN0 0 1 IDAC0 function disabled (no DAC current). IDAC0 function enabled. The DAC current charges the analog mux bus. If the SplitMux is set high, the charging current only charges the mux bus left (Muxbus0). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 309 IDAC_CR0 1,FDh 310 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Section D: Digital System The configurable Digital System section discusses the digital components of the PSoC® device and the registers associated with those components. This section encompasses the following chapters: ■ Global Digital Interconnect (GDI) on page 317 ■ Row Digital Interconnect (RDI) on page 327 ■ Array Digital Interconnect (ADI) on page 325 ■ Digital Blocks on page 335 Top-Level Digital Architecture The following figure displays the top-level architecture of the PSoC’s digital system. Each component of the figure is discussed at length in this section. PSoC Digital System Block Diagram Port 5 Port 3 Port 4 Port 1 Port 2 Digital Clocks From Core To System Bus Port 0 To Analog System Interpreting the Digital Documentation Information in this section covers all PSoC devices with a base part number of CY8C28xxx. The primary digital distinction between these devices is the number of digital rows. This can be either 2 or 3 rows. The following table lists the resources available for specific device groups. While reading the digital system section, determine and keep in mind the number of digital rows that are in your device, to accurately interpret this documentation. DCC03 4 8 DBC10 DBC11 DCC12 4 DCC13 4 Row 2 DBC20 DBC21 DCC22 4 DCC23 4 GIE[7:0] GIO[7:0] Global Digital Interconnect 8 Row Output Configuration Row Input Configuration Row 1 Row Output Configuration Row Input Configuration 8 3 12 8 0 0 0 0 40 3 12 40 0 2 0 4 CY8C28x23 44 3 12 10 2 2 6 0 CY8C28x33 40 3 12 40 2 4 6 4 CY8C28x43 44 3 12 44 4 4 12 0 CY8C28x45 44 3 12 44 4 4 12 4 CY8C28x52 24 2 8 24 4 4 12 4 Analog Columns 24 Analog Outputs CY8C28x03* CY8C28x13* PSoC Part Number 8 Limited Analog Blocks DCC02 Regular Analog Blocks DBC01 Digital Blocks DBC00 4 Digital Rows Row 0 Row Output Configuration Row Input Configuration Digital PSoC Block Array Digital I/O (max) DIGITAL SYSTEM Analog Inputs (max) PSoC Device Characteristics * Limited analog functionality. GOE[7:0] GOO[7:0] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 311 Digital Register Summary The following table lists all the PSoC registers for the digital system in address order (Add. column) within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. The naming conventions for the digital row registers and the digital block registers are detailed in their respective table title rows. Note that all PSoC devices with a base part number of CY8C28xxx fall into one of the following categories with respect to their digital PSoC rows: 3 row device or 2 row device. The “PSoC Digital System Block Diagram” at the beginning of this section illustrates this. In the following table, the third column from the left titled “Digital Rows” indicates which of the two PSoC device categories the register falls into. To determine the number of digital rows in your PSoC device, refer to the table titled “PSoC Device Characteristics” on page 311. Summary Table of the Digital Registers Add. Name Digital Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access GLOBAL DIGITAL INTERCONNECT (GDI) REGISTERS (page 322) 1,A0h GDI_O_IN_CR 3, 2, GDIOICR7 GDIOICR6 GDIOICR5 GDIOICR4 GDIOICR3 GDIOICR2 GDIOICR1 GDIOICR0 RW : 00 1,A1h GDI_E_IN_CR 3, 2, GDIEICR7 GDIEICR6 GDIEICR5 GDIEICR4 GDIEICR3 GDIEICR2 GDIEICR1 GDIEICR0 RW : 00 1,A2h GDI_O_OU_CR 3, 2, GDIOOCR7 GDIOOCR6 GDIOOCR5 GDIOOCR4 GDIOOCR3 GDIOOCR2 GDIOOCR1 GDIOOCR0 RW : 00 1,A3h GDI_E_OU_CR 3, 2, GDIEOCR7 GDIEOCR6 GDIEOCR5 GDIEOCR4 GDIEOCR3 GDIEOCR2 GDIEOCR1 GDIEOCR0 RW : 00 1,D0h GDI_O_IN 3, 2, GIONOUT7 GIONOUT6 GIONOUT5 GIONOUT4 GIONOUT3 GIONOUT2 GIONOUT1 GIONOUT0 RW : 00 1,D1h GDI_E_IN 3, 2, GIENOUT7 GIENOUT6 GIENOUT5 GIENOUT4 GIENOUT3 GIENOUT2 GIENOUT1 GIENOUT0 RW : 00 1,D2h GDI_O_OU 3, 2, GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 RW : 00 1,D3h GDI_E_OU 3, 2, GOEUTIN7 GOEUTIN6 GOEUTIN5 GOEUTIN4 GOEUTIN3 GOEUTIN2 GOEUTIN1 GOEUTIN0 RW : 00 DIGITAL ROW REGISTERS (page 329) x,B0h RDI0RI 3, 2, x,B1h RDI0SYN 3, 2, x,B2h RDI0IS 3, 2, x,B3h RDI0LT0 3, 2, RI3[1:0] RI2[1:0] BCSEL[1:0] RI1[1:0] RI0[1:0] RW : 00 RI3SYN RI2SYN RI1SYN RI0SYN IS3 IS2 IS1 IS0 LUT1[3:0] LUT0[3:0] x,B4h RDI0LT1 3, 2, RDI0RO0 3, 2, GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN x,B6h RDI0RO1 3, 2, GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN x,B7h RDI0DSM 3, 2, x,B8h RDI1RI 3, 2, RDI1SYN 3, 2, x,BAh RDI1IS 3, 2, x,BBh RDI1LT0 3, 2, LUT2[3:0] AVG_SEL[3:0] RI3[1:0] RW : 00 AVG_EN[3:0] RI2[1:0] BCSEL[1:0] RI1[1:0] RI0[1:0] RI1SYN RI0SYN IS3 IS2 IS1 IS0 LUT0[3:0] x,BCh RDI1LT1 3, 2, RDI1RO0 3, 2, GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN x,BEh RDI1RO1 3, 2, GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN x,BFh RDI1DSM 3, 2, LUT2[3:0] RW : 00 AVG_EN[3:0] RI2[1:0] RW : 00 RW : 00 RW : 00 x,C0h RDI2RI 3 RDI2SYN 3 x,C2h RDI2IS 3 x,C3h RDI2LT0 3 LUT1[3:0] LUT0[3:0] RW : 00 x,C4h RDI2LT1 3 LUT3[3:0] LUT2[3:0] RW : 00 x,C5h RDI2RO0 3 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN x,C6h RDI2RO1 3 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN x,C7h RDI2DSM 3 BCSEL[1:0] AVG_SEL[3:0] RI1[1:0] RW : 00 x,C1h 312 RI3[1:0] RW : 00 RW : 00 x,BDh AVG_SEL[3:0] RW : 00 RW : 00 RI2SYN LUT3[3:0] RW : 00 RW : 00 RI3SYN LUT1[3:0] RW : 00 RW : 00 x,B5h x,B9h LUT3[3:0] RW : 00 RI0[1:0] RW : 00 RI3SYN RI2SYN RI1SYN RI0SYN RW : 00 IS3 IS2 IS1 IS0 RW : 00 AVG_EN[3:0] RW : 00 RW : 00 RW : 00 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Summary Table of the Digital Registers (continued) Add. Name Digital Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access DIGITAL BLOCK REGISTERS (page 348) Digital Block Data and Control Registers (page 348) 0,20h DBC00DR0 3, 2, Data[7:0] # : 00 0,21h DBC00DR1 3, 2, Data[7:0] W : 00 0,22h DBC00DR2 3, 2, 0,23h DBC00CR0 3, 2, 1,20h DBC00FN 3, 2, 1,21h DBC00IN 3, 2, 1,22h DBC00OU 3, 2, Data[7:0] # : 00 Function control/status bits for selected function[6:0] Data Invert BCEN End Single Mode[1:0] Function[2:0] Data Input[3:0] AUXCLK AUXEN Enable Clock Input[3:0] AUX IO Select[1:0] OUTEN # : 00 RW : 00 RW : 00 Output Select[1:0] RW : 00 1,23h DBC00CR1 3, 2, Function control/status bits for selected function[7:0] 0,24h DBC01DR0 3, 2, Data[7:0] # : 00 0,25h DBC01DR1 3, 2, Data[7:0] W : 00 0,26h DBC01DR2 3, 2, 0,27h DBC01CR0 3, 2, 1,24h DBC01FN 3, 2, 1,25h DBC01IN 3, 2, 1,26h DBC01OU 3, 2, RW : 00 Data[7:0] # : 00 Function control/status bits for selected function[6:0] Data Invert BCEN End Single Mode[1:0] Function[2:0] Data Input[3:0] AUXCLK AUXEN Enable Clock Input[3:0] AUX IO Select[1:0] OUTEN # : 00 RW : 00 RW : 00 Output Select[1:0] RW : 00 1,27h DBC01CR1 3, 2, Function control/status bits for selected function[7:0] 0,28h DCC02DR0 3, 2, Data[7:0] # : 00 0,29h DCC02DR1 3, 2, Data[7:0] W : 00 0,2Ah DCC02DR2 3, 2, 0,2Bh DCC02CR0 3, 2, 1,28h DCC02FN 3, 2, 1,29h DCC02IN 3, 2, 1,2Ah DCC02OU 3, 2, RW : 00 Data[7:0] # : 00 Function control/status bits for selected function[6:0] Data Invert BCEN End Single Mode[1:0] Function[2:0] Data Input[3:0] AUXCLK AUXEN Enable Clock Input[3:0] AUX IO Select[1:0] OUTEN # : 00 RW : 00 RW : 00 Output Select[1:0] RW : 00 1,2Bh DCC02CR1 3, 2, Function control/status bits for selected function[7:0] 0,2Ch DCC03DR0 3, 2, Data[7:0] # : 00 0,2Dh DCC03DR1 3, 2, Data[7:0] W : 00 0,2Eh DCC03DR2 3, 2, 0,2Fh DCC03CR0 3, 2, 1,2Ch DCC03FN 3, 2, 1,2Dh DCC03IN 3, 2, 1,2Eh DCC03OU 3, 2, RW : 00 Data[7:0] # : 00 Function control/status bits for selected function[6:0] Data Invert BCEN End Single Mode[1:0] Function[2:0] Data Input[3:0] AUXCLK AUXEN Enable Clock Input[3:0] AUX IO Select[1:0] OUTEN # : 00 RW : 00 RW : 00 Output Select[1:0] RW : 00 1,2Fh DCC03CR1 3, 2, Function control/status bits for selected function[7:0] 0,30h DBC10DR0 3, 2, Data[7:0] # : 00 0,31h DBC10DR1 3, 2, Data[7:0] W : 00 0,32h DBC10DR2 3, 2, 0,33h DBC10CR0 3, 2, 1,30h DBC10FN 3, 2, 1,31h DBC10IN 3, 2, 1,32h DBC10OU 3, 2, RW : 00 Data[7:0] # : 00 Function control/status bits for selected function[7:1] Data Invert BCEN End Single Mode[1:0] Function[2:0] Data Input[3:0] AUXCLK AUXEN Enable Clock Input[3:0] AUX IO Select[1:0] OUTEN # : 00 RW : 00 RW : 00 Output Select[1:0] RW : 00 1,33h DBC10CR1 3, 2, Function control/status bits for selected function[7:0] 0,34h DBC11DR0 3, 2, Data[7:0] # : 00 0,35h DBC11DR1 3, 2, Data[7:0] W : 00 0,36h DBC11DR2 3, 2, 0,37h DBC11CR0 3, 2, 1,34h DBC11FN 3, 2, 1,35h DBC11IN 3, 2, 1,36h DBC11OU 3, 2, 1,37h DBC11CR1 3, 2, RW : 00 Data[7:0] # : 00 Function control/status bits for selected function[7:1] Data Invert BCEN End Single Mode[1:0] Data Input[3:0] AUXCLK AUXEN Enable Function[2:0] Clock Input[3:0] AUX IO Select[1:0] OUTEN Function control/status bits for selected function[7:0] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Output Select[1:0] # : 00 RW : 00 RW : 00 RW : 00 RW : 00 313 Summary Table of the Digital Registers (continued) Add. Name Digital Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,38h DCC12DR0 3, 2, Data[7:0] # : 00 0,39h DCC12DR1 3, 2, Data[7:0] W : 00 0,3Ah DCC12DR2 3, 2, 0,3Bh DCC12CR0 3, 2, 1,38h DCC12FN 3, 2, Data[7:0] # : 00 Function control/status bits for selected function[7:1] Data Invert BCEN End Single Enable Mode[1:0] Function[2:0] 1,39h DCC12IN 3, 2, 1,3Ah DCC12OU 3, 2, 1,3Bh DCC12CR1 3, 2, Function control/status bits for selected function[7:0] 0,3Ch DCC13DR0 3, 2, Data[7:0] # : 00 0,3Dh DCC13DR1 3, 2, Data[7:0] W : 00 0,3Eh DCC13DR2 3, 2, 0,3Fh DCC13CR0 3, 2, 1,3Ch DCC13FN 3, 2, Data Input[3:0] # : 00 RW : 00 AUXCLK AUXEN Clock Input[3:0] AUX IO Select[1:0] OUTEN RW : 00 Output Select[1:0] RW : 00 Data[7:0] # : 00 Function control/status bits for selected function[7:1] Data Invert BCEN End Single RW : 00 Enable Mode[1:0] Function[2:0] Data Input[3:0] # : 00 RW : 00 1,3Dh DCC13IN 3, 2, 1,3Eh DCC13OU 3, 2, 1,3Fh DCC13CR1 3, 2, 0,40h DBC20DR0 3 Data[7:0] # : 00 0,41h DBC20DR1 3 Data[7:0] W : 00 AUXCLK AUXEN Clock Input[3:0] AUX IO Select[1:0] OUTEN RW : 00 Output Select[1:0] Function control/status bits for selected function[7:0] RW : 00 RW : 00 0,42h DBC20DR2 3 0,43h DBC20CR0 3 Data[7:0] # : 00 1,40h DBC20FN 3 1,41h DBC20IN 3 1,42h DBC20OU 3 1,43h DBC20CR1 3 Function control/status bits for selected function[7:0] 0,44h DBC21DR0 3 Data[7:0] # : 00 0,45h DBC21DR1 3 Data[7:0] W : 00 Function control/status bits for selected function[7:1] Data Invert BCEN End Single Mode[1:0] Function[2:0] Data Input[3:0] AUXCLK AUXEN Enable RW : 00 Clock Input[3:0] AUX IO Select[1:0] OUTEN # : 00 RW : 00 Output Select[1:0] RW : 00 RW : 00 0,46h DBC21DR2 3 0,47h DBC21CR0 3 Data[7:0] # : 00 1,44h DBC21FN 3 1,45h DBC21IN 3 1,46h DBC21OU 3 1,47h DBC21CR1 3 Function control/status bits for selected function[7:0] 0,48h DCC22DR0 3 Data[7:0] # : 00 0,49h DCC22DR1 3 Data[7:0] W : 00 Function control/status bits for selected function[7:1] Data Invert BCEN End Single Mode[1:0] Function[2:0] Data Input[3:0] AUXCLK AUXEN Enable RW : 00 Clock Input[3:0] AUX IO Select[1:0] OUTEN # : 00 RW : 00 Output Select[1:0] RW : 00 RW : 00 0,4Ah DCC22DR2 3 0,4Bh DCC22CR0 3 1,48h DCC22FN 3 1,49h DCC22IN 3 1,4Ah DCC22OU 3 1,4Bh DCC22CR1 3 Function control/status bits for selected function[7:0] 0,4Ch DCC23DR0 3 Data[7:0] # : 00 0,4Dh DCC23DR1 3 Data[7:0] W : 00 0,4Eh DCC23DR2 3 0,4Fh DCC23CR0 3 1,4Ch DCC23FN 3 1,4Dh DCC23IN 3 1,4Eh DCC23OU 3 1,4Fh DCC23CR1 3 Data[7:0] # : 00 Function control/status bits for selected function[7:1] Data Invert BCEN End Single Mode[1:0] Function[2:0] Data Input[3:0] AUXCLK AUXEN Enable RW : 00 Clock Input[3:0] AUX IO Select[1:0] OUTEN RW : 00 Output Select[1:0] Data[7:0] BCEN End Single # : 00 AUXEN Enable Mode[1:0] Data Input[3:0] AUXCLK RW : 00 RW : 00 Function control/status bits for selected function[7:1] Data Invert # : 00 Function[2:0] RW : 00 Clock Input[3:0] AUX IO Select[1:0] OUTEN # : 00 RW : 00 Output Select[1:0] Function control/status bits for selected function[7:0] RW : 00 RW : 00 Digital Block Interrupt Mask Registers (page 359) 0,DEh 314 INT_MSK3 ENSWINT Analog 5 Analog 4 RTC SARADC I2C1 I2C0 RW : 00 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Summary Table of the Digital Registers (continued) Add. Name 0,DFh INT_MSK2 0,E0h INT_MSK0 0,E1h INT_MSK1 Digital Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 DCC23 DCC22 VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 VC3 Sleep GPIO Analog 1 Analog 0 V Monitor DCC13 DCC12 DBC11 DCC02 DBC01 DBC00 3 3, 2 DBC10 DCC03 Bit 2 Bit 1 Bit 0 Access DBC21 DBC20 RW : 00 Analog 0 V Monitor RW : 00 RW : 00 LEGEND x An ‘x’ before the comma in the address field indicates that this register can be read or written to no matter what bank is used. R: Read register or bit(s). # Access is bit specific. Refer to the Register Details chapter on page 125 for additional information. R Read register or bit(s). W Write register or bit(s). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 315 316 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 14. Global Digital Interconnect (GDI) This chapter discusses the Global Digital Interconnect (GDI) and its associated registers. All PSoC® CY8C28xxx devices have the exact same global digital interconnect options, varying only in the number of 8-bit ports connected to the globals. For a complete table of the GDI registers, refer to the “Summary Table of the Digital Registers” on page 312. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 14.1 Architectural Description Global Digital Interconnect (GDI) consists of four 8-bit buses (refer to the figures that follow). Two of the buses are input buses, which allow signals to pass from the device pins to the core of the PSoC device. These buses are called Global Input Odd (GIO[7:0]) and Global Input Even (GIE[7:0]). The other two buses are output buses that allow signals to pass from the core of the PSoC device to the device pins. They are called Global Output Odd (GOO[7:0]) and Global Output Even (GOE[7:0]). The word “odd” or “even” in the bus name indicates which device ports the bus connects to. Buses with odd in their name connect to all odd numbered ports. Buses with even in their name connect to all even numbered ports. There are two ends to the global digital interconnect core signals and port pins. An end may be configured as a source or a destination. For example, a GPIO pin may be configured to drive a global input or receive a global output and drive it to the package pin. Globals cannot “loop through” a GPIO. Currently, there are two types of core signals connected to the global buses. The digital blocks, which may be a source or a destination for a global net, and system clocks, which may only drive global nets. Many of the digital clocks may also be driven on to the global bus to allow the clocks to route directly to I/O pins. This is shown in the global interconnect block diagrams on the following pages. For more information on this feature, see the Digital Clocks chapter on page 465. Each global input and global output has a keeper on it. The keeper sets the value of the global to ‘1’ on system reset and holds the last driven value of the global should it stop being driven. The primary goal, of the architectural block diagrams that follow, is to communicate the relationship between global buses (GOE, GOO, GIE, GIO) and pins. Note that any global input may be connected to its corresponding global output, using the tri-state buffers located in the corners of the figures. Also, global outputs may be shorted to global inputs using these tri-state buffers. The rectangle in the center of the figure represents the array of digital PSoC blocks. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 317 Global Digital Interconnect (GDI) 14.1.1 20-Pin Global Interconnect To determine the number of digital rows and digital blocks in your PSoC device, refer to the table titled “PSoC Device Characteristics” on page 311. Figure 14-1. Global Interconnect Block Diagram for the CY8C28243 20-Pin Package GOE[7] GOE[5] GOE[3] GOE[1] GIE[6] GIE[4] GIE[2] GIE[0] GIE[7] GIE[5] GIE[3] GIE[1] GOE[6] GOE[4] GOE[2] GOE[0] Even Numbered Pins VC3 P0[5] GO GI P0[3] GO GI P0[1] GO GI VC2 VC1 SYSCLK CLK24M CLK32K GIE[2] GIE[4] GIE[6] GIE[0] GO GI GO GI GO GI GO GI P0[6] GO GI GO GI GO GI GO GI P1[6] P0[4] P0[2] P0[0] CLK32K VC3 VC2 VC1 SYSCLKX2 ACMP[3:0] DB[7:0] DBI INT[23:8] SYSCLKX2 GOE[0] SLPINT GOE[2] Digital Clocks P0[7] GO GI GOE[4] GOE[6] GOE[7] GOE[5] GOE[3] GOE[1] GIE[7] GIE[5] GIE[3] GIE[1] Odd Numbered Pins GIE[7,5,3,1] GOE[7,5,3,1] GIE[6,4,2,0] GOE[6,4,2,0] Digital PSoC Array Odd Numbered Ports Even Numbered Ports GIO[7,5,3,1] GOO[7,5,3,1] GIO[6,4,2,0] GOO[6,4,2,0] CY8C28xxx Analog Array P1[7] GO GI P1[5] GO GI ACC Comp Bus 1 ACC Comp Bus 0 ACC Comp Bus 3 ACC Comp Bus 2 CY8C28xxx Type-E Column AEC1 AEC0 P1[4] P1[2] P1[0] GIO[0] GIO[2] GIO[4] GIO[6] GOO[0] GOO[2] GOO[6] GOO[7] GOO[5] GOO[3] GOO[1] GIO[7] GIO[5] GIO[3] GIO[1] GOO[4] P1[3] GO GI P1[1] GO GI Even Numbered Pins Odd Numbered Pins GOO[0] GOO[2] GOO[4] GOO[6] GIO[1] GIO[3] GIO[5] GIO[7] GIO[0] GIO[2] GIO[4] GIO[6] GOO[1] GOO[3] GOO[5] GOO[7] 318 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Global Digital Interconnect (GDI) 14.1.2 28-Pin Global Interconnect For 28-pin PSoC devices, there are three 8-bit ports. Therefore, there are two ports connected to the even global buses and one port connected to the odd global buses. Table 14-1 lists the mapping between global buses and ports. Table 14-1. 28-Pin Global Bus to Port Mapping Global Bus Ports GIO[7:0], GOO[7:0] P1 GIE[7:0], GOE[7:0] P0, P2 Because up to two ports are connected to a single global bus, there is a one-to-many mapping between individual nets in a global bus and port pins. For example, if GIE[1] is used to bring an input signal into a digital PSoC block, either pin P0[1] or P2[1] may be used. The same is true for the outputs. For example, if GOE[3] is used to carry a signal from a digital PSoC block to a port pin, either or both of the following pins may be used: P0[3] or P2[3]. Only Port 1 pins connect to the GIO/GOO globals in these 28-pin PSoC devices. To determine the number of digital rows and digital blocks in your PSoC device, refer to the table titled “PSoC Device Characteristics” on page 311. Figure 14-2. Global Interconnect Block Diagram for the CY8C284xx 28-Pin Package GOE[7] GOE[5] GOE[3] GOE[1] GIE[6] GIE[4] GIE[2] GIE[0] GIE[7] GIE[5] GIE[3] GIE[1] GOE[6] GOE[4] GOE[2] GOE[0] Even Numbered Pins VC2 VC1 P0[3] GO GI SYSCLKX2 SYSCLK P0[1] GO GI CLK24M CLK32K GIE[0] GIE[2] GIE[4] GIE[6] CLK32K VC3 VC2 VC1 SYSCLKX2 ACMP[3:0] DB[7:0] DBI INT[23:8] GOE[0] VC3 P0[5] GO GI GOE[2] SLPINT GOE[4] Digital Clocks P0[7] GO GI P2[7] GO GI P2[5] GO GI P2[3] GO GI P2[1] GO GI GOE[6] GOE[7] GOE[5] GOE[3] GOE[1] GIE[7] GIE[5] GIE[3] GIE[1] Odd Numbered Pins GIE[7,5,3,1] GOE[7,5,3,1] GO GI GO GI GO GI GO GI P0[6] GO GI GO GI GO GI GO GI P2[6] GO GI GO GI GO GI GO GI P1[6] P0[4] P0[2] P0[0] P2[4] P2[2] P2[0] GIE[6,4,2,0] GOE[6,4,2,0] Digital PSoC Array Odd Numbered Ports Even Numbered Ports GIO[7,5,3,1] GOO[7,5,3,1] GIO[6,4,2,0] GOO[6,4,2,0] CY8C28xxx Analog Array P1[7] GO GI P1[5] GO GI ACC Comp Bus 1 ACC Comp Bus 0 ACC Comp Bus 3 ACC Comp Bus 2 CY8C28xxx Type-E Column P1[3] GO GI AEC1 P1[4] P1[2] P1[0] GIO[0] GIO[2] GIO[4] GIO[6] GOO[0] GOO[2] GOO[4] GOO[6] GOO[7] GOO[5] GOO[3] GIO[7] GIO[5] GIO[3] GIO[1] GOO[1] P1[1] GO GI AEC0 Even Numbered Pins Odd Numbered Pins GOO[0] GOO[2] GOO[4] GOO[6] GIO[1] GIO[3] GIO[5] GIO[7] GIO[0] GIO[2] GIO[4] GIO[6] GOO[1] GOO[3] GOO[5] GOO[7] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 319 Global Digital Interconnect (GDI) 14.1.3 44-Pin Global Interconnect For 44-pin PSoC devices, there are five 8-bit ports. Therefore, there are up to three ports connected to the even global buses and two ports connected to the odd global buses. Table 14-2 lists the mapping between global buses and ports. Table 14-2. 44-Pin Global Bus to Port Mapping Global Bus To determine the number of digital rows and digital blocks in your PSoC device, refer to the table titled “PSoC Device Characteristics” on page 311. Ports GIO[7:0], GOO[7:0] P1, P3 GIE[7:0], GOE[7:0] P0, P2, P4 Because several ports are connected to a single global bus, there is a one-to-many mapping between individual nets in a global bus and port pins. For example, if GIO[1] is used to bring an input signal into a digital PSoC block, either pin P1[1] or P3[1] may be used. The same is true for the outputs. For example, if GOE[3] is used to carry a signal from a digital PSoC block to a port pin, any or all of the following pins may be used: P0[3], P2[3], or P4[3]. Figure 14-3. Global Interconnect Block Diagram for the CY8C285xx 44-Pin Package GOE[7] GOE[5] GOE[3] GOE[1] GIE[6] GIE[4] GIE[2] GIE[0] GIE[7] GIE[5] GIE[3] GIE[1] GOE[6] GOE[4] GOE[2] GOE[0] Even Numbered Pins VC2 VC1 SYSCLK CLK24M CLK32K GIE[0] GIE[2] GIE[4] GIE[6] CLK32K VC3 VC2 VC1 SYSCLKX2 ACMP[3:0] DB[7:0] DBI INT[23:8] SYSCLKX2 GOE[0] VC3 P0[5] GO GI P0[3] GO GI P0[1] GO GI GOE[2] SLPINT GOE[4] Digital Clocks P0[7] GO GI P2[7] GO GI P2[5] GO GI P2[3] GO GI P2[1] GO GI GOE[6] GOE[7] GOE[5] GOE[3] GOE[1] GIE[7] GIE[5] GIE[3] GIE[1] Odd Numbered Pins GIE[7,5,3,1] GOE[7,5,3,1] P4[7] GO GI GIE[6,4,2,0] GOE[6,4,2,0] P4[5] GO GI P4[3] GO GI P4[1] GO GI Odd Numbered Ports Digital PSoC Array Even Numbered Ports P3[7] GO GI P3[5] GO GI P3[3] GO GI P3[1] GO GI GIO[7,5,3,1] GOO[7,5,3,1] P1[7] GO GI GIO[6,4,2,0] GOO[6,4,2,0] CY8C28xxx Analog Array P1[5] GO GI ACC Comp Bus 1 ACC Comp Bus 0 P1[3] GO GI ACC Comp Bus 3 ACC Comp Bus 2 P0[6] GO GI GO GI GO GI GO GI P2[6] GO GI GO GI GO GI GO GI P4[6] GO GI GO GI GO GI GO GI P3[6] GO GI GO GI GO GI GO GI P1[6] P0[4] P0[2] P0[0] P2[4] P2[2] P2[0] P4[4] P4[2] P4[0] P3[4] P3[2] P3[0] P1[4] P1[2] P1[0] GIO[0] GIO[2] GIO[4] GIO[6] GOO[0] AEC0 GOO[2] AEC1 GOO[4] CY8C28xxx Type-E Column GOO[6] GOO[7] GOO[5] GOO[3] GIO[7] GIO[5] GIO[3] GIO[1] GOO[1] P1[1] GO GI GO GI GO GI GO GI GO GI Even Numbered Pins Odd Numbered Pins GOO[0] GOO[2] GOO[4] GOO[6] GIO[1] GIO[3] GIO[5] GIO[7] GIO[0] GIO[2] GIO[4] GIO[6] GOO[1] GOO[3] GOO[5] GOO[7] 320 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Global Digital Interconnect (GDI) 14.1.4 48-Pin Global Interconnect To determine the number of digital rows and digital blocks in your PSoC device, refer to the table titled “PSoC Device Characteristics” on page 311. Figure 14-4. Global Interconnect Block Diagram for the CY8C286xx 48-Pin Package GOE[7] GOE[5] GOE[3] GOE[1] GIE[6] GIE[4] GIE[2] GIE[0] GIE[7] GIE[5] GIE[3] GIE[1] GOE[6] GOE[4] GOE[2] GOE[0] Even Numbered Pins VC2 VC1 SYSCLK CLK24M CLK32K GIE[0] GIE[2] GIE[4] GIE[6] CLK32K VC3 VC2 VC1 SYSCLKX2 ACMP[3:0] DB[7:0] DBI INT[23:8] SYSCLKX2 GOE[0] VC3 P0[5] GO GI P0[3] GO GI P0[1] GO GI GOE[2] SLPINT GOE[4] Digital Clocks P0[7] GO GI P2[7] GO GI P2[5] GO GI P2[3] GO GI P2[1] GO GI GOE[6] GOE[7] GOE[5] GOE[3] GOE[1] GIE[7] GIE[5] GIE[3] GIE[1] Odd Numbered Pins GIE[7,5,3,1] GOE[7,5,3,1] P4[7] GO GI P4[5] GO GI P4[3] GO GI P4[1] GO GI Odd Numbered Ports GIE[6,4,2,0] GOE[6,4,2,0] Digital PSoC Array Even Numbered Ports P3[7] GO GI GIO[7,5,3,1] GOO[7,5,3,1] GIO[6,4,2,0] GOO[6,4,2,0] CY8C28xxx Analog Array ACC Comp Bus 1 ACC Comp Bus 0 ACC Comp Bus 3 ACC Comp Bus 2 GIO[0] GIO[2] GIO[4] GIO[6] GOO[0] AEC0 GOO[2] AEC1 GOO[4] CY8C28xxx Type-E Column GOO[6] GOO[7] GOO[5] GOO[3] GOO[1] GIO[7] GIO[5] GIO[3] GIO[1] P3[5] GO GI P3[3] GO GI P3[1] GO GI P5[3] GO GI P5[1] GO GI P1[7] GO GI P1[5] GO GI P1[3] GO GI P1[1] GO GI GO GI GO GI GO GI GO GI P0[6] GO GI GO GI GO GI GO GI P2[6] GO GI GO GI GO GI GO GI P4[6] GO GI GO GI GO GI GO GI GO GI GO GI GO GI GO GI GO GI GO GI P3[6] P0[4] P0[2] P0[0] P2[4] P2[2] P2[0] P4[4] P4[2] P4[0] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4] P1[2] P1[0] Even Numbered Pins Odd Numbered Pins GOO[0] GOO[2] GOO[4] GOO[6] GIO[1] GIO[3] GIO[5] GIO[7] GIO[0] GIO[2] GIO[4] GIO[6] GOO[1] GOO[3] GOO[5] GOO[7] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 321 Global Digital Interconnect (GDI) 14.1.5 56-Pin Global Interconnect The CY8C28xxx 56-pin PSoC device is only for OCD purposes. Therefore the 56-pin global connection is the same as the CY8C28xxx 44-pin package. 14.2 Register Definitions The following registers are associated with the Global Digital Interconnect and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of GDI registers, refer to the “Summary Table of the Digital Registers” on page 312. In the PSoC device with two digital rows, the configurable GDI is used to resynchronize the feedback between two digital PSoC blocks. This is accomplished by connecting a digital PSoC block’s output to a global output that has been configured to drive its corresponding global input. The global input is chosen to drive one of the row inputs. The row input is configured to synchronize the signal to the device’s 24 MHz system clock. Finally, the row input is used by the second digital PSoC block. 14.2.1 GDI_x_IN Registers/GDI_x_IN_CR Registers GDI_x_IN Add. Name Bit 7 Bit 6 Bit 5 1,D0h Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access GDI_O_IN GIONOUT7 GIONOUT6 GIONOUT5 GIONOUT4 GIONOUT3 GIONOUT2 GIONOUT1 GIONOUT0 RW : 00 1,D1h GDI_E_IN GIENOUT7 GIENOUT6 GIENOUT5 GIENOUT4 GIENOUT3 GIENOUT2 GIENOUT1 GIENOUT0 RW : 00 GDI_x_IN_CR Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,A0h GDI_O_IN_CR GDIOICR7 GDIOICR6 GDIOICR5 GDIOICR4 GDIOICR3 GDIOICR2 GDIOICR1 GDIOICR0 RW : 00 1,A1h GDI_E_IN_CR GDIEICR7 GDIEICR6 GDIEICR5 GDIEICR4 GDIEICR3 GDIEICR2 GDIEICR1 GDIEICR0 RW : 00 The Global Digital Interconnect Odd and Even Input Registers (GDI_x_IN/GDI_x_IN_CR) are used to configure a global input to drive a global output. The PSoC device has a configurable Global Digital Interconnect (GDI). Note that the GDI_x_IN and GDI_x_OU registers should never have the same bits connected. This results in multiple drivers of one bus. Bits 7 to 0: GIxNOUTx. Using the configuration bits in the GDI_x_IN registers, a global input net may be configured to drive its corresponding global output net. For example, GIE 7 GOE 7 The configurability of the GDI does not allow odd and even nets to be connected; however, connections from N to N+1 are allowed, and decided by GDI_x_IN_CR. The following are examples of connections that are not possible in the PSoC devices. GOE 7 GIO 7 GOE 0 GIE 7 There are a total of 16 bits that control the ability of global inputs to drive global outputs. These bits are in the GDI_x_IN registers. Table 14-3 enumerates the meaning of each bit position in either of the GDI_O_IN or GDI_E_IN registers. Table 14-3. GDI_x_IN Register GDI_x_IN[0] 0: No connection between GIx[0]/GIx[7] to GOx[0] 1: Allow GIx[0]/GIx[7] to drive GOx[0] GDI_x_IN[1] 0: No connection between GIx[1]/GIx[0] to GOx[1] 1: Allow GIx[1]/GIx[0] to drive GOx[1] GDI_x_IN[2] 0: No connection between GIx[2]/GIx[1] to GOx[2] 1: Allow GIx[2]/GIx[1] to drive GOx[2] GDI_x_IN[3] 0: No connection between GIx[3]/GIx[2] to GOx[3] 1: Allow GIx[3]/GIx[2] to drive GOx[3] GDI_x_IN[4] 0: No connection between GIx[4]/GIx[3] to GOx[4] 1: Allow GIx[4]/GIx[3] to drive GOx[4] GDI_x_IN[5] 0: No connection between GIx[5]/GIx[4] to GOx[5] 1: Allow GIx[5]/GIx[4] to drive GOx[5] GDI_x_IN[6] 0: No connection between GIx[6]/GIx[5] to GOx[6] 1: Allow GIx[6]/GIx[5] to drive GOx[6] GDI_x_IN[7] 0: No connection between GIx[7]/GIx[6] to GOx[7] 1: Allow GIx[7]/GIx[6] to drive GOx[7] For additional information, refer to the GDI_O_IN register on page 286 and the GDI_E_IN register on page 287. 322 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Global Digital Interconnect (GDI) Bits 7 to 0: GDIxICRx. Using the configuration bits in the GDI_x_IN_CR registers, a global input net may be configured to drive its corresponding next global output net. For example, Table 14-4. GDI_x_IN_CR Register GIE 7 GOE 0 Therefore it is possible to drive two global nets with same data source, or shift data to other global nets (see Section 14.2.2). For example, GIE 7 GOE 0 GIE 7 GOE 7 GIO[0] GOO[1] GIO[2] There are a total of 16 bits that control the data source of global inputs to drive global outputs. These bits are in the GDI_x_IN_CR registers. Table 14-4 enumerates the meaning of each bit position in either of the GDI_O_IN_CR or GDI_E_IN_CR registers. 14.2.2 GDI_xICR[0] 0: Data source is GIx[0] 1: Data source is GIx[7] GDI_xICR[1] 0: Data source is GIx[1] 1: Data source is GIx[0] GDI_xICR[2] 0: Data source is GIx[2] 1: Data source is GIx[1] GDI_xICR[3] 0: Data source is GIx[3] 1: Data source is GIx[2] GDI_xICR[4] 0: Data source is GIx[4] 1: Data source is GIx[3] GDI_xICR[5] 0: Data source is GIx[5] 1: Data source is GIx[4] GDI_xICR[6] 0: Data source is GIx[6] 1: Data source is GIx[5] GDI_xICR[7] 0: Data source is GIx[7] 1: Data source is GIx[6] For additional information, refer to the GDI_O_IN_CR register on page 271 and the GDI_E_IN_CR register on page 272. GDI_x_OU/GDI_x_OU_CR Registers GDI_x_OU Add. Name Bit 7 Bit 6 Bit 5 1,D2h Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access GDI_O_OU GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 RW : 00 1,D3h GDI_E_OU GOEUTIN7 GOEUTIN6 GOEUTIN5 GOEUTIN4 GOEUTIN3 GOEUTIN2 GOEUTIN1 GOEUTIN0 RW : 00 GDI_x_OU_CR Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,A2h GDI_O_OU_CR GDIOOCR7 GDIOOCR6 GDIOOCR5 GDIOOCR4 GDIOOCR3 GDIOOCR2 GDIOOCR1 GDIOOCR0 RW : 00 1,A3h GDI_E_OU_CR GDIEOCR7 GDIEOCR6 GDIEOCR5 GDIEOCR4 GDIEOCR3 GDIEOCR2 GDIEOCR1 GDIEOCR0 RW : 00 The Global Digital Interconnect Odd and Even Output Registers (GDI_x_OU/GDI_x_OU_CR) are used to configure a global output to drive a global input. The PSoC device has a configurable Global Digital Interconnect (GDI). Note that the GDI_x_IN and GDI_x_OU registers should never have the same bits connected. This results in multiple drivers of one bus. Bits 7 to 0: GOxUTINx. Using the configuration bits in the GDI_x_OU registers, a global output net may be configured to drive its corresponding global input. For example, GOE 7 GIE 7 The configurability of the GDI does not allow odd and even nets or nets with different indexes to be connected; however, connections from N to N+1 are allowed, and decided by GDI_x_IN_CR. The following are examples of connections that are not possible in the PSoC devices. GOE 7 GIO 7 GOE 0 GIE 7 There are a total of 16 bits that control the ability of global outputs to drive global inputs. These bits are in the GDI_x_OU registers. Table 14-5 enumerates the meaning of each bit position in either of the GDI_O_OU or GDI_E_OU registers. Table 14-5. GDI_x_OU Register GDI_x_OU[0] 0: No connection between GOx[0]/GOx[7] to GIx[0] 1: Allow GOx[0]/GOx[7] to drive GIx[0] GDI_x_OU[1] 0: No connection between GOx[1]/GOx[0] to GIx[1] 1: Allow GOx[1]/GOx[0] to drive GIx[1] GDI_x_OU[2] 0: No connection between GOx[2]/GOx[1] to GIx[2] 1: Allow GOx[2]/GOx[1] to drive GIx[2] GDI_x_OU[3] 0: No connection between GOx[3]/GOx[2] to GIx[3] 1: Allow GOx[3]/GOx[2] to drive GIx[3] GDI_x_OU[4] 0: No connection between GOx[4]/GOx[3] to GIx[4] 1: Allow GOx[4]/GOx[3] to drive GIx[4] GDI_x_OU[5] 0: No connection between GOx[0]/GOx[4] to GIx[5] 1: Allow GOx[5]/GOx[4] to drive GIx[5] GDI_x_OU[6] 0: No connection between GOx[6]/GOx[5] to GIx[6] 1: Allow GOx[6]/GOx[5] to drive GIx[6] GDI_x_OU[7] 0: No connection between GOx[7]/GOx[6] to GIx[7] 1: Allow GOx[7]/GOx[6] to drive GIx[7] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 323 Global Digital Interconnect (GDI) For additional information, refer to the GDI_O_OU register on page 288 and the GDI_E_OU register on page 289. Bits 7 to 0: GDIxOCRx. Using the configuration bits in the CY8C28xxx GDI_x_OU_CR registers, a global output net may be configured to drive its corresponding next global input. For example, There are a total of 16 bits that control the ability of global outputs to drive global inputs. These bits are in the GDI_x_OU_CR registers. Table 14-6 enumerates the meaning of each bit position in either of the GDI_O_OU_CR or GDI_E_OU_CR registers. Table 14-6. GDI_x_OU_CR Register GOE 7 GIE 0 GDIxOCR[0] 0: Data source is GOx[0] 1: Data source is GOx[7] Therefore it is possible to drive two global nets with same data source, or shift data to other global nets (see Section 14.2.1). For example, GDIxOCR[1] 0: Data source is GOx[1] 1: Data source is GOx[0] GDIxOCR[2] 0: Data source is GOx[2] 1: Data source is GOx[1] GOE 4 GIE 4 GDIxOCR[3] 0: Data source is GOx[3] 1: Data source is GOx[2] GDIxOCR[4] 0: Data source is GOx[4] 1: Data source is GOx[3] GDIxOCR[5] 0: Data source is GOx[5] 1: Data source is GOx[4] GDIxOCR[6] 0: Data source is GOx[6] 1: Data source is GOx[5] GDIxOCR[7] 0: Data source is GOx[7] 1: Data source is GOx[6] GOE 4 GIE 5 GOO[3] GIO[4] GOO[5] For additional information, refer to the GDI_O_OU_CR register on page 273 and the GDI_E_OU_CR register on page 274. 324 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 15. Array Digital Interconnect (ADI) This chapter presents the Array Digital Interconnect (ADI). The digital PSoC® array uses a scalable architecture that is designed to support from one to four digital PSoC rows, as defined in the Row Digital Interconnect (RDI) chapter on page 327. The digital PSoC array does not have any configurable interconnect; therefore, there are no associated registers in this chapter. 15.1 Architectural Description The Array Digital Interconnect (ADI) is shown in Figure 15-1. The array structure varies depending on the number of digital rows your PSoC device has (see the table titled “PSoC Device Characteristics” on page 311). The ADI is not configurable; therefore, the information in this chapter is provided to improve the reader’s understanding of the structure. Figure 15-1. Digital PSoC Block Array Structure DB[7:0] DBI GIE[7:0] VC2 VC3 CLK32K GIO[7:0] low BCw GOO[7:0] GOE[7:0] INT[3:0] TNB FNB BCrow0 BCw GOO[7:0] GOE[7:0] INT[3:0] TNB FNB BCrow1 BCw GOO[7:0] GOE[7:0] INT[3:0] TNB FNB BCrow2 BCw GOO[7:0] GOE[7:0] INT[3:0] TNB FNB BCrow3 INT[23:8] INT[15:12] INT[19:16] low CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F INT[23:20] BCx BCy BCz previous block data previous block clk GIO[7:0] Digital PSoC Block Row 3 GlE[7:0] FPB TPB DBC30 DBC31 DCC32 DCC33 DB[7:0] DBI ACMP[3:0] SYSCLKX2 VC1 VC2 VC3 CLK32K BCrow0 BCrow1 BCrow2 BCx BCy BCz previous block data previous block clk GIO[7:0] Digital PSoC Block Row 2 GlE[7:0] FPB TPB DBC20 DBC21 DCC22 DCC23 DB[7:0] DBI ACMP[3:0] SYSCLKX2 VC1 VC2 VC3 CLK32K BCrow0 BCrow1 BCrow3 BCx BCy BCz previous block data previous block clk GIO[7:0] Digital PSoC Block Row 1 GlE[7:0] FPB TPB DBC10 DBC11 DCC12 DCC13 DB[7:0] DBI ACMP[3:0] SYSCLKX2 VC1 VC2 VC3 CLK32K BCrow0 BCrow2 BCrow3 GOE[7:0] GOO[7:0] INT[11:8] low low BCx BCy BCz previous block data previous block clk GIO[7:0] Digital PSoC Block Row 0 GlE[7:0] FPB TPB DBC00 DBC01 DCC02 DCC03 DB[7:0] DBI ACMP[3:0] SYSCLKX2 VC1 VC2 VC3 CLK32K BCrow1 BCrow2 BCrow3 VC1 SYSCLKX2 ACMP[3:0] 325 Array Digital Interconnect (ADI) In Figure 15-1, the detailed view of a Digital PSoC block row has been replaced by a box labeled digital PSoC block row x. The rest of this figure illustrates how all rows are connected to the same globals, clocks, and so on. The figure also illustrates how the broadcast clock nets (BCrowx) are connected between rows. The different PSoC CY8C28xxx devices have varying numbers of digital PSoC blocks in the digital array. These blocks are arranged into rows and the ADI provides a regular interconnect architecture between the Global Digital Interconnect (GDI) and the Row Digital Interconnect (RDI), regardless of the number of rows available in a particular device. The most important aspect of the ADI and the digital PSoC rows is that all digital PSoC rows have the same connections to global inputs and outputs. The connections that make a row’s position unique are explained as follows. ■ Register Address: Rows and the blocks within them need to have unique register addresses. ■ Interrupt Priority: Each digital PSoC block has its own interrupt priority and vector. A row’s position in the array determines the relative priority of the digital PSoC blocks within the row. The lower the row number, the higher the interrupt priority, and the lower the interrupt vector address. ■ Broadcast: Each digital PSoC row has an internal broadcast net that may be either driven internally, by one of the four digital PSoC blocks, or driven externally. In the case where the broadcast net is driven externally, the source may be any one of the other rows in the array. Therefore, depending on the row’s position in the array, it will have different options for driving its broadcast net. ■ Chaining Position: Rows in the array form a string of digital blocks equal in length to the number of rows multiplied by four. The first block in the first row and the last block in the last row are not connected; therefore, the array does not form a loop. The first row in the array has its previous chaining inputs tied low. If there is a second row in the array, the next chaining outputs are connected to the next row. For the last row in the array, the next inputs are tied low. 326 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 16. Row Digital Interconnect (RDI) This chapter explains the Row Digital Interconnect (RDI) and its associated registers. This chapter discusses a single digital PSoC® block row. It does not discuss the functions, inputs, or outputs for individual digital PSoC blocks; nor does it cover specific instances of multiple rows in a single part. Therefore, the information contained here is valid for 3 and 2 row configurations. Information about individual digital PSoC blocks is covered in the Digital Blocks chapter on page 335. For a complete table of the RDI registers, refer to the “Summary Table of the Digital Registers” on page 312. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 16.1 Architectural Description Many signals pass through the digital PSoC block row on their way to or from individual digital blocks. However, only a small number of signals pass though configurable circuits on their way to and from digital blocks. The configurable circuits allow for greater flexibility in the connections between digital blocks and global buses. What follows is a discussion of the signals that are configurable by way of the registers listed in the “Register Definitions” on page 329. In Figure 16-1, within a digital PSoC block row, there are four digital PSoC Blocks. The first two blocks are of the type basic (DBC). The second two are of the type communication (DCC). This figure shows the connections between digital blocks within a row. Only the signals that pass outside the gray background box in Figure 16-1 are shown at the next level of hierarchy in Figure 16-2. In Figure 16-2, the detailed view shown in Figure 16-1 of the four PSoC block grouping, has been replaced by the box in the center of the figure labeled “4 PSoC Block Grouping.” The rest of the configurable nature of the Row Inputs (RI), Row Outputs (RO), and Broadcast clock net (BC) is shown for the next level of hierarchy. Figure 16-1. Detailed View of Four PSoC Block Grouping Digital PSoC Block 0 Basic Input Signals DS2[15:0] CLK[15:0] DATA[15:0] AUX[3:0] KS[15:0] CLKS[15:0] DATAS[15:0] AUXDATA[3:0] Chaining Signals FPB TPB KS[15:0] CLKS[15:0] DATAS[15:0] AUXDATA[3:0] Chaining Signals Digital PSoC Block 2 Communications Input Signals Digital PSoC Block 3 Communications Input Signals KS[15:0] CLKS[15:0] DATAS[15:0] AUXDATA[3:0] KS[15:0] CLKS[15:0] DATAS[15:0] AUXDATA[3:0] Chaining Signals Chaining Signals To next block To next block To next block To next block From next block From previous block To previous block From next block From previous block To previous block From next block From previous block To previous block From next block From previous block To previous block Bus Interface DB[7:0] DBI Digital PSoC Block 1 Basic Input Signals DB[7:0] Inputs Bus Interface DB[7:0] Inputs Output Signals Bus Interface DB[7:0] Inputs Output Signals TNB FNB Bus Interface DB[7:0] Inputs Output Signals Output Signals INT RO[3:0] INT RO[3:0] INT RO[3:0] INT RO[3:0] Broadcast Broadcast Broadcast Broadcast CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F INT[3:0] RO[3:0] BC 327 Row Digital Interconnect (RDI) As shown in Figure 16-2, there is a keeper connected to the row broadcast net and each of the row outputs. The keeper sets the value of these nets to ‘1’ on system reset and holds the value of the net should it stop being driven. Notice on the left side of Figure 16-2 that global inputs (GIE[n] and GIO[n]) are inputs to 4-to-1 multiplexers. The output of these muxes are Row Inputs (RI[x]). Because there are four 4-to-1 muxes, each with a unique set of inputs, a row has access to every global input line in a PSoC device. Figure 16-2. Digital PSoC Block Row Structure Low High 4x1 MUX VC3 BCROW 0 BCROW 1 BCROW 2 BCROW 3 Previous Block Data* Previous Block CLK* ACMP[3:0] SYSCLKX2 VC1 VC2 CLK32K Digital PSoC Block Row ROW 16 DBs’ FO1 Broadcast (BC) BCROW KEEPER Resets to 1 RI[0] | RO[0] L0 RO[1] RI[1] | RO[1] RO[3:0] L1 RI[3:0] RO[2] GIE[0] GlE[4] GlO[0] GlO[4] RI[0] S0 GIE[1] GlE[5] GlO[1] GlO[5] RI[1] GIE[2] GlE[6] GlO[2] GlO[6] RI[2] GIE[3] GlE[7] GlO[3] GlO[7] FPB TPB DB[7:0] DBI RI[3] S1 4 PSoC Block Grouping BCROW KS[15:0] RO[3:0] DATA[15:0] CLK[15:0] AUX[3:0] DBCx0 DBCx1 DCCx2 DCCx3 S2 FPB TPB DB[7:0] DBI RI[2] | RO[2] L2 RO[3] RI[3] | RO[3] L3 RO[0] TNB FNB INT[3:0] GOE[0] GOE[4] GOO[0] GOO[4] GOE[1] GOE[5] GOO[1] GOO[5] GOE[2] GOE[6] GOO[2] GOO[6] GOE[3] GOE[7] GOO[3] GOO[7] KEEPER[3:0] Resets to 1 TNB FNB INT[3:0] S3 * "Previous" inputs always come from the previous block. Therefore, block ‘0’ inputs come from the previous row, while block ‘1’ inputs come from block 0, etc. If there is no previous block (i.e., there is no row above the current row), previous inputs are tied low. The chaining inputs FPB and FNB are also tied low when there is no previous block or next block. 328 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Row Digital Interconnect (RDI) 16.2 Register Definitions The following registers are associated with the Row Digital Interconnect (RDI) and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of RDI registers, refer to the “Summary Table of the Digital Registers” on page 312. Depending on how many digital rows your PSoC device has (see the Rows column in the register tables below and refer to the table titled “PSoC Device Characteristics” on page 311), only certain bits are accessible to be read or written. The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. The only configurable inputs to a digital PSoC block row are the Global Input Even and Global Input Odd 8-bit buses. The only configurable outputs from the digital PSoC block row are the Global Output Even and Global Output Odd 8-bit buses. Figure 16-2 on page 328 illustrates the relationships between global signals and row signals. 16.2.1 Add. RDIxRI Register Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B0h RDI0RI 3, 2 RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00 x,B8h RDI1RI 3, 2 RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00 x,C0h RDI2RI 3 RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Row Digital Interconnect Row Input Register (RDIxRI) is used to control the input mux that determines which global inputs will drive the row inputs. The RDIxRI Register and the RDIxSYN Register are the only two registers that affect digital PSoC row input signals. All other registers are related to output signal configuration. The RDIxRI register has select bits that are used to control four muxes, where “x” denotes a place holder for the row index. Table 16-1 lists the meaning for each mux’s four possible settings. Bits 7 and 6: RI3[1:0]. These bits control the input mux for row 3. Bits 5 and 4: RI2[1:0]. These bits control the input mux for row 2. Table 16-1. RDIxRI Register RI3[1:0] 00b: GIE[3] 01b: GIE[7] 10b: GIO[3] 11b: GIO[7] RI2[1:0] 00b: GIE[2] 01b: GIE[6] 10b: GIO[2] 11b: GIO[6] RI1[1:0] 00b: GIE[1] 01b: GIE[5] 10b: GIO[1] 11b: GIO[5] RI0[1:0] 00b: GIE[0] 01b: GIE[4] 10b: GIO[0] 11b: GIO[4] For additional information, refer to the RDIxRI register on page 179. Bits 3 and 2: RI1[1:0]. These bits control the input mux for row 1. Bits 1 and 0: RI0[1:0]. These bits control the input mux for row 0. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 329 Row Digital Interconnect (RDI) 16.2.2 RDIxSYN Register Add. Name Bit 3 Bit 2 Bit 1 Bit 0 Access x,B1h RDI0SYN Rows 3, 2 Bit 7 Bit 6 Bit 5 Bit 4 RI3SYN RI2SYN RI1SYN RI0SYN RW : 00 x,B9h RDI1SYN 3, 2 RI3SYN RI2SYN RI1SYN RI0SYN RW : 00 x,C1h RDI2SYN 3 RI3SYN RI2SYN RI1SYN RI0SYN RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Row Digital Interconnect Synchronization Register (RDIxSYN) is used to control the input synchronization. Bit 1: RI1SYN. This bit controls the input synchronization for row 1. The RDIxRI Register and the RDIxSYN Register are the only two registers that affect digital PSoC row input signals. All other registers are related to output signal configuration. Bit 0: RI0SYN. This bit controls the input synchronization for row 0. By default, each row input is double synchronized to the SYSCLK (system clock), which runs at 24 MHz unless external clocking mode is enabled. However, a user may choose to disable this synchronization by setting the appropriate RIxSYN bit in the RDIxSYN register. Table 16-2 lists the bit meanings for each implemented bit of the RDIxSYN register. Bit 3: RI3SYN. This bit controls the input synchronization for row 3. Bit 2: RI2SYN. This bit controls the input synchronization for row 2. 330 Table 16-2. RDIxSYN Register RI3SYN 0: Row input 3 is synchronized to SYSCLK 1: Row input 3 is passed without synchronization RI2SYN 0: Row input 2 is synchronized to SYSCLK 1: Row input 2 is passed without synchronization RI1SYN 0: Row input 1 is synchronized to SYSCLK 1: Row input 1 is passed without synchronization RI0SYN 0: Row input 0 is synchronized to SYSCLK 1: Row input 0 is passed without synchronization For additional information, refer to the RDIxSYN register on page 180. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Row Digital Interconnect (RDI) 16.2.3 Add. RDIxIS Register Bit 3 Bit 2 Bit 1 Bit 0 Access x,B2h RDI0IS Name Rows 3, 2 Bit 7 Bit 6 Bit 5 BCSEL[1:0] Bit 4 IS3 IS2 IS1 IS0 RW : 00 x,BAh RDI1IS 3, 2 BCSEL[1:0] IS3 IS2 IS1 IS0 RW : 00 x,C2h RDI2IS 3 BCSEL[1:0] IS3 IS2 IS1 IS0 RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Row Digital Interconnect Input Select Register (RDIxIS) is used to configure the A inputs to the digital row LUTS and select a broadcast driver from another row if present. Each LUT has two inputs, where one of the inputs is configurable (Input A) and the other input (Input B) is fixed to a row output. Figure 16-3 presents an example of LUT configuration Bits 5 and 4: BCSEL[1:0]. These bits are used to determine which digital PSoC row will drive the local broadcast net. If a row number is selected that does not exist, the broadcast net is driven to a logic 1 value. If any digital PSoC block in the local row has its DxCxFN[BCEN] bit set, the broadcast select is disabled. See the “DxCxxFN Registers” on page 360. Bit 3: IS3. This bit controls the ‘A’ input of LUT 3. Figure 16-3. Example of LUT0 Configuration. G O E [0 ] R I[0 ] R O [0 ] A G O E [4 ] LUT0 R O [1 ] B G O O [0 ] G O O [4 ] M IX _S IG The configurable LUT input (Input A) chooses between a single row output and a single row input. Table 16-3 lists the options for each LUT in a row. The bits are labeled IS, meaning Input Select. The LUT’s fixed input is always the RO[LUT number + 1], such as LUT0’s fixed input is RO[1], LUT1’s fixed input is RO[2], …, and LUT3’s fixed input is RO[0]. Bit 2: IS2. This bit controls the ‘A’ input of LUT 2. Bit 1: IS1. This bit controls the ‘A’ input of LUT 1. Bit 0: IS0. This bit controls the ‘A’ input of LUT 0. Table 16-3. RDIxIS Register Bits 00b: Row broadcast net driven by row 0 broadcast net.* 01b: Row broadcast net driven by row 1 broadcast net.* 10b: Row broadcast net driven by row 2 broadcast net.* 11b: Row broadcast net driven by row 3 broadcast net.* 0: The ‘A’ input of LUT3 is RO[3] IS3 1: The ‘A’ input of LUT3 is RI[3] 0: The ‘A’ input of LUT2 is RO[2] IS2 1: The ‘A’ input of LUT2 is RI[2] 0:The ‘A’ input of LUT1 is RO[1] IS1 1: The ‘A’ input of LUT1 is RI[1] 0: The ‘A’ input of LUT0 is RO[0] IS0 1: The ‘A’ input of LUT0 is RI[0] * When the BCSEL value is equal to the row number, the tri-state buffer that drives the row broadcast net from the input select mux is disabled, so that one of the row’s blocks may drive the local row broadcast net. BCSEL[1:0] * Refer to Figure 16-2. * If the row is not present in the part, the selection provides a logic 1 value. For additional information, refer to the RDIxIS register on page 181. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 331 Row Digital Interconnect (RDI) 16.2.4 RDIxLTx Registers Add. Name x,B3h RDI0LT0 Rows 3, 2 Bit 7 Bit 6 LUT1[3:0] Bit 5 Bit 4 Bit 3 Bit 2 LUT0[3:0] Bit 1 Bit 0 RW : 00 Access x,B4h RDI0LT1 3, 2 LUT3[3:0] LUT2[3:0] RW : 00 x,BBh RDI1LT0 3, 2 LUT1[3:0] LUT0[3:0] RW : 00 x,BCh RDI1LT1 3, 2 LUT3[3:0] LUT2[3:0] RW : 00 x,C3h RDI2LT0 3 LUT1[3:0] LUT0[3:0] RW : 00 x,C4h RDI2LT1 3 LUT3[3:0] LUT2[3:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Row Digital Interconnect Logic Table Register 0 and 1 (RDIxLT0 and RDIxLT1) are used to select the logic function of the digital row LUTS. The outputs from a digital PSoC row are a bit more complicated than the inputs. Figure 16-2 on page 328 illustrates the output circuitry in a digital PSoC row. In the figure, find a block labeled Lx. This block represents a 2-input look-up table (LUT). The LUT allows the user to specify any one of 16 logic functions that should be applied to the two inputs. The output of the logic function will determine the value that may be driven on to the Global Output Even and Global Output Odd buses. Table 16-4 lists the relationship between a look-up table’s four configuration bits and the resulting logic function. Some users may find it easier to determine the proper configuration bits setting, by remembering that the configuration’s bits represent the output column of a twoinput logic truth table. Table 16-4 lists seven examples of the relationship between the LUT’s output column for a truth table and the LUTx[3:0] configuration bits. Figure 16-3 on page 331 presents an example of LUT configuration. Bits 7 to 4: LUTx[3:0]. These configuration bits are for a row output LUT. For additional information, refer to the RDIxLT0 register on page 182 and the RDIxLT1 register on page 184. Table 16-4. Example LUT Truth Tables A B 0 0 0 1 1 0 1 1 LUTx[3:0] AND 0 0 0 1 1h OR 0 1 1 1 7h A+B 1 0 1 1 Bh A&B 0 0 1 0 2h A 0 0 1 1 3h B 0 1 0 1 5h True 1 1 1 1 Fh Table 16-5. RDIxLTx Register LUTx[3:0] 0h: 0000: FALSE 1h: 0001: A .AND. B 2h: 0010: A .AND. B 3h: 0011: A 4h: 0100: A .AND. B 5h: 0101: B 6h: 0110: A .XOR. B 7h: 0111: A .OR. B 8h: 1000: A .NOR. B 9h: 1001: A .XNOR. B Ah: 1010: B Bh: 1011: A .OR. B Ch: 1100: A Dh: 1101: A .OR. B Eh: 1110: A. NAND. B Fh: 1111: TRUE Bits 3 to 0: LUTx[3:0]. These configuration bits are for a row output LUT. 332 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Row Digital Interconnect (RDI) 16.2.5 RDIxROx Registers Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B5h RDI0RO0 Rows 3, 2 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00 x,B6h RDI0RO1 3, 2 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00 x,BDh RDI1RO0 3, 2 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00 x,BEh RDI1RO1 3, 2 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00 x,C5h RDI2RO0 3 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00 x,C6h RDI2RO1 3 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Row Digital Interconnect Row Output Register 0 and 1 (RDIxRO0 and RDIxRO1) are used to select the global nets that the row outputs drive. The final configuration bits for outputs from digital PSoC rows are in the two RDIxROx registers. These registers hold the 16 bits that can individually enable the tri-state buffers that connect to all eight of the Global Output Even lines and all eight of the Global Output Odd lines to the row LUTs. The input to these tri-state drivers are the outputs of the row’s LUTs, as shown in Figure 16-2. This means that any row can drive any global output. Keep in mind that tri-state drivers are being used to drive the global output lines; therefore, it is possible for a part, with more than one digital PSoC row, to have multiple drivers on a single global output line. It is the user’s responsibility to ensure that the part is not configured with multiple drivers on any of the global output lines. Figure 16-3 presents an example LUT configuration. 16.2.5.1 RDIxRO0 Register Bits 7 to 4: GOxxEN. These configuration bits enable the tri-state buffers that connect to the global output lines for LUT 1. Bits 3 to 0: GOxxEN. These configuration bits enable the tri-state buffers that connect to the global output lines for LUT 0. For additional information, refer to the RDIxRO0 register on page 186. 16.2.5.2 RDIxRO1 Register Bits 7 to 4: GOxxEN. These configuration bits enable the tri-state buffers that connect to the global output lines for LUT 3. Bits 3 to 0: GOxxEN. These configuration bits enable the tri-state buffers that connect to the global output lines for LUT 2. For additional information, refer to the RDIxRO1 register on page 187. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 333 Row Digital Interconnect (RDI) 16.2.6 RDIxDSM Register Add. Name x,B7h RDI0DSM Rows 3, 2 Bit 7 Bit 6 AVG_SEL[3:0] Bit 5 Bit 4 Bit 3 Bit 2 AVG_EN[3:0] Bit 1 Bit 0 RW : 00 Access x,BFh RDI1DSM 3, 2 AVG_SEL[3:0] AVG_EN[3:0] RW : 00 x,C7h RDI2DSM 3 AVG_SEL[3:0] AVG_EN[3:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Row Digital Interconnect Delta Sigma Modulator Function Register (RDIxDSM) is used to select the Delta Sigma Modulator function on the row outputs. Refer to Figure 16-2 and Figure 16-3. Bits 3 to 0: AVG_EN[3:0]. These configuration bits enable average function on corresponding RO channel. For additional information, refer to the RDIxDSM register on page 188. Bits 7 to 4: AVG_SEL[3:0]. These configuration bits select 1 from 12 digital blocks' primary output as average-control signal. 16.3 Timing Diagram Figure 16-4. Optional Row Input Synchronization to SYSCLK Set up to positive edge. SYSCLK GLOBAL INPUT ROW INPUT Output of the synchronizer changes on the second positive edge that follows the input transition. 334 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 17. Digital Blocks This chapter covers the configuration and use of the digital PSoC® blocks and their associated registers. For a complete table of the Digital PSoC Block registers, refer to the “Summary Table of the Digital Registers” on page 312. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 17.1 Architectural Description At the top level, the main components of the digital block are the data path, input multiplexers (muxes), output de-muxes, configuration registers, and chaining signals (see Figure 17-1). Figure 17-1. Digital Blocks Top-Level Block Diagram D ig ita l P S o C B lo c k C lo ck S e le ct D a ta S e le ct 1 6 -1 MUX P rim a ry F u n c tio n O u tp u t, clo ck ch a in in g to n e x t b lo ck. D a ta P a th CLK R eS yn c CLK 1 6 -1 MUX DATA Aux D a ta S e le ct 4 -1 MUX AUX_DATA D a ta S e le c t 2 1 6 -1 MUX DS2 F1 1 -4 DMUX R O [3 :0 ] F2 1 -4 DMUX R O [3 :0 ] IN T B lo ck In te rru p t BC B ro a d ca st O u tp u t C o n fig u ra tio n R e g is te rs F U N C T IO N [7 :0 ] IN P U T [7 :0 ] C R 0 [7 :4 ] C R 1 [7 :0 ] All digital PSoC blocks may be configured to perform any one of seven basic functions: timer, counter, pulse width modulator (PWM), pseudo random sequence (PRS), Dead Band Generator, Delta Sigma Modulator, or cyclic redundancy check (CRC). These functions may be used by configuring an individual PSoC block or chaining several PSoC blocks together to form functions that are greater than 8 bits. Digital communications PSoC blocks have two additional functions: master or slave SPI and a full duplex UART. O U T P U T [7 :0 ] Each digital PSoC block’s function is independent of all other PSoC blocks. Up to eight registers are used to determine the function and state of a digital PSoC block. These registers are discussed in the Register Definitions section. Digital PSoC block function registers end with FN. The individual bit settings for a block’s function register are listed in Table 17-23 on page 360. The input registers end with IN and its bit meanings are listed in Table 17-25 on page 361. Finally, the block’s outputs are controlled by the output register, which ends in OU. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 335 Digital Blocks Each digital PSoC block also has three data registers (DR0, DR1, and DR2) and two control registers (CR0 and CR1). The bit meanings for these registers are heavily function dependent and are discussed with each function’s description. In addition to eight registers that control the digital PSoC block’s function and state, a separate interrupt mask bit is available for each digital PSoC block. Each digital PSoC block has a unique interrupt vector; therefore, it can have its own interrupt service routine. 17.1.1 Input Multiplexers Typically, each function has a clock, kill, and a data input that may be selected from a variety of sources. Each of these inputs is selected with a 16-to-1 input mux. In addition, there is a 4-to-1 mux which provides an auxiliary input for the SPI Slave function that requires three inputs: Clock, Data, and SS_ (unless the SS_ is forced active with the Aux IO Enable bit). The inputs to this mux are intended to be a selection of the row inputs. 17.1.2 Input Clock Resynchronization Digital blocks allow a clock selection from one of 16 sources. Possible sources are the system clocks (VC1, VC2, VC3, SYSCLK, and SYSCLKX2), row inputs, and other digital block outputs. To manage clock skew and ensure that the interfaces between blocks meet timing in all cases, all digital block input clocks must be resynchronized to either SYSCLK or SYSCLKX2, which are the source clocks for all the PSoC device clocking. Also, SYSCLK or SYSCLKX2 may be used directly. The AUXCLK bits in the DxCxxOU register are used to specify the input synchronization. The following rules apply to the use of input clock resynchronization. 1. If the clock input is derived (for example, divided down) from SYSCLK, resynchronize to SYSCLK at the digital block. Most the PSoC device clocks are in this category. For example, VC1 and VC2, and the output of other blocks clocked by VC1 and VC2, or SYSCLK (for setting see Table 17-1). 4. Choose direct SYSCLKX2 (select SYSCLKX2 in the Clock Input field of the DxCxxIN register) for clocking directly off of SYSCLKX2. 5. Bypass Synchronization. This should be a very rare selection; because if clocks are not synchronized, they may fail setup to CPU read and write commands. However, it is possible for an external pin to asynchronously clock a digital block (for example, if you want to synchronize CPU interaction through interrupts or other techniques, by setting 00 in AUXCLK). This setting is also required for blocks to remain active while in sleep. Use this setting when directly clocking the block from SYSCLKX2. The following note enumerates configurations that are not allowed, although the hardware does not prevent them. The clock dividers (VC1, VC2, and VC3) may not be configured in such a way as to create an output clock that is equal to SYSCLK or SYSCLKX2. Note If the input clock frequency matches the frequency of the clock used for synchronization, the block will never receive a clock (see Figure 17-2). As for SYSCLK, this can happen in the following cases: ■ Using VC1 configured as divide by one. ■ Using VC2 with VC1 and VC2 both configured as divide by one. ■ Using VC3 divided by one with a source of VC1 divided by one. ■ Using VC3 divided by one with a source of VC2, where both VC1 and VC2 are divided by one. ■ Using VC3 divided by one with SYSCLK source. In all of these cases, select SYSCLK directly in the block. Similarly, if VC3 is configured as divide by one with a source of SYSCLKX2, then select SYSCLKX2 to clock the block directly instead of VC3. The clock resynchronizer is illustrated in Figure 17-2. Figure 17-2. Input Clock Resynchronization 2. If the clock input is derived from SYSCLKX2, resynchronize to SYSCLKX2. For example, VC3 clocked by SYSCLKX2 or other digital blocks clocked by SYSCLKX2 (for setting, see Table 17-1). 3. Choose direct SYSCLK for clocking directly off of SYSCLK (for setting, see Table 17-1). Current Decoding 0 SYSCLKX2 SEL_SYSCLKX2 SYSCLK 1 2-1 00 = BYPASS 01 = SYSCLK 10 = SYSCLKX2 11 = SYSCLK DIRECT 4-1 BLK CLK 16-1 SYSCLKX2 CLK MUX AUXCLK MUX SYSCLK In sleep, SYSCLK is powered down, and therefore input synchronization is not available. 336 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks Table 17-1. AUXCLK Bit Selections Code 00 01 10 11 Description Usage Use this setting only when SYSCLKX2 (48 MHz) is selected. Other than this case, asynchronous clock Bypass inputs are not recommended. This setting is also required for blocks to remain active while in sleep. Use this setting for any SYSCLK-based clock. VC1, Resynchronize VC2, VC3 driven by SYSCLK, digital blocks with SYSCLK-based source clocks, broadcast bus with to SYSCLK source based on SYSCLK, row input and row out(24 MHz) puts with source based on SYSCLK. Use this setting for any SYSCLKX2-based clock. Resynchronize VC3 driven by SYSCLKX2, digital blocks with to SYSCLKX2 SYSCLKX2-based source clocks, broadcast bus with source based on SYSCLKX2, row input and (48 MHz) row outputs with source based. on SYSCLKX2. Use this setting to clock the block directly using SYSCLK. Note that this setting is not strictly related SYSCLK Direct to clock resynchronization; because YSCLK cannot resynchronize itself, it allows a direct skew controlled SYSCLK source. 17.1.2.1 Clock Resynchronization Summary ■ Digital PSoC blocks have extremely flexible clocking configurations. To maintain reliable timing, input clocks must be resynchronized. ■ The master clock for any clock in the system is either SYSCLK or SYSCLKX2. Determine the master clock for a given input clock and resynchronize to that clock. ■ Do not use divide by 1 clocks derived from SYSCLK and SYSCLKX2. Use the direct SYSCLK or SYSCLKX2 clocking option available at the block. 17.1.3 Output Demultiplexers Most functions have two outputs: a primary and an auxiliary output, the meaning of which are function dependent. Each of these outputs may be driven onto the row output bus. Each demux is implemented with four tri-state drivers. There are two bits in the output register to select one of the four tristate drivers and an additional bit to enable the selected driver. 17.1.4 Block Chaining Signals Each digital block has the capability to be chained and to create functions with bit widths greater than eight. There are signals to propagate information, such as Compare, Carry, Enable, Capture and Gate, from one block to the next to implement higher precision functions. The selection made in the function register determines which signals are appropriate for the desired function. User Modules that have been designed to implement digital functions, with greater than 8bit width, will automatically make the proper selections of the chaining signals, to ensure the correct information flow between blocks. 17.1.5 Input Data Synchronization Any asynchronous input derived from an external source, such as a GPIO pin input, must be resynchronized through the row input before use into any digital block clock or data input. This is the default mode of operation (resynchronization is on). 17.1.6 Timer Function A timer consists of a period register, a synchronous down counter, and a capture/compare register, all of which are byte wide. When the timer is disabled and a period value is written into DR1, the period value is also loaded into DR0. When the timer is enabled, the counter counts down until positive terminal count (a count of 00h) is reached. On the next clock edge, the period is reloaded and, on subsequent clocks, counting continues. The terminal count signal is the primary function output. (Refer to the timing diagram for this function on page 363.) This can be configured as a full or half clock cycle. This function also supports multi-shot mode. When the multi-shot register is set to non-zero, the function is in multishot mode. For example, if the multi-shot register is set to 01h, the function is disabled after it reaches the first 00 value in DR0. If the multi-shot register is set to 02h, when the function reaches the first 00, DR0 is reloaded and runs again. The function is disabled after the second 00 in DR0 register. The multi-shot supports up to a MAX number of 15 shots. Hardware capture occurs on the positive edge of the data input. This event transfers the current count from DR0 to DR2. The captured value may then be read directly from DR2. A software capture function is equivalent to a hardware capture. A CPU read of DR0, with the timer enabled, triggers the same capture mechanism. The hardware and software capture mechanisms are ORed in the capture circuitry. Because the capture circuitry is positive edge sensitive, during an interval where the hardware capture input is high, a software capture is masked and will not occur. The timer also implements a compare function between DR0 and DR2. The compare signal is the auxiliary function output. A limitation, in regards to the compare function, is that the capture and compare function both use the same register (DR2). Therefore, if a capture event occurs, it will overwrite the compare value. There is another mode, called NPS mode, supported at the compare output. When it is set, the compare output is delayed half clock cycle. It is used to achieve a higher resolution when 48MHz clock is used as block clock. This function also supports KILL function. There are two KILL modes: KILL-Disable and KILL-Reload. In KILL-Disable mode, the function is disabled immediately when kill is asserted. The function must be restarted in firmware. In KILL-Reload mode, the DR0 register and multi-shot counter register stays in reload state when KILL is high, and the function counts down when KILL is released. The function outputs are gated to zeros when KILL is asserted. For more detail see “Timing Diagrams” on page 363. Mode bit 1 in the function register sets the compare type (DR0 <= DR2 or DR0 < DR2) and Mode bit 0 sets the interrupt type (Terminal Count or Compare). There are also two more bits used to control interrupts, located at bit 1 in CR0 and bit 0 in CR1. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 337 Digital Blocks Table 17-2. Timer Interrupt Source Non Multi-shot Mode Interrupt Source Multi-shot Mode KILL_INT Capture INT Compare True KILL_INT Capture INT Compare True (CR1[0]) (CR0[1]) (FN[1]) (CR1[0]) (CR0[1]) (FN[1]) KILL 1 * * 1 * * Capture 0 1 * 0 1 * Compare 0 0 1 0 0 1 TC 0 0 0 0 0 0 Last-Shot Timers may be chained in 8-bit lengths up to 32 bits. ■ The compare output is the primary output and the Terminal Count (TC) is the auxiliary output (opposite of the Timer). ■ Terminal count output is full cycle only. Table 17-3. Timer Control Signals in Chained Block Item Configured in Capture LSB Block KILL LSB Block Multi-shot Period MSB Block Clock All chained Blocks KILL Mode All chained Blocks 17.1.6.1 Usability Exceptions The following are usability exceptions for the Timer function: 1. Capture operation is not supported at 48 MHz. 2. DR2 is not writeable when the Timer is enabled. 3. CR1 is not writeable when the Timer is enabled. 17.1.6.2 Block Interrupt The Timer block has a selection of four interrupt sources. Interrupt on Terminal Count (TC) and Interrupt on Compare may be selected in Mode bit 0 of the function register. The third interrupt source, Interrupt on Capture, may be selected with the Capture Interrupt bit in the control register. ■ Interrupt on Terminal Count: The positive edge of terminal count (primary output) generates an interrupt for this block. The timing of the interrupt follows the TC pulse width setting in the control register. ■ Interrupt on Compare: The positive edge of compare (auxiliary output) generates an interrupt for this block. ■ Interrupt on Capture: Hardware or software capture generates an interrupt for this block. The interrupt occurs at the closing of the DR2 latch on capture. ■ Interrupt on KILL: The interrupt occurs when KILL is asserted. 17.1.7 Counter Function A Counter consists of a period register, a synchronous down counter, and a compare register. The Counter function is identical to the Timer function, with the following exceptions: ■ The data input is a counter gate (enable), rather than a capture input. Counters do not implement synchronous capture. The DR0 register in a counter should not be read when it is enabled. 338 When the counter is disabled and a period value is written into DR1, the period value is also loaded into DR0. When the counter is enabled, the counter counts down until terminal count (a count of 00h) is reached. On the next clock edge, the period is reloaded and, on subsequent clocks, counting continues. (Refer to the timing diagram for this function on page 365.) 17.1.7.1 Counter Timing This function also supports multi-shot mode. When the multi-shot register is set to non-zero, the function is in multishot mode. For example, if the multi-shot register is set to 01h, the function is disabled after it reaches the first 00 value in DR0. If the multi-shot register is set to 02h, when the function reaches the first 00, DR0 reloads and runs again. The function is disabled after the second 00 in DR0 register. The multi-shot supports up to the MAX number of 15 shots. The counter implements a compare function between DR0 and DR2. The Compare signal is the primary function output. Mode bit 1 sets the compare type (DR0 <= DR2 or DR0 < DR2) and Mode bit 0 sets the interrupt type (terminal count or compare). Note that in default if you write to DR2 in function running state, DR2 data changes immediately and then the compare output may change immediately after. A configuration bit in CR0[1] can be used to delay the DR2 data changing until TC occurs (that is, at DR0 reloading). Therefore unusual changes will not be seen on compare out after changing the DR2 data. There is another mode, called NPS mode, supported at the compare output. When it is set, the compare output is delayed half clock cycle. It is used to achieve a higher resolution when 48 MHz clock is used as block clock. This function also supports KILL function. There are two KILL modes: KILL-Disable and KILL-Reload. In KILL-Disable mode, the function is disabled immediately when kill is asserted. The function must be restarted in firmware. In KILL-Reload mode, the DR0 register and multi-shot counter register stays in reload state when KILL is high, and the function counts down when KILL is released. The function CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks outputs are gated to zeros when KILL is asserted. For more detail see “Timing Diagrams” on page 363. The data input functions as a gate to counter operation. The counter only counts and reloads when the data input is asserted (logic 1). When the data input is negated (logic 0), counting (including the period reload) is halted. The Interrupt is controlled by two register bits. See the following table. Table 17-4. Counter Interrupt Source Non Multi-shot Mode Interrupt Source Multi-shot Mode KILL_INT Compare True KILL_INT Compare True (CR1[0]) (FN[1]) (CR1[0]) (FN[1]) KILL 1 * 1 * Compare 0 1 0 1 TC 0 0 0 0 Last-Shot Counters may be chained in 8-bit blocks up to 32 bits. Table 17-5. Counter Control Signals in Chained Blocks Item Gate Configured in LSB Block KILL LSB Block Multi-shot Period MSB Block Clock All Chained Blocks KILL Mode All Chained Blocks 17.1.7.2 Usability Exceptions The following are usability exceptions for the Counter function: 1. DR0 may only be read (to transfer DR0 data to DR2) when the block is disabled. 2. CR1 is not writeable when the Counter is enabled. 17.1.7.3 Block Interrupt The Counter block has a selection of three interrupt sources. Interrupt on Terminal Count (TC) and Interrupt on Compare may be selected in Mode bit 0 of the function register. ■ Interrupt on Terminal Count: The positive edge of terminal count (auxiliary output) generates an interrupt for this block. The timing of the interrupt follows the TC pulse width setting in the control register. ■ Interrupt on Compare: The positive edge of compare (primary output) generates an interrupt for this block. ■ Interrupt on KILL: The interrupt occurs when KILL is asserted. 17.1.8 Dead Band Function The Dead Band function generates output signals on both the primary and auxiliary outputs of the block, see Figure 17-3. Each of these outputs is one phase of a twophase, non-overlapping clock generated by this function. The two clock phases are never high at the same time and the period between the clock phases is known as the dead band. The width of the dead band time is determined by the value in the period register. This dead band function can be driven with a PWM as an input clock or it can be clocked directly by toggling a bit in software using the Bit-Bang interface. If the clock source is a PWM, this will make a two output PWM with guaranteed non-overlapping outputs. An active asynchronous signal on the KILL data input disables both outputs immediately. The PWM with the Dead Band User Module configures one or two blocks to create an 8- or 16-bit PWM and configures an additional block as the Dead Band function. A dead band consists of a period register, a synchronous down counter, and a special dead band circuit. The DR2 register is only used to read the contents of DR0. As with the counter, when the dead band is disabled and a period value is written into DR1, the period value is also loaded into DR0. (Refer to the timing diagrams for this function on page 367.) The dead band has two inputs: a PWM reference signal and a KILL signal. The PWM reference signal may be derived from one of two sources. By default, it is hardwired to be the primary output of the previous block. This previous block output is wired as an input to the 16-to-1 clock input mux. In the dead band case, the previous block output is wired directly to the dead band reference input. If this mode is used, a PWM, or some other waveform generator, must be instantiated in the previous digital block. There is also an optional Bit Bang mode. In this mode, firmware toggles a register bit to generate a PWM reference; and therefore, the dead band may be used as a stand-alone block. The KILL signal is derived from the data input signal to the block. Mode [1:0] is encoded as the Kill Type. In all cases when kill is asserted, the output is forced low immediately. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 339 Digital Blocks Figure 17-3. Dead Band Functional Overview Primary Output D e a d b a n d Dead Band Function D e a d b a n d D e a d b a n d D e a d b a n d D e a d b a n d Auxiliary Output Mode bits are encoded for kill options and are detailed in the following table. 3. If the period (of either the high time or the low time of the reference input) is less than the programmed dead time, than the associated output phase will be held low. Table 17-6. Dead Band Kill Options 4. DR0 may only be read (to transfer DR0 data to DR2) when the block is disabled. Mode [1:0] Description 00b Synchronous Restart KILL mode. Internal state is reset and reference edges are ignored, until the KILL signal is negated. 01b Disable KILL mode. Block is disabled. KILL signal must be negated and user must re-enable the block in firmware to resume operation. 10b Asynchronous KILL mode. Outputs are low only for the duration that the KILL signal is asserted, subject to a minimum disable time between one-half to one and one-half clock cycles. Internal state is unaffected. 11b Reserved 17.1.8.2 When the block is initially enabled, both outputs are low. After enabling, a positive or negative edge of the incoming PWM reference enables the counter. The counter counts down from the period value to terminal count. At terminal count, the counter is disabled and the selected phase is asserted high. On the opposite edge of the PWM input, the output that was high is negated low and the process is repeated with the opposite phase. This results in the generation of a two phase non-overlapping clock matching the frequency and pulse width of the incoming PWM reference, but separated by a dead time derived from the period and the input clock. There is a deterministic relationship between the incoming PWM reference and the output phases. The positive edge of the reference causes the primary output to be asserted to '1' and the negative edge of the reference causes the auxiliary output to be asserted to '1'. 17.1.8.1 Usability Exceptions The following are usability exceptions for the Dead Band function. 1. The Dead Band function may not be chained. 2. Programming a dead band period value of 00h is not supported. The block output is undefined under this condition. 340 5. If the asynchronous KILL signal is being used in a given application, the output of the dead band cannot be connected directly to the input of another digital block in the same row. Because the kill is asynchronous, the digital block output must be resynchronized through a row input before using it as a digital block input. Block Interrupt The Dead Band block has two interrupt sources. The default one is the Phase 1 primary output clock. When the KILL signal is asserted, the interrupt follows the same behavior of the Phase 1 output with respect to the various KILL modes. When KILL_INT is selected the KILL signal itself becomes interrupt. This is the second choice. However, set KILL_INT only in KILL-Sync and KILL-Async mode. 17.1.9 PWMDBL Function The PWMDBL is an integrated dead band PWM. From a functional perspective, it combines the counter and dead band function in a single block with limited dead band width selections. A PWMDBL consists of a period register, a synchronous down counter, a compare register, and a dead band width register. The PWMDBL counter function is identical to the Counter function, with the following exceptions: ■ There is no counter gate input. The counting down is controlled by different sub modes. ■ The multi-shot mode in PWMDBL is called PPG (Programmable Pulse Generator) mode. The function is not disabled at last-shot but instead stops counting. Hardware or software start (write one again to ‘EN’ bit) resumes the counting. Similarly, if a last shot occurs, and the start bit is high, counting continues, and the high of START does not affect the running counting. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks ■ The comparison is DR0 > DR2, instead of DR0<= DR2 or DR0<DR2. Therefore the compare out waveform is reversed. ■ Writing to DR2 is always buffered when PWMDBL is running. Therefore you do not need to set the register such as in the Counter function. ■ TC and Compare are not directly available; they are only available through the dead band function. ■ KILL modes follow dead band function’s setting. ■ KILL does not affect the counter running state except in KILL-disable mode. The whole function is disabled when KILL is asserted in KILL-Disable mode. The PWMDBL dead band function is identical to the Dead Band function, with the following exceptions: ■ No need to set ref clock input from previous block. It derives from counter function’s compare out in current block. ■ Dead band width selections are limited. It can be 0/1/2/4/ 8/16/32/64 block clock cycles. 0 means there is no dead band protection. DR0 is not the dead band width register. ■ ■ Dead band function uses the digital block clock, the same as is used by the counter. disabled and a seed value is written into DR2, the seed value is also loaded into DR0. When the CRCPRS is enabled, and synchronous clock and data are applied to the inputs, a CRC is computed on the serial data input stream. When the data input is forced to '0', then the block functions as a pseudo random sequencer (PRS) generator with the output data generated at the clock rate. The most significant bit (MSb) of the CRCPRS function is the primary output. The CRCPRS has a selection of compare modes between DR0 and DR2. The default behavior of the compare is DR0==DR2. When the PRS function cycles through the seed value as one of the valid counts, the compare output is asserted high for one clock cycle. This is regarded as the epoch of the pseudo random sequence. The mode bits can be used to set other compare types. Setting Mode bit 0 to '1' causes the compare behavior to revert to DR0 <= DR2 or DR0 < DR2, depending upon Mode bit 1. The compare value is the auxiliary output. An interrupt is generated on compare true. In PRS mode (that is, data input is fixed to zero), the Multishot and KILL functions are available. These modes are identical to the Timer/Counter function with the following exceptions: ■ The multi-shot counter will count down when DR0 is equal to DR2 (seed), rather than when DR0 is equal to 00h in Timer/Counter. Note that the equivalence caused by writing DR2 in function disable mode or caused by KILL-reload will be ignored. ■ KILL-Reload will reload DR2 data (seed) to DR0 instead of DR1 data (period in Timer/Counter). The Kill signal can act as an interrupt source. PWMDBL may be chained in 8-bit blocks up to 32 bits. Table 17-7. PWMDBL Control signals in Chained Blocks Item Configured in KILL LSB Block START LSB Block Multi-shot Period MSB Block Dead Band Width MSB Block KILL Mode (in FN) MSB Block Clock All Chained Blocks 17.1.9.1 Usability Exceptions The following are usability exceptions for the PWMDBL function: 1. DR0 may only be read (to transfer DR0 data to DR2) when the block is disabled. 2. CR1 is not writeable when the PWMDBL is enabled. 17.1.9.2 CRCPRS mode offers an optional Pass function. By setting the Pass Mode bit in the CR0 register (bit 1), the CRCPRS function is overridden. In this mode, the data input is passed transparently to the primary output and an interrupt is generated on the rising of the data input. Similarly, the CLK input is passed transparently to the auxiliary output. This can only be used to pass signals to the global outputs. If the output of a pass function is needed as an input to another digital block, it must be resynchronized through the globals and row inputs. CRCPRS supports shift mode. The LFSR acts as a digital delay line if all feedbacks are tied to zero. The shift-out data will appear on MSB bus. Note that 'Pass' mode has higher priority than 'Shift' mode. Block Interrupt The PWMDBL block has two interrupt sources. They are identical to the Dead Band function. 17.1.10 CRCPRS Function A Cyclic Redundancy Check/Pseudo Random Sequence (CRCPRS) function consists of a polynomial register, a Linear Feedback Shift Register (LFSR), and a seed register. (See Figure 17-4 on page 342.) When the CRCPRS block is CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 341 Digital Blocks Figure 17-4. CRCPRS LFSR Structure POLY[7] POLY[6] POLY[1] POLY[0] SHIFT_ FB Tri-state Bus (Data input for CRC, if PRS, force to logic ‘0’.) DATA 2:1 0 1 2 6 DO 7 (To next block, if chained.) DIN (From previous block DO, if chained.) MSB SEL SHIFT_ In Shift mode, the shift registers are just like a digital delay line. The length is determined by polynomial. LFSR Structure The LFSR (Linear Feedback Shift register) structure, as shown in Figure 17-4, is implemented as a modular shift register generator. The least significant block in the chain inputs the MSb and XORs it with the DATA input, in the case of CRC computation. For PRS computation, the DATA input is forced to logic 0 (by input selection); and therefore, the MSb bus is directly connected to the FB bus. In the case of a chained block, the data input (DIN) comes directly from the data output (DO) of the LFSR in the previous block. The MSb selection, derived from the priority decode of the polynomial, enables one of the tri-state drivers to drive the MSb bus. Determining the CRC Polynomial Computation of an n-bit result is generally specified by a polynomial with n+1 terms, the last of which is X16, where X0 = 1 Equation 1 As an example, the CRC-CCIT 16-bit polynomial is: CRC – CCIT = X 16 + X 12 + X 5 + 1 Equation 2 The CRCPRS hardware assumes the presence of the X0 term; and therefore, this polynomial can be expressed in 16 bits as 1000 1000 0001 0000b or 8810h. Two consecutive digital blocks may be allocated to perform this function, with 88h as the MS block polynomial (DR1) and 10h as the LS block polynomial value. Determining the PRS Polynomial Generally, PRS polynomials are selected from pre-computed reference tables. It is important to note that there are two common ways to specify a PRS polynomial: simple register configuration and modular configuration. In the simple method, a shift register is implemented with a reduction XOR of the MSb and feedback taps as input into the least significant bit. In the modular method, there is an XOR oper- 342 MSB Tri-state Bus MSB SEL is determined by a priority decode of the MSB, of the polynomial across all blocks of a CRCPRS function. ation implemented between each register bit and each tap point enables the XOR with the MSb for that given bit. The CRCPRS function implements the modular approach. These are equivalent methods. However, there is a conversion that should be understood. If tables are specified in simple register format, then a conversion can be made to the modular format by subtracting each tap from the MS tap, as shown in the following example. To implement a 7-bit PRS of length 127, one possible code is [7,6,4,2]s, which is in simple format. The modular format is [7,7-6,7-4,7-2]m or [7,1,3,5]m which is equivalent to [7, 5, 3, 1]. Determining the polynomial to program is similar to the CRC example above. Set a binary bit for each tap (with bit 0 of the register corresponding to tap 1). Therefore, the code [7,5,3,1] corresponds to 0101 0101b or 55h. In both the CRC and PRS cases, an appropriate seed value should be selected. All ones for PRS, or all ones or all zeros for CRC are typical values. Note that a seed value of all zeros should not be used in a PRS function, because PRS counting is inhibited by this seed. 17.1.10.1 Usability Exceptions The following are usability exceptions for the CRCPRS function: 1. The polynomial register must only be written when the block is disabled. 2. CR1 is not writeable when the CRCPRS is enabled. 17.1.10.2 Block Interrupt The CRCPRS block has three interrupt sources. The default one is the compare auxiliary output; that is, the compare output. The second one is data input when CRCPRS is in passby mode. The third one is the KILL signal when KILL_INT is selected. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.1.11 SPI Protocol Function The Serial Peripheral Interface (SPI) is a Motorola™ specification for implementing full-duplex synchronous serial communication between devices. The 3-wire protocol uses both edges of the clock to enable synchronous communication, without the need for stringent setup and hold requirements. Figure 17-5 shows the basic signals in a simple connection Figure 17-5. Basic SPI Configuration. Data is registered at the input of both devices, on the opposite edge of the clock. Data is output by both the Master and Slave, on one edge of the clock. MISO MOSI SCLK MOSI MISO SCLK SCLK SS_ SS_ MOSI MISO SPI Master SPI Slave A device can be a master or slave. A master outputs clock and data to the slave device and inputs slave data. A slave device inputs clock and data from the master device and outputs data for input to the master. The master and slave together are essentially a circular shift register, where the master is generating the clocking and initiating data transfers. A basic data transfer occurs when the master sends eight bits of data, along with eight clocks. In any transfer, both master and slave are transmitting and receiving simultaneously. If the master is only sending data, the received data from the slave is ignored. If the master wishes to receive data from the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. 17.1.11.1 SPI Protocol Signal Definitions The SPI Protocol signal definitions are located in Table 17-8. The use of the SS_ signal varies according to the capability of the slave device. Table 17-8. SPI Protocol Signal Definitions Name Function Description MOSI Master Out Slave In Master data output. MISO Master In Slave Out Slave data output. SCLK Serial Clock Clock generated by the master. SS_ This signal is provided to enable multi-slave connections to the MISO pin. The MOSI and Slave Select SCLK pins can be connected to multiple (active low) slaves, and the SS_ input selects which slave will receive the input data and drive the MISO line. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 343 Digital Blocks 17.1.12 SPI Master Function 17.1.12.1 Usability Exceptions The SPI Master (SPIM) offers SPI operating modes 0-3. By default, the MSb of the data byte is shifted out first. An additional option can be set to reverse the direction and shift the data byte out LSb first. (Refer to the timing diagrams for this function on page 371.) The following are usability exceptions for the SPI Protocol function: When configured for SPIM, DR0 functions as a shift register, with input from the DATA input (MISO) and output to the primary output F1 (MOSI). DR1 is the TX Buffer register and DR2 is the RX Buffer register. 3. CR1 is not writeable when the SPIM is enabled. The SPI protocol requires data to be registered at the device input, on the opposite edge of the clock that operates the output shifter. An additional register (RXD), at the input to the DR0 shift register, has been implemented for this purpose. This register stores received data for one-half cycle, before it is clocked into the shift register. The SPIM controls data transmission between master and slave, because it generates the bit clock for internal clocking and for clocking the SPIS. The bit clock is derived from the CLK input selection. Because the PSoC system clock generators produce clocks with varying duty cycles, the SPIM divides the input CLK by two to produce a bit clock with a 50 percent duty cycle. This clock is gated, to provide the SCLK output on the auxiliary output, during byte transmissions. There are four control bits and four status bits in the control register that provide for PSoC device interfacing and synchronization. The SPIM hardware has no support for driving the Slave Select (SS_) signal. The behavior and use of this signal is application and PSoC device dependent and, if required, must be implemented in firmware. SPIM supports variable length from 8 bits to 16 bits. Two adjacent communication blocks are able to be chained together to achieve MAX 16-bit SPI. Note the last DCC block in one row can be chained with the first DCC block in next row. Table 17-9 shows the configurations in different length requirement. Note that the same clock setting should be used in both blocks. And the SPI output comes from LSB Block and SPI input goes to MSB block if LSB first option is set. Otherwise SPI output comes from MSB block and SPI input goes to LSB block. Table 17-9. Variable Length SPI Configuration MSB Block SPI SPI Length Chain LSB Length LSB Block End Block Chain LSB (in FN) SPI Length End Block (in FN) 8-bit 0 * * * N/A N/A N/A N/A 12-bit 1 0 5’b0_1100 1 1 1 5’b0_1100 0 1. The MISO input must be resynchronized at the row inputs. 2. The DR2 (Rx Buffer) register is not writeable. 17.1.12.2 Block Interrupt The SPIM block has a selection of two interrupt sources: Interrupt on TX Reg Empty (default) or interrupt on SPI Complete. Mode bit 1 in the function register controls the selection. These mode are discussed in detail in “SPIM Timing” on page 371. If SPI Complete is selected as the block interrupt, the control register must be read in the interrupt routine so that this status bit is cleared; otherwise, no subsequent interrupts are generated. 17.1.13 SPI Slave Function The SPI Slave (SPIS) offers SPI operating modes 0-3. By default, the MSb of the data byte is shifted out first. An additional option can be set to reverse the direction and shift the data byte out LSb first. (Refer to the timing diagrams for this function on page 374.) When configured for SPI, DR0 functions as a shift register, with input from the DATA input (MOSI) and output to the primary output F1 (MISO). DR1 is the TX Buffer register and DR2 is the RX Buffer register. The SPI protocol requires data to be registered at the device input, on the opposite edge of the clock that operates the output shifter. An additional register (RXD), at the input to the DR0 shift register, is implemented for this purpose. This register stores received data for one-half cycle before it is clocked into the shift register. The SPIS function derives all clocking from the SCLK input (typically an external SPI Master). This means that the master must initiate all transmissions. For example, to read a byte from the SPIS, the master must send a byte. There are four control bits and four status bits in the control register that provide for PSoC device interfacing and synchronization. In the SPIS, there is an additional data input, Slave Select (SS_), which is an active low signal. SS_ must be asserted to enable the SPIS to receive and transmit. SS_ has two high level functions: 1) To allow for the selection of a given slave in multi-slave environment, and 2) To provide additional clocking for TX data queuing in SPI modes 0 and 1. SS_ may be controlled from an external pin through a Row Input or can be controlled by way of user firmware. 344 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks When SS_ is negated, the SPIS ignores any MOSI/SCLK input from the master. In addition, the SPIS state machine is reset, and the MISO output is forced to idle at logic 1. This allows for a wired-AND connection in a multi-slave environment. Note that if High-Z output is required when the slave is not selected, this behavior must be implemented in firmware with I/O writes to the port drive register. 17.1.13.1 SPIS also supports variable length from 8 bits to 16 bits. Two adjacent communication blocks can be chained together to achieve MAX 16-bit SPI. Note the last DCC block in one row can be chained with the first DCC block in the next row. SPIS variable length configuration is identical to variable length configuration in SPIM. The SPIS block has a selection of two interrupt sources: Interrupt on TX Reg Empty (default) or interrupt on SPI Complete (same selection as the SPIM). Mode bit 1 in the function register controls the selection. 17.1.14 Usability Exceptions The following are usability exceptions for the SPI Slave function: 1. CR1 is not writeable when the SPIS is enabled. 17.1.13.2 Block Interrupt If SPI Complete is selected as the block interrupt, the control register must still be read in the interrupt routine so that this status bit is cleared; otherwise, no subsequent interrupts are generated. Asynchronous Transmitter and Receiver Functions The Asynchronous Transmitter and Receiver functions are illustrated in Figure 17-6. Figure 17-6. Asynchronous Transmitter and Receiver Block Diagram C1 PSoC® DCCx2 DCCx3 RX TX RS232 Drivers/Receivers, such as MAX232 TX CMOS Input RX CMOS Output RS232 Output RS232 Input Vss 17.1.14.1 Asynchronous Transmitter Function In the Transmitter function, DR0 functions as a shift register, with no input and with the TXD serial data stream output to the primary output F1. DR1 is a TX Buffer register and DR2 is unused in this configuration. (Refer to the timing diagrams for this function on page 377.) Unlike SPI, which has no output latency, the TXD output has one cycle of latency. This is because a mux at the output must select which bits to shift out: the shift register data, framing bits, parity, or mark bits. The output of this mux is registered to remove glitches. When the block is first enabled or when it is idle, a mark bit (logic 1) is output. The clock generator is a free running divide-by-eight circuit. Although dividing the clock is not necessary for the Transmitter function, the Receiver function does require a divide by eight for input sampling. It is also done in the Transmitter function, to allow the TX and RX functions to run off the same baud rate generator. There are two formats supported: A 10-bit frame size including one start bit, eight data bits, and one stop bit or an 11-bit frame size including one start bit, eight data bits, one parity bit, and one stop bit. The parity generator can be configured to output either even or odd parity on the eight data bits. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 345 Digital Blocks A write to the TX Buffer register (DR1) initiates a transmission and an additional byte can be buffered in this register, while transmission is in progress. RXD input at the center of the bit time. Every subsequent START bit resynchronizes the clock generator to the incoming bit rate. An additional feature of the Transmitter function is that a clock, generated with setup and hold time for the data bits only, is output to the auxiliary output. This allows connection to a CRC generator or other digital blocks. There are two formats supported: A 10-bit frame size including one start bit, eight data bits, and one stop bit, or an 11-bit frame size including one start bit, eight data bits, one parity bit, and one stop bit. 17.1.14.2 The received data is an input to the parity generator. It is compared with a received parity bit, if this feature is enabled. The parity generator can be configured to output either even or odd parity on the eight data bits. Usability Exceptions The following is a usability exception for the Transmitter function. 1. The Transmitter function may not be chained. 17.1.14.3 After eight bits of data are received, the byte is transferred from the DR0 shifter to the DR2 RX Buffer register. Block Interrupt The Transmit block has a selection of two interrupt sources. Interrupt on TX Reg Empty (default) or interrupt on TX Complete. Mode bit 1 in the function register controls the selection. If TX Complete is selected as the block interrupt, the control register must still be read in the interrupt routine so that this status bit is cleared; otherwise, no subsequent interrupts are generated. 17.1.14.4 Asynchronous Receiver Function 17.1.14.5 Usability Exceptions The following are usability exceptions for the Asynchronous Receiver function. 1. The RXD input must be resynchronized through the row inputs. 2. DR2 is a read only register. In the Receiver function, DR0 functions as the serial data shift register with RXD input from the DATA input selection. DR2 is an RX Buffer register and DR1 is unused in this configuration. (Refer to the timing diagrams for this function on page 379.) The clock generator and START detection are integrated. The clock generator is a divide by eight which, when the system is idle, is held in reset. When a START bit (logic 0) is detected on the RXD input, the reset is negated and a bit rate (BR) clock is generated, subsequently sampling the 17.1.15 An additional feature of the Receiver function is that input data (RXD) and the synchronized clock are passed to the primary output and auxiliary output, respectively. This allows connection to a CRC generator or other digital block. 17.1.14.6 Block Interrupt The Receiver has one fixed interrupt source, which is the RX Reg Full status. The RX Buffer register must always be read in the RX interrupt routine, regardless of error status, and so on., so that RX Reg Full status bit is cleared; otherwise, no subsequent interrupts are generated. DSM function The Delta-Sigma-Modulator (DSM) performs density domain operation. It includes two parts in one dig-block: density signal generation and density domain multiplication. Figure 17-7. Density Domain Signal Generator DR1 Initial Phase DR0 ACC Reg A 8-bit A-B DR2 Density Reg 346 B CO Density Signal Output CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks Figure 17-7 illustrates density signal generation flow. The initial data will be loaded into DR0 by writing it into DR1. DR2 is density register. Then DR0 = DR0 – DR2 and the registered carry out is the generated density signal output. It can go to auxiliary output. For example, if you want the density at 50%, set DR2 to 80h, then CO occurs every other clock. Figure 17-8. Density Signal Multiplication Data Multiplication Type Density Multiplication Density Signal Output Figure 17-8 shows 2-input density signal multiplication flow. The multiplication type can be bipolar-reference type (through an XNOR) or signal-reference type (through an AND). One input comes from on-block generated density signal. Another comes from outside block through DATA selection MUX. The multiplying result can go to primary output of the block. DSM function supports two types of KILL mode: KILL-Async or KILL-Disable. In KILL-Async mode, the block outputs are gated by KILL signal. In KILL-Disable mode, the function is disabled when KILL is asserted. 17.1.15.1 Usability Exception DSM function exists only in communication blocks, and is a signal block function. 1. DR1 is only writable when DSM function is disabled. 17.1.15.2 Block interrupt There are two interrupt types in DSM function: 1. By default, interrupt occurs when CO goes high. 2. Interrupt occurs when KILL goes high. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 347 Digital Blocks 17.2 Register Definitions The following registers are associated with the Digital Blocks and listed in address order. Note that there are two banks of registers associated with the PSoC device. Bank 0 encompasses the user registers (Data and Control registers, and Interrupt Mask registers) for the device and Bank 1 encompasses the Configuration registers for the device. Refer to the “Bank 0 Registers” on page 127 and the “Bank 1 Registers” on page 218 for a quick reference of PSoC registers in address order. Each register description that follows has an associated register table showing the bit structure for that register. Depending on how many digital rows your PSoC device has (see the Rows column in the register tables below), only certain bits are accessible to be read or written (refer to the table titled “PSoC Device Characteristics” on page 311). The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. The Digital Block registers in this chapter are organized by function, as presented in Table 17-10. To reference timing diagrams associated with the digital block registers, see “Timing Diagrams” on page 363. For a complete table of digital block registers, refer to the “Summary Table of the Digital Registers” on page 312. Data and Control Registers The following table summarizes the Data and Control registers, by function type, for the digital blocks. Table 17-10. Digital Block Data and Control Register Definitions Function Type DR0 DR1 DR2 CR0 CR1 Function Access Function Access Function Access Function Access Function Access Timer Down Counter R* Period W Capture/Compare RW Control RW Control RW Counter Down Counter R* Period W Compare RW Control RW Control RW Dead Band Down Counter R* Period W N/A N/A Control RW Control RW PWMDBL Down Counter R* Period W Compare RW Control RW Control RW CRCPRS LFSR R* Polynomial W Seed RW Control RW Control RW SPIM Shifter N/A TX Buffer W RX Buffer R Control/Status RW ** Control RW SPIS Shifter N/A TX Buffer W RX Buffer R Control/Status RW ** Control RW TXUART Shifter N/A TX Buffer W N/A N/A Control/Status RW ** N/A N/A RXUART Shifter N/A N/A N/A RX Buffer R Control/Status RW ** N/A N/A Subtract R* Init-Phase W Density RW Control RW Control RW DSM LEGEND * In Timer, Counter, Dead Band, CRCPRS, PWMDBL, and DSM functions, a read of the DR0 register returns 00h and transfers DR0 to DR2. ** In the Communications functions, control bits are read/write accessible and status bits are read only accessible. 348 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.2.1 Add. DxCxxDRx Registers Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,xxh DxCxxDR0 3, 2 Data[7:0] # : 00 0,xxh DxCxxDR1 3, 2 Data[7:0] W : 00 0,xxh DxCxxDR2 3, 2 Data[7:0] # : 00 LEGEND # Access is bit specific. Refer to the register detail for additional information. xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. The DxCxxDRx Registers are the digital blocks’ Data registers. Bits 7 to 0: Data[7:0]. The Data registers and bits presented in this section encompass the DxCxxDR0, DxCxxDR1, and DxCxxDR2 registers. They are discussed according to which bank they are located in and then detailed in the tables that follow by function type. 17.2.1.1 For additional information, refer to the Register Details chapter for the following registers: ■ DxCxxDR0 register on page 131. ■ DxCxxDR1 register on page 132. ■ DxCxxDR2 register on page 133. Timer Register Definitions There are three 8-bit Data registers and two 8-bit Control registers. Table 17-11 explains the meaning of the data registers in the context of timer operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Note DR2 is not writeable when the Timer is enabled. Table 17-11. Timer Data Register Descriptions Name Function Description Not directly readable or writeable. During normal operation, DR0 stores the current count of a synchronous down counter. When disabled, a write to the DR1 period register is also simultaneously loaded into DR0 from the data bus. In KILL-Reload mode DR1 period data is loaded into DR0 at each rising edge of block clock when KILL is asserted. DR0 Count Value When disabled, a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2. This transfer only occurs in the addressed block. When enabled, a read of DR0 returns 00h to the data bus and synchronously transfers the contents of DR0 to DR2. It operates simultaneously on the byte addressed and all higher bytes in a multi-block timer. Note that when the hardware capture input is high, the read of DR0 (software capture) will be masked and will not occur. The hardware capture input must be low for a software capture to occur. Write only register. Data in this register sets the period of the count. The actual number of clocks counted is Period + 1. DR1 Period In the default one-half cycle Terminal Count mode (TC), a period value of 00h results in the primary output to be the inversion of the input clock. In the optional full cycle TC mode, a period of 00h gives a constant logic high on the primary output. When disabled, a write to this register also transfers the period value directly into DR0. When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, but the period will only be reloaded into DR0 in the clock following a TC. If the block frequency is 48 MHz, the Terminal Count or Compare Interrupt should be used to synchronize the new period register write; otherwise, the counter can be incorrectly loaded. Read write register (see Exception below). DR2 has multiple functions in a timer configuration. It is typically used as a capture register, but it also functions as a compare register. DR2 Capture/ Compare When enabled and a capture event occurs, the current count in DR0 is synchronously transferred into DR2. When enabled, the compare output is computed using the compare type (set in the function register mode bits) between DR0 and DR2. The result of the compare is output to the Auxiliary output. When disabled, a read of DR0 transfers the contents of DR0 into DR2 for the addressed block only. Exception: When enabled, DR2 is not writeable. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 349 Digital Blocks 17.2.1.2 Counter Register Definitions There are three 8-bit Data registers and two Control registers (a 7 bit and an 8 bit). Table 17-12 explains the meaning of these registers in the context of the Counter operation. Note that the descriptions of the registers are dependent on the enable/disable state of the block. This behavior is only related to the enable bit in the Control register, not the data input that provides the counter gate (unless otherwise noted). The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Note DR0 may only be read (to transfer DR0 data to DR2) when the block is disabled. Table 17-12. Counter Data Register Descriptions Name Function Description Not directly readable or writeable. During normal operation, DR0 stores the current count of a synchronous down counter. DR0 Count Value When disabled, a write to the DR1 period register is also simultaneously loaded into DR0 from the data bus. In KILL-Reload mode DR1 period data is loaded into DR0 at each rising edge of block clock when KILL is asserted. When disabled or the data input (counter gate) is low, a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2. This register should not be read when the counter is enabled and counting. Write only register. Data in this register sets the period of the count. The actual number of clocks counted is Period + 1. A period of 00h gives a constant logic high on the auxiliary output. DR1 Period When disabled, a write to this register also transfers the period value directly into DR0. When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, but the period will only be reloaded into DR0 in the clock following a TC. If the block frequency is 48 MHz, the Terminal Count or Compare Interrupt should be used to synchronize the new period register write; otherwise, the counter can be incorrectly loaded. Read write register. DR2 functions as a Compare register. DR2 Compare When enabled, the compare output is computed using the compare type (set in the function register mode bits) between DR0 and DR2. The result of the compare is output to the primary output. When disabled or the data input (counter gate) is low, a read of DR0 will transfer the contents of DR0 into DR2. DR2 may be written to when the function is enabled or disabled. In DR2-buffer mode in counter running, the data written to DR2 is stored first, then transferred to DR2 register when DR0 is being reloaded. 17.2.1.3 Dead Band Register Definitions There are three 8-bit Data registers and a 3-bit Control register. Table 17-13 explains the meaning of these registers in the context of Dead Band operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Note DR0 may only be read (to transfer DR0 data to DR2) when the block is disabled. Table 17-13. Dead Band Register Descriptions Name Function Description Not directly readable or writeable. DR0 Count Value During normal operation, DR0 stores the current count of a synchronous down counter. When disabled, a write to the DR1 period register is also simultaneously loaded into DR0 from the data bus. When disabled, a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2. Write only register. Data in this register sets the period of the dead band count. The actual number of clocks counted is Period + 1. The minimum period value is 00h, which sets a dead band time of one clock. DR1 Period When disabled, a write to this register also transfers the period value directly into DR0. When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, but the period will only be reloaded into DR0 in the clock following a Terminal Count (TC). If the block frequency is 48 MHz, the Terminal Count or Compare Interrupt should be used to synchronize the new period register write; otherwise, the counter can be incorrectly loaded. DR2 350 Buffer When disabled, a read of DR0 transfers the contents of DR0 into DR2. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.2.1.4 PWMDBL Register Definitions There are three 8-bit Data registers and two Control registers (a 7-bit and an 8-bit). Table 17-14 explains the meaning of these registers in the context of the PWMDBL operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Note Read DR0 (to transfer DR0 data to DR2) only when the block is disabled. Table 17-14. PWMDBL Data Register Descriptions Name Function Description Not directly readable or writeable. During normal operation, DR0 stores the current count of a synchronous down counter. DR0 Count Value When disabled, a write to the DR1 period register is also simultaneously loaded into DR0 from the data bus. When disabled, a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2. This register should not be read when the counter is enabled and counting. Write only register. Data in this register sets the period of the count. The actual number of clocks counted is Period + 1. A period of 00h gives a constant logic high on the auxiliary output. DR1 Period When disabled, a write to this register also transfers the period value directly into DR0. When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, but the period will only be reloaded into DR0 in the clock following a TC. If the block frequency is 48 MHz, the Terminal Count or Compare Interrupt should be used to synchronize the new period register write; otherwise, the counter can be incorrectly loaded. Read write register. DR2 DR2 functions as a Compare register. Compare When enabled, the compare output is computed using the compare type (set in the function register mode bits) between DR0 and DR2. The result of the compare is output to the primary output. When disabled, a read of DR0 will transfer the contents of DR0 into DR2. DR2 may be written to when the function is enabled or disabled. When counter is running, the data written to DR2 is stored first, then transferred to DR2 register when DR0 is being reloaded. 17.2.1.5 CRCPRS Register Definitions There are three 8-bit Data registers and two Control registers (a 7-bit and an 8-bit). Table 17-15 explains the meaning of these registers in the context of CRCPRS operation. Note that in the CRCPRS function a write to the DR2 Seed register is also loaded simultaneously into DR0. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Table 17-15. CRCPRS Register Descriptions Name Function Description Not directly readable or writeable. During normal operation, DR0 stores the state of a synchronous Linear Feedback Shift register. DR0 LFSR When disabled, a write to the DR2 Seed register is also simultaneously loaded into DR0 from the data bus. In KILL-Reload mode DR2 seed data is loaded into DR0 at each rising edge of block clock when KILL is asserted. When disabled, a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2. This register should not be read while the block is enabled. Write only register. DR1 Polynomial Data in this register sets the polynomial for the CRC or PRS function. Exception: This register must only be written when the block is disabled. Read write register. DR2 functions as a Seed and Residue register. When disabled, a write to this register also transfers the seed value directly into DR0. DR2 Seed/Residue When enabled, DR2 may be written to at any time. The value written will be used in the Compare function. When enabled, the compare output is computed using the compare type (set in the function register mode bits) between DR0 and DR2. The result of the compare is output to the auxiliary output. When disabled, a read of DR0 will transfer the contents of DR0 into DR2. This feature can be used to read out the residue, after a CRC operation is complete. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 351 Digital Blocks 17.2.1.6 SPI Master Register Definitions There are three 8-bit Data registers and two Control/Status registers (an 8-bit and a 7-bit). Table 17-16 explains the meaning of these registers in the context of SPIM operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Table 17-16. SPIM Data Register Descriptions Name DR0 Function Shifter Description Not readable or writeable. During normal operation, DR0 implements a Shift register for shifting serial data. Write only register. DR1 TX Buffer If no transmission is in progress and this register is written to, the data from this register (DR1) is loaded into the Shift register (DR0), on the following clock edge, and a transmission is initiated. If a transmission is currently in progress, this register serves as a buffer for TX data. This register should only be written to when TX Reg Empty status is set, and this write clears the TX Reg Empty status bit in the Control register. When the data is transferred from this register (DR1) to the Shift register (DR0), then TX Reg Empty status is set. Read only register. DR2 RX Buffer When a byte transmission/reception is complete, the data in the shifter (DR0) is transferred into the RX Buffer register and RX Reg Full status in the Control register is set. A read from this register (DR2) clears the RX Reg Full status bit in the Control register. 17.2.1.7 SPI Slave Register Definitions There are three 8-bit Data registers and two Control/Status registers (an 8-bit and a 7-bit). Table 17-17 explains the meaning of these registers in the context of SPIS operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Table 17-17. SPIS Data Register Descriptions Name Function DR0 Shifter DR1 TX Buffer DR2 RX Buffer Description Not readable or writeable. During normal operation, DR0 implements a Shift register for shifting serial data. Write only register. This register should only be written to when TX Reg Empty status is set and the write clears the TX Reg Empty status bit in the Control register. When the data is transferred from this register (DR1) to the Shift register (DR0), then TX Reg Empty status is set. Read only register. When a byte transmission/reception is complete, the data in the shifter (DR0) is transferred into the RX Buffer register and RX Reg Full status in the Control (CR0) register is set. A read from this register (DR2) clears the RX Reg Full status bit in the Control register. 17.2.1.8 Transmitter Register Definitions There are three 8-bit Data registers and one 5-bit Control/Status register. Table 17-18 explains the meaning of these registers in the context of Transmitter operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Table 17-18. Transmitter Data Register Descriptions Name DR0 Function Shifter Description Not readable or writeable. During normal operation, DR0 implements a shift register for shifting out serial data. Write only register. DR1 TX Buffer If no transmission is in progress and this register is written to, subject to the setup time requirement, the data from this register (DR1) is loaded into the Shift register (DR0) on the following clock edge and a transmission is initiated. If a transmission is currently in progress, this register serves as a buffer for TX data. This register should only be written to when TX Reg Empty status is set and this write clears the TX Reg Empty status bit in the Control (CR0) register. When the data is transferred from this register (DR1) to the Shift register (DR0), then TX Reg Empty status is set. DR2 352 NA Not used in this function. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.2.1.9 Receiver Register Definitions There are three 8-bit Data registers and one 8-bit Control/Status register. Table 17-19 explains the meaning of these registers in the context of Receiver operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Table 17-19. Receiver Data Register Descriptions Name Function Description Not readable or writeable. DR0 Shifter DR1 NA DR2 RX Buffer During normal operation, DR0 implements a Shift register for shifting in serial data from the RXD input. Not used in this function. Read only register. 17.2.1.10 After eight bits of data are received, the contents of the shifter (DR0) is transferred into the RX Buffer register and the RX Reg Full status is set. The RX Reg Full status bit in the Control register is cleared when this register is read. DSM Register Definitions There are three 8-bit Data registers and two Control registers (a 5-bit and a 2-bit). Table 17-20 explains the meaning of these registers in the context of DSM operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. Table 17-20. DSM Data Register Descriptions Name Function Description Not directly readable or writeable. During normal operation, DR0 stores the current value of a synchronous subtracter. DR0 Difference When disabled, a write to the DR1 initial minuend register is also simultaneously loaded into DR0 from the data bus. When disabled, a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2. This register should not be read when the subtracter is enabled. Write only register. DR1 Data in this register sets the initial data of the subtracter. Initial phase DR1 may only be written to when the function is disabled. When disabled, a write to this register also transfers the initial value directly into DR0. Read write register. DR2 functions as a subtrahend register. When enabled, DR0 = DR0 – DR2 is performed. The carry out is outputted to the auxiliary output. DR2 Density Value When disabled, a read of DR0 will transfer the contents of DR0 into DR2. DR2 may be written to when the function is enabled or disabled. When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, If the block frequency is 48 MHz, the DSM function should be disabled first. 17.2.2 DxCxxCR0 Register The DxCxxCR0 Registers are the digital blocks’ Control registers. Add. Name 0,xxh DxCxxCR0 (Timer Control:000) Rows Bit 7 Bit 6 Bit 5 KILL[3:0] 3, 2 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NPS TC Pulse Width Capture Int Enable Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. For a complete description of bit functionality, refer to the DxCxxCR0 (Timer Control:000) register on page 134. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 353 Digital Blocks Add. Name 0,xxh DxCxxCR0 (Counter Control:001) Rows Bit 7 Bit 6 Bit 5 Bit 4 KILL[3:0] Bit 3 Bit 2 NPS Bit 1 Bit 0 DR2BufEN Enable 3, 2 Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. For a complete description of bit functionality, refer to the DxCxxCR0 (Counter Control:001) register on page 135. Add. Name 0,xxh DxCxxCR0 (CRCPRS Control:010) Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 KILL[3:0] Bit 2 Bit 1 Bit 0 Shift Mode Pass Mode Enable 3, 2 Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. For a complete description of bit functionality, refer to the DxCxxCR0 (CRCPRS Control:010) register on page 137. Add. Name 0,xxh DxCxxCR0 (PWMDBL Control:011) Rows Bit 7 Bit 6 Bit 5 Bit 4 KILL[3:0] Bit 3 Bit 2 Bit 1 Bit 0 NPS KILL_INT SWT Enable 3, 2 Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. For a complete description of bit functionality, refer to the DxCxxCR0 (PWMDBL Control:011) register on page 138. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. Add. Name 0,xxh DxCxxCR0 (Dead Band Control:100) Rows Bit 7 Bit 6 Bit 5 3, 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Bit Bang Clock Bit Bang Mode Enable RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. For a complete description of bit functionality, refer to the DxCxxCR0 (Dead Band Control:100) register on page 136. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. 354 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks Add. Name 0,xxh DCCxxCR0 (SPIM Control:0-110) Rows 4, 3, 2, 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access LSb First Overrun SPI Complete TX Reg Empty RX Reg Full Clock Phase Clock Polarity Enable # : 00 LEGEND # Access is bit specific. Refer to the register detail for additional information. xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. For a complete description of bit functionality, refer to the DCCxxCR0 (SPIM Control:0-110) register on page 140. Add. Name 0,xxh DCCxxCR0 (SPIS Control:1-110) Rows 4, 3, 2, 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access LSb First Overrun SPI Complete TX Reg Empty RX Reg Full Clock Phase Clock Polarity Enable # : 00 LEGEND # Access is bit specific. Refer to the register detail for additional information. xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. For a complete description of bit functionality, refer to the DCCxxCR0 (SPIS Control:1-110) register on page 141. Add. Name 0,xxh DCCxxCR0 (UART Transmitter Control) Rows Bit 7 Bit 6 3, 2, Bit 5 Bit 4 TX Complete TX Reg Empty Bit 3 Bit 2 Bit 1 Bit 0 Access Parity Type Parity Enable Enable # : 00 LEGEND # Access is bit specific. Refer to the register detail for additional information. xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. For a complete description of bit functionality, refer to the DCCxxCR0 (UART Transmitter Control) register on page 143. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. Add. Name 0,xxh DCCxxCR0 (UART Receiver Control) Rows 3, 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Parity Error Overrun Framing Error RX Active RX Reg Full Parity Type Parity Enable Enable # : 00 LEGEND # Access is bit specific. Refer to the register detail for additional information. xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. For a complete description of bit functionality, refer to the DCCxxCR0 (UART Receiver Control) register on page 144. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 355 Digital Blocks Add. 0,xxh Name DxCxxCR0 (DSM Control:111) Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 KILL_SEL[3:0] Bit 0 Access Enable 3, 2 RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. Bits 7 to 1: The bits for this register are described by function in Table 17-21. Bit 0: Enable. This bit is used to synchronously enable or disable the programmed function. For a complete description of bit functionality, refer to the DxCxxCR0 (DSM Control:111) register on page 142. Table 17-21. DxCxxCR0 Control Register Descriptions Function Description Timer There are eight bits in the Control (CR0) register: one to enable the block, one to set the optional interrupt on capture, one to select between one-half and a full clock for Terminal Count (TC) output, one to select between extending or not extending compare output half cycle, and four bits for KILL signal selection. Counter There are eight bits in the Control (CR0) register: one to enable the block, one to enable DR2 update buffer, one to select between extending or not extending compare output half cycle, and four bits for KILL signal selection. Dead Band There are three bits in the Control (CR0) register: one bit to enable the block, and two bits to enable and control Dead Band Bit Bang mode. When Bit Bang mode is enabled, the output of this register is substituted for the PWM reference. This register may be toggled by user firmware, to generate PHI1 and PHI2 output clock with the programmed dead time. The options for Bit Bang mode are as follows: 0 1 Function uses the previous clock primary output as the input reference. Function uses the Bit Bang Clock register as the input reference. PWMDBL There are seven bits in the Control (CR0) register: one to enable the block, one to set software trigger mode, one to select between extending or not extending compare output half cycle, and four bits for START signal selection. Note The PWMDBL function does not support NPS mode when integrated dead band function is enabled. CRCPRS There are seven bits in the Control (CR0) register: one to enable the block, one for bypass mode, one for shift mode, and four bits for KILL signal selection. SPIM The SPI Control (CR0) register contains both control and status bits. There are four control bits that are read/write: Enable, Clock Phase and Clock Polarity to set the mode, and LSb First which controls bit ordering. There are two read only status bits: Overrun and SPI Complete. There are two additional read only status bits to indicate TX and RX Buffer status. SPIS The SPI Control (CR0) register contains both control and status bits. There are four control bits that are read/write: Enable, Clock Phase and Clock Polarity to set the mode, and LSb First which controls bit ordering. There are two read only status bits: Overrun and SPI Complete. There are two additional read only status bits to indicate TX and RX Buffer status. TXUART The Transmitter Control (CR0) register contains three control bits and two status bits. The control bits are Enable, Parity Enable, and Parity Type, and have read/write access. The status bits, TX Reg Empty and TX Complete, are read only. RXUART The Receiver Control (CR0) register contains both control and status bits. The three control bits are read/write: Enable, Parity Enable, and Parity Type. There are five read only status bits: RX Reg Full, RX Active, Framing Error, Overrun, and Parity Error. DSM There are five bits in the Control (CR0) register: one to enable the block, and four bits for KILL signal selection. 356 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.2.3 DxCxxCR1 Register The DxCxxCR1 registers are the digital blocks’ Control registers (located in bank 1 of the PSoC device’s memory map). The bits for the following registers are described by function in Table 17-22. Add. Name 1,xxh DxCxxCR1 (Timer Control:000) Rows Bit 7 3, 2 Bit 6 Bit 5 Bit 4 Multi-Shot Bit 3 KILL_INV Bit 2 Bit 1 KILL_MD[1:0] Bit 0 Access KILL_INT RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. For a complete description of bit functionality, refer to the DxCxxCR1 (Timer Control:000) register on page 228. Add. Name 1,xxh DxCxxCR1 (Counter Control:001) Rows Bit 7 3, 2 Bit 6 Bit 5 Bit 4 Multi-Shot Bit 3 KILL_INV Bit 2 Bit 1 KILL_MD[1:0] Bit 0 Access KILL_INT RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. For a complete description of bit functionality, refer to the DxCxxCR1 (Counter Control:001) register on page 229. Add. Name 1,xxh DxCxxCR1 (CRCPRS Control:010) Rows Bit 7 3, 2 Bit 6 Bit 5 Bit 4 Multi-Shot Bit 3 KILL_INV Bit 2 Bit 1 KILL_MD[1:0] Bit 0 Access KILL_INT RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. For a complete description of bit functionality, refer to the DxCxxCR1 (CRCPRS Control:010) register on page 230. Add. Name 1,xxh DxCxxCR1 (PWMDBL Control:011) Rows Bit 7 3, 2 Bit 6 Bit 5 Bit 4 Multi-Shot Bit 3 Bit 2 STARTINV Bit 1 Bit 0 DBW[2:0] Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. For a complete description of bit functionality, refer to the DxCxxCR1 (PWMDBL Control:011) register on page 231. Add. Name 1,xxh DxCxxCR1 (Dead Band Control:100) Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 3, 2 Bit 1 Bit 0 Access KILL_INT RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. For a complete description of bit functionality, refer to the DxCxxCR1 (Dead Band Control:100) register on page 232. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 357 Digital Blocks Add. Name 1,xxh DxCxxCR1 (SPIM Control:0-110) Rows 3, 2 Bit 7 Bit 6 Chain LSB Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Length Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. For a complete description of bit functionality, refer to the DxCxxCR1 (SPIM Control:0-110) register on page 233. Add. Name 1,xxh DxCxxCR1 (SPIS Control:0-110) Rows 3, 2 Bit 7 Bit 6 Chain LSB Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Length Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. For a complete description of bit functionality, refer to the DxCxxCR1 (SPIS Control:0-110) register on page 234. Add. 1,xxh Name DxCxxCR1 (DSM Control:111) Rows Bit 7 Bit 6 Bit 5 Bit 4 3, 2 Bit 3 Bit 2 Bit 1 KILL_INV Bit 0 Access KILL_INT RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. For a complete description of bit functionality, refer to the DxCxxCR1 (DSM Control:111) register on page 235. Table 17-22. DxCxxCR1 Control Register Descriptions Function Description Timer There are 8 bits in the Control (CR1) register: one for KILL interrupt select, two to select KILL mode, one to decide whether invert KILL signal, and four to set multi-shot times. Counter There are 8 bits in the Control (CR1) register: one for KILL interrupt select, two to select KILL mode, one to decide whether invert KILL signal, and four to set multi-shot times. Dead Band There is 1 bit in the CR1 register for KILL interrupt select. PWMDBL There are 8 bits in the Control (CR1) register: three for dead band width selection, one to decide whether invert START signal, and four to set multi-shot times. CRCPRS There are 8 bits in the Control (CR1) register: one for KILL interrupt select, two to select KILL mode, one to decide whether invert KILL signal, and four to set multi-shot times. SPIM There are 7 bits in the Control (CR1) register: five to set SPI length, one to set whether it is LSB block, and one to set it is chained block. SPIS There are 7 bits in the Control (CR1) register: five to set SPI length, one to set whether it is LSB block, and one to set it is chained block. TXUART N/A RXUART N/A DSM There are 2 bits in the Control (CR1) register: one for KILL interrupt select, and one to decide whether invert KILL signal. 358 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks Interrupt Mask Registers The following are the interrupt mask registers for the digital blocks. 17.2.4 Add. 0,E1h INT_MSK1 Register Name INT_MSK1 Rows 3, 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access DCC13 DCC12 DBC11 DBC10 DCC03 DCC02 DBC01 DBC00 RW : 00 The Interrupt Mask Register 1 (INT_MSK1) is used to enable the individual sources’ ability to create pending interrupts for digital blocks. Depending on the digital row configuration of your PSoC device, some bits may not be available in the INT_MSK1 register. Bit 7: DCC13. Digital communications enable for row 1 block 3. block Bit 6: DCC12. Digital communications enable for row 1 block 2. block interrupt interrupt Bit 5: DBC11. Digital basic block interrupt enable for row 1 block 1. Bit 4: DBC10. Digital basic block interrupt enable for row 1 block 0. Bit 3: DCC03. Digital communications enable for row 0 block 3. block interrupt Bit 2: DCC02. Digital communications enable for row 0 block 2. block interrupt Bit 1: DBC01. Digital basic block interrupt enable for row 0 block 1. Bit 0: DBC00. Digital basic block interrupt enable for row 0 block 0. For additional information, refer to the INT_MSK1 register on page 209. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 359 Digital Blocks Configuration Registers The configuration block contains 3 registers: Function (DxCxxFN), Input (DxCxxIN), and Output (DxCxxOU). The values in these registers should not be changed while the block is enabled. Note that the Digital Block Configuration registers are all located in bank 1 of the PSoC device’s memory map. 17.2.5 Add. 1,xxh DxCxxFN Registers Name DxCxxFN Rows 3, 2 Bit 7 Bit 6 Bit 5 Data Invert BCEN End Single Bit 4 Bit 3 Bit 2 Mode[1:0] Bit 1 Function[2:0] Bit 0 Access RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. The Digital Basic/Communications Type B Block Function Registers (DxCxxFN) contain the primary Mode and Function bits that determine the function of the block. Bits 2 to 0: Function[2:0]. The function bits configure the block into one of the available block functions (six for the Comm block, four for the Basic block). All bits in these registers are common to all functions, except those specified in Table 17-24. For additional information, refer to the DxCxxFN register on page 222. Bit 7: Data Invert. This bit inverts the selected data input. Table 17-23. DxCxxFN Function Registers Bit 6: BCEN. This bit enables the primary output of the block, to drive the row broadcast block. The BCEN bit is set independently in each block; and therefore, care must be taken to ensure that only one BCEN bit, in a given row, is enabled. However, if any of the blocks in a given row have the BCEN bit set, the input that allows the broadcast net from other rows to drive the given row’s broadcast net is disabled (see Figure 16-2 on page 328). [7]: Data Invert 1: Invert block’s data input 0: Do not invert block’s data input [6]: BCEN 1: Enable 0: Disable [5]: End Single 1: Block is not chained or is at the end of a chain 0: Block is at the start of or in the middle of a chain [4:3]: Mode Function specific [2:0]: Function 000b: Timer 001b: Counter 010b: CRCPRS 011b: PWMDBL 100b: Dead band for PWM 101b: UART (DCCxx blocks only) 110b: SPI (DCCxx blocks only) 111b: DSM Bit 5: End Single. This bit is used to indicate the last or most significant block in a chainable function. This bit must also be set if the chainable function only consists of a single block. Bits 4 and 3: Mode[1:0]. The mode bits select the options available for the selected function. These bits should only be changed when the block is disabled. Table 17-24. Digital Block Configuration Register Functional Descriptions Function Description Timer The mode bits in the Timer block control the Interrupt Type and the Compare Type. Counter The mode bits in the Counter block control the Interrupt Type and the Compare Type (same as the Timer function). Dead Band The mode bits are encoded as the kill type. See the table titled “Dead Band Kill Options” on page 340 for an explanation of Kill options. PWMDBL The mode bits are encoded as the kill type. It is identical to Dead Band function. CRCPRS The mode bits are encoded to determine the Compare type. SPIM Mode bit 1 selects interrupt type. Mode bit 0 selects master or slave (for SPIM, it is '0'). SPIS Mode bit 1 selects interrupt type. Mode bit 0 selects master or slave (for SPIS, it is '1'). TXUART Mode bit 0 selects between Transmitter and Receiver (in this case Mode bit 0 is set to ‘1’ for TX) and Mode bit 1 selects the interrupt type. RXUART Mode bit 0 selects between Transmitter and Receiver (in this case Mode bit 0 is set to ‘0’ for RX) and Mode bit 1 selects the interrupt type. DSM Mode bit 1 selects KILL mode. Mode bit 0 selects multiplication type. 360 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.2.6 DxCxxIN Registers Add. Name 1,xxh DxCxxIN Rows Bit 7 Bit 6 4, 3, 2, 1 Bit 5 Bit 4 Bit 3 Bit 2 Data Input[3:0] Bit 1 Bit 0 Access Clock Input[3:0] RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. The Digital Basic/Communications Type B Block Input Registers (DxCxxIN) are used to select the data and clock inputs. These registers are common to all functional types, except the SPIS. The SPIS is unique in that it has three function inputs and one function output defined. Refer to the DxCxxOU registers. The input registers are eight bits and consist of two 4-bit fields to control each of the 16-to-1 Clock and Data input muxes. The meaning of these fields depends on the external clock and data connections, which is context specific. See Table 17-25. Bits 7 to 4: Data Input[3:0]. These bits control the data input. Table 17-25. Digital Block Input Definitions Inputs Function DATA CLK Auxiliary Timer Capture CLK N/A Counter Enable CLK N/A Kill CLK Reference * N/A Dead Band CRCPRS Serial Data ** CLK SPIM MISO CLK N/A SPIS MOSI SCLK SS_ Transmitter N/A 8X Baud CLK N/A Receiver RXD 8X Baud CLK N/A * The Dead Band reference input does not use the auxiliary input mux. It is hardwired to be the primary output of the previous block. ** For CRC computation, the input data is a serial data stream synchronized to the clock. For PRS mode, this input should be forced to logic 0. For additional information, refer to the DxCxxIN register on page 224. Bits 3 to 0: Clock Input[3:0]. These bits control the clock input. 17.2.7 Add. 1,xxh DxCxxOU Registers Name DxCxxOU Rows 3, 2 Bit 7 Bit 6 AUXCLK Bit 5 AUXEN Bit 4 Bit 3 AUX IO Select[1:0] Bit 2 OUTEN Bit 1 Bit 0 Access Output Select[1:0] RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary” on page 312. The Digital Basic/Communications Type B Block Output Registers (DxCxxOU) are used to control the connection of digital block outputs to the available row interconnect and control clock resynchronization. When the selected function is SPI Slave (SPIS), the AUXEN and AUX IO bits change meaning, and select the input source and control for the Slave Select (SS_) signal. The Digital Block Output register is common to all functional types, except the SPIS. The SPIS function is unique in that it has three function inputs and one function output defined. When the Aux IO Enable bit is '0', the Aux IO Select bits are used to select one of four inputs from the auxiliary data input mux to drive the SS_ input. Alternatively, when the Aux IO Enable bit is a '1', the SS_ signal is driven directly from the value of the Aux IO Select[0] bit. Thus, the SS_ input can be controlled in firmware, eliminating the need to use an additional GPIO pin for this purpose. Regardless of how the SS_ bit is configured, a SPIS block has the auxiliary row output drivers forced off; and therefore, the auxiliary output is not available in this block. The following table enumerates the Primary and Auxiliary outputs that are defined for a given block function. Most functions have two outputs defined (the exception is the SPI Slave, which has only one). One or both of these outputs can optionally be enabled for output. When output, these signals can be routed to other block inputs through row or global interconnect, or output to chip pins. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 361 Digital Blocks The following table summarizes the available selections of the AUXCLK bits. Table 17-26. Digital Block Output Definitions Function Timer Outputs Primary Terminal Count Auxiliary Interrupt Compare Terminal Count or Last-shot or Compare True or Capture or KILL Counter Compare Terminal Count Terminal Count or Last-shot or Compare True or KILL Dead Band Phase 1 Phase 2 Phase 1 or KILL PWMDBL Phase 1 Phase 2 Phase 1 or KILL CRCPRS MSB Compare Compare or DS or KILL SPIM MOSI SCLK TX Reg Empty or SPI Complete SPIS MISO N/A ** TX Reg Empty or SPI Complete Transmitter TXD SCLK * TX Reg Empty or TX Compete Receiver RXD SCLK * RX Reg Full Density Signal or DSM Multiplication Density Signal KILL * The UART blocks generate an SPI mode 3 style clock that is only active during the data bits of a received or transmitted byte. ** In the SPIS, the field that is used to select the auxiliary output is used to control the auxiliary input to select the SS_. Bits 7 and 6: AUXCLK. All digital block clock inputs must be resynchronized. The digital blocks have numerous selections for clocking. In addition to the system clocks such as VC1, VC2, and VC3, clocks generated by other digital blocks may be selected through row or global interconnect. To maintain the integrity of block timing, all clocks are resynchronized at the input to the digital block. The two AUXCLK bits are used to enable the input clock resynchronization. When enabled, the input clock is resynchronized to the selected system clock, which occurs after the 16-to-1 multiplexing. The rules for selecting the value for this register are as follows: ■ If the input clock is based on SYSCLK (for example, VC1, VC2, VC3 based on SYSCLK) or the output of other blocks whose clock source is based on SYSCLK, synchronize to SYSCLK. ■ If the input clock is based on SYSCLKX2 (for example, VC3 based on SYSCLKX2) or another digital block clocked by SYSCLKX2, or a SYSCLKX2 based clock, synchronize to SYSCLKX2. ■ If you want to clock the block at 24 MHz (SYSCLK), choose SYSCLK direct in the resynchronized bits (the 16-to-1 input clock selection is ignored). ■ If you want to clock the block at 48 MHz (SYSCLKX2), choose SYSCLKX2 as the clock input selection and leave the resynchronized bits in bypass mode. 362 Table 17-27. AUXCLK Bit Selections Code Description Usage 00 Bypass Use this selection only when SYSCLKX2 (48 MHz) is selected by the 16-to-1 clock multiplexer (see the DxCxxIN register). 01 Resynchronize to SYSCLK (24 MHz) This is a typical selection. Use this setting for any SYSCLK-based clock: VC1, VC2, VC3 driven by SYSCLK, digital blocks with SYSCLK based source clocks, broadcast bus with source based on SYSCLK, row input and row outputs with source based on SYSCLK. 10 Resynchronize to SYSCLKX2 (48 MHz) Use this setting for any SYSCLKX2-based clock: VC3 driven by SYSCLKX2, digital blocks with SYSCLKX2 based source clocks, broadcast bus with source based on SYSCLKX2, row input and row outputs with source based on SYSCLKX2. 11 SYSCLK Direct Use this setting to clock the block directly using SYSCLK. Note that this setting is not strictly related to clock resynchronization: because SYSCLK cannot resynchronize itself, it allows a direct skew controlled SYSCLK source. Note Selecting VC1/1 or VC2/1 (when VC1 is 1), or VC3/1 when the input is SYSCLK, or SYSCLKX2 is not allowed. Bit 5: AUXEN. The AUXEN bit enables the Auxiliary output to be driven onto the selected row output. If the selected function is SPI Slave, the meaning of this bit is different. The SPI Slave does not have a defined Auxiliary output, so this bit is used, in conjunction with the AUX IO Select bits to control the Slave Select input signal (SS_). When this bit is set, the SS_ input is forced active; and therefore, routing SS_ from an input pin is unnecessary. Bits 4 and 3: AUX IO Select[1:0]. These two bits select one (out of the four) row outputs to drive the Auxiliary output onto. In SPI Slave mode, these bits are used in conjunction with the AUXEN bit to control the Slave Select (SS_) signal. In this mode, these two bits are used to select one of four row inputs for use as SS_. If no SS_ is required in a given application, the AUXEN bit can be used to force the SS_ input active; and therefore, routing SS_ in through a Row Input is not required. Bit 2: OUTEN. This bit enables the Primary output to be driven onto the selected row output. Bits 1 and 0: Output Select[1:0]. These two bits indicate which of the four row outputs the Primary output will be driven onto. For additional information, refer to the DxCxxOU register on page 226. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.3 Timing Diagrams The timing diagrams in this section are presented according to their functionality and are in the following order. ■ “Timer Timing” on page 363 ■ “SPIM Timing” on page 371 ■ “Counter Timing” on page 366 ■ “SPIS Timing” on page 374 ■ “Dead Band Timing” on page 367 ■ “Transmitter Timing” on page 377 ■ “PWMDBL Timing” on page 369 ■ “Receiver Timing” on page 379 ■ “CRCPRS Timing” on page 370 ■ “DSM Timing” on page 382 ■ “SPI Mode Timing” on page 370 17.3.1 Timer Timing Enable/Disable Operation. When the block is disabled, the clock is immediately gated low. All outputs are gated low, including the interrupt output. All internal states are reset to their configuration-specific reset states, except for DR0, DR1, and DR2 which are unaffected. Terminal Count/Compare Operation. In the clock cycle following the count of 00h, the Terminal Count (TC) output is asserted. It is one-half cycle or a full cycle depending on the TC Pulse Width mode, as set in the block Control register. If this block stands alone or is the least significant block in a chain, the Carry Out (CO) signal is also asserted. If the period is set to 00h and the TC Pulse Width mode is onehalf cycle, the output is the inversion of the input clock. The Compare (CMP) output will be asserted in the cycle follow- ing the compare true and will be negated one cycle after compare false. Multi-shot Operation. A 4-bit multi-shot down counter is available to count shot times. This counter is loaded with the value of the multi-shot period register in CR1. The value is reloaded on the first block clock following the last shot, or when the multi-shot period is written in CR1. Reloading only occurs if the block is enabled. In multi-shot mode, the last shot is generated at the rising edge of the block clock when the terminal count is 1 and the multi-shot counter is 1. DR0 is reloaded at this time as well. At the next falling edge of the block clock, the block enable bit is cleared.The multi-shot counter is not reloaded until the block is re-enabled. Figure 17-9. Last-shot Generation and DR0/Multi-shot Counter Reloaded DR0 reloaded Multi-shot counter reloaded CLK DR0 Multi-Shot Counter 0 1 1 N 0 N-1 N-2 M Last-Shot ENCLR (internal) EN CMP OUT CMP OUT is still changing at next rising edge of clock even ‘EN’ has gone low. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 363 Digital Blocks Figure 17-10. Last-shot meets IOW CLK DR0 Multi-Shot Counter CLK 0 1 1 N DR0 0 Multi-Shot Counter Last-Shot ENCLR (internal) IOW_ Last shot takes over the control ENCLR (internal) IOW disable N 1 N-1 0 N-2 M IOW enable takes over the control IOW_ IOW enable EN CMP OUT CMP OUT If the ENCLR and IOW enable occur simultaneously, the system IOW enable has higher priority. However if the ENCLR and IOW disable occur simultaneously, ENCLR takes over, shown as shown in Figure 17-10. In the special case when DR1 is zero, the function is not in multi-shot mode, whether or not the multi-shot period register in CR1 is written zero. Therefore the minimal count period in multi-shot mode is two cycles. KILL Disable Operation. In KILL-Disable mode, the KILL signal is first synchronized at the falling edge of SYSCLK, and then the synchronized KILL is used to clear EN bit. Synchronizing at the falling edge of SYSCLK allows for a safe timing window if an IOW enable follows the kill signal. Note that the block outputs are immediately asserted low at detection of a kill signal. Figure 17-11. KILL-Disable and IOW Timing SYSCLK KILL KILL-Synced EN IOW enable Block Ouput KILL Reload Operation. In KILL-Reload mode, the KILL signal is synchronized at the rising edge of block clock and is extended one block clock cycle. DR0 reloads at rising edge of the block clock when KILL-synced is high. The multishot counter reloading occurs at rising edge of the block clock after KILL-synced is released. 364 0 Last-Shot EN IOW_ 1 Figure 17-12. KILL-Reload Timing Block Clock KILL KILL-Synced DR0 Multi-Shot Counter X N N X N-1 M If wrong data is registered, it does not affect multi-shot counter. Multi-Block Terminal Count/Compare Operation. When timers are chained, the CO signal of a given block becomes the Carry In (CI) of the next most significant block in the chain. In a chained timer, the CO output indicates that the block and all lower blocks are at 00h count. The CO is set up to the next positive edge of the clock, to enable the next higher block to count once for every Terminal Count (TC) of all lower blocks. The terminal count out of a given block becomes the terminal count in of the next least significant block in the chain. The terminal count output indicates that the block and all higher blocks are at 00h count. The terminal count in/terminal count out chaining signals provide a way for the lower blocks to know when the upper blocks are at TC. Reload occurs when all blocks are at TC, which can be determined by CI, terminal count in, and the block zero detect. Example timing for a three block timer is shown in Figure 17-13. The compare circuit compares registers DR0 <= DR2. (When Mode[1] = 1, the comparison is DR0 < DR2.) Each block has an internal compare condition (DR0 compared to DR2), a chaining signal to the next block called CMPO, and the chaining signal from the previous block called CMPI. In any given block of a timer, the CMPO is used to generate the auxiliary output (primary output in the counter) with a one cycle clock delay. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks Figure 17-13. Multi-Block Timing Reload occurs when all blocks reach Terminal Count (TC). Example of multi-block timer counting MSB Period = k, ISB Period = m, LSB Period = n CLK Count LSB 2 1 0 FF FE 2 1 0 n n-1 Zero Detect LSB Carry Out LSB Count ISB 0 1 m 0 Zero Detect ISB Carry Out ISB Count MSB 0 k Zero Detect MSB Carry Out MSB Multi-Block TC CMPO is generated from a combination of the internal compare condition and the CMPI input using the following rules: 1. For any given block, if DR0 < DR2, the CMPO condition is unconditionally asserted. 2. For any given block, if DR0 == DR2, CMPO is asserted only if the CMPI input to that block is asserted. 3. If the block is a start block, the effective CMPI depends on the compare type. If it is DR0 <= DR2, the effective CMPI input is '1'. If it is DR0 < DR2, the effective input is '0'. Capture Operation. In the timer implementation, a rising edge of the data input or a CPU read of DR0 triggers a synchronous capture event. The result of this is to generate a latch enable to DR2 that loads the current count from DR0 into DR2. The latch enable signal is synchronized in such a way that it is not closing near an edge on which the count is changing. A limitation is that capture will not work with the block clock of 48 MHz. (A fundamental limitation to Timer Capture operation is the fact the GPIO inputs are currently synchronized to the 24 MHz system clock). KILL Interrupt Generation . KILL interrupt occurs when the function is enabled. Therefore no interrupt occurs if the KILL is already high in KILL-Disable mode when you write the function control register to be enabled. This is due to the function not being enabled due to KILL assertion. Figure 17-14. Timer KILL Interrupt Generation SYSCLK SYSCLK KILL KILL KILL-Sync’ed KILL-Sync’ed IOW_ EN EN EN-Sync’ed KILL-Interrupt EN-Sync’ed A half cycle delay KILL-Disable Mode A half cycle delay KILL-Interrupt KILL-Reload Mode CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 365 Digital Blocks 17.3.2 Counter Timing Enable/Disable Operation. See Operation” on page 363. Timer “Enable/Disable Terminal Count/Compare Operation. See Timer “Terminal Count/Compare Operation” on page 363. Multi-Shot Operation. See Timer “Multi-shot Operation” on page 363. KILL-Disable Operation. See Timer “KILL Disable Operation” on page 364. KILL-Reload Operation. See Timer “KILL Reload Operation” on page 364. Multi-Block Operation. See Timer “Multi-Block Terminal Count/Compare Operation” on page 364. Gate (Enable) Operation. The data input controls the counter enable. The transition on this enable must have at least one 24 MHz cycle of setup time to the block clock. This will be ensured if internal or synchronized external inputs are used. As shown in Figure 17-15, when the data input is negated (counting is disabled) and the count is 00h, the TC output stays low. When the data input goes high again, the TC occurs on the following input clock. When the block is disabled, the clock is immediately gated low. All internal state is reset, except for DR0, DR1, and DR2, which are unaffected. Figure 17-15. Counter Terminal Count Timing with Gate Disable CLK DATA (GATE) COUNT 2 1 0 N N-1 TC KILL Interrupt Generation. See Generation” on page 365. 366 Timer “KILL Interrupt CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.3.3 Dead Band Timing Figure 17-16. Basic Dead Band Timing A PWM reference edge running on the same clock occurs here. A Bit Bang clock can occur anywhere up to one 24 MHz clock, before the next block clock edge. A high on the reference asserts PH1, a low PHI2. CLOCK PWM REFERENCE COUNT P P-1 P-2 1 0 P PHI1 (Primary Output) PHI2 (Auxiliary Output) Dead Time Dead time in clocks is the Period + 1. Enable/Disable Operation. Initially both outputs are low. There are no critical timing requirements for enabling the block because dead band processing does not start until the first incoming positive or negative reference edge. In typical operation, it is recommended that the dead band block be enabled first, then the Pulse Width Modulator (PWM) generator block. When the block is disabled, the clock is immediately gated low. All outputs are gated low, including the interrupt output. All internal states are reset to their configuration specific reset states, except for DR0, DR1, and DR2 which are unaffected. Normal Operation. Figure 17-16 shows typical dead band timing. The incoming reference edge can occur up to one 24 MHz system clock before the edge of the block clock. On the edge of the block clock, the currently asserted output is negated and the dead band counter is enabled. After Period + 1 clocks, the phase associated with the current state of the PWM reference is asserted (Reference High = Phase 1, Reference Low = Phase 2). The minimum dead time occurs with a period value of 00h and that dead time is one clock cycle. 17.3.3.1 Changing the PWM Duty Cycle Under normal circumstances, the dead band period is less than the minimum PWM high or low time. As an example, consider Figure 17-17 where the low of the PWM is four clocks, the dead band period is two clocks, and the high time of the PHI2 is two clocks. Figure 17-17. DB High Time is PWM Width Minus DB Period CLK PWM 4 PHI1 PHI2 2 2 2 Figure 17-18 illustrates the reduction of the width of the PWM low time by one clock (to three clocks). The dead band period remains the same, but the high time for PHI2 is reduced by one clock (to one clock). Of course the opposite phase, PHI1, decreases in length by one clock. Figure 17-18. DB High Time is Reduced as PWM Width is Reduced CLK PWM 3 PHI1 PHI2 1 2 2 If the width of the PWM low time is reduced to a point where it is equal to the dead band period, the corresponding phase, PHI2, disappears altogether. Note that after the rising edge of the PWM, the opposite phase still has the programmed dead band. Figure 17-19 shows an example where the dead band period is two and the PWM width is two. In this case, the high time of PHI2 is zero clocks. Note that the Phase 1 dead band time is still two clocks. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 367 Digital Blocks Figure 17-19. PWM Width Equal to Dead Band Period Figure 17-20. Synchronous Restart KILL Mode Short KILL, outputs off for remainder of current cycle. CLK PWM 2 PWM REFERENCE PHI1 PHI2 Operation resumes on the next PWM edge. 2 2 PHI1 PHI2 In the case where the dead band period is greater than the high or low of the PWM reference, the output of the associated phase will not be asserted high. 17.3.3.2 Kill Operation KILL Output is off for duration of KILL on time. These edges Operation resumes on this edge. are skipped. PWM REFERENCE It is assumed that the KILL input will not be synchronized at the row input. (This is not a requirement; however, if synchronized, the KILL operation will have up to two 24 MHz clock cycles latency which is undesirable.) To support the restart modes, the negation of KILL is internally (in the block) synchronized to the 24 MHz system clock. There are three KILL modes supported. In all cases, the KILL signal asynchronously forces the outputs to logic 0. The differences in the modes come from how dead band processing is restarted. 1. Synchronous Restart Mode: When KILL is asserted high, the internal state is held in reset and the initial dead band period is reloaded into the counter. While KILL is held high, incoming PWM reference edges are ignored. When KILL is negated, the next incoming PWM reference edge restarts dead band processing. See Figure 17-20. 2. Asynchronous Restart Mode: When KILL is asserted high, the internal state is not affected. When KILL is negated, the outputs are restored, subject to a minimum disable time between one-half and one and one-half clock cycle. See Figure 17-21. 3. Disable Mode: There is no specific timing associated with Disable mode. The block is disabled and the user must re-enable the function in firmware to continue processing. PHI1 PHI2 KILL Figure 17-21. Asynchronous Restart Kill Mode Outputs are disabled immediately on KILL. Minimum disable time is between ½ and 1½ block clock cycle. BLOCK CLK PHI1 or PHI2 KILL Example of KILL shorter than the minimum. Outputs are forced low only as long as the KILL is asserted, subject to the minimum disable time. Internal operation is unaffected. PWM REFERENCE PHI1 PHI2 KILL Example of KILL longer than the minimum. PWM REFERENCE PHI1 PHI2 KILL 368 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.3.4 PWMDBL Timing Enable/Disable Operation. See Operation” on page 363. Timer “Enable/Disable PPG Start Operation. The PWMDBL function is in PPG mode when multi-shot period register is written with a nonzero value. In non-PPG mode, the PWMDBL continuously outputs its PWM signal. Oppositely, in PPG mode a START signal, either a hardware signal or a software signal (write ‘1’ to EN bit), is used to trigger the PWM output. The PWM output is stopped after the current PWM output period finishes if there is not another trigger signal. The PWM output period will start in the following conditions: ■ If there is no PWM output (that is, PWMDBL is enabled and stopped), a START starts a new PWM output period. ■ A new PWM output period follows the previous one if START is high when the current PWM output finishes (that is, at last-shot). In any other condition, the START signal does not affect PWMDBL. To ensure safe timing, START is synchronized at the rising edge of the block clock. See Figure 17-22. Compare Operation. The Compare operation is identical to the Timer function, except the polarity of compare output is swapped. Note that this compare output is also the reference input to the integrated dead band (see Figure 17-23). The dead band requires at least 2 cycles: high or low pulse on its reference input clock (the dead band needs a removal timing check in the dead band generator sub-block if it is a 2-cycle high or low pulse; it does not need this if it is larger than or equal to 3 cycles). KILL Operation. The KILL operation has the same mechanism as the Dead Band function. The KILL mode is also identical to the Dead Band function. Refer to the Dead Band function KILL operation. Figure 17-22. PPG Start Timing Block Clock START START-Synced DR0 N Multi-Shot Counter 0 N-1 N-2 N-3 1 M 0 1 N N-1 0 M M*(N+1) Cycles Figure 17-23. PWMDBL Compare Output Timing Block Clock START START-Synced DR0 N Multi-Shot Counter 0 N-1 N-2 N-3 1 0 1 N 0 Compare Out Compare out is low when PWM is not running Condition: DR0 > 1 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 369 Digital Blocks 17.3.5 CRCPRS Timing Enable/Disable Operation. See Operation” on page 363. 17.3.6 Timer Figure 17-24 shows the SPI modes, which are typically defined as 0,1, 2, or 3. These mode numbers are an encoding of two control bits: Clock Phase and Clock Polarity. “Enable/Disable Multi-Shot Operation in PRS. See Timer “Multi-shot Operation” on page 363. Clock phase indicates the relationship of the clock to the data. When the clock phase is '0', it means that the data is registered as an input on the leading edge of the clock and the next data is output on the trailing edge of the clock. When the clock phase is '1', it means that the next data is output on the leading edge of the clock and that data is registered as an input on the trailing edge of the clock. KILL-Disable Operation in PRS. See Timer “KILL Disable Operation” on page 364. KILL-Reload Operation in PRS. See Timer “KILL Reload Operation” on page 364. KILL Interrupt Generation. See Generation” on page 365. Timer “KILL SPI Mode Timing Clock polarity controls clock inversion. When clock polarity is set to '1’, the clock idle state is high. Interrupt Figure 17-24. SPI Mode Timing MODE 0, 1 (Phase=0) Input on leading edge. Output on trailing edge. SCLK, Polarity=0 (Mode 0) SCLK, Polarity=1 (Mode 1) MOSI 7 6 5 4 3 2 1 0 MISO SS_ MODE 2, 3 (Phase=1) Output on leading edge. Input on trailing edge. SCLK, Polarity=0 (Mode 2) SCLK, Polarity=1 (Mode 3) MOSI 7 6 5 4 3 2 1 0 MISO SS_ 370 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.3.7 SPIM Timing Enable/Disable Operation. As soon as the block is configured for SPIM, the primary output is the MSb or LSb of the Shift register, depending on the LSb First configuration in bit 7 of the Control register. The auxiliary output is '1' or '0' depending on the idle clock state of the SPI mode. This is the idle state. When the SPIM is enabled, the internal reset is released on the divide-by-2 flip-flop and on the next positive edge of the selected input clock. This 1-bit divider transitions to a '1' and remains free-running thereafter. When the block is disabled, the SCLK and MOSI outputs revert to their idle state. All internal state is reset (including CR0 status) to its configuration-specific reset state, except for DR0, DR1, and DR2 which are unaffected. Normal Operation. Typical timing for a SPIM transfer is shown in Figure 17-25 and Figure 17-26. The user initially writes a byte to transmit when TX Reg Empty status is true. If no transmission is currently in progress, the data is loaded into the shifter and the transmission is initiated. The TX Reg Empty status is asserted again and the user is allowed to write the next byte to be transmitted to the TX Buffer register. After the last bit is output, if TX Buffer data is available with one-half clock setup time to the next clock, a new byte transmission will be initiated. A SPIM block receives a byte at the same time that it sends one. The SPI Complete or RX Reg Full can be used to determine when the input byte has been received. Figure 17-25. Typical SPIM Timing in Mode 0 and 1 Free running, internal bit rate clock is CLK input divided by two. Setup time for TX Buffer write. Shifter is loaded with first byte. Last bit of received data is valid on this edge and is latched into RX Buffer. Shifter is loaded with next byte. CLK INPUT INTERNAL CLOCK TX REG EMPTY RX REG FULL MOSI D7 D6 D5 D2 D1 D0 D7 SCLK (MODE 0) SCLK (MODE 1) User writes first byte to the TX Buffer register. User writes next First input bit First shift byte to the TX is latched. Buffer register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 371 Digital Blocks Figure 17-26. Typical SPIM Timing in Mode 2 and 3 Last bit of received data is valid on this Shifter is loaded Setup time edge and is latched with the first byte. for the TX into RX Buffer. Buffer write. Free running, internal bit rate clock is CLK input divided by two. Shifter is loaded with the next byte. CLK INPUT INTERNAL CLOCK TX REG EMPTY RX REG FULL MOSI D7 D6 D5 D2 D1 D0 D7 SCLK (MODE 2) SCLK (MODE 3) User writes first byte to the TX Buffer register. First input bit is latched. First shift Status Generation and Interrupts. There are four status bits in an SPI Block: TX Reg Empty, RX Reg Full, SPI Complete, and Overrun. TX Reg Empty indicates that a new byte can be written to the TX Buffer register. When the block is enabled, this status bit is immediately asserted. This status bit is cleared when the user writes a byte of data to the TX Buffer register. TX Reg Empty is a control input to the state machine and, if a transmission is not already in progress, the assertion of this control signal initiates one. This is the default SPIM block interrupt. However, an initial interrupt is not generated when the block is enabled. The user must write a byte to the TX Buffer register and that byte must be loaded into the shifter before interrupts generated from the TX Reg Empty status bit are enabled. User writes next byte to the TX Buffer register. Overrun status is set, if RX Reg Full is still asserted from a previous byte when a new byte is about to be loaded into the RX Buffer register. Because the RX Buffer register is implemented as a latch, Overrun status is set one-half bit clock before RX Reg Full status. See Figure 17-27 and Figure 17-28 for status timing relationships. RX Reg Full is asserted on the edge that captures the eighth bit of receive data. This status bit is cleared when the user reads the RX Buffer register (DR2). SPI Complete is an optional interrupt and is generated when eight bits of data and clock have been sent. In modes 0 and 1, this occurs one-half cycle after RX Reg Full is set; because in these modes, data is latched on the leading edge of the clock and there is an additional one-half cycle remaining to complete that clock. In modes 2 and 3, this occurs at the same edge that the receive data is latched. This signal may be used to read the received byte or it may be used by the SPIM to disable the block after data transmission is complete. 372 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks Figure 17-27. SPI Status Timing for Modes 0 and 1 SS Forced Low Transfer in Progress SS SCLK (Mode 0) SCLK (Mode 1) SS Toggled on a Message Basis Transfer in Progress Transfer in Progress SS SCLK (Mode 0) SCLK (Mode 1) SS Toggled on Each Byte Transfer in Progress Transfer in Progress SS SCLK (Mode 0) SCLK (Mode 1) Figure 17-28. SPI Status Timing for Modes 2 and 3 MODE 2, 3 (Phase=1) Output on leading edge. Input on trailing edge. User writes the next byte. SCLK, Polarity=0 (Mode 2) SCLK, Polarity=1 (Mode 3) MOSI 7 6 5 4 3 2 1 0 7 MISO 7 6 5 4 3 2 1 0 7 SS_ TX REG EMPTY RX REG FULL SPI COMPLETE Last bit of byte is received. All clocks and data for this byte completed. OVERRUN TX Buffer is transferred into the shifter Overrun occurs onehalf cycle before the last bit is received. TX Buffer is transferred into the shifter. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 373 Digital Blocks Chained SPIM. When two adjacent communication blocks are chained to form a more-than-8-bit SPIM function, the preceding operations are maintained the same, with the following exceptions: the primary output is the MSb or LSb of the shift register, depending on the LSb First configuration in bit 7 of the Control register. The auxiliary output of the SPIS is always forced into tri-state. ■ More transmissions for more bits. ■ Only need to enable LSB block to enable the function such as in chained Timer/Counter/CRCPRS/PWMDBL functions. ■ Need to write MSB TX register first and then LSB register to initiate a transmission. ■ Always read MSB RX data first and then LSB RX data. Because the SPIS has no internal clock, it must be enabled with setup time to any external master supplying the clock. Setup time is also required for a TX Buffer register write, before the first edge of the clock or the first falling edge of SS_, depending on the mode. This setup time must be assured through the protocol and an understanding of the timing between the master and slave in a system. ■ Always check LSB status bits for whole SPIM status if you follow above TX/RX read/write operation sequence. ■ The interrupt in both blocks can be enabled and selected arbitrarily. (But if clearing SPI complete bit or TX Empty bit, still need to read the CR0 register or write DR1 register in that block). 17.3.8 SPIS Timing Enable/Disable Operation. As soon as the block is configured for SPI Slave and before enabling, the MISO output is set to idle at logic 1. Both the enable bit must be set and the SS_ asserted (either driven externally or forced by firmware programming) for the block to output data. When enabled, When the block is disabled, the MISO output reverts to its idle '1' state. All internal state is reset (including CR0 status) to its configuration-specific reset state, except for DR0, DR1, and DR2 which are unaffected. Normal Operation. Typical timing for a SPIS transfer is shown in Figure 17-29 and Figure 17-30. If the SPIS is primarily being used as a receiver, the RX Reg Full (polling only) or SPI Complete (polling or interrupt) status may be used to determine when a byte has been received. In this way, the SPIS operates identically with the SPIM. However, there are two main areas in which the SPIS operates differently: 1) SPIS behavior related to the SS_ signal, and 2) TX data queuing (loading the TX Buffer register). Figure 17-29. Typical SPIS Timing in Modes 0 and 1 At the falling edge of SS_, MISO First input transitions from an IDLE (high) bit is to output the first bit of data. latched. First Shift Last bit of received data is valid on this edge and is latched into the RX Buffer register. SCLK (internal) TX REG EMPTY RX REG FULL SS_ MISO D7 D6 D5 D2 D1 D0 D7 D7 D6 SCLK (MODE 0) SCLK (MODE 1) User writes first byte to the TX Buffer register in advance of transfer. 374 User writes the next byte to the TX Buffer register. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks Figure 17-30. Typical SPIS Timing in Modes 2 and 3 Shifter is loaded with first byte (by leading edge of the SCLK). First input bit latched. Last bit of received data is valid Shifter is on this edge and is latched into loaded with the RX Buffer register. the next byte. First Shift SCLK (Internal) TX REG EMPTY RX REG FULL MISO D7 D6 D5 D2 D1 D0 D7 SCLK (MODE 2) SCLK (MODE 3) User writes the first byte to the TX Buffer register. Slave Select (SS_, active low). Slave Select must be asserted to enable the SPIS for receive and transmit. There are two ways to do this: 1. Drive the auxiliary input from a pin (selected by the Aux IO Select bits in the output register). This gives the SPI master control of the slave selection in a multi-slave environment. 2. SS_ may be controlled in firmware with register writes to the output register. When Aux IO Enable = 1, Aux IO Select bit 0 becomes the SS_ input. This allows the user to save an input pin in single slave environments. When SS_ is negated (whether from an external or internal source), the SPIS state machine is reset and the MISO output is forced to idle at logic 1. In addition, the SPIS will ignore any incoming MOSI/SCLK input from the master. Status Generation and Interrupts. There are four status bits in the SPIS Block: TX Reg Empty, RX Reg Full, SPI Complete, and Overrun. The timing of these status bits are identical to the SPIM, with the exception of TX Reg Empty which is covered in the section on TX data queuing. User writes the next byte to the TX Buffer register. is available in the TX Buffer register, the byte is loaded into the shifter. The only difference between the modes is that the definition of “transfer in progress” is slightly different between modes 0 and 1, and modes 2 and 3. Figure 17-31 illustrates TX data loading in modes 0 and 1. A transfer in progress is defined to be from the falling edge of SS_ to the point at which the RX Buffer register is loaded with the received byte. This means that to send a byte in the next transfer, it must be loaded into the TX Buffer register before the falling edge of SS_. This ensures a minimum setup time for the first bit, because the leading edge of the first SCLK must latch in the received data. If SS_ is not toggled between each byte or is forced low through the configuration register, the leading edge of SCLK is used to define the start of transfer. However, in this case, the user must provide the required setup time (one-half clock minimum before the leading edge), with a knowledge of system latencies and response times. Status Clear On Read. Refer to the same subsection in “SPIM Timing” on page 371. TX Data Queuing. Most SPI applications call for data to be sent back from the slave to the master. Writing firmware to accomplish this requires an understanding of how the Shift register is loaded from the TX Buffer register. All modes use the following mechanism: (1) If there is no transfer in progress, (2) if the shifter is empty, and (3) if data CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 375 Digital Blocks Figure 17-31. Mode 0 and 1 Transfer in Progress SS Forced Low Transfer in Progress SS SCLK (Mode 0) SCLK (Mode 1) SS Toggled on a Message Basis Transfer in Progress Transfer in Progress SS SCLK (Mode 0) SCLK (Mode 1) SS Toggled on Each Byte Transfer in Progress Transfer in Progress SS SCLK (Mode 0) SCLK (Mode 1) Figure 17-32 illustrates TX data loading in modes 2 and 3. In this case, there is no dependence on SS and a transfer in progress is defined to be from the leading edge of the first SCLK to the point at which the RX Buffer register is loaded with the received byte. Loading the shifter by the leading edge of the clock has the effect of providing the required one-half clock setup time, as the data is latched into the receiver on the trailing edge of the SCLK in these modes. Figure 17-32. Mode 2 and 3 Transfer in Progress ■ Need to write MSB TX register first and then LSB register to set new data. ■ Always read MSB RX data first and then LSB RX data. ■ Always check LSB status bits for whole SPIM status if you follow above TX/RX read/write operation sequence. ■ The interrupt in both blocks can be enabled and selected arbitrarily. (But if clearing SPI Complete bit or TX Empty bit, still need to read the CR0 register or write DR1 register in that block). Transfer in Progress SCLK (Mode 2) SCLK (Mode 3) (No Dependance on SS) Chained SPIS. When two adjacent communication blocks are chained to form a more-than-8-bit SPIS function, the preceding SPIS operations are maintained the same, with the following exceptions: ■ More transits for more bits. ■ Only need to enable LSB block to enable the function such as in chained Timer/Counter/CRCPRS/PWMDBL functions. 376 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.3.9 Transmitter Timing Enable/Disable Operation. As soon as the block is configured for the Transmitter and before enabling, the primary output is set to idle at logic 1, the mark state. The output will remain '1' until the block is enabled and a transmission is initiated. The auxiliary output will also idle to '1', which is the idle state of the associated SPI mode 3 clock. When the Transmitter is enabled, the internal reset is released on the divide-by-eight clock generator circuit. On the next positive edge of the selected input clock, this 3-bit up counter circuit, which generates the bit clock with the MSb, starts counting up from 00h, and is free-running thereafter. When the block is disabled, the clock is immediately gated low. All internal state is reset (including CR0 status) to its configuration-specific reset state, except for DR0, DR1, and DR2 which are unaffected. Transmit Operation. Transmission is initiated with a write to the TX Buffer register (DR1). The CPU write to this register is required to have one-half bit clock setup time for the data, to be recognized at the next positive internal bit clock edge. As shown in Figure 17-33, after the setup time is met, there is one clock of latency until the data is loaded into the shifter and the START bit is generated to the TXD (primary) output. Figure 17-33. Typical Transmitter Timing Free Running clock is CLK input divided by eight. User writes first byte to the TX Buffer register. User writes next byte to the TX Buffer register. Shifter is loaded with the next byte. Shifter is loaded with the first byte. INTERNAL CLOCK TX REG EMPTY TXD (F1) START D0 D4 D5 D6 D7 PAR STOP START SCLK (F2) TX Buffer write needs one-half cycle setup time to the internal clock. One cycle of latency before START bit at the TXD output. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 377 Digital Blocks Figure 17-34 shows a detail of the Tx Buffer load timing. The data bits are shifted out on each of the subsequent clocks. Following the eighth bit, if parity is enabled, the parity bit is sent to the output. Finally, the STOP bit is multiplexed into the data stream. With one-half cycle setup to the next clock, if new data is available from the TX Buffer register, the next byte is loaded on the following clock edge and the process is repeated. If no data is available, a mark (logic 1) is output. TX Reg Empty indicates that a new byte can be written to the TX Buffer register. When the block is enabled, this status bit is immediately asserted. This status bit is cleared when the user writes a byte of data to the TX Buffer register and set when the data byte in the TX Buffer register is transferred into the shifter. If a transmission is not already in progress, the assertion of this signal initiates one subject to the timing. Figure 17-34. Tx Buffer Load Timing The default interrupt in the Transmitter is tied to TX Reg Empty. However, an initial interrupt is not generated when the block is enabled. The user must write an initial byte to the TX Buffer register. That byte must be transferred into the shifter, before interrupts generated from the TX Reg Empty status bit are enabled. This prevents an interrupt from occurring immediately on block enable. INTERNAL CLOCK IOW TXREGEMPTY TXD START Write is valid on rising edge of low. A Tx Buffer write valid in this range will result in a START bit 1 cycle, after the subsequent rising edge of the clock. The SCLK (auxiliary) output has a SPI mode 3 clock associated with the data bits (for the mode 3 timing, see Figure 17-24). During the mark (idle) and framing bits the SCLK output is high. TX Complete is an optional interrupt and is generated when all bits of data and framing bits have been sent. It is cleared on a read of the CR0 register. This signal may be used to determine when it is safe to disable the block after data transmission is complete. In an interrupt driven Transmitter application, if interrupt on TX Complete is selected, the status must be cleared on every interrupt; otherwise, the status will remain high and no subsequent interrupts are logged. See Figure 17-35 for timing relationships. Status Clear On Read. Refer to the SPIM subsection in “SPIM Timing” on page 371. Status Generation. There are two status bits in the Transmitter CR0 register: TX Reg Empty and TX Complete. Figure 17-35. Status Timing for the Transmitter CCLK START TXD (F1) D0 D5 D6 D7 STOP SCLK (F2) TX REG EMPTY TX COMPLETE Full STOP bit is sent. A write to the TX Buffer register clears this status. 378 The Shifter is loaded from the TX Buffer register on this clock edge. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks 17.3.10 Receiver Timing Enable/Disable Operation. As soon as the block is configured for Receiver and before enabling, the primary output is connected to the data input (RXD). This output will continue to follow the input, regardless of enable state. The auxiliary output will idle to '1', which is the idle state of the associated SPI mode 3 clock. When the Receiver is enabled, the internal clock generator is held in reset until a START bit is detected on the input. The block must be enabled with a setup time to the first START bit input. When the block is disabled, the clock is immediately gated low. All internal state is reset (including CR0 status) to its configuration-specific reset state, except for DR0, DR1, and DR2 which are unaffected. Receive Operation. A clock, which must be eight times the desired baud rate, is selected as the CLK input. This clock is an input to the RX block clock divider. When the receiver is idle, the clock divider is held in reset. As shown in Figure 17-36, reception is initiated when a START bit (logic 0) is detected on the RXD input. When this occurs, the reset is negated to the clock divider and the 3-bit counter starts an up-count. The block clock is derived from the MSb of this counter (corresponding to a count of four), which serves to sample each incoming bit at the nominal center point. This clock also sequences the state machine at the specified bit rate. The sampled data is registered into an input flip-flop. This flip-flop feeds the DR0 Shift register. Only data bits are shifted into the Shift register. At the STOP sample point, the block is immediately (within one cycle of the 24 MHz system clock) set back into an idle state. In this way, the clock generation circuit can immediately enable the search for the next START bit, thereby resynchronizing the bit clock with the incoming bit rate on every new data byte reception. The RX Reg Full status bit, as well as error status, is also set at the STOP sample point. To facilitate connection to other digital blocks, the RXD input is passed directly to the RXDOUT (primary) output. The SCLK (auxiliary) output has an SPI mode 3 clock associated with the data bits (for mode 3 timing see Figure 17-36). During the mark (idle) and framing bits, the SCLK output is high. Figure 17-36. Receiver Operation At STOP edge, FSM is reset to IDLE, to search for next START after one 24 MHz clock (42 ns). Input is sampled at the center of the bit time. CCLK Start bit is detected; clock divider is enabled. D0 RXD STATE IDLE START D1 D6 BIT0 D7 BIT6 BIT7 PAR PAR RX REG FULL RXDOUT (F1) Clock divider is resynchronized from IDLE on detect of the next START bit. D0 IDLE START BIT0 STOP D0 D1 D6 D7 PAR D0 SCLK (F2) Serial data is passed through to the primary output. Mode 3 type clock on auxiliary output for data only RX buffer is loaded with the received byte and status is set on STOP bit detection edge. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 379 Digital Blocks Clock Generation and Start Detection. The input clock selection is a free running, eight times over-sampling clock. This clock is used by the clock divider circuit to generate the block clock at the bit rate. As shown in Figure 17-37, the clock block is derived from the MSb of a 3-bit counter, giving a sample point as near to the center of the bit time as possible. This block clock is used to clock all internal circuits. count at the eight times rate. If the RXD input is still logic 0 after three samples of the input clock, the status RXACTIVE is asserted, which initiates a reception. If this sample of the RXD line is a logic 1, the input '0' transition was assumed to be a false start and the Receiver remains in the idle state. Figure 17-37 shows that the internal bit clock (CCLK) is running slower than the external TX bit clock and the STOP bit is sampled later than the actual center point. After the STOP bit is sampled, the 24 MHz reset pulse forces the Receiver back to an idle state. In this state, the next START bit search is initiated, resynchronizing the RX bit clock to the TX bit clock. Because the RXD bit rate is asynchronous to the block bit clock, these clocks must be continually re-aligned. This is accomplished with the START bit detection. When in IDLE state, the clock divider is held in reset. On START (when the input RXD transitions are detected as a logic 0), the reset is negated and the divider is enabled to Figure 17-37. Clock Generation and Start Detection Actual center of STOP bit. Input is sampled at the center of the bit time. Start detection enables the clock divider. STOP bit sample point. Reset to IDLE and initiate search for a new START bit. CLKIN RXD START BIT (ASYNCH) RESET STOP BIT0 (CLK GEN) RXACTIVE COUNT 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 7 0 1 2 3 0 1 CCLK STATE IDLE START is confirmed with another sample at the 3rd sample clock. 380 START BIT0 IDLE Width of reset is STOP one 24 MHz clock pulse. Next START bit CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Digital Blocks This resynchronization process (forcing the state back to idle) occurs regardless of the value of the STOP bit sample. It is important to reset as soon as possible, so that maximum performance can be achieved. Figure 17-38 shows an example where the RX block clock bit rate is slower than the external TX bit rate. The sample point shifts to successively later times. In the extreme case shown, the RX samples the STOP bit at the trailing edge. In this case, the receiver has counted 9.5 bit times, while the transmitter has counted 10 bit times. Therefore, for a 10-bit message, the maximum theoretical clock offset, for the message to be received correctly, is represented by one-half bit time or five percent. If the RX and TX clocks exceed this offset, a logic 0 may be sampled for the STOP bit. In this case, the Framing Error status is set. Figure 17-38. Example RX Resynchronization RX clock is slower than TX clock. RXD Start 1 1 0 Sample points are successively later in the bit times. 1 0 0 1 Stop Bit is just recognized. Need to re-sync as soon as possible. 0 Stop Start 1 Any delay in re-sync will cut into the optimal sync of the next byte. This theoretical maximum will be degraded by the resynchronization time, which is fixed at approximately 42 ns. In a typical 115.2 Kbaud example, the bit time is 8.70 s. In this case the new maximum offset is: ((4.35 ms – 42 ns) / 4.35 ms) x 5% or 4.95% Status Generation. There are five status bits in a Receiver block: RX Reg Full, RX Active, Framing Error, Overrun, and Parity Error. All status bits, except RX Active and Overrun, are set synchronously on the STOP bit sample point. RX Reg Full indicates a byte has been received and transferred into the RX Buffer register. This status bit is cleared when the user reads the RX Buffer register (DR2). The setting of this bit is synchronized to the STOP sample point. This is the earliest point at which the Framing Error status can be set; and therefore, error status is defined to be valid when RX Reg Full is set. RX Active can be polled to determine if a reception is in progress. This bit is set on START detection and cleared on STOP detection. This bit is not sticky and there is no way for the user to clear it. Framing Error status indicates that the STOP bit associated with a given byte was not received correctly (expecting a '1', but received a '0'). This will typically occur when the difference between the baud rates of the transmitter and receiver is greater than the maximum allowed. Overrun occurs when there is a received data byte in the RX Buffer register and a new byte is loaded into the RX Buffer register, before the user has had a chance to read the previous one. Because the RX Buffer register is actually a latch, Overrun status is set one-half cycle before RX Reg Full. This means that although the new data is not available, the previous data has been overwritten because the latch was opened. Parity Error status indicates that resulting parity calculation on the received byte does not match the value of the parity bit that was transmitted. This status is set on the sample point of the STOP signal. At slower baud rates, this value gets closer to the theoretical maximum of five percent. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 381 Digital Blocks Status Clear On Read. Refer to the SPIM subsection in “SPIM Timing” on page 371. Figure 17-39. Status Timing for Receiver All status, except Overrun, is set synchronously with the STOP bit sample point. STOP CCLK STATE IDLE START RXD D0 BIT0 D1 BIT1 BIT5 BIT6 D6 BIT7 IDLE D7 RX_REG_FULL OVERRUN PARITY_ERROR, FRAMING_ERROR RX_ACTIVE Overrun is set one half cycle before RX REG Full. 17.3.11 DSM Timing Enable/Disable Operation. The enable/disable timing is similar to Timer/Counter but looser because it is only single block function. KILL Operation. DSM supports two KILL modes: KILL-Disable and KILL_Async. KILL-Disable is same as Timer/Counter KILL-Disable. KILL-Async is same as Dead Band KILL-Async mode. 382 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Section E: Analog System The configurable Analog System section discusses the analog components of the PSoC® device and the registers associated with those components. Note that the analog output drivers are described in the PSoC Core section, Analog Output Drivers chapter on page 79, because they are part of the core input and output signals. This section encompasses the following chapters: Analog Interface on page 393 ■ Analog Array on page 409 ■ Analog Input Configuration on page 417 ■ Analog Reference on page 421 Top Level Analog Architecture The following figures show the analog system architecture for each of the CY8C28xxx subfamilies in detail. Note that the CY8C28x03 devices have no analog blocks. With the exception of the analog drivers, each component of the figure is discussed at length in this section. ■ Switched Capacitor PSoC® Block on page 431 ■ Continuous Time PSoC® Block on page 425 ■ Two Column Limited Analog System on page 441 Analog System Block Diagram for CY8C28x13 Devices All GPIO Analog Mux Bus ■ P0[7] P0[5] P0[6] P0[4] P0[3] P0[2] P0[1] P0[0] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACE00 ACE01 ASE10 ASE11 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) The CY8C28x13 device group has limited analog functionality. It has no regular analog blocks and four Type-E Limited analog blocks. This device group has an analog mux bus which allows analog input on all GPIO. It has no analog outputs and two analog columns. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 383 Analog System Block Diagram for CY8C28x23 Devices Analog System Block Diagram for CY8C28x33 Devices P0[7] All GPIO P0[5] P0[6] P0[7] P0[4] P0[5] P0[3] P0[6] P0[1] P2[3] P0[2] P0[3] P0[0] P0[1] P0[4] P0[2] P2[3] P2[1] P2[4] P0[0] AGNDIn RefIn P2[6] Analog Mux Bus AGNDIn RefIn P2[1] P2[6] P2[4] Array Input Configuration ACI0[1:0] Array Input Configuration ACI1[1:0] ACI0[1:0] ACI1[1:0] ACI4[1:0] ACI5[1:0] Block Array ACC00 ACC01 ASC10 ASD11 ASD20 ASC21 Block Array ACC00 ACC01 ASC10 ASD11 ASD20 ASC21 ACE00 ACE01 ASE10 ASE11 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap Analog Reference Interface to Digital System M8C Interface (Address Bus, Data Bus, Etc.) The CY8C28x23 device group has six regular analog blocks and no Type-E Limited analog blocks. It has two analog outputs and two analog columns. 384 RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) The CY8C28x33 device group has six regular analog blocks and four Type-E Limited analog blocks. This device group has an analog mux bus which allows analog input on all GPIO.It has two analog outputs and four analog columns. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog System Block Diagram for CY8C28x43 Devices All GPIO P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] AGNDIn RefIn P0[7] Analog Mux Bus P2[3] P2[1] P2[6] P2[4] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] Block Array ACC00 ACC01 ACC02 ACC03 ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD22 ASC23 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) The CY8C28x43 device group has12 regular analog blocks and no Type-E Limited analog blocks. This device group has an analog mux bus which allows analog input on all GPIO. It has four analog outputs and four analog columns. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 385 Analog System Block Diagram for CY8C28x45 and CY8C28x52 Devices All GPIO P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] AGNDIn RefIn P0[7] Analog Mux Bus P2[3] P2[1] P2[6] P2[4] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] ACI4[1:0] ACI5[1:0] Block Array ACC00 ACC01 ACC02 ACC03 ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD22 ASC23 ACE00 ACE01 ASE10 ASE11 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) The CY8C28x45 and CY8C28x52 device groups have 12 regular analog blocks and four Type-E Limited analog blocks. These device groups have an analog mux bus which allows analog input on all GPIO. They have four analog outputs and six analog columns. 386 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Interpreting the Analog Documentation Defining the Analog Blocks Information in this section covers all PSoC devices with a base part number of CY8C28xxx. The primary analog distinction between these devices is the number of analog columns: 0, 2, or 4 columns. The following table lists the resources available for specific device groups. While reading the analog system section, determine and keep in mind the number of analog columns that are in your device, to accurately interpret the documentation. Digital I/O (max) Digital Rows Digital Blocks Analog Inputs (max) Analog Outputs Analog Columns Regular Analog Blocks Limited Analog Blocks PSoC Device Characteristics CY8C28x03* 24 3 12 8 0 0 0 0 CY8C28x13* 40 3 12 40 0 2 0 4 CY8C28x23 44 3 12 10 2 2 6 0 CY8C28x33 40 3 12 40 2 4 6 4 CY8C28x43 44 3 12 44 4 4 12 0 CY8C28x45 44 3 12 44 4 4 12 4 CY8C28x52 24 2 8 24 4 4 12 4 PSoC Part Number * Limited analog functionality. Application Description PSoC blocks are user configurable system resources. Onchip analog PSoC blocks reduce the need for many MCU part types and external peripheral components. Analog PSoC blocks are configured to provide a wide variety of peripheral functions. The PSoC Designer Software Integrated Development Environment provides automated configuration of PSoC blocks by selecting the desired functions. PSoC Designer then generates the proper configuration information and prints a device data sheet unique to that configuration. A precision internal voltage reference provides accurate analog comparisons. A temperature sensor input is provided to the analog PSoC block array, supporting applications such as battery chargers and data acquisition, without requiring external components. There are three analog PSoC block types: Continuous Time (CT) blocks, and Type C and Type D Switch Capacitor (SC) blocks. CT blocks provide continuous time analog functions. SC blocks provide switched capacitor analog functions. Each of the analog blocks has many potential inputs and several outputs. The inputs to these blocks include analog signals from external sources, intrinsic analog signals driven from neighboring analog blocks, or various voltage reference sources. The analog blocks are organized into columns. Each column contains one Continuous Time (CT) block, Type C (ACC); one Switched Capacitor (SC) block, Type C (ASC); and one Switched Capacitor block, Type D (ASD). However, the number of analog columns in a specific part can either be 0, 2, or 4 columns. To determine the number of columns in your PSoC device, refer to the PSoC Device Characteristics table at the beginning of this section. The blocks in a particular column all run off the same clocking source. The blocks in a column also share some output bus resources. There are three types of outputs from each analog block and additional two discrete outputs in the Continuous Time blocks. 1. The analog output bus (ABUS) is an analog bus resource that is shared by all of the analog blocks in a column. Only one block in a column can actively drive this bus at any one time, with the user having control of this output through register settings. This is the only analog output that can be driven directly to a pin. 2. The comparator bus (CBUS) is a digital bus resource that is shared by all of the analog blocks in a column. Only one block in a column can be actively driving this bus at any one time, with the user having control of this output through register settings. 3. The local outputs (OUT, GOUT, and LOUT in the Continuous Time blocks) are routed to neighbor blocks. The various input multiplexer (mux) connections (NMux, PMux, RBotMux, AMux, BMux, and CMux) all use the output bus from one block as their input. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 387 Analog Functionality The following is a sampling of the functions that operate within the capability of the analog PSoC blocks, using one analog PSoC block, multiple analog blocks, a combination of more than one type of analog block, or a combination of analog and digital PSoC blocks. Most of these functions are currently available as user modules in PSoC Designer. Others will be added in the future. Refer to the PSoC Designer software for additional information and the most up-to-date list of user modules. ■ Delta-Sigma Analog-to-Digital Converters ■ Successive Approximation Analog-to-Digital Converters ■ Incremental Analog-to-Digital Converters ■ Digital to Analog Converters ■ Programmable Gain/Loss Stage ■ Analog Comparators ■ Zero-Crossing Detectors ■ Sample and Hold ■ Low-Pass Filter ■ Band-Pass Filter ■ Notch Filter ■ Amplitude Modulators ■ Amplitude Demodulators ■ Sine-Wave Generators ■ Sine-Wave Detectors ■ Sideband Detection ■ Sideband Stripping ■ Temperature Sensor ■ Audio Output Drive ■ DTMF Generator ■ FSK Modulator ■ Embedded Modem By modifying registers, as described in this document, users can configure PSoC blocks to perform these functions and more. The philosophy of the analog functions supplied is as follows. ■ Cost effective, single-ended configuration for reasonable speed and accuracy, providing a simple interface to most real-world analog inputs and outputs. ■ Flexible, System-on-Chip programmability, providing variations in functions. ■ Function specific, easily selected trade-offs of accuracy and resolution with speed, resources (number of analog blocks), and power dissipated for that application. 388 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Register Summary The following table lists all the PSoC registers for the analog system in address order (Add. column) within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. The naming conventions for the SC and CT registers and their arrays of PSoC blocks are detailed in their respective table title rows. Note that all PSoC devices, with a base part number of CY8C28xxx fall into one of the following categories with respect to their analog PSoC arrays: 4 column device, 2 column device, or 0 column device. The “PSoC Analog System Block Diagram” at the beginning of this section illustrates this. In the following table, the third column from the left titled “Analog Columns” indicates which of the three PSoC device categories the register falls into. To determine the number of analog columns in your PSoC device, refer to the table titled “PSoC Device Characteristics” on page 387. Summary Table of the Analog Registers Add. Name Analog Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access ANALOG INTERFACE REGISTERS (page 400) 0,62h CLK_CR3 0,64h CMP_CR0 0,65h ASY_CR 0,66h CMP_CR1 0,E6h DEC_CR0 0,E7h DEC_CR1 1,60h CLK_CR0 1,61h CLK_CR1 1,63h AMD_CR0 4 SYSDIR[3:0] COMP[3:0] 4 COMP[1:0] 2 SARCNT[2:0] 4, 2 4 CLDIS[3] CLDIS[2] 2 4, 2 2 4 CLDIS[0] CLDIS[1] CLDIS[0] ECNT SARCOL[1:0] SYNCEN CLK1X[1] ICLKS0 DCOL[1:0] CLK1X[0] DCLKS0 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 AColumn3[1:0] AColumn2[1:0] 2 SHDIS 4, 2 # : 00 AINT[1:0] SARSIGN CLDIS[1] IGEN[3:0] 4 RW : 00 AINT[3:0] AColumn1[1:0] AColumn0[1:0] AColumn1[1:0] AColumn0[1:0] ACLK1[2:0] ACLK0[2:0] AMOD2[2:0] 4 RW : 00 RW : 00 RW : 00 RW : 00 RW : 00 AMOD0[2:0] RW : 00 AMOD0[2:0] 2 RW : 00 1,64h CMP_GO_EN 2 GOO5 GOO1 SEL1[1:0] GOO4 GOO0 SEL0[1:0] RW : 00 1,65h CMP_GO_EN1 2 GOO7 GOO3 SEL3[1:0] GOO6 GOO2 SEL2[1:0] RW : 00 1,66h AMD_CR1 AMOD3[2:0] 4 AMOD1[2:0] RW : 00 AMOD1[2:0] 2 1,67h ALT_CR0 4, 2 LUT1[3:0] LUT0[3:0] 1,68h ALT_CR1 4 LUT3[3:0] LUT2[3:0] 1,69h CLK_CR2 4 RW : 00 RW : 00 ACLK1R ACLK0R RW : 00 ANALOG INPUT CONFIGURATION REGISTERS (page 419) 0,60h AMX_IN 1,62h ABF_CR0 4 ACI3[1:0] ACI2[1:0] 2 4 ACol1Mux 2 ACol1Mux ABusMux3 1,6Ah AMUX_CFG1 ACol2Mux ABUF1EN ABUF2EN ABUF1EN ABusMux2 ACol3Mux ACI1[1:0] ACI0[1:0] ACI1[1:0] ACI0[1:0] ABUF0EN ABUF3EN ABUF0EN ACol0Mux RW : 00 Bypass PWR Bypass PWR MUXCLKR[2:0] ENR RW : 00 RW : 00 ANALOG REFERENCE REGISTER (page 421) 0,63h ARF_CR 4, 2 HBE REF[2:0] PWR[2:0] RW : 00 CONTINUOUS TIME PSoC BLOCK REGISTERS (page 426) 0,70h ACC00CR3 4, 2 0,71h ACC00CR0 4, 2 AGND_PD 0,72h ACC00CR1 4, 2 AnalogBus CompBus 0,73h ACC00CR2 4, 2 CPhase CLatch RTopMux1 RTapMux[3:0] LPCMPEN CMOUT Gain RTopMux NMux[2:0] CompCap TMUXEN INSAMP EXGAIN RBotMux[1:0] PMux[2:0] TestMux[1:0] CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F PWR[1:0] RW : 00 RW : 00 RW : 00 RW : 00 389 Summary Table of the Analog Registers (continued) Add. Name Analog Cols. 0,74h ACC01CR3 4, 2 0,75h ACC01CR0 4, 2 0,76h ACC01CR1 4, 2 AnalogBus CompBus 0,77h ACC01CR2 4, 2 CPhase CLatch 0,78h ACC02CR3 4 0,79h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 AGND_PD RTopMux1 RTapMux[3:0] ACC02CR0 4 0,7Ah ACC02CR1 4 AnalogBus CompBus 0,7Bh ACC02CR2 4 CPhase CLatch 0,7Ch ACC03CR3 4 0,7Dh ACC03CR0 4 0,7Eh ACC03CR1 4 AnalogBus CompBus 0,7Fh ACC03CR2 4 CPhase CLatch Bit 2 Bit 1 Bit 0 Access LPCMPEN CMOUT INSAMP EXGAIN RW : 00 Gain RTopMux NMux[2:0] CompCap TMUXEN AGND_PD RTopMux1 RTapMux[3:0] PMux[2:0] TestMux[1:0] CMOUT Gain RTopMux CompCap TMUXEN RTopMux1 RTapMux[3:0] TMUXEN EXGAIN RBotMux[1:0] PMux[2:0] TestMux[1:0] CMOUT Gain RTopMux INSAMP EXGAIN RBotMux[1:0] PMux[2:0] TestMux[1:0] RW : 00 RW : 00 RW : 00 RW : 00 PWR[1:0] LPCMPEN NMux[2:0] CompCap INSAMP RW : 00 RW : 00 PWR[1:0] LPCMPEN NMux[2:0] AGND_PD RBotMux[1:0] RW : 00 RW : 00 RW : 00 RW : 00 PWR[1:0] RW : 00 ACI0[1:0] RW : 00 CY8C28XXX REMAPPED PSoC BLOCK REGISTERS (page 441) 1,73h ACE_AMD_CR0 4 1,75h ACE_AMX_IN 4 1,76h ACE_CMP_CR0 4 COMP[1:0] 1,77h ACE_CMP_CR1 4 CLDIS[1:0] 1,79h ACE_CMP_GI_EN 4 1,7Ah ACE_ALT_CR0 4 1,7Bh ACE_ABF_CR0 4 1,7Dh ACE00CR1 4 1,7Eh ACE00CR2 4 AMOD0[3:0] ACI1[1:0] GIO5 GIO1 SEL1[1:0] AINT[1:0] GIO4 CompBus NMux[2:0] PMux[2:0] 1,85h ACE_PWM_CR 4 1,86h ACE_ADC0_CR 4 CMPST LOREN SHEN CBSRC 1,87h ACE_ADC1_CR 4 CMPST LOREN SHEN CBSRC 1,89h ACE_CLK_CR0 4 1,8A ACE_CLK_CR1 4 1,8Bh ACE_CLK_CR3 4 SYS1 CompBus 4 RW : 00 PWR RW : 00 RW : 00 4 1,Fh * ASE11CR0 RW : 00 FullRange 4 4 RW : 00 RW : 00 ACE_AMD_CR1 4 SEL0[1:0] ACE0Mux 1,83h 1,8Dh ACE01CR1 GIO0 LUT0[3:0] 1,7Fh ASE10CR0 1,8Eh ACE01CR2 # : 00 RW : 00 LUT1[3:0] ACE1Mux RW : 00 FVal AMOD1[3:0] HIGH[2:0] RW : 00 LOW[1:0] PWMEN RW : 00 AUTO ADCEN # : 00 AUTO ADCEN AColumn1[1:0] ACLK1[3:0] RW : 00 DIVCLK0[1:0] RW : 00 ACLK0[3:0] DIVCLK1[1:0] SYS0 NMux[2:0] # : 00 AColumn0[1:0] RW : 00 PMux[2:0] FullRange RW : 00 PWR RW : 00 RW : 00 FVal SWITCHED CAPACITOR PSoC BLOCK REGISTERS (page 434) Switched Capacitor Block Registers, Type C (page 435) 0,80h ASC10CR0 4, 2 0,81h ASC10CR1 4, 2 0,82h ASC10CR2 4, 2 0,83h ASC10CR3 4, 2 0,88h ASC12CR0 4 0,89h ASC12CR1 4 0,8Ah ASC12CR2 4 0,8Bh ASC12CR3 4 0,94h ASC21CR0 4, 2 0,95h ASC21CR1 4, 2 0,96h ASC21CR2 4, 2 0,97h ASC21CR3 4, 2 0,9Ch ASC23CR0 4 0,9Dh ASC23CR1 4 390 FCap ClockPhase ASign ACMux[2:0] AnalogBus CompBus ARefMux[1:0] FCap ClockPhase AutoZero FSW1 CompBus ARefMux[1:0] FSW0 ASign FCap ClockPhase AutoZero FSW1 CompBus ARefMux[1:0] FSW0 ASign FCap ClockPhase ACMux[2:0] AutoZero FSW1 ASign RW : 00 BMuxSC[1:0] RW : 00 PWR[1:0] ACap[4:0] RW : 00 RW : 00 BMuxSC[1:0] RW : 00 PWR[1:0] RW : 00 ACap[4:0] RW : 00 BCap[4:0] RW : 00 CCap[4:0] FSW0 RW : 00 BCap[4:0] CCap[4:0] ACMux[2:0] AnalogBus RW : 00 CCap[4:0] ACMux[2:0] AnalogBus ACap[4:0] BCap[4:0] BMuxSC[1:0] RW : 00 PWR[1:0] RW : 00 ACap[4:0] RW : 00 BCap[4:0] RW : 00 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Summary Table of the Analog Registers (continued) Name Analog Cols. 0,9Eh ASC23CR2 4 0,9Fh ASC23CR3 4 Add. Bit 7 Bit 6 Bit 5 AnalogBus CompBus AutoZero ARefMux[1:0] FSW1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CCap[4:0] FSW0 BMuxSC[1:0] Access RW : 00 PWR[1:0] RW : 00 Switched Capacitor Block Registers, Type D (page 438) 0,84h ASD11CR0 4, 2 0,85h ASD11CR1 4, 2 0,86h ASD11CR2 4, 2 0,87h ASD11CR3 4, 2 0,8Ch ASD13CR0 4 0,8Dh ASD13CR1 4 0,8Eh ASD13CR2 4 0,8Fh ASD13CR3 4 0,90h ASD20CR0 4, 2 0,91h ASD20CR1 4, 2 0,92h ASD20CR2 4, 2 0,93h ASD20CR3 4, 2 0,98h ASD22CR0 4 0,99h ASD22CR1 4 0,9Ah ASD22CR2 4 0,9Bh ASD22CR3 4 FCap ClockPhase ASign AMux[2:0] AnalogBus CompBus ARefMux[1:0] FCap ClockPhase AutoZero FSW1 CompBus ARefMux[1:0] FCap ClockPhase BSW CompBus ARefMux[1:0] FCap ClockPhase CompBus ARefMux[1:0] BMuxSD RW : 00 PWR[1:0] RW : 00 ACap[4:0] BCap[4:0] RW : 00 AutoZero CCap[4:0] RW : 00 FSW1 FSW0 BSW BMuxSD RW : 00 PWR[1:0] RW : 00 ASign ACap[4:0] BCap[4:0] RW : 00 AutoZero CCap[4:0] RW : 00 FSW1 FSW0 BSW BMuxSD RW : 00 PWR[1:0] RW : 00 ASign ACap[4:0] BCap[4:0] RW : 00 AutoZero CCap[4:0] RW : 00 AMux[2:0] AnalogBus RW : 00 ASign AMux[2:0] AnalogBus RW : 00 BCap[4:0] CCap[4:0] FSW0 AMux[2:0] AnalogBus ACap[4:0] FSW1 FSW0 BSW BMuxSD RW : 00 PWR[1:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. # Access is bit specific. Refer to the Register Details chapter on page 125 for additional information. R Read register or bit(s). W Write register or bit(s). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 391 392 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 18. Analog Interface This chapter explains the Analog Interface and its associated registers. The analog system interface is a collection of system level interfaces to the analog array and analog reference block. For a complete table of the analog interface registers, refer to the “Summary Table of the Analog Registers” on page 389. For a quick reference of all PSoC® registers in address order, refer to the Register Details chapter on page 125. 18.1 Architectural Description Figure 18-1 displays the top-level diagram of the PSoC device’s analog interface system. Figure 18-1. Analog Comparator Bus Slice Data Output From DBC01 Data Output From DCC02 Data Output From DBC11 Data Output From DCC12 One Analog Column Continuous Time Block CMP Analog Comparator Bus Slice Latch Transparent, PHI1 or PHI2 CBUS Driver Incremental Gate, One per Column (From Digital Blocks) IGEN[1:0] From Col (i+1) Switched Capacitor Block CMP (DEC_CR0[5:4]) Latch PHI1 or PHI2 CBUS Driver Latch Switched Capacitor Block Latch PHI1 or PHI2 B A LUT (ALT_CR0[7:0]) PHI2 CMP Destinations BYPASS To Col (i-1) (CLDIS, CMP_CR1[7:4]) PHI2 CBUS Driver 1) Comparator Register 2) Data Inputs for Digital Blocks 3) Input to Decimator Column Interrupt AINT (CMP_CR0[1:0]) Output to SAR Accelerator Input Mux CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 393 Analog Interface 18.1.1 Analog Data Bus Interface The Analog Data Bus Interface isolates the analog array and analog system interface registers from the CPU system data bus, to reduce bus loading. Transceivers are implemented on the system data bus to isolate the analog data bus from the system data bus. This creates a local analog data bus. 18.1.2 Analog Comparator Bus Interface Each analog column has a dedicated comparator bus associated with it. Every analog PSoC block has a comparator output that can drive this bus. However, only one analog block in a column can actively drive the comparator bus for a column at any one time. The output on the comparator bus drives into the digital blocks as a data input. It also serves as an input to the decimator, as an interrupt input, and is available as read only data in the Analog Comparator Control register (CMP_CR0). Figure 18-1 illustrates one column of the comparator bus. In the Continuous Time (CT) analog blocks, the CPhase and CLatch bits of CT Block Control Register 2 determine whether the output signal on the comparator bus is latched inside the block, and if it is, which clock phase it is latched on. In the Switched Capacitor (SC) analog blocks, the output on the comparator bus is always latched. The ClockPhase bit in SC Block Control Register 0 determines the phase on which this data is latched and available. The comparator bus is latched before it is available, to either drive the digital blocks, interrupt, decimator, or for it to be read in the CMP_CR0 register. The latch for each comparator bus is transparent (the output tracks the input) during the high period of PHI2. During the low period of PHI2, the latch retains the value on the comparator bus during the high-tolow transition of PHI2. The CMP_CR0 register is described in the “CMP_CR0 Register” on page 401. There is also an option to force the latch in each column into a transparent mode by setting bits in the CMP_CR1 register. The CY8C28xxx PSoC devices have an additional comparator synchronization option in which the 1X direct column clock selection is used to synchronize the analog comparator bus. This allows for higher frequency comparator sampling. As shown in Figure 18-1, the comparator bus output is gated by the primary output of a selected digital block. This feature is used to precisely control the integration period of an incremental ADC. Any digital block can be used to drive the gate signal. This selection may be made with the ICLKS bits in registers DEC_CR0 and DEC_CR1. This function may be enabled on a column-by-column basis, by setting the IGEN bits in the DEC_CR0 register. The analog comparator bus output values can be modified or combined with another analog comparator bus through the Analog look-up table (LUT) function. The LUT takes two inputs, A and B, and provides a selection of 16 possible 394 logic functions for those inputs. The LUT A and B inputs for each column comparator output is shown in the following table. Table 18-1. A and B Inputs for Each Column Comparator LUT Output Comparator LUT Output A B Column 0 ACMP0 ACMP1 Column 1 ACMP1 ACMP2 Column 2 ACMP2 ACMP3 Column 3 ACMP3 ACMP0 Column 0 ACMP0 ACMP1 Column 1 ACMP1 0 Column 2 0 0 Column 3 0 ACMP0 4 Column PSoCs 2 Column PSoCs The LUT configuration is set in two control registers, ALT_CR0 and ALT_CR1. Each selection for each column is encoded in four bits. The function value corresponding to the bit encoding is shown in the following table. Table 18-2. RDIxLTx Register LUTx[3:0] 18.1.3 0h: 0000: FALSE 1h: 0001: A .AND. B 2h: 0010: A .AND. B 3h: 0011: A 4h: 0100: A .AND. B 5h: 0101: B 6h: 0110: A .XOR. B 7h: 0111: A .OR. B 8h: 1000: A .NOR. B 9h: 1001: A .XNOR. B Ah: 1010: B Bh: 1011: A .OR. B Ch: 1100: A Dh: 1101: A .OR. B Eh: 1110: A. NAND. B Fh: 1111: TRUE Analog Column Clock Generation The analog array switched capacitor blocks require a twophase, non-overlapping clock. The switched cap blocks are arranged in four columns, two to a column (a third block in the column is a continuous time block). An analog column clock generator is provided for each column and this clock is shared among the blocks in that column. The input clock source for each column clock generator is selectable according to the CLK_CR0 register. It is important to note that regardless of the clock source selected, the output frequency of the column clock generator is the input frequency divided by four. There are four selections for each column: V1, V2, ACLK0, and ACLK1. The V1 and V2 clock signals are global system clocks. Programming options for these system clocks can be accessed in the OSC_CR1 register. Each of the ACLK0 and ACLK1 clock selections are driven by a selection of digital block outputs. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Interface The settings for the digital block selection are located in register CLK_CR1 and the register CLK_CR2. The timing for analog column clock generation is shown in Figure 18-2. The dead band time between two phases of the clock is designed to be a minimum of 21 ns. Figure 18-2. Two Phase Non-Overlapping Clock Generation 18.1.4 Decimator and Incremental ADC Interface The Decimator and Incremental ADC Interface provides hardware support and signal routing for analog-to-digital conversion functions, specifically the Delta Signal ADC and the Incremental ADC. The control signals for this interface are split between two registers: DEC_CR0 and DEC_CR1. 18.1.4.1 Decimator INPUT CLK The Decimator is a hardware block that is used to perform digital processing on the analog block outputs. Note that the decimator function is not in the CY8C28x03 devices. COL CLK PHI1 PHI2 Underlap is 21 ns to 42 ns. COL CLK transitions on the falling edge of each phase. The decimator interface provides the following signals, which are routed between the analog array and analog clock generation circuitry to the decimator block. 1. CD: Comparator Data 2. CLK2X: Selected analog column’s 2x clock 18.1.3.1 Column Clock Synchronization When analog signals are routed between blocks in adjacent columns, it is important that the clocks in these columns are synchronized in phase and frequency. Frequency synchronization may be achieved by selecting the same input source to two or more columns. However, there is a special feature of the column clock interface logic that provides a resynchronization of clock phase. This function is activated on any I/O write to either the Column Clock Selection register (CLK_CR0) or the Reference Calibration Clock register (RCL_CR). A write to either of these registers initiates a synchronous reset of the column clock generators, restarting all clocks to a known state. This action causes all columns with the same selected input frequency to be in phase. Writing these registers should be avoided during critical analog processing, as column clocks are all re-initialized and thus a discontinuity in PHI1/PHI2 clocking will occur. Figure 18-3. Column Clock Resynchronize on an I/O Write Write new clock selection. All clocks are restarted in phase. IOW CLK24 SOURCE CLOCK CLOCK COLUMN REGISTER 4. BW The source for the decimator data input (CD) is selected from any of the four column comparator outputs plus several other sources. After the source column is selected, the two clocks associated with that column (CLK2X and CLK) are also routed to the decimator. These clocks are by-products of the column clock generators and are specific to the timing of the decimator. See the Decimator chapter for details. The DCLKS0 and DCLKS1 bits, which are split between the DEC_CR0 and DEC_CR1 registers, are used to select a source for the decimator output latch enable. The decimator is typically run autonomously over a given period. The length of this period is set in a timer block that is running in conjunction with the analog processing. At the terminal count of this timer, the primary output goes high for one clock cycle. This pulse is translated into the decimator output latch enable signal, which transfers data from the internal accumulators to an output buffer. The terminal count also causes an interrupt and the CPU may read this output buffer at any time between one latch event and the next. 18.1.4.2 COL CLK RESET PHI2 Selected analog column’s 1x clock Note If the Decimation Rate bits in DECx_CR are set, then this timer is not needed. All decimator timing is handled internal to the decimator block. CPUCLK PHI1 3. CLK: Setup time to next same input clock. Incremental ADC The analog interface has support for the incremental ADC operation through the ability to gate the analog comparator outputs. This gating function is required to precisely control the digital integration period that is performed in a digital block, as part of the function. A digital block pulse width modulator (PWM) is used as a source to provide the gate signal. Only one source for the gating signal can be selected. However, the gating can be applied independently to any of the column comparator outputs. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 395 Analog Interface The ICLKS bits, which are split between the DEC_CR0 and DEC_CR1 registers, are used to select a source for the incremental gating signal. The four IGEN bits are used to independently enable the gating function on a column-bycolumn basis. The E type analog columns in CY8C28x13, CY8C28x33, CY8C28x45, and CY8C28x52 devices contain a dedicated block that can perform this gating function using VC3. When this dedicated PWM is configured, it overrides the ICLKS selection as defined by the DEC_CR0 and DEC_CR1 registers. Figure 18-4. Synchronized Write to a DAC Register Stall is released here. CPUCLK (Generated) CPUCLK (To CPU) IOW STALL PHI CLK24 18.1.5 Analog Modulator Interface (Mod Bits) The Analog Modulator Interface provides a selection of signals that are routed to any of the four analog array modulation control signals. There is one modulation control signal for each Type C Analog Switched Capacitor block in every analog column. There are eight selections, which include the analog comparator bus outputs, two global outputs, and a digital block broadcast bus. The selections for all columns are identical and are contained in the AMD_CR0 and AMD_CR1 registers. The Mod bit is XORed with the Switched Capacitor block sign bit (ASign in ASCxxCR0) to provide dynamic control of that bit. 18.1.6 Analog Synchronization Interface (Stalling) Note that this function is not supported in the CY8C28x03, and CY8C28x13 PSoC devices. For high precision analog operation, it is necessary to precisely time when updated register values are available to the analog PSOC blocks. The optimum time to update values in Switch Capacitor registers is at the beginning of the PHI1 active period. Depending on the relationship between the CPU CLK and the analog column clock, the CPU I/O write cycle can occur at any 24 MHz master clock boundary in the PHI1 or PHI2 cycle. Register values may be written at arbitrary times; however, glitches may be apparent at analog outputs. This is because the capacitor value is changing when the circuit is designed to be settling. The SYNCEN bit in the Analog Synchronization Control register (ASY_CR) is designed to address this problem. When the SYNCEN bit is set, an I/O write instruction to any Switch Capacitor register is blocked at the interface and the CPU will stall. On the subsequent rising edge of PHI1, the CPU stall is released, allowing the I/O write to be performed at the destination analog register. This mode synchronizes the I/O write action to perform at the optimum point in the analog cycle, at the expense of CPU bandwidth. Figure 18-4 shows the timing for this operation. AIOW AIOW completes here. As an alternative to stalling, the source for the analog column interrupts is set as the falling edge of the PHI2 clock. This configuration synchronizes the CPU to perform the I/O write after the PHI2 phase is completed, which is equivalent to the start of PHI1. 18.2 Application Description 18.2.1 SAR Hardware Acceleration Note This is different from the dedicated SAR10 block. Using the SAR10 block is recommended if a SAR ADC is needed. The Successive Approximation Register (SAR) algorithm is a binary search on the Digital-to-Analog Converter (DAC) code that best matches the input voltage that is being measured. The first step is to take an initial guess at mid-scale, which effectively splits the range by half. The DAC output value is then compared to the input voltage. If the guess is too low, a result bit is set for that binary position and the next guess is set at mid-scale of the remaining upper range. If the guess is too high, a result bit is cleared and the next guess is set at mid-scale of the remaining lower range. This process is repeated until all bits are tested. The resulting DAC code is the value that produces an output voltage closest to the input voltage. This code should be within one LSb of the input voltage. The successive approximation analog-to-digital algorithm requires the following building blocks: a DAC, a comparator, and a method or apparatus to sequence successive writes to the DAC based on the comparator output. The SAR hardware accelerator represents a trade off between a fully automatic hardware sequencing approach and a pure firmware approach. 18.2.1.1 Architectural Description The architectural description for the SAR hardware accelerator is illustrated in Figure 18-5. 396 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Interface Figure 18-5. SAR Hardware Accelerator System Data Bus Analog Data Bus DB Read M8C Micro Switched Capacitor Block SAR Accelerator Input Mux DAC Register DAC Analog Input SAR Accelerator CMP Latch CBUS Driver PHI1 or PHI2 As shown in Figure 18-5, the SAR accelerator hardware is interfaced to the analog array through the comparator output and the analog array data bus. To create DAC output, values are written directly to the ACAP field in the DAC register. To facilitate the sequencing of the DAC writes in the SAR algorithm, the M8C is programmed to do a sequence of READ, MODIFY, and WRITE instructions. This is an atomic operation that consists of an I/O read (IOR) followed closely by an I/O write (IOW). One example of an assembly level instruction is as follows. OR reg[DAC_REG],0 The SAR hardware is designed to process six bits of a result in a given sequence. A higher resolution SAR is implemented with multiple passes. 18.2.1.2 Application Description There are a number of ways to map a SAR6 module into the analog array. A SAR6 can be created from 1 SC block, 2 SC blocks, or 1 SC block and 1 CT block. In the following example, the programming, the clock selection, connectivity, inputs, of a two block SAR6 will be demonstrated. This type of SAR6 is made up of 1 SC block that operates as a DAC6, and 1 SC block that operates as a voltage summer and comparator. The 2 block SAR6 is placed in column 0 as shown in Figure 18-6. Figure 18-6. SAR6 Module Example ASA10 (DAC6) During each I/O read operation, the SAR hardware overrides two bits of the data: ■ To correct the previous bit guess based on the current comparator value. ■ To set the next guess (next least significant bit). Port 2[3] CMP BUS The effect of this instruction is to read the DAC register and follow it closely in time by a write back. The OR instruction does not modify the read data (it is ORed with ‘0’). The CPU does not need to do any additional computation in conjunction with this procedure. The SAR hardware transparently does the data modification during the read portion of the cycle. The only purpose for executing this instruction is to initiate a read that is modified by the SAR hardware, then to follow up with a write that transfers the data back to the DAC register. Comparator Bus Outputs from Other Columns ASB20 (CMP) The CPU latches this SAR modified data, ORs it with ‘0’ (no CPU modification), and writes it back to the DAC register. A counter in the SAR hardware is used to decode which bits are being operated on in each cycle. In this way, the capability of the CPU and the IOR/IOW control lines are used to implement the read and write. Use the SAR accelerator hardware to make the decisions and to control the values written, achieving the optimal level of performance for the current system. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 397 Analog Interface The programming for the DAC6 block is as follows: CR0: CR1: CR2: CR3: initializes this register to ‘6’. When these bits are any value other than ‘0’, an IOR command to an SC block is assumed to be part of a SAR sequence. mov reg[ASC10CR0], a0h // Full Feedback, ACap Value = > // Start with Sign = 1 mov reg[ASC10CR1], 40h // Select REFHI for DAC function mov reg[ASC10CR2], a0h // OBUS ON, Auto-Zero ON mov reg[ASC10CR3], 33h // Feedback ON, Power ON Assuming the comparator bus output is programmed for column 0, a typical firmware sequence is as follows. mov The programming for the SUMMING/COMPARATOR block is as follows: CR0: CR1: CR2: CR3: mov // mov // mov // mov // reg[ASD20CR0], bfh Full Feedback, Sign = 1, ACap = 31 reg[ASC20CR1], 3fh A Input = P2_3, BCap = 31 reg[ASC20CR2], 60h Cmp Bus ON, Auto Zero ON reg[ASC20CR3], 17h Feedback OFF, B Input = North Firmware Support Examples In addition to the use of the OR instruction to sequence the algorithm, there are some minimal setup requirements. The SAR control bits are in the ASY_CR register. The definition of these bits as related to the SAR are as follows. Bits [2:1] Column Select for the SAR Comparator Input The DAC portion of the SAR can reside in any of the appropriate positions in the analog PSOC block array. However, when the COMPARATOR block is positioned (and it is possible to have the DAC and COMPARATOR in the same block), this should be the column selected. Bit [3] Sign Selection This bit optionally inverts the comparator input to the SAR accelerator. It must be set based on the type of PSOC block configuration selected. Some typical examples are listed in Table 18-3. or or or or or or reg[ASY_CR], 60h // SAR count value=6, // Sign=0, Col=0 reg[ASC10CR0], 0 // Check sign, set bit 4 reg[ASC10CR0], 0 // Check bit 4, set bit 3 reg[ASC10CR0], 0 // Check bit 3, set bit 2 reg[ASC10CR0], 0 // Check bit 2, set bit 1 reg[ASC10CR0], 0 // Check bit 1, set bit 0 reg[ASC10CR0], 0 // Check bit 0 SAR6 Calculation Example This example assumes an input voltage level (VIn) of 3.0 V on the PSoC input pin. The selection is made of +/- VREF for the DAC references. Assuming VREF = 1.25, the input range will be from 1.25 to 3.75 volts. The 6-bit DAC will yield a sign magnitude result with 64 discrete values, thus giving 39 mV of resolution over the input range. With 3.0 V input, the expected magnitude of the result is (3.0-2.5)/1.25 * 32 = 12.8. The expected sign of the result is ‘0’, meaning positive; therefore, the result is Sign=0, Magnitude=12 or 13. The error in this basic SAR algorithm is always less than one LSb in the final result. Table 18-4 shows the sequence of calculations which correspond to the six OR instructions. The final result of the computation is: Sign = 1 and Magnitude = 011000 or 12. To represent the true sign of the input voltage, you must invert the sign of the result from the DAC register. Therefore the result becomes Sign = 0, Magnitude = 12 which is (3.75 – 2.5)/32 * 12 + 2.5 = 2.96875. The error is 31.25 mV, or less that one LSb of 39 mV. Table 18-3. Example SAR Configuration Configuration Description Sign SAR6 – 2 block 1 DAC6, 1 COMP (can be CT) 0 SAR6 – 1 block 1 for both DAC6 and COMP 1 MS SAR10 –3 blocks 1 DAC9, 1 COMP (can be CT) (when processing MS DAC block) 0 LS SAR10 – 3 blocks 1 DAC9, 1 COMP (can be CT) (when processing LS DAC block) 1 Bits [6:4] SAR Count Value These three bits are used to initialize a 3-bit counter to sequence the 6 bits of the SAR algorithm. Typically, the user 398 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Interface Table 18-4. SAR Sequence Example Step Current ACap VIn VDac Comparator Bus (CMP) VSum New ACap Comment 1 100000 3.0 2.5 2.75 0 110000 Keep the sign bit and set bit 4. 2 110000 3.0 1.875 2.4375 1 101000 Overshoot, clear bit 4, set bit 3. 3 101000 3.0 2.1875 2.59375 0 101100 Keep bit 3, and set bit 2. 4 101100 3.0 2.03125 2.515625 0 101110 Keep bit 2, and set bit 1. 5 101110 3.0 1.953125 2.4765625 1 101101 Overshoot, clear bit 1, set bit 0. 6 101101 3.0 1.992188 2.496094 1 101100 Overshoot, clear bit 0 101100 3.0 2.03125 2.515625 0 101100 Final Result Notes 1. VSum is the voltage at the summing node, that is, the input to the comparator. 2. VDac is the voltage generated by the DAC block from the ACap value. 3. When VSum > AGND, CMP = 0; when VSum < AGND, CMP = 1. 4. CMP = 0 means keep the bit (undershoot); CMP = 1 means clear the bit (overshoot). 5. Start with Sign = 1 (configuration programming), equivalent to setting that bit to test. As shown in Table 18-4, the value of the result from Step 5, Magnitude = 13, is closer to the actual value of 12.8. This demonstrates that even though it is possible that the resulting code can be closer to the actual value, in the SAR algorithm there is no provision to detect this. The result is a maximum theoretical error of less than one LSb. Implementing Higher Resolution SARs It is straightforward to implement higher resolution SARs using the SAR hardware accelerator. For example, to create an 11-bit SAR, 3 blocks are allocated: 2 SC blocks to make a DAC9 and one SC or CT block for summing and compare. To get the results of the most significant (MS) block, which is the first 6 bits (Sign and 5 bits of Magnitude), the firmware sequencing will proceed exactly as in the previous SAR6 example. The trick with the least significant (LS) block of the DAC9 is to get the sign right. For the output to be correct, the sign of the LS block of a DAC9 should be opposite to that of the MS block (because it is connected through an inverting input to the MS block). There are two possible ways to handle this. 1. In firmware, one can manually compute what the sign bit should be from the result in the MS block and write it to the LS block. Then the SAR count value should be set to 5 instead of 6 to skip the sign bit check. 2. An interesting property of the SAR algorithm is that the resulting voltage at the summing node after the first 6 steps (MS block processing) is going to be the same polarity (above or below AGND) as the input voltage. The reason for this is that, by definition, if the polarity of the summing voltage is opposite to that of the input voltage, this triggers a Clear of the previous bit set. By defi- nition, the final result of the summing voltage is less than one LSb from AGND; therefore, clearing the LSb will result in a summing voltage of the same polarity as the input voltage. According to number 2 above, the sign bit of the LS block can be handled exactly as the sign bit of the MS block, just another OR instruction. This sequence is then appended on the above MS processing sequence (substituting the LS DAC block address for <LS_CR0>). Note that the meaning of the comparator is inverted by setting the SIGN bit in the ASYNC Control register. This is because the LS block is inverted with respect to the MS block. mov or or or or or or reg[ASY_CR], 68h // SAR count value=6, // Sign=1, Col=0 reg[<LS_CR0>], reg[<LS_CR0>], reg[<LS_CR0>], reg[<LS_CR0>], reg[<LS_CR0>], reg[<LS_CR0>], 18.2.1.3 0 0 0 0 0 0 // // // // // // Check Check Check Check Check Check sign, set bit 4 bit 4, set bit 3 bit 3, set bit 2 bit 2, set bit 1 bit 1, set bit 0 bit 0 SAR Timing Another important function of the SAR hardware is to synchronize the I/O read (the point at which the comparator value is used to make the SAR decision) to when the analog comparator bus is valid. Under normal conditions, this point is at the rising edge of PHI1 for the previous compute cycle. When the OR instruction is executed in the CPU, a few CPU clocks cycle into the instruction and an IOR signal is asserted to initiate a read of the DAC register. The SAR hardware then stalls the CPU clock, for one 24 MHz clock cycle after the rising edge of PHI1. When the stall is released, the I/O Read completes and is immediately followed by an I/O write. In this sequence of events, the DAC CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 399 Analog Interface register is written with the new value within a few CPU clocks after PHI1. positive edge of PHI1 to the start of the I/O write is 4.5 clocks, which at 24 MHz is 189 ns. If the analog clock is running at 1 MHz, this allows over 300 ns for the DAC output and comparator to settle. The rising edge of PHI1 is also the optimal time to write the DAC register for maximum settling time. The timing from the Figure 18-7. General SAR Timing Comparator is valid on PHI1 rising. SAR computation is done and IOR finishes. DAC output is valid at end of PHI2. Comparator is now valid for previous IOW, repeat process. PHI1 PHI2 ACMP IOR IOW STALL IOR causes STALL to assert, to wait for PHI1 rising. 18.3 New value is written to DAC register. Register Definitions The following registers are associated with the Analog Interface and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of analog interface registers, refer to the “Summary Table of the Analog Registers” on page 389. Depending on how many analog columns your PSoC device has (see the Cols. column in the register tables below), only certain bits are accessible to be read or written (refer to the table titled “PSoC Device Characteristics” on page 387). The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. 18.3.1 Address 0,62h CLK_CR3 Register Name Bit 7 Bit 6 Bit 5 CLK_CR3 Bit 4 Bit 3 Bit 2 Bit 1 SYSDIR[3:0] The Analog Clock Source Control Register 3 (CLK_CR3) is used to select the clock source for an individual analog column. Bit 0 Access RW : 00 Bits 3 to 0: SYSDIR[3:0] . When the corresponding bit is 1, then the associated ACC column's clock source is SYSCLK. Otherwise it follows the setting of the CLK_CR0 register. For additional information, refer to the CLK_CR3 register on page 147. 400 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Interface 18.3.2 Add. 0,64h CMP_CR0 Register Name CMP_CR0 Cols. 4 2 Bit 7 Bit 6 Bit 5 Bit 4 COMP[3:0] Bit 3 Bit 2 Bit 1 Bit 0 AINT[3:0] COMP[1:0] Access # : 00 AINT[1:0] #: Access is bit specific. Refer to the Register Details chapter on page 125. The Analog Comparator Bus Register 0 (CMP_CR0) is used to poll the analog column comparator bits and select column interrupts. This register contains two fields: COMP and AINT. By default, the interrupt is the comparator bit. A rising edge on a comparator bit causes an interrupt to be registered. However, if a bit in this field is set, the interrupt input for that column will be derived from the falling edge of PHI2 clock for that column (that is, the falling edge of PHI2 will leave a rising interrupt signal). Firmware can use this capability to synchronize to the current column clock. Bits 7 to 4: COMP[x]. These bits are the read only bits corresponding to the comparator bits in each analog column. They are synchronized to the column clock, and thus may be reliably polled by the CPU. Bits 3 to 0: AINT[x]. These bits select the interrupt source for each column, as the input to the interrupt controller. Note In PSoC devices with less than four columns, the comparator signal for each un-implemented column is tied to logic zero. For additional information, refer to the CMP_CR0 register on page 149. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 401 Analog Interface 18.3.3 ASY_CR Register Add. Name 0,65h ASY_CR Cols. Bit 7 4, 2 Bit 6 Bit 5 SARCNT[2:0] The Analog Synchronization Control Register (ASY_CR) is used to control SAR operation, except for bit 0, SYNCEN. SYNCEN is associated with analog register write stalling and is described in “Analog Synchronization Interface (Stalling)” on page 396. The SAR hardware accelerator is a block of specialized hardware designed to sequence the SAR algorithm for efficient analog-to-digital conversion. A SAR ADC is implemented conceptually with a DAC of the desired precision and a comparator. This functionality is configured from one or more PSoC blocks. For each conversion, the firmware should initialize the ASY_CR register and set the sign bit of the DAC as the first guess in the algorithm. A sequence of OR instructions (read, modify, write) to the ASxxxCR0 register is then executed. Each of these OR instructions causes the SAR hardware to read the current state of the comparator, checking the validity of the previous guess. It either clears it or leaves it set, accordingly. The next LSb in the DAC register is also set as the next guess. Six OR instructions will complete the conversion of a 6-bit DAC. The resulting DAC code, which matches the input voltage to within one LSb, is then read back from the ASxxxCR0 register. Bits 6 to 4: SARCNT[2:0]. These bits are the SAR count value and are used to initialize a three-bit counter to sequence the six bits of the SAR algorithm. Typically, the user initializes this register to ‘6’. When these bits are any value other than ‘0’, a register read command to an SC block is assumed to be part of a SAR sequence. Assuming the comparator bus output is programmed for column 0, a typical firmware sequence is as follows. mov or or or or or or reg[ASY_CR], 60h // // reg[ASC10CR0], 0 // reg[ASC10CR0], 0 // reg[ASC10CR0], 0 // reg[ASC10CR0], 0 // reg[ASC10CR0], 0 // reg[ASC10CR0], 0 // 402 SAR count value=6, Sign=0, Col=0 Check sign, set bit 4 Check bit 4, set bit 3 Check bit 3, set bit 2 Check bit 2, set bit 1 Check bit 1, set bit 0 Check bit 0 Bit 4 Bit 3 SARSIGN Bit 2 Bit 1 SARCOL[1:0] Bit 0 Access SYNCEN RW : 00 Bit 3: SARSIGN. This bit is the SAR sign selection and optionally inverts the comparator input to the SAR accelerator. It must be set based on the type of PSoC block configuration selected. Table 18-5 lists some typical examples. Table 18-5. Typical PSOC Block Configurations Configuration Description Sign SAR6 – 2 blocks 1 DAC6, 1 COMP (can be CT) 0 SAR6 – 1 block DAC6 and COMP in 1 block 1 MS SAR10 – 3 blocks 1 DAC9, 1 COMP (can be CT) (when processing MS DAC block) 0 Bits 2 and 1: SARCOL[1:0]. These bits are the column select for the SAR comparator input. The DAC portion of the SAR can reside in any of the appropriate positions in the analog PSOC block array. However, when the COMPARATOR block is positioned (and it is possible to have the DAC and COMPARATOR in the same block), this position should be the column selected. Bit 0: SYNCEN. This bit is to synchronize CPU data writes to Switched Capacitor (SC) block operation in the analog array. The SC block clock is selected in the CLK_CR0 register. The selected clock source is divided by four and the output is a pair of two-phase, non-overlapping clocks: PHI1 and PHI2. There is an optimal time, with respect to the PHI1 and PHI2 clocks, to change the capacitor configuration in the SC block, which is typically the rising edge of PHI1. This is normally the time when the input branch capacitor is charging. When this bit is set, any write to an SC block register is stalled until the rising edge of the next PHI1 clock phase, for the column associated with the SC block address. The stalling operation is implemented by suspending the CPU clock. No CPU activity occurs during the stall, including interrupt processing. Therefore, the effect of stalling on CPU throughput must be considered. For additional information, refer to the ASY_CR register on page 150. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Interface 18.3.4 Add. 0,66h CMP_CR1 Register Name CMP_CR1 Cols. 4 Bit 7 Bit 6 Bit 5 Bit 4 CLDIS[3] CLDIS[2] CLDIS[1] CLDIS[0] CLDIS[1] CLDIS[0] 2 The Analog Comparator Bus Register 1 (CMP_CR1) is used to override the analog column comparator synchronization. Bits 7 to 4: CLDIS[x]. When these bits are set, the given column is not synchronized to PHI2 in the analog interface. This capability is typically used to allow a continuous time comparator result to propagate directly to the interrupt controller during sleep. Because the master clocks (except the 32-kHz clock) are turned off during sleep, the synchronizer must be bypassed. 18.3.5 Add. 0,E6h Bit 3 Bit 2 Bit 1 Bit 0 CLK1X[1] CLK1X[0] Access RW : 00 Bits 1 and 0: CLK1X[1:0]. These bits are only used by the CY8C24x94 and CY7C64215 PSoC devices. When these bits are set for a given column, the analog comparator synchronization is implemented using the direct 1X column clock, rather than the divide by 4 PHI2 clock. This allows for high frequency comparator sampling. For additional information, refer to the CMP_CR1 register on page 151. DEC_CR0 Register Name DEC_CR0 Cols. 4, 2 Bit 7 Bit 6 Bit 5 ACC_IGEN[3:0] The Decimator Control Register 0 (DEC_CR0) contains control bits to access hardware support for both the Incremental ADC and the DELISG ADC. This register can only be used with four and two analog column PSoC devices. Bits 7 to 4: ACC_IGEN[3:0]. For incremental support, these bits select which column comparator bit will be gated by the output of a digital block. The output of that digital block is typically a PWM signal; the high time of which corresponds to the ADC conversion period. This ensures that the comparator output is only processed for the precise conversion time. The digital block selected for the gating function is controlled by ICLKS0 in this register, and ICLKS3, ICLKS2 and ICLKS1 bits in the DEC_CR1 register. Bit 3: ICLKS0. In conjunction with ICLKS1, ICLKS2, and ICLKS3 in the DEC_CR1 register, these bits select up to one of 16 digital blocks (depending on the PSoC device resources) to provide the gating signal for an incremental ADC conversion. Bit 4 Bit 3 ICLKS[0] Bit 2 Bit 1 ACE_IGEN[1:0] Bit 0 Access DCLKS0 RW : 00 Bits 2 and 1: ACE_IGEN[1:0]. For incremental support, these bits select which type E column comparator bit will be gated by the output of a digital block. The output of that digital block is typically a PWM signal, the high time of which corresponds to the ADC conversion period. This ensures that the comparator output is only processed for the precise conversion time. The digital block selected for the gating function is controlled by ICLKS[3:0] Bit 0: DCLKS0. The decimator requires a timer signal to sample the current decimator value to an output register that may subsequently be read by the CPU. This timer period is set to be a function of the DELSIG conversion time and may be selected from up to one of twelve digital blocks (depending on the PSoC device resources) with DCLKS0 in this register and DCLKS3, DCLKS2, and DCLKS1 in the DEC_CR1 register. If the Decimation Rate bits are set in DECx_CR this setting is overwritten For additional information, refer to the DEC_CR0 register on page 212. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 403 Analog Interface 18.3.6 Address 0,E7h DEC_CR1 Register Name Cols. DEC_CR1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 4 Bit 7 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 RW : 00 2 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 RW : 00 tor output to be sampled. However, when the IDEC bit is set, the negative edge of the selected digital block input causes the decimator value to be sampled. The Decimator Control Register 1 (DEC_CR1) is used to configure the decimator prior to using it. This register can only be used with four and two analog column PSoC devices. Bits 5 to 0: ICLKSx and DCLKSx. The ICLKS3, ICLKS2, ICLKS1, DCLKS3, DCLKS2, and DCLKS1 bits in this register select the digital block sources for Incremental and DELSIG ADC hardware support (see the DEC_CR0 register). Depending on how many analog columns your PSoC device has (see the Cols. column in the register table above), only certain bits are accessible to be read or written. For additional information, refer to the DEC_CR1 register on page 213. Bit 6: IDEC. Any function using the decimator requires a digital block timer to sample the current decimator value. Normally, the positive edge of this signal causes the decima- 18.3.7 Add. 1,60h CLK_CR0 Register Name CLK_CR0 Cols. 4 Bit 7 Bit 6 AColumn3[1:0] Bit 5 2 The Analog Clock Source Control Register 0 (CLK_CR0) is used to select the clock source for an individual analog column. An analog column clock generator is provided for each column. The bits in this register select the source for each column clock generator, depending on how many analog columns are supported in your PSoC device. Regardless of the source selected, the input clock is divided by four to generate the PHI1/PHI2 non-overlapping clocks for the column. There are four selections for each clock: VC1, VC2, ACLK0, and ACLK1. VC1 and VC2 are the programmable global system clocks. ACLK0 and ACLK1 sources are each selected from up to one of twelve digital block outputs (functioning as clock generators), for four and two analog column devices, and up to one of four digital block outputs (functioning as clock generators), for one analog column device as selected by CLK_CR1. 404 Bit 4 AColumn2[1:0] Bit 3 Bit 2 Bit 1 Bit 0 AColumn1[1:0] AColumn0[1:0] AColumn1[1:0] AColumn0[1:0] Access RW : 00 Bits 7 and 6: AColumn3[1:0]. These bits select the source for analog column 3. Bits 5 and 4: AColumn2[1:0]. These bits select the source for analog column 2. Bits 3 and 2: AColumn1[1:0]. These bits select the source for analog column 1. Bits 1 and 0: AColumn0[1:0]. These bits select the source for analog column 0. For additional information, refer to the CLK_CR0 register on page 236. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Interface 18.3.8 CLK_CR1 Register Add. Name 1,61h CLK_CR1 Cols. Bit 7 4, 2 Bit 6 Bit 5 SHDIS Bit 4 Bit 3 Bit 2 ACLK1[2:0] The Analog Clock Source Control Register 1 (CLK_CR1) is used to select the clock source for an individual analog column. This register can only be used with four and two column PSoC devices. Bit 6: SHDIS. The SHDIS bit functions as follows. During normal operation of an SC block, for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of PHI2. (During PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven.) This forms a sample and hold operation using the output bus and its associated capacitance. This design prevents the output bus from being perturbed by the intermediate states of the SC operation (often a reset state for PHI1 and settling to the valid state during PHI2). Bit 1 Bit 0 ACLK0[2:0] Access RW : 00 The following are the exceptions: 1) If the ClockPhase bit in ASCxx_CR0 (for the SC block in question) is set to ‘1’, then the output is enabled if the analog bus output is enabled during both PHI1 and PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Source Control register, then sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their respective output buses, for the entire period of their respective PHI2s. Bits 5 to 0: ACLKx[2:0]. There are two 3-bit fields in this register that can select up to one of twelve digital blocks (depending on the PSoC device resources), to function as the clock source for ACLK0 and ACLK1. ACLK0 and ACLK1 are alternative clock inputs to the analog column clock generators (see the CLK_CR0 register above). For additional information, refer to the CLK_CR1 register on page 237. 18.3.9 Add. 1,63h AMD_CR0 Register Name AMD_CR0 Cols. 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 AMOD2[2:0] 2 The Analog Modulation Control Register 0 (AMD_CR0) is used to select the modulator bits used with each column. This register can only be used with four and two column PSoC devices. The MODBIT is an input into an Switched Capacitor C Type block only and is XORed with the currently programmed value of the ASIGN bit in the CR0 register for that SC block. This allows the ACAP sign bit to be dynamically modulated by hardware signals. Three bits for each column allow a one of eight selection for the MODBIT. Sources include any of the analog column comparator buses, two global buses, and Bit 1 AMOD0[2:0] AMOD0[2:0] Bit 0 Access RW : 00 one broadcast bus. The default for this function is zero or off. Bits 6 to 4: AMOD2[2:0]. These bits control the selection of the MODBITs for analog column 2. Bits 2 to 0: AMOD0[2:0]. These bits control the selection of the MODBITs for analog column 0. For additional information, refer to the AMD_CR0 register on page 239. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 405 Analog Interface 18.3.10 Address 1,64h CMP_GO_EN Register Name CMP_GO_EN Bit 7 Bit 6 GOO5 GOO1 Bit 5 Bit 4 SEL1[1:0] The Comparator Bus to Global Outputs Enable Register (CMP_GO_EN) controls options for driving the analog comparator bus and column clock to the global bus. Bit 0 SEL0[1:0] Access RW : 00 Bits 1 and 0: SEL0[1:0]. These bits select the column 0 signal to output. For additional information, refer to the CMP_GO_EN register on page 240. Bits 5 and 4: SEL1[1:0]. These bits select the column 1 signal to output. Address Bit 1 Bit 2: GOO0. This bit drives the selected column 0 signal to GOO0. Bit 6: GOO1. This bit drives the selected column 1 signal to GOO1. 1,65h Bit 2 GOO0 Bit 3: GOO4. This bit drives the selected column 0 signal to GOO4. Bit 7: GOO5. This bit drives the selected column 1 signal to GOO5. 18.3.11 Bit 3 GOO4 CMP_GO_EN1 Register Name Bit 7 Bit 6 CMP_GO_EN1 GOO7 GOO3 Bit 5 Bit 4 SEL3[1:0] The Comparator Bus to Global Outputs Enable Register 1 (CMP_GO_EN1) controls options for driving the analog comparator bus and column clock to the global bus. This register is only used by the CY8C28x43, CY8C28x45, and CY8C28x52 PSoC devices. Bit 7: GOO7. This bit drives the selected column 3 signal to GOO7. Bit 6: GOO3. This bit drives the selected column 3 signal to GOO3. Bit 3 Bit 2 GOO6 GOO2 Bit 1 Bit 0 SEL2[1:0] Access RW : 00 Bits 5 and 4: SEL3[1:0]. These bits select the column 3 signal to output. Bit 3: GOO6. This bit drives the selected column 2 signal to GOO6. Bit 2: GOO2. This bit drives the selected column 2 signal to GOO2. Bits 1 and 0: SEL2[1:0]. These bits select the column 2 signal to output. For additional information, refer to the CMP_GO_EN1 register on page 241. 406 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Interface 18.3.12 Add. 1,66h AMD_CR1 Register Name AMD_CR1 Cols. Bit 7 Bit 6 Bit 5 Bit 2 Bit 1 Bit 0 AMOD1[2:0] The MODBIT is an input into an Switched Capacitor Type C block only and is XORed with the currently programmed value of the ASIGN bit in the CR0 register for that SC block. This allows the ACAP sign bit to be dynamically modulated by hardware signals. Three bits for each column allow a one of eight selection for the MODBIT. Sources include any of the analog column comparator buses, two global buses, and Access RW : 00 AMOD1[2:0] This register can only be used with four and two column PSoC devices. one broadcast bus. The default for this function is zero or off. Bits 6 to 4: AMOD3[2:0]. These bits control the selection of the MODBITs for analog column 3. Bits 2 to 0: AMOD1[2:0]. These bits control the selection of the MODBITs for analog column 1. For additional information, refer to the AMD_CR1 register on page 242. ALT_CR0 Register Add. Name 1,67h ALT_CR0 Cols. Bit 7 4, 2 Bit 6 Bit 5 Bit 4 Bit 3 LUT1[3:0] The Analog LUT Control Register 0 (ALT_CR0) is used to select the logic function. A one of 16 look-up table (LUT) is applied to the outputs of each column comparator bit and optionally a neighbor bit to implement two input logic functions. Table 18-1 shows the available functions, where the A input applies to the selected column and the B input applies to the next most significant neighbor column. Column 0 settings apply to combinations of column 0 and column 1. Column 1 settings apply to combinations of column 1 and column 2, where B=0 for one column PSoC devices. 18.3.14 Bit 3 2 The Analog Modulation Control Register 1 (AMD_CR1) is used to select the modulator bits used with each column. 18.3.13 Bit 4 AMOD3[2:0] 4 Bit 2 Bit 1 Bit 0 LUT0[3:0] Access RW : 00 Bits 7 to 4: LUT1[3:0]. These bits control the selection of the LUT 1 logic functions that may be selected for the analog comparator bits in column 0 (for two and four column PSoC devices only) and column 1. Bits 3 to 0: LUT0[3:0]. These bits control the selection of LUT 0 logic functions that may be selected for the analog comparator bits in column 0 (for two and four column PSoC devices only) and column 1. For additional information, refer to the ALT_CR0 register on page 243. ALT_CR1 Register Add. Name 1,68h ALT_CR1 Cols. 4 Bit 7 Bit 6 Bit 5 LUT3[3:0] Bit 4 Bit 3 Bit 2 Bit 1 LUT2[3:0] Bit 0 Access RW : 00 The Analog LUT Control Register 1 (ALT_CR1) is used to select the logic function performed by the LUT for each analog column. Bits 3 to 0: LUT2[3:0]. These bits control the selection of LUT 2 logic functions that may be selected for the analog comparator bits. This register can only be used with four column PSoC devices. For additional information, refer to the ALT_CR1 register on page 244. Bits 7 to 4: LUT3[3:0]. These bits control the selection of the LUT 3 logic functions that may be selected for the analog comparator bits. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 407 Analog Interface 18.3.15 CLK_CR2 Register Add. Name 1,69h CLK_CR2 Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ACLK1R 4 The Analog Clock Source Control Register 2 (CLK_CR2), in conjunction with the CLK_CR1 and CLK_CR0 registers, selects a digital block as a source for analog column clocking. This register can only be used with four column PSoC devices. Bit 2 Bit 1 Bit 0 Access ACLK0R RW : 00 Bit 0: ACLK0R. This bit selects bank zero of eight digital blocks and is only used in devices with more than eight digital blocks. For additional information, refer to the CLK_CR2 register on page 245. Bit 3: ACLK1R. This bit selects bank one of eight digital blocks and is only used in devices with more than eight digital blocks. 408 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 19. Analog Array This chapter presents the Analog Array, which has no registers directly associated with it. This chapter is important because it discusses the block and column level interconnects that exist in the analog PSoC® array. 19.1 Architectural Description The analog array is designed to allow interaction between PSoC devices without modifying projects, except for resource limitations. Refer to the table at the beginning of the Analog System section, on page 383, to determine how many columns of analog PSoC blocks a particular PSoC device has. The figures that follow illustrate the analog multiplexer (mux) connections for the various PSoC devices, which vary depending on column availability. Figure 19-1 displays the various analog arrays, depending on the column configuration of the PSoC device. Each analog column has 3 analog blocks associated with it. In the figures throughout this chapter, shading and call outs portray the different column configurations that are available in a PSoC device. Note The CY8C28x03 and CY8C28x13 devices do not have the analog array discussed in this section. CY8C28x13, CY8C28x33, CY8C28x45, and CY8C28x52 have an array of type E limited analog blocks in addition to the array of blocks discussed in this section. See Two Column Limited Analog System chapter on page 441 for details. Figure 19-1. Array of Analog PSoC Blocks 4 Column PSoC 2 Column PSoC Analog Column 0 Analog Column 1 Analog Column 2 Analog Column 3 ACC00 ACC01 ACC02 ACC03 ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD22 ASC23 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 409 Analog Array 19.1.1 NMux Connections The NMux is an 8-to-1 mux which determines the source for the inverting (also called negative) input of Continuous Time PSoC blocks. These blocks are named ACC00, ACC01, ACC02, and ACC03. More details on the Continuous Time PSoC blocks are available in the chapter Continuous Time PSoC® Block, on page 425. The NMux connections are described in detail in the ACCxxCR1 register on page 159, bits NMux[2:0]. The numbers in Figure 19-2, which are associated with each arrow, are the corresponding NMux select line values for the data in the NMux portion of the register. The call out names in the figure show nets selected for each NMux value. For one column PSoC devices, the figure view is expanded in a circular area to the left of the main diagram, where black call outs and arrows signify exclusive one column functionality and gray call outs and arrows signify commonality with four and two column PSoC devices. Figure 19-2. NMux Connections Port Inputs REFLO (2) REFHI (7) (4) Port Inputs Port Inputs (3) ACC00 REFH I (3) (0) REFLO (7) (4) (2) REFLO (2) ACC01 REFHI (7) (4) (1) LEGEND: 410 (6) REFHI (3) (0) (7) (4) REFLO (2) ACC03 (0) (6) (1) (1) (6) (1) (6) (5) (5) ASD11 ASC12 ASD13 ASC21 ASD22 ASC23 (5) (5) ASC10 ASD20 Two Column Array (3) ACC02 (0) AGND Port Inputs AGND AGND AGND Four Column Array CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Array 19.1.2 PMux Connections The PMux is an 8-to-1 mux which determines the source for the non-inverting (also called positive) input of Continuous Time PSoC blocks. These blocks are named ACC00, ACC01, ACC02, and ACC03. More details on the Continuous Time PSoC blocks are available in the chapter Continuous Time PSoC® Block, on page 425. The PMux connections are described in detail in the ACCxxCR1 register on page 159, bits PMux[2:0]. The numbers in Figure 19-3, which are associated with each arrow, are the corresponding PMux select line values for the data in the PMux portion of the register. The call out names in the figure show nets selected for each PMux value. For one column PSoC devices, the figure view is expanded in a circular area to the left of the main diagram, where black call outs and arrows signify exclusive one column functionality, and gray call outs and arrows signify commonality with four and two column PSoC devices. Figure 19-3. PMux Connections Port Inputs Port Inputs ABUS 0 (1) REFLO (0) (7) (3) ACC00 (2) (2) (7) (3) (5) (3) AGN D (1) (6) ACC01 (5) Port Inputs ABUS 1 (0) (7) (3) (3) (4) (4) ASC10 ASD11 ACC02 (1) (6) (2) (6) (0) (2) (7) (3) (5) (3) AGN D ABUS 3 ABUS 2 (1) (6) (0) (0) Port Inputs REFLO ACC03 (3) (5) (4) (4) ASC12 ASD13 ASD22 ASC23 AGN D Vss for 2 Column Arrays ASD20 LEGEND: Two Column Array ASC21 Four Column Array CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 411 Analog Array 19.1.3 RBotMux Connections The RBotMux connections in Figure 19-4 are the mux inputs for the bottom of the resistor string, see Figure 22-1 on page 426. The RBotMux connections are used in the Continuous Time PSoC blocks. These blocks are named ACC00, ACC01, ACC02, and ACC03. The RBotMux connections are described in detail in the ACCxxCR0 register on page 157, bits RBotMux[1:0]. The numbers in Figure 19-4, which are associated with each arrow, are the corresponding RBotMux select line values for the data in the RBotMux portion of the register. The call out names in the figure show nets selected for each RBotMux value. The logic statements in Figure 19-4 are the RBotMux connections that are selected by the combination of the RBot- Mux bits (ACC0xCR0 bits 1 and 0) and the INSAMP bit (ACC0xCR3 bit 1). For example, the RBotMux selects a connection to AGND, if the INSAMP bit is low and the RBotMux bits are 01b. This is shown in the figure as the logic statement INSAMP RB = 1 . For one column PSoC devices, the figure view is expanded in a circular area to the left of the main diagram, where black call outs and arrows signify exclusive one column functionality, and gray call outs and arrows signify commonality with four and two column PSoC devices. Note The RBotMux connections are not available to the CY8C28x03 and CY8C28x13 PSoC devices. Figure 19-4. RBotMux Connections VS S INSAMP (RB=0) INSAMP (RB=2) VS S S INSAMP (RB=2) ACC00 INSAMP INSAMP INSAMP (RB=3) INSAMP (RB=3) ACC02 412 VS S INSAMP (RB=2) INSAMP INSAMP ACC03 INSAMP (RB=1) INSAMP (RB=1) AGND AGND AGND LEGEND: INSAMP (RB=0) INSAMP (RB=2) ACC01 INSAMP (RB=1) INSAMP (RB=1) AGND VS INSAMP (RB=3) INSAMP (RB=3) ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD22 ASC23 Two Column Array Four Column Array CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Array 19.1.4 AMux Connections The AMux connections in Figure 19-5 are the mux inputs for controlling both the A and C capacitor branches. The high order bit, ACMux[2], selects one of two inputs for the C branch, which is used to control both the AMux and CMux. (See the A inputs in Figure 23-1 on page 432 and Figure 23-2 on page 433.) The AMux connections are used in the Switched Capacitor PSoC blocks. These blocks are named ASC10, ASD11, ASC12, ASD13, ASD20, ASC21, ASD22, and ASC23. The AMux connections are described in detail in the ASCxxCR1 register on page 162, bits ACMux[2:0], and ASDxxCR1 register on page 166, bits AMux[2:0]. The numbers in Figure 19-5, which are associated with each arrow, are the corresponding AMux select line values for the data in the ACMux portion of the register. The call out names in the figure show nets selected for each AMux value. For one column PSoC devices, the figure view is expanded in a circular area to the left of the main diagram, where black call outs and arrows signify exclusive one column functionality, and gray call outs and arrows signify commonality with four and two column PSoC devices. Note The AMux connections are not available to the CY8C28x03 and CY8C28x13 PSoC devices. Figure 19-5. AMux Connections ACC00 ACC01 (4 ) (3) REFHI ) (2 (4 ) (0) (4 ) (4 ) ASC21 (4 ) ) (5 ) (2 (1,5) ASD22 REFHI (7) ASC23 (2) (1) (2) P2.2 (2) (7) ASD20 ASD13 (7) ) (2 (1,5) (1) P2.1 (0) ) (5 (1) (1,6) ASC12 (4 ) (3) (0) (2) ) (2 (1) ASD11 (0) ASC10 P2.1 (3) (1) (1,6) ) (4 (0) P2.2 (3) ) ( 0,5 ) (4 ACC03 (5 ) (0) ( 0,5 ) (5 ) (7) REFHI ACC02 P2.2 (1) ABUS(0) LEGEND: ABUS(1) Two Column Array VTemp ABUS(2) (3,6) (3) (3) (3) (6) P2.2 ABUS(3) Four Column Array CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 413 Analog Array 19.1.5 CMux Connections The CMux connections in Figure 19-6 are the mux inputs for controlling the C capacitor branches. The high order bit, ACMux[2], selects one of two inputs for the C branch, which is used to control both the AMux and CMux. (See the C inputs in Figure 23-1 on page 432.) The CMux connections are used in the Switched Capacitor PSoC blocks. These blocks are named ASC10, ASC21, ASC12, and ASC23. The CMux connections are described in detail in the ASCxxCR1 register on page 162, bits ACMux[2:0]. The numbers in the figure, which are associated with each arrow, are the corresponding CMux select line values for the data in the CMux portion of the register. The call out names in the figure show nets selected for each CMux value. Note The CMux connections are not available to the CY8C28x03 and CY8C28x13 PSoC devices. Figure 19-6. CMux Connections ACC01 ACC02 ASD11 ASC12 ASD20 LEGEND: 414 ASC21 Two Column Array ASD22 ASD13 (0-7) (4-7) (0-7) (4-7) ASC10 ACC03 (0-3) (0-3) ACC00 ASC23 Four Column Array CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Array 19.1.6 BMux SC/SD Connections The BMux SC/SD connections in Figure 19-7 are the mux inputs for controlling the B capacitor branches. (See Figure 23-1 on page 432 and Figure 23-2 on page 433.) The BMux SC/SD connections are used in the Switched Capacitor PSoC blocks. These blocks are named ASC10, ASD11, ASC12, ASD13, ASD20, ASC21, ASD22, and ASC23. The BMux connections are described in detail in the ASCxxCR3 register on page 164, bits BMuxSC[1:0], and ASDxxCR3 register on page 168, bit BMuxSD[2]. The numbers in Figure 19-7, which are associated with each arrow, are the corresponding BMux select line values for the data in the BMux portion of the register. The call out names in the figure show nets selected for each BMux value. For one column PSoC devices, the figure view is expanded in a circular area to the left of the main diagram, where black call outs and arrows signify exclusive one column functionality, and gray call outs and arrows signify commonality with four and two column PSoC devices. Note The BMux SC/SD connections are not available to the CY8C28x03 and CY8C28x13 PSoC devices. Figure 19-7. BMux SC/SD Connections ACC00 ACC01 ACC02 ACC03 (0 ) (1) (2) ASC10 ASD11 (1) ASC12 ASD13 ) (0 (1) ASD20 (1) (2) ASC21 (0) (3) (0) (3) (1) ) (0 (1) (2) P2.3 (1) (0) (1) (0) (0 ) ASD22 (2) ASC23 (3) (3) P2.0 TRefGND LEGEND: Two Column Array ABUS3 Four Column Array CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 415 Analog Array 19.1.7 Analog Comparator Bus Each analog column has a dedicated comparator bus associated with it. Every analog PSoC block has a comparator output that can drive out on this bus. However, the comparator output from only one analog block in a column can be actively driving the comparator bus for that column at any one time. Refer to the “Analog Comparator Bus Interface” on page 394 in the Analog Interface chapter for more information. Refer to the “Analog Comparator Bus Interface” on page 442 for information on the Type E analog comparator buses in the CY8C28x13, CY8C28x33, CY8C28x45, and CY8C28x52 devices. 19.2 Temperature Sensing Capability A temperature-sensitive voltage, derived from the bandgap sensing on the die, is buffered and available as an analog input into the Analog Switch Cap Type C block ASC21. Temperature sensing allows protection of device operating ranges for fail-safe applications. Temperature sensing, combined with a long sleep timer interval (to allow the die to approximate ambient temperature), can give an approximate ambient temperature for data acquisition and battery charging applications. The user may also calibrate the internal temperature rise based on a known current consumption. The temperature sensor input to the ASC21 block is labeled VTemp and its associated ground reference is labeled TRefGND. 416 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 20. Analog Input Configuration This chapter discusses the Analog Input Configuration and its associated registers. For a complete table of analog input configuration registers, refer to the “Summary Table of the Analog Registers” on page 389. For a quick reference of all PSoC® registers in address order, refer to the Register Details chapter on page 125. 20.1 Architectural Description Depending on which PSoC device you have (2 column or 4 column), you will use one of the three analog input configuration and arrays as illustrated with three different shaded areas in Figure 20-1. Note that the CY8C28x13 PSoC device has two column limited functionality and no output drivers. Figure 20-1. Analog Input Configuration Column Overview Array Input Configuration Figure 20-2 presents a view of each analog column configuration, along with their analog driver and pin specifics. The input multiplexer (mux) maps device inputs (package pins) to analog array columns, based on bit values in the AMX_IN and ABF_CR0 registers. Edge columns, in the four column configuration, are fed by one of two 4-to-1 muxes; inner columns are fed by one of two 4-to-1 muxes. The muxes are CMOS switches with typical resistances in the range of 2K ohms. Refer to the analog block diagrams, on the following pages, to view the various analog input configurations. For a four analog column device, the PSoC device has four analog drivers used to output analog values on port pins P0[5], P0[3], P0[4], and P0[2]. For a two analog column device, the PSoC device has two analog drivers used to output analog values on port pins P0[5] and P0[3]. For a one analog column device, the PSoC device has one analog driver used to output analog values on port pin P0[5]. Also in the figures that follow, depending on the pin configuration of your PSoC device, various shades of gray boxes are displayed denoting which port pins are associated with which pin parts. ACI0[1:0] ACOL0MUX ACI1[1:0] ACI2[1:0] ACOL1MUX ACI3[1:0] ACOL2MUX ACOL3MUX Array ACC00 ACC01 ACC02 ACC03 ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD22 ASC23 2 Column PSoC Device CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 4 Column PSoC Device 417 Analog Input Configuration 20.1.1 Six Column Analog Input Configuration The six column analog input configuration is detailed in Figure 20-2, along with the analog driver and pin specifics. Figure 20-2. Six Column PSoC Analog Pin Block Diagram P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] 20 Pin Part P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[5] 28 Pin Part RefIn P2[6] AGNDIn P2[4] P2[3] P2[2] P2[1] P2[0] P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] P4[7] P4[6] P4[5] P4[4] 44 Pin Part P4[3] P4[2] P4[1] P4[0] P5[3] P5[2] 48/56 Pin Part P5[1] P5[0] Array Input Configuration ACI0[1:0] ACOL0MUX ACI1[1:0] ACI2[1:0] ACOL1MUX ACI3[1:0] ACOL2MUX ABusMux0 ABusMux1 ACI6[1:0] ACOL3MUX ACE0Mux ACI7[1:0] ACE1Mux ABusMux2 ABusMux3 Array SplitMux Bit ACC00 ACC01 ACC02 ACC03 ACE00 ACE01 ASC10 ASD11 ASC12 ASD13 ASE10 ASE11 ASD20 ASC21 ASD22 ASC23 Interface to Digital System Vdd Vss AGND=VBG Additional Type E Columns Reference Generators Bandgap Microcontroller Interface (Address Bus, Data Bus, Etc.) 418 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Input Configuration 20.2 Register Definitions The following registers are associated with Analog Input Configuration and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of the analog input configuration registers, refer to the “Summary Table of the Analog Registers” on page 389. Depending on how many analog columns your PSoC device has (see the Cols. column in the register tables below), only certain bits are accessible to be read or written. The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. Note For the CY8C28x13, CY8C28x33, CY8C28x43, CY8C28x45, and CY8C28x52 PSoC devices, refer to the I/O Analog Multiplexer chapter on page 525 for information on bringing that device’s analog mux bus into the analog array. 20.2.1 Add. 0,60h AMX_IN Register Name Cols. AMX_IN 4 Bit 7 Bit 6 ACI3[1:0] Bit 5 Bit 4 ACI2[1:0] 2 The Analog Input Select Register (AMX_IN) controls the analog muxes that feed signals in from port pins into the analog column. This register can only be used with four and two column PSoC devices. Bits 7 to 0: ACIx[1:0]. For four column PSoC devices, each of the analog columns can have up to four port bits connected to its muxed input. There are up to four additional analog inputs that go directly into the Switch Capacitor PSoC blocks. Bit 3 Bit 2 Bit 1 Bit 0 ACI1[1:0] ACI0[1:0] ACI1[1:0] ACI0[1:0] Access RW : 00 For two column PSoC devices, the ACI1[1:0] and ACI0[1:0] bits control the analog muxes that feed signals in from port pins into the analog column. The analog column can have up to eight port bits connected to its muxed input. ACI1 and ACI0 are used to select among even and odd pins. The AC1Mux bit field controls the bits for those muxes and is located in the Analog Output Buffer Control register (ABF_CR0). There are up to two additional analog inputs that go directly into the Switch Capacitor PSoC blocks. For additional information, refer to the AMX_IN register on page 145. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 419 Analog Input Configuration 20.2.2 Add. 1,62h ABF_CR0 Register Name Cols. ABF_CR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 ACol1Mux ACol2Mux ABUF1EN ABUF2EN ABUF0EN ABUF3EN Bypass PWR 2 ACol1Mux Bypass PWR ABUF1EN ABUF0EN The Analog Output Buffer Control Register 0 (ABF_CR0) controls analog input muxes from Port 0 and the output buffer amplifiers that drive column outputs to device pins. Bit 1: Bypass. Bypass mode connects the analog output driver input directly to the output. When this bit is set, all analog output drivers will be in bypass mode. This is a high impedance connection used primarily for measurement and calibration of internal references. Use of this feature is not recommended for customer designs. Bit 7: ACol1MUX. A mux selects the output of column 0 input mux or column 1 input mux. When set, this bit sets the column 1 input to column 0 input mux output. Bit 0: PWR. This bit is used to set the power level of the analog output drivers. When this bit is set, all of the analog output drivers will be in a High Power mode. Bit 6: ACol2MUX. A mux selects the output of column 2 input mux or column 3 input mux. When set, this bit sets the column 2 input to column 3 input mux output. Address 1,6Ah For additional information, refer to the ABF_CR0 register on page 238. AMUX_CFG1 Register Name AMUX_CFG1 Bit 7 Bit 6 Bit 5 Bit 4 ABusMux3 ABusMux2 ACol3Mux ACol0Mux Bit 7: ABusMux3. 0: Select analog column 3 input to analog column 3 mux output. (Selects among P0[6,4,2,0].) 1: Select analog column 3 input to the analog mux bus right. Bit 6: ABusMux2. 0: Select analog column 2 input to analog column 2 mux output. (Selects among P0[7,5,3,1].) 1: Select analog column 2 input to the analog mux bus left. Bit 5: ACol3Mux. 0: Select analog column 3 input to analog column 3 input mux output. (Selects among P0[6,4,2,0].) 1: Select analog column 3 input to analog column 2 input mux output. (Selects among P0[7,5,3,1].) Bit 4: ACol0Mux. 0: Select analog column 0 input to analog column 0 input mux output. (Selects among P0[7,5,3,1].) 1: Select analog column 0 input to analog column 1 input mux output. (Selects among P0[6,4,2,0].) 420 RW : 00 Bits 5 to 2: ABUFxEN. These bits enable or disable the column output amplifiers. Depending on the number of analog columns your PSoC device has, bits 6, 4, 3, and 2 may be reserved. Refer to the table titled “PSoC Device Distinctions” on page 25. 20.2.3 Access Bit 3 Bit 2 MUXCLK1[2:0] Bit 1 Bit 0 Access EN1 RW : 0 Bits 3 to 1: MUXCLK1[2:0]. Selects a precharge clock source for analog mux bus right connections: 000b Precharge clock is off; no switching. 001b VC1 010b VC2 011b Row1 Broadcast 100b Analog column clock 0 101b Analog column clock 1 110b Analog column clock 2 111b Analog column clock 3 Bit 0: EN1. 0: Disable MUXCLK Right output. 1: Enable MUXCLK Right output. For additional information, refer to the AMUX_CFG1 register on page 246. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 21. Analog Reference This chapter discusses the Analog Reference generator and its associated register. The reference generator establishes a set of three internally fixed reference voltages for AGND, RefHi, and RefLo. For PSoC® devices with one analog column, a fixed analog ground (AGND) of Vdd/2 is supplied. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 21.1 Architectural Description The PSoC device is a single supply part, with no negative voltage available or applicable. Depending on the number of analog columns in your PSoC device (refer to the table titled “PSoC Device Characteristics” on page 387), Figure 21-1 shows the analog reference control schematic. The reference array supplies voltage to all blocks and current to the Switched Capacitor blocks. At higher block clock rates, there is increased reference current demand; the reference power should be set equal to the highest power level of the analog blocks used. Analog ground (AGND) is constructed near mid-supply. This ground is routed to all analog blocks and separately buffered within each block. Note that there may be a small offset voltage between buffered analog grounds. RefHi and RefLo signals are generated, buffered, and routed to the analog blocks. RefHi and RefLo are used to set the conversion range (that is, span) of analog-to-digital (ADC) and digitalto-analog (DAC) converters. RefHi and RefLo can also be used to set thresholds in comparators for four and two column PSoC devices. Figure 21-1. Analog Reference Structure RefHi VRefHi AGND VAGND VRefLo Vss RefLo Figure 21-2. Analog Reference Control Schematic 4 and 2 Analog Columns 1 Analog Column Vdd Vbandgap P2[4] Vdd/2 x1 x1.6 x2 Vdd RefHi to Analog Blocks RefHi to Analog Blocks R 8.1K 0.4K AGND R AGND (Vdd/2) P2[4] (External Cap) Vbandgap x1 RefLo to Analog Blocks P2[6] RefLo to Analog Blocks Vss Vss CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 421 Analog Reference 21.2 Register Definitions The following register is associated with the Analog Reference. For a complete table of all analog registers, refer to the “Summary Table of the Analog Registers” on page 389. The register description below has an associated register table showing the bit structure. Depending on how many analog columns your PSoC device has (see the Cols. column in the register tables below), only certain bits are accessible to be read or written. The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register description that follows. Reserved bits should always be written with a value of ‘0’. 21.2.1 ARF_CR Register Add. Name 0,63h ARF_CR Cols. 4, 2 Bit 7 Bit 6 Bit 5 HBE The Analog Reference Control Register (ARF_CR) is used to configure various features of the configurable analog references. This register can only be used with four and two column PSoC devices. Note The external bypass capacitor bit 6 (AGNDBYP) in the Bandgap Trim register (BDG_TR: 1, EAh) controls the external bypass capacitor. The default value is zero, which disables this function (see Figure 21-2). The figure shows the two switches in the AGND path in their default state. If bit 6 is set, then the P2[4] I/O should be tri-stated and an external capacitor connect from P2[4] to Vss. Bit 6: HBE. This bit controls the bias level for all the opamps. It operates with the power setting in each block, to set the parameters of that block. Most applications will benefit from the low bias level. At high bias, the analog block opamps have a faster slew rate, but slightly less voltage swing and higher power. Bit 4 Bit 3 Alternatively, the power supply can be scaled to provide analog ground and references; this is particularly useful for 422 Bit 1 Bit 0 Access PWR[2:0] RW : 00 signals which are ratiometric to the power supply voltage. See Table 21-2. User supplied external precision references can be connected to Port 2 inputs (available on 28 pin and larger parts). This is useful in setting reference for specific customer applications, such as a ±1.00 V (from AGND) ADC scale. References derived from Port 2 inputs are limited to the same output voltage range as the opamps in the analog blocks. Note that only the 010b setting for REF[2:0] is valid in the one column PSoC device. This sets AGND = Vdd/2, RefHi = Vdd, and RefLo = Vss. Bits 2 to 0: PWR[2:0]. PWR controls the bias current and bandwidth for all of the opamps in the analog reference block. PWR also provides on/off control in various rows of the analog array. Table 21-1. Analog Array Power Control Bits PWR[2:0] 000b Bits 5 to 3: REF[2:0]. REF (AGND, RefHI, and RefLO) sets the analog array reference control, selecting specific combinations of voltage for analog ground and references. Many of these reference voltages are based on the precision internal reference, a silicon bandgap operating at 1.30 volts. This reference has good thermal stability and power supply rejection. Bit 2 REF[2:0] CT Row Off Both SC Rows Off REF Bias Off 001b On Off Low 010b On Off Medium 011b On Off High 100b Off Off Off 101b On On Low 110b On On Medium 111b On On High For additional information, refer to the ARF_CR register on page 148. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Analog Reference Table 21-2. REF[2:0]: AGND, RefHI, and RefLO Operating Parameters for 4 and 2 Column PSoC Devices REF [2:0] AGND Source Voltage RefHI Source Voltage RefLO Source Voltage 000b Vdd/2 2.5 V 1.65 V Vdd/2 + Vbg 3.8 V 2.95 V Vdd/2 – Vbg 1.2 V 0.35 V 5.0 V System 3.3 V System 001b P2[4] 2.2 V P2[4] + P2[6] 3.2 V P2[4] – P2[6] 1.2 V User Adjustable. Example: P2[4] = 2.2 V and P2[6] = 1.0 V 010b Vdd/2 2.5 V 1.65 V Vdd 5.0 V 3.3 V Vss 0.0 V 0.0 V 5.0 V System 3.3 V System 011b 2 × Vbg 2.6 V 3 × Vbg 3.9 V 1 × Vbg 1.3 V Not for 3.3 V Systems 100b 2 × Vbg 2.6 V 2 × Vbg + P2[6] 3.6 V 2 × Vbg – P2[6] 1.6 V P2[6] < Vdd – 2.6 V. Example: P2[6] = 1.0 V 101b P2[4] 2.2 V P2[4] + Vbg 3.5 V P2[4] – Vbg 0V User Adjustable. Example: P2[4] = 2.2 V. 1.3 < P2[4] < Vdd – 1.3 110b Vbg 1.30 V 2 × Vbg 2.6 V Vss 0 5.0 V System 3.3 V System 111b 1.6 × Vbg 2.08 V 3.2 × Vbg 4.16 V Vss 0 Not for 3.3 V Systems Notes CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 423 Analog Reference 424 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 22. Continuous Time PSoC® Block This chapter discusses the Analog Continuous Time PSoC® Block and its associated registers. This block supports programmable gain or attenuation opamp circuits; instrumentation amplifiers, using two CT blocks (differential gain); and modest response-time analog comparators. For a complete table of the Continuous Time PSoC Block registers, refer to the “Summary Table of the Analog Registers” on page 389. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 22.1 Architectural Description The Analog Continuous Time blocks are built around a railto-rail input and output, low offset, low noise opamp. There are several analog multiplexers (muxes) controlled by register bit settings in the control registers that determine the signal topology inside the block. There is also a precision resistor string located in the feedback path of the opamp which is controlled by register bit settings. The block also contains a low power comparator, connected to the same inputs and outputs as the main amplifier. This comparator is useful for providing a digital compare output in low power sleep modes, when the main amplifier is powered off. There are three discrete outputs from this block. These outputs connect to the following buses: 1. The analog output bus (ABUS), which is an analog bus resource shared by all of the analog blocks in the analog column. This signal may also be routed externally through an output buffer. 2. The comparator bus (CBUS), which is a digital bus resource shared by all of the analog blocks in the analog column. 3. The local output buses (OUT, GOUT, and LOUT), which are routed to neighboring blocks. GOUT and LOUT refer to the gain/loss mode configuration of the block and connect to GIN/LIN inputs of neighboring blocks. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 425 Continuous Time PSoC® Block Figure 22-1. Analog Continuous Time Block Diagram TestMux LPCMPEN RefHi RefLo AGND + Gain ABUS PMuxOut AnalogBus CompCap OUT PWR CBUS Latch Block Inputs Port Input CBUS Driver Transparent, PHI1 or PHI2 ABUS GOUT AGND Vdd PMux NMux RefHi RTopMux1, RTopMux Block Inputs AGND RefHi, RefLo FB RESISTOR MATRIX LOUT Gain EXGAIN RTapMux RBotMux CMOUT GIN LIN 22.2 AGND SCBLK Vss Adjacent Column RBOTMUX INSAMP Register Definitions The following registers are associated with the Continuous Time (CT) PSoC Block and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of the CT PSoC Block registers, refer to the “Summary Table of the Analog Registers” on page 389. Depending on how many analog columns your PSoC device has (see the Cols. column in the register tables below), only certain bits are accessible to be read or written. The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. In the tables below, an “x” before the comma in the address field (in the “Add.” column) indicates that the register exists in both register banks. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index and n = column index. Therefore, ACC01CR2 is a register for an analog PSoC block in row 0 column 1. 426 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Continuous Time PSoC® Block 22.2.1 ACCxxCR3 Register Add. Name Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,70h ACC00CR3 Cols. 4, 2 Bit 7 Bit 6 AGND_PD RTopMux1 LPCMPEN CMOUT INSAMP EXGAIN RW : 00 0,74h ACC01CR3 4, 2 AGND_PD RTopMux1 LPCMPEN CMOUT INSAMP EXGAIN RW : 00 0,78h ACC02CR3 4 AGND_PD RTopMux1 LPCMPEN CMOUT INSAMP EXGAIN RW : 00 0,7Ch ACC03CR3 4 AGND_PD RTopMux1 LPCMPEN CMOUT INSAMP EXGAIN RW : 00 The Analog Continuous Time Type C Block Control Register 3 (ACCxxCR3) is one of four registers used to configure a type C continuous time PSoC block. Figure 22-2. Two-Opamp Instrumentation Amplifier The analog array can be used to build two different forms of instrumentation amplifiers. Two continuous time blocks combine to make the two-opamp instrumentation amplifier illustrated in Figure 22-2. RB Two continuous time blocks and one switched capacitor block combine to make a three-opamp instrumentation amplifier (see Figure 22-3). The three-opamp instrumentation amplifier handles a larger common mode input range but takes more resources. Bit 2 (CMOUT) and bit 1 (INSAMP) control switches are involved in the three-opamp instrumentation amplifier. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four, two, and one column PSoC devices (in the “Cols.” column). The following are descriptions of the ACCxxCR3 register bits that are not reserved. Bit 5: AGND_PD. Used to power down AGND buffer in CT block. 0: AGND buffer power on 1: AGND buffer power off Bit 4: RTopMux1. 0: RTop to Vdd or opamp's output depending on ACCxxCR0 bit 2. 1: RTop to RefHi. NON-INV + - 1ST CT BLOCK INV OUT RA + - RA RB 2ND CT BLOCK GAIN = 1+ RB RA Bit 2: CMOUT. If this bit is high, then the node formed by the connection of the resistors, between the continuous time blocks, is connected to that continuous time block’s ABUS. This node is the common mode of the inputs to the instrumentation amplifier. The CMOUT bit is optional for the threeopamp instrumentation amplifier. Bit 1: INSAMP. This bit is used to connect the resistors of two continuous time blocks as part of a three-opamp instrumentation amplifier. The INSAMP bit must be high for the three-opamp instrumentation amplifier (see Figure 22-3). Bit 3: LPCMPEN. Each continuous time block has a low power comparator connected in parallel with the block’s main opamp/comparator. The low power comparator is used in applications where low power is more important than low noise and low offset. The low power comparator operates when the LPCMPEN bit is set high. Because the main opamp/comparator’s output is connected to the low power comparator’s output, only one of the comparators should be active at a particular time. The main opamp/comparator is powered down by setting ACCxxCR2: PWR[1:0] to 00b, or setting ARF_CR: PWR[2:0] to x00b. The low power comparator is unaffected by the PWR bits in the ACCxxCR2 and ARF_CR registers. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 427 Continuous Time PSoC® Block Figure 22-3. Three-Opamp Instrumentation Amplifier 1st CT Block NON + - RB PHI1 PHI1 RA 1st ABUS 2nd ABUS Cx Cy PHI2 CMOUT PHI2 INSAMP PHI1 + - INSAMP CMOUT PHI2 OUT Cx RA SC Block Type C or D PHI1 RB INV + - 2nd CT Block GAIN = 1+ Bit 0: EXGAIN. The continuous time block’s resistor tap is specified by the value of ACCxxCR3 EXGAIN, combined with the value of ACCxxCR0 RtapMux[3:0]. For RtapMux values from 0010b through 1111b, the EXGAIN bit has no effect on which tap is selected. (See the ACCxxCR0 register for details.) The EXGAIN bit enables additional resistor tap selections for RtapMux = 0001b and RtapMux = 0000b (see Figure 22-4). For additional information, refer to the ACCxxCR3 register on page 156. RB RA Cx Cy Figure 22-4. CT Block in Gain Configuration IN + - OUT RTapMux[3:0] Fh EXGAIN X R R Eh X R R R Dh X 1h 0 R Total number of unit resistors = 48 R R 0h 0 R 1h 1 R 0h 1 R R 428 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Continuous Time PSoC® Block 22.2.2 ACCxxCR0 Register Add. Name 0,71h ACC00CR0 Cols. 4, 2 Bit 7 Bit 6 Bit 5 0,75h ACC01CR0 4, 2 RTapMux[3:0] Gain RTopMux RBotMux[1:0] RW : 00 0,79h ACC02CR0 4 RTapMux[3:0] Gain RTopMux RBotMux[1:0] RW : 00 0,7Dh ACC03CR0 4 RTapMux[3:0] Gain RTopMux RBotMux[1:0] RW : 00 The Analog Continuous Time Type C Block Control Register 0 (ACCxxCR0) is one of four registers used to configure a type C continuous time PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four, two, and one column PSoC devices (in the “Cols.” column). Bits 7 to 4: RTapMux[3:0]. These bits, in combination with the EXGAIN bit 0 in the ACCxxCR3 register, select the tap of the resistor string. Bit 3: Gain. This bit controls whether the resistor string is connected around the opamp as for gain (tap to inverting opamp input) or for loss (tap to output of the block). Note 22.2.3 Bit 4 RTapMux[3:0] Bit 3 Bit 2 Gain RTopMux Bit 1 Bit 0 RBotMux[1:0] Access RW : 00 that setting Gain alone does not guarantee a gain or loss block. Routing of the ends of the resistor string determine this. Bit 2: RTopMux. This bit controls the top end of the resistor string, which can either be connected to Vdd or to the opamp output. Bits 1 and 0: RBotMux[1:0]. These bits, in combination with the INSAMP bit 1 in the ACCxxCR3 register, control the connection of the bottom end of the resistor string. For additional information, refer to the ACCxxCR0 register on page 157. ACCxxCR1 Register Add. Name 0,72h ACC00CR1 Cols. 4, 2 Bit 7 Bit 6 AnalogBus CompBus Bit 5 0,76h ACC01CR1 4, 2 AnalogBus CompBus NMux[2:0] PMux[2:0] RW : 00 0,7Ah ACC02CR1 4 AnalogBus CompBus NMux[2:0] PMux[2:0] RW : 00 0,7Eh ACC03CR1 4 AnalogBus CompBus NMux[2:0] PMux[2:0] RW : 00 The Analog Continuous Time Type C Block Control Register 1 (ACCxxCR1) is one of four registers used to configure a type C continuous time PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four or two column PSoC devices (in the “Cols.” column). Bit 7: AnalogBus. This bit controls the analog output bus (ABUS). A CMOS switch connects the opamp output to the analog bus. Bit 6: CompBus. This bit controls a tri-state buffer that drives the comparator logic. If no block in the analog column Bit 4 Bit 3 Bit 2 NMux[2:0] Bit 1 PMux[2:0] Bit 0 Access RW : 00 is driving the comparator bus, it will be driven low externally to the blocks. Bits 5 to 3: NMux[2:0]. These bits control the multiplexing of inputs to the inverting input of the opamp. There are seven input choices from outside the block, plus the internal feedback selection from the resistor string top. Bits 2 to 0: PMux[2:0]. These bits control the multiplexing of inputs to the non-inverting input of the opamp. There are seven input choices from outside the block, plus the internal feedback selection from the resistor string top. For additional information, refer to the ACCxxCR1 register on page 159. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 429 Continuous Time PSoC® Block 22.2.4 ACCxxCR2 Register Add. Name 0,73h ACC00CR2 Cols. 4, 2 Bit 7 Bit 6 Bit 5 Bit 4 CPhase CLatch CompCap TMUXEN 0,77h ACC01CR2 0,7Bh ACC02CR2 0,7Fh ACC03CR2 TestMux[1:0] 4, 2 CPhase CLatch CompCap TMUXEN TestMux[1:0] PWR[1:0] RW : 00 4 CPhase CLatch CompCap TMUXEN TestMux[1:0] PWR[1:0] RW : 00 4 CPhase CLatch CompCap TMUXEN TestMux[1:0] PWR[1:0] RW : 00 The Analog Continuous Time Type C Block Control Register 2 (ACCxxCR2) is one of four registers used to configure a type C continuous time PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four or two column PSoC devices (in the “Cols.” column). Bit 7: CPhase. This bit controls which internal clock phase the comparator data is latched on. Bit 6: CLatch. This bit controls whether the latch is active or if it is always transparent. Bit 5: CompCap. This bit controls whether or not the compensation capacitor is enabled in the opamp. By not switching in the compensation capacitance, a much faster response is obtained if the amplifier is used as a comparator. 430 Bit 3 Bit 2 Bit 1 Bit 0 PWR[1:0] Access RW : 00 Bit 4: TMUXEN. If the TMUXEN bit is high, then the value of TestMux[1:0] determines which test mux input is connected to the ABUS for that particular continuous time block. If the TMUXEN bit is low, then none of the test mux inputs are connected to the ABUS regardless of the value of TestMux[1:0]. Bits 3 and 2: TextMux[1:0]. These bits select which signal is connected to the analog bus. Bits 1 and 0: PWR[1:0]. Power is encoded to select one of three power levels or power down (off). The blocks power up in the off state. Combined with the Turbo mode, this provides six power levels. Turbo mode is controlled by the HBE bit of the Analog Reference Control register (ARF_CR). For additional information, refer to the ACCxxCR2 register on page 160. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 23. Switched Capacitor PSoC® Block This chapter presents the Analog Switched Capacitor Block and its associated registers. The analog Switched Capacitor (SC) blocks are built around a low offset, low noise operational amplifier. For a complete table of the Switched Capacitor PSoC® Block registers, refer to the “Summary Table of the Analog Registers” on page 389. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. 23.1 Architectural Description The Analog Switched Capacitor blocks are built around a rail-to-rail, input and output, low offset and low noise opamp. (Refer to Figure 23-1 and Figure 23-2.) There are several analog multiplexers (muxes) controlled by register bit settings in the control registers that determine the signal topology inside the block. There are four user-selectable capacitor arrays inside this block connected to the opamp. There are two types of Analog Switched Capacitor blocks called Type C and Type D. Their primary differences relate to connections of the C Cap Array and the block’s position in a two-pole filter section. The Type D block also has greater flexibility in switching the B Cap Array. There are four analog arrays. Three of the four arrays are input arrays and are labeled A Cap Array, B Cap Array, and C Cap Array. The fourth array is the feedback path array and is labeled F Cap Array. All arrays have user-selectable unit values: one array is in the feedback path of the opamp and three arrays are in the input path of the opamp. Analog muxes, controlled by bit settings in control registers, set the capacitor topology inside the block. A group of muxes are used for the signal processing and switch synchronously to clocks PHI1 and PHI2, with behavior that is modified by control register settings. There is also an analog comparator that converts the opamp output (relative to the local analog ground) into a digital signal. 1. The analog output bus (ABUS), which is an analog bus resource shared by all of the analog blocks in the analog column. This signal may also be routed externally through the output buffer. The ABUS of each column has a 1.4 pF capacitor to GND. This capacitor may be used to hold a sampled value on the ABUS net. Although there is only one capacitor per column, it is shown in both Figure 23-1 and Figure 23-2 to allow visualization of the sample and hold function. See the description of the ClockPhase bit in the ASCxxCR0 and ASDxxCR0 registers in section 23.3 Register Definitions. There are three discrete outputs from this block. These outputs connect to the following buses: 2. The comparator bus (CBUS), which is a digital bus resource shared by all of the analog blocks in the analog column. 3. The local output bus (OUT), which is an analog node, is routed to neighboring block inputs. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 431 Switched Capacitor PSoC® Block Figure 23-1. Analog Switch Cap Type C PSoC Blocks 1 *AutoZero BQTA P CCa p 0,1,…,30,31 C FCap 16,32 C C Inputs 2+!AutoZero) * FSW1 1* FSW0 ACMux 1 A Inputs RefHi RefLo AGND ARefMux ACap 0,1,…,30,31 C 2+AutoZero 1 * !AutoZero 2 ASign Modulation Inputs Mod Bit Control BCap 0,1,…,30,31 C OUT AnalogBus 2B * ABU S Powe r (Comparator) CBUS 2 B Inputs BMuxSC 432 2 1 CBUS Driver 1 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Switched Capacitor PSoC® Block Figure 23-2. Analog Switch Cap Type D PSoC Blocks 1 *AutoZero FCap 16,32 C CCa p 0,1,…,30,31 C 2+!AutoZero) * FSW1 BQTA P 1* FSW0 A Mux A Inputs RefHi RefLo AGND ARefMux ASign 1 ACap 0,1,…,30,31 C 2+AutoZero 1 * !AutoZero 2 BCap 0,1,…,30,31 C 2 +!BSW B Inputs OUT AnalogBus 2B * ABU S 2 +!BSW+AutoZero Powe r 1*BSW (Comparator) 1 *BSW*!AutoZero BMuxSD 23.2 CBUS 2 1 CBUS Driver Application Description The analog Switched Capacitor (SC) blocks support DeltaSigma, Successive Approximation, and Incremental Analogto-Digital Conversion, Capacitor DACs, and SC filters. They have three input arrays of binary-weighted switched capacitors, allowing user programmability of the capacitor weights. This provides summing capability of two (CDAC) scaled inputs and a non-switched capacitor input. The non-switched capacitor node is labeled “BQTAP” in Figure 23-2. For two and four column PSoC devices, the local connection of BQTAP is between horizontal neighboring SC blocks within an analog bi-column. For one column PSoC devices, the local connection of BQTAP is vertical between the SC blocks. Because the input of SC Block C (ASCxx) has this additional switched capacitor, it is configured for the input stage of such a switched capacitor bi-quad filter. When followed by an SC Block D (ASDxx) integrator, this combination of blocks can be used to provide a full universal two-pole switched capacitor bi-quad filter. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 433 Switched Capacitor PSoC® Block 23.3 Register Definitions The following registers are associated with the Switched Capacitor (SC) PSoC Block and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of SC PSoC Block registers, refer to the “Summary Table of the Analog Registers” on page 389. Depending on how many analog columns your PSoC device has (see the Cols. column in the register tables below), only certain bits are accessible to be read or written. The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. Figure 23-3 applies to the ACap, BCap, and CCap functionality for the capacitor registers. The XCap field is used to store the binary encoded value for capacitor X, where X can be A (ACap), B (BCap), or C (CCap), in both the ASCxxCRx and ASDxxCRx registers. Figure 23-3 illustrates the switch settings for the example ACap[4:0]=14h=10100b=20d. Figure 23-3. Example Switch Capacitor Settings 1 BOTTOM 16C AGND 8C AGND 0 1 TOP 4C AGND 2C AGND 0 1C AGND 434 0 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Switched Capacitor PSoC® Block Analog Switch Cap Type C PSoC Block Control Registers In the tables below, an “x” before the comma in the address field (in the “Add.” column) indicates that the register exists in both register banks. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index and n = column index. Therefore, ASC21CR2 is a register for an analog PSoC block in row 2 column 1. 23.3.1 ASCxxCR0 Register Add. Name 0,80h ASC10CR0 0,88h 0,94h 0,9Ch Cols. Bit 7 Bit 6 Bit 5 4, 2 FCap ClockPhase ASign ACap[4:0] RW : 00 ASC12CR0 4 FCap ClockPhase ASign ACap[4:0] RW : 00 ASC21CR0 4, 2 FCap ClockPhase ASign ACap[4:0] RW : 00 ASC23CR0 4 FCap ClockPhase ASign ACap[4:0] RW : 00 The Analog Switch Cap Type C Block Control Register 0 (ASCxxCR0) is one of four registers used to configure a type C switch capacitor PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four and two column PSoC devices (in the “Cols.” column). Bit 7: FCap. This bit controls the size of the switched feedback capacitor in the integrator. Bit 6: ClockPhase. This bit controls the internal clock phasing relative to the input clock phasing. ClockPhase affects the output of the analog column bus, which is controlled by the AnalogBus bit in the Control 2 register. This bit is the ClockPhase select that inverts the clock internal to the blocks. During normal operation of an SC block, for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of PHI2. (During PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven.) This forms a sample and hold operation, using the output bus and its associated capacitance. This design prevents the output bus from being perturbed by the intermediate states of the SC operation (often a reset state for PHI1 and settling to the valid state during PHI2). The following are the exceptions: Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 2. If the SHDIS signal is set in bit 6 of the Analog Clock Source Control register, then sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their respective output buses for the entire period of their respective PHI2s. This bit also affects the latching of the comparator output (CBUS). Both clock phases, PHI1 and PHI2, are involved in the output latching mechanism. The capture of the next value to be output from the latch (capture point event) happens during the falling edge of one clock phase. The rising edge of the other clock phase will cause the value to come out (output point event). This bit determines which clock phase triggers the capture point event, and the other clock will trigger the output point event. The value output to the comparator bus will remain stable between output point events. Bit 5: ASign. This bit controls the switch phasing of the switches on the bottom plate of the ACap capacitor. The bottom plate samples the input or the reference. Bits 4 to 0: ACap[4:0]. The ACap bits set the value of the capacitor in the A path. For additional information, refer to the ASCxxCR0 register on page 161. 1. If the ClockPhase bit in CR0 (for the SC block in question) is set to ‘1’, then the output is enabled for the whole of PHI2. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 435 Switched Capacitor PSoC® Block 23.3.2 ASCxxCR1 Register Add. Name 0,81h ASC10CR1 0,89h 0,95h 0,9Dh Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BCap[4:0] Access 4, 2 ACMux[2:0] RW : 00 ASC12CR1 4 ACMux[2:0] BCap[4:0] RW : 00 ASC21CR1 4, 2 ACMux[2:0] BCap[4:0] RW : 00 ASC23CR1 4 ACMux[2:0] BCap[4:0] RW : 00 The Analog Switch Cap Type C Block Control Register 1 (ASCxxCR1) is one of four registers used to configure a type C switch capacitor PSoC block. Bits 7 to 5: ACMUX[2:0]. These bits control the input muxing for both the A and C capacitor branches. The high order bit, ACMux[2], selects one of two inputs for the C branch. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four and two column PSoC devices (in the “Cols.” column). Bits 4 to 0: BCap[4:0]. The BCap bits set the value of the capacitor in the B path. For additional information, refer to the ASCxxCR1 register on page 162. 23.3.3 ASCxxCR2 Register Add. Name 0,82h ASC10CR2 0,8Ah 0,96h 0,9Eh Cols. Bit 7 Bit 6 Bit 5 4, 2 AnalogBus CompBus AutoZero ASC12CR2 4 AnalogBus CompBus AutoZero CCap[4:0] RW : 00 ASC21CR2 4, 2 AnalogBus CompBus AutoZero CCap[4:0] RW : 00 ASC23CR2 4 AnalogBus CompBus AutoZero CCap[4:0] RW : 00 The Analog Switch Cap Type C Block Control Register 2 (ASCxxCR2) is one of four registers used to configure a type C switch capacitor PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four and two column PSoC devices (in the “Cols.” column). Bit 7: AnalogBus. This bit gates the output to the analog column bus (ABUS). The output on the ABUS is affected by the state of the ClockPhase bit in the Control 0 register. If AnalogBus is set to ‘0’, the output to the analog column bus is tri-stated. If AnalogBus is set to ‘1’, the signal that is output to the analog column bus is selected by the ClockPhase bit. If the ClockPhase bit is ‘0’, the block output is gated by sampling clock on the last part of PHI2. If the ClockPhase bit is ‘1’, the block output continuously drives the ABUS. Bit 6: CompBus. This bit controls the output to the column comparator bus (CBUS). Note that if the CBUS is not driven 436 Bit 4 Bit 3 Bit 2 CCap[4:0] Bit 1 Bit 0 Access RW : 00 by anything in the column, it is pulled low. The comparator output is evaluated on the rising edge of internal PHI1 and is latched so it is available during internal PHI2. Bit 5: AutoZero. This bit controls the shorting of the output to the inverting input of the opamp. When shorted, the opamp is basically a follower. The output is the opamp offset. By using the feedback capacitor of the integrator, the block can memorize the offset and create an offset cancellation scheme. AutoZero also controls a pair of switches between the A and B branches and the summing node of the opamp. If AutoZero is enabled, then the pair of switches is active. AutoZero also affects the function of the FSW1 bit in the Control 3 register. Bits 4 to 0: CCap[4:0]. The CCap bits set the value of the capacitor in the C path. For additional information, refer to the ASCxxCR2 register on page 163. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Switched Capacitor PSoC® Block 23.3.4 ASCxxCR3 Register Add. Name 0,83h ASC10CR3 0,8Bh 0,97h 0,9Fh Cols. Bit 5 Bit 4 4, 2 Bit 7 ARefMux[1:0] Bit 6 FSW1 FSW0 BMuxSC[1:0] PWR[1:0] RW : 00 ASC12CR3 4 ARefMux[1:0] FSW1 FSW0 BMuxSC[1:0] PWR[1:0] RW : 00 ASC21CR3 4, 2 ARefMux[1:0] FSW1 FSW0 BMuxSC[1:0] PWR[1:0] RW : 00 ASC23CR3 4 ARefMux[1:0] FSW1 FSW0 BMuxSC[1:0] PWR[1:0] RW : 00 The Analog Switch Cap Type C Block Control Register 3 (ASCxxCR3) is one of four registers used to configure a type C switch capacitor PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four and two column PSoC devices (in the “Cols.” column). Bits 7 and 6: ARefMux[1:0]. These bits select the reference input of the A capacitor branch. Bit 5: FSW1. This bit is used to control a switch in the integrator capacitor path. It connects the output of the opamp to the integrating cap. The state of the feedback switch is affected by the state of the AutoZero bit in the Control 2 register. If the FSW1 bit is set to ‘0’, the switch is always disabled. If the FSW1 bit is set to ‘1’, the AutoZero bit Bit 3 Bit 2 Bit 1 Bit 0 Access determines the state of the switch. If the AutoZero bit is ‘0’, the switch is enabled at all times. If the AutoZero bit is ‘1’, the switch is enabled only when the internal PHI2 is high. Bit 4: FSW0. This bit is used to control a switch in the integrator capacitor path. It connects the output of the opamp to analog ground. Bits 3 and 2: BMuxSC[1:0]. These bits control the muxing to the input of the B capacitor branch. Bits 1 and 0: PWR[1:0]: The power bits serve as encoding for selecting one of four power levels. The block always powers up in the off state. For additional information, refer to the ASCxxCR3 register on page 164. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 437 Switched Capacitor PSoC® Block Analog Switch Cap Type D PSoC Block Control Registers In the tables below, an “x” before the comma in the address field (in the “Add.” column) indicates that the register exists in both register banks. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index and n = column index. Therefore, ASD01CR0 is a register for an analog PSoC block in row 0 column 1. 23.3.5 ASDxxCR0 Register Add. Name 0,84h ASD11CR0 0,8Ch 0,90h 0,98h Cols. Bit 7 Bit 6 Bit 5 4, 2 FCap ClockPhase ASign ACap[4:0] RW : 00 ASD13CR0 4 FCap ClockPhase ASign ACap[4:0] RW : 00 ASD20CR0 4, 2 FCap ClockPhase ASign ACap[4:0] RW : 00 ASD22CR0 4 FCap ClockPhase ASign ACap[4:0] RW : 00 The Analog Switch Cap Type D Block Control Register 0 (ASDxxCR0) is one of four registers used to configure a type D switch capacitor PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four and two column PSoC devices (in the “Cols.” column). Bit 7: FCap. This bit controls the size of the switched feedback capacitor in the integrator. Bit 6: ClockPhase. This bit controls the internal clock phasing relative to the input clock phasing. ClockPhase affects the output of the analog column bus which is controlled by the AnalogBus bit in the Control 2 register. This bit is the ClockPhase select that inverts the clock internal to the blocks. During normal operation, of an SC block for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of PHI2. (During PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven.) This forms a sample and hold operation using the output bus and its associated capacitance. This design prevents the output bus from being perturbed by the intermediate states of the SC operation (often a reset state for PHI1 and settling to the valid state during PHI2). The following are the exceptions: Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 2. If the SHDIS signal is set in bit 6 of the Analog Clock Select register, then sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their respective output buses, for the entire period of their respective PHI2s. This bit also affects the latching of the comparator output (CBUS). Both clock phases, PHI1 and PHI2, are involved in the output latching mechanism. The capture of the next value to be output from the latch (capture point event) happens during the falling edge of one clock phase. The rising edge of the other clock phase will cause the value to come out (output point event). This bit determines which clock phase triggers the capture point event, and the other clock will trigger the output point event. The value output to the comparator bus will remain stable between output point events. Bit 5: ASign. This bit controls the switch phasing of the switches on the bottom plate of the A capacitor. The bottom plate samples the input or the reference. Bits 4 to 0: ACap[4:0]. The ACap bits set the value of the capacitor in the A path. For additional information, refer to the ASDxxCR0 register on page 165. 1. If the ClockPhase bit in CR0 (for the SC block in question) is set to ‘1’, then the output is enabled for the whole of PHI2. 438 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Switched Capacitor PSoC® Block 23.3.6 ASDxxCR1 Register Add. Name 0,85h ASD11CR1 0,8Dh 0,91h 0,99h Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 4, 2 AMux[2:0] BCap[4:0] RW : 00 ASD13CR1 4 AMux[2:0] BCap[4:0] RW : 00 ASD20CR1 4, 2 AMux[2:0] BCap[4:0] RW : 00 ASD22CR1 4 AMux[2:0] BCap[4:0] RW : 00 The Analog Switch Cap Type D Block Control Register 1 (ASDxxCR1) is one of four registers used to configure a type D switch capacitor PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four and two column PSoC devices (in the “Cols.” column). 23.3.7 Bits 7 to 5: AMux[2:0]. These bits control the input muxing for the A capacitor branch. Bits 4 to 0: BCap[4:0]. The BCap bits set the value of the capacitor in the B path. For additional information, refer to the ASDxxCR1 register on page 166. ASDxxCR2 Register Add. Name 0,86h ASD11CR2 0,8Eh 0,92h 0,9Ah Cols. Bit 7 Bit 6 Bit 5 4, 2 AnalogBus CompBus AutoZero CCap[4:0] RW : 00 ASD13CR2 4 AnalogBus CompBus AutoZero CCap[4:0] RW : 00 ASD20CR2 4, 2 AnalogBus CompBus AutoZero CCap[4:0] RW : 00 ASD22CR2 4 AnalogBus CompBus AutoZero CCap[4:0] RW : 00 The Analog Switch Cap Type D Block Control Register 2 (ASDxxCR2) is one of four registers used to configure a type D switch capacitor PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four and two column PSoC devices (in the “Cols.” column). Bit 7: AnalogBus. This bit gates the output to the analog column bus (ABUS). The output on the ABUS is affected by the state of the ClockPhase bit in the Control 0 Register. If AnalogBus is set to ‘0’, the output to the ABUS is tri-stated. If AnalogBus is set to ‘1’, the ClockPhase bit selects the signal that is output to the analog-column bus. If the ClockPhase bit is ‘0’, the block output is gated by sampling clock on the last part of PHI2. If the ClockPhase bit is ‘1’, the block ClockPhase continuously drives the ABUS. Bit 6: CompBus. This bit controls the output to the column comparator bus (CBUS). Note that if the CBUS is not driven Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access by anything in the column, it is pulled low. The comparator output is evaluated on the rising edge of internal PHI1 and is latched so it is available during internal PHI2. Bit 5: AutoZero. This bit controls the shorting of the output to the inverting input of the opamp. When shorted, the opamp is basically a follower. The output is the opamp offset. By using the feedback capacitor of the integrator, the block can memorize the offset and create an offset cancellation scheme. AutoZero also controls a pair of switches between the A and B branches and the summing node of the opamp. If AutoZero is enabled, then the pair of switches is active. AutoZero also affects the function of the FSW1 bit in the Control 3 register. Bits 4 to 0: CCap[4:0]. The CCap bits set the value of the capacitor in the C path. For additional information, refer to the ASDxxCR2 register on page 167. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 439 Switched Capacitor PSoC® Block 23.3.8 ASDxxCR3 Register Add. Name 0,87h ASD11CR3 Cols. Bit 5 Bit 4 Bit 3 Bit 2 ARefMux[1:0] FSW1 FSW0 BSW BMuxSD PWR[1:0] RW : 00 0,8Fh ASD13CR3 0,93h ASD20CR3 4 ARefMux[1:0] FSW1 FSW0 BSW BMuxSD PWR[1:0] RW : 00 4, 2 ARefMux[1:0] FSW1 FSW0 BSW BMuxSD PWR[1:0] 0,9Bh ASD22CR3 4 RW : 00 ARefMux[1:0] FSW1 FSW0 BSW BMuxSD PWR[1:0] RW : 00 4, 2 Bit 7 Bit 6 The Analog Switch Cap Type D Block Control Register 3 (ASDxxCR3) is one of four registers used to configure a type D switch capacitor PSoC block. Depending on the address of the registers in the above table (in the “Add.” column), these registers are used for four and two column PSoC devices (in the “Cols.” column). Bits 7 and 6: ARefMux[1:0]. These bits select the reference input of the A capacitor branch. Bit 5: FSW1. This bit is used to control a switch in the integrator capacitor path. It connects the output of the opamp to the integrating cap. The state of the switch is affected by the state of the AutoZero bit in the Control 2 register. If the FSW1 bit is set to ‘0’, the switch is always disabled. If the FSW1 bit is set to ‘1’, the AutoZero bit determines the state of the switch. If the AutoZero bit is ‘0’, the switch is enabled at all times. If the AutoZero bit is ‘1’, the switch is enabled only when the internal PHI2 is high. Bit 1 Bit 0 Access Bit 4: FSW0. This bit is used to control a switch in the integrator capacitor path. It connects the output of the opamp to analog ground. Bit 3: BSW. This bit is used to control switching in the B branch. If disabled, the B capacitor branch is a continuous time branch such as the C branch of the SC A Block. If enabled, then on internal PHI1, both ends of the cap are switched to analog ground. On internal PHI2, one end is switched to the B input and the other end is switched to the summing node. Bit 2: BMuxSD. This bit controls muxing to the input of the B capacitor branch. The B branch can be switched or unswitched. Bits 1 and 0: PWR[1:0]. The power bits serve as encoding for selecting one of four power levels. The block always powers up in the off state. For additional information, refer to the ASDxxCR3 register on page 168. 440 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 24. Two Column Limited Analog System This chapter explains the Two Column Limited Analog System PSoC® devices and their associated registers. It details the entire analog system for two column limited functionality, including the analog interface, analog array, analog input configuration, analog reference, CT and SC blocks. For a complete table of the Two Column Limited Analog System registers, refer to the “Summary Table for Two Column Limited Analog System Registers” on page 452. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. Unique to the CY8C28xxx PSoC devices is the use of an I/O analog multiplexer system resource. The I/O Analog Multiplexer is described in the I/O Analog Multiplexer chapter on page 525. A summary of the I/O Analog Multiplexer registers are located in the section called “System Resources” on page 461. 24.1 Architectural Description 24.1.1 Analog Interface Figure 24-1 displays the top-level diagram of the PSoC devices’ analog interface system. Figure 24-1. Analog Comparator Bus Slice of the CY8C28xxx PSoC Devices VC3 Data Output From Dedicated ADC PWM (one per device) Data Output From DBxxx (any digital block) One Analog Column Continuous Time Block Type E PWM Analog Comparator Bus Slice Single Slope, ADC Gate, One per Column Global In Odd i, i+4 (From Digital Blocks) AMP (ACE_CMP_GI_EN) IGEN CBUS Driver (DEC_CR0[5:4]) CBSRC (ACE_ADC_CR[3]) From Col (i+1) Switched Capacitor Block Type E Destinations Integrator B A MODBIT (ACE_ALT_CR0[7:0]) Analog Column Clock AMODx[2:0] Digital Stream Sources LUT To Col (i-1) PWM BYPASS (CLDIS, ACE_CMP_CR1[5:4]) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 1) Comparator Register 2) Data Inputs for Digital Blocks Column Interrupt AINT (ACE_CMP_CR0[1:0]) 441 Two Column Limited Analog System 24.1.1.1 Analog Comparator Bus Interface Each analog column has a dedicated comparator bus associated with it. In the CY8C28xxx, PSoC devices, only the Continuous Time (CT) block can drive this bus. The output on the comparator bus cannot drive into the digital blocks as a data input. It can serve as an input to Switched Capacitor (SC) blocks as an interrupt input, and is available as read only data in the Analog Comparator Control register (ACE_CMP_CR0). It can be driven to the global output bus by way of the Comparator to Global Input Enable register (ACE_CMP_GI_EN). Figure 24-1 illustrates one column of the comparator bus. The comparator bus is synchronized by the selected column clock before it is available, to either drive the digital blocks, interrupt, SC blocks, or for it to be read in the ACE_CMP_CR0 register. There is also an option to bypass the synchronization in each column into a transparent mode by setting bits in the ACE_CMP_CR1 register. As shown in Figure 24-1, the comparator bus output is gated by the primary output of a selected digital block. This feature is used to precisely control the conversion period of a single slope ADC. Any digital block can be used to drive the gate signal. This selection may be made with the ICLKS bits in registers DEC_CR0 and DEC_CR1. This function may be enabled on a column-by-column basis, by setting the ACE_IGEN bits in the DEC_CR0 register. Alternately, the dedicated ADC PWM, with VC3 as input, can be used to gate the ADC conversion period without the need for a digital block. When this dedicated PWM is configured, it overrides the ICLKS selection as defined by the DEC_CR0 and DEC_CR1 registers. The analog comparator bus output values can be modified or combined with another analog comparator bus through the Analog Look-Up-Table (LUT) function. The LUT takes two inputs, A and B, and provides a selection of 16 possible logic functions for those inputs. The LUT A and B inputs for each column comparator output is shown in the following table. Table 24-1. A and B Inputs for Each Column Comparator LUT Output for the CY8C28xxx Devices Comparator LUT Output A B Column 4 ACMP4 ACMP5 Column 5 ACMP5 0 The LUT configuration is set in two control registers, ACE_ALT_CR0 and ACE_ALT_CR1. Each selection for each column is encoded in four bits. The function value corresponding to the bit encoding is shown in Table 24-2. 442 Table 24-2. RDIxLTx Register LUTx[3:0] 24.1.1.2 0h: 0000: FALSE 1h: 0001: A .AND. B 2h: 0010: A .AND. B 3h: 0011: A 4h: 0100: A .AND. B 5h: 0101: B 6h: 0110: A .XOR. B 7h: 0111: A .OR. B 8h: 1000: A .NOR. B 9h: 1001: A .XNOR. B Ah: 1010: B Bh: 1011: A .OR. B Ch: 1100: A Dh: 1101: A .OR. B Eh: 1110: A. NAND. B Fh: 1111: TRUE Analog Column Clock Generation The input clock source for each column clock generator is selectable according to the ACE_CLK_CR0 register. There are four selections for each column: VC1, VC2, ACLK4, and ACLK5. An additional selection, SYSCLK, is controlled by the ACE_CLK_CR3 register. The VC1 and VC2 clock signals are global system clocks. Programming options for these system clocks can be accessed in the OSC_CR1 register. Each of the ACLK4 and ACLK5 clock selections are driven by a selection of digital block outputs. The settings for the digital block selection are located in the ACE_CLK_CR1 register. The ACE_CLK_CR3 register has additional column clock options. This register allows for a direct SYSCLK option as well as the option to divide the selected column clock by 2, 4, or 8. 24.1.1.3 Single Slope ADC A simplified block diagram of the single slope ADC (SSADC) implementation is show in Figure 24-2. The core of the conversion algorithm involves a current source, an integrating capacitor, and a comparator. When the current source is activated, a linear voltage ramp is generated on the capacitor. This voltage is an input to an analog comparator circuit; the other input of which is the analog input voltage to be converted. With the polarity of hookup as shown, the comparator will be high until the ramp voltage equals the input voltage, at which time it will transition low. A counter gate is generated by the AND of the PWM high time (which defines the start of the ramp) and the comparator (which defines the trip point or the end of the conversion for a given voltage). When the conversion is complete, the code may be read from the counter. Each column has an ADC configuration register (ACE_ADCx_CR). CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Two Column Limited Analog System Figure 24-2. Single Slope ADC Block Diagram PWM output controls the ramp on time and discharge off time. VIN EN PWM Dedicated ADC PWM To Column INT Counter Synchronized PWM is gated with analog comparator to enable the Counter. Falling edge of selected PWM is routed to column interrupt to signal end-of-conversion. To interface the asynchronous analog comparator to the digital block array, a double synchronization is required. As shown in Figure 24-2, the PWM is also delayed to align with the valid comparator output. The basic conversion waveforms are shown in Figure 24-3. The high time of the PWM is set so that the counter will count to a full-scale value. For example, for 8-bit resolution, the high time of the PWM corresponds to 255 (or 256) counter clocks. The low time of the PWM is designed to allow the capacitor to discharge. When a PWM is used for continuous conversions, the Terminal Count of the PWM can be used as a consistent interrupt to read the result of the previous conversion. If only a single conversion is desired, the comparator trip point can be used as an interrupt to signal the end of conversion. A trim register (ADCx_TR) is provided for each column. The converter must be calibrated for a given maximum voltage, resolution, and frequency of operation before use. Figure 24-3. Basic ADC Waveforms Start of conversion Ramp voltage is equal to input voltage and comparator trips. End of conversion (max range) TC PWM Voltage Ramp Comparator Counter Gate Counter measures the time from the start of the voltage ramp to the comparator trip. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 443 Two Column Limited Analog System 24.1.1.4 PWM ADC Interface The analog interface provides hardware support and signal routing for analog-to-digital (ADC) conversion functions, specifically the single slope ADC. The control signals for this interface are split between three registers: DEC_CR0, DEC_CR1, and ACE_PWM_CR. The analog interface has support for the single slope ADC operation through the ability to gate the analog comparator outputs. This gating function is required to precisely control the digital integration period that is performed in a digital block as part of the function. A digital block PWM or the dedicated ADC PWM may be used as a source to provide the gate signal. Only one source for the gating signal can be selected. However, the gating can be applied independently to any of the column comparator outputs. The CY8C28xxx devices contain a dedicated block that can perform this PWM gating function using VC3. The VC3 signal, out of the VC3 divider block, can be further divided to provide for gating the incremental ADC. The ACE_PWM_CR register controls the duty cycle selection in terms of VC3 periods, as shown in the following tables. When enabled, the PWM block becomes the source for the incremental gating, overriding the digital block selection. Table 24-3. PWM High Time HI[2:0] 000b 001b 010b 011b 100b 101b Description Block is not selected, input to incremental gate is from selected digital block. High time is 1 VC3 period. High time is 2 VC3 period. High time is 4 VC3 period. High time is 8 VC3 period. High time is 16 VC3 period. 24.1.1.5 Analog Modulator Interface (Mod Bits) The Analog Modulator Interface provides a selection of signals that are routed to either of the two analog array modulation control signals. There is one modulation control signal for the CY8C28xxx Switched Capacitor block. There are nine selections, which include the dedicated reference voltage generator PWM output, the analog comparator bus outputs (include CS comparator output), two global outputs, and a digital block broadcast bus. The selections for all columns are contained in the ACE_AMD_CR0 and ACE_AMD_CR1 registers. One use of the modulator interface is to provide a selectable reference to one of the comparator inputs. This can be done by configuring a digital block as a PWM or PRS output with the desired duty cycle. The SC block will then give a lowpass filtered version of this signal, which will be a DC voltage relative to the supply with some ripple. 24.1.1.6 Sample and Hold Feature Sample and Hold capability can be selected for improved analog-to-digital conversion accuracy. This is done by setting the SHEN bit in the ADCx_CR register. When enabled, this feature works in conjunction with the selected SSADC PWM input. During the PWM high time, the conversion is active and the sample and hold is in “hold” mode. During the PWM low time, the conversion is inactive, and the sample and hold circuit is in “sample” mode. Table 24-4. PWM Low Time LO[1:0] 00b 01b 10b 11b Description No low time. Comparator gate is continually high. Low time is one VC3 period. Low time is two VC3 period. Low time is three VC3 period. As an alternative to the PWM, the ICLKS bits, which are split between the DEC_CR0 and DEC_CR1 registers, may be used to select a digital block source for the incremental gating signal. Regardless of the source of the gating, the two IGEN bits are used to independently enable the gating function on a column-by-column basis. 444 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Two Column Limited Analog System 24.1.2 Analog Array Figure 24-4. Array of Limited Analog PSoC Block The analog array is designed to allow moving between families without modifying projects, except for resource limitations. The CY8C28x13 PSoC devices have limited analog array functionality. The only analog array connections available to the limited analog array in the CY8C28x13 are the NMux and PMux connections. Figure 24-4 displays the limited analog arrays for the CY8C28x13 devices, containing the type E continuous time blocks (ACE) and the type E switched capacitor blocks (ASE). Each analog column has 2 analog blocks associated with it. The figures that follow illustrate the analog multiplexer (mux) connections. Each analog column has a dedicated comparator bus associated with it. Only the CT block in each column can drive this bus. When the CT block is not configured as a comparator, a zero is driven to the comparator block. Refer to the ACCxxCR1 register on page 159 and the “Analog Comparator Bus Interface” on page 442 in the Analog Interface section for more information. 24.1.2.1 2 Column CY8C28x13 PSoC Device Analog Column 4 Analog Column 5 ACE00 ACE01 ASE10 ASE11 NMux Connections The NMux is an 8-to-1 mux which determines the source for the inverting (also called negative) input of Continuous Time (CT) PSoC blocks. These blocks are named ACE00 and ACE01. More details on the CT PSoC blocks are available in this chapter, in the section titled “Continuous Time PSoC Block” on page 450. The NMux connections are described in detail in the ACExxCR1 register on page 125, bits NMux[2:0]. The numbers in Figure 24-5, which are associated with each arrow, are the corresponding NMux select line values for the data in the NMux portion of the register. The call out names in the figure show nets selected for each NMux value. Figure 24-5. NMux Connections Port Inputs Port Inputs (7) Analog Mux (3) Bus0 (2) (4) (7) ACE00 (0) (4) ACE01 Analog Mux (3) Bus1 (2) (0) (1) VBG (6) (6) (1) (5) (5) ASE10 ASE11 VBG CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 445 Two Column Limited Analog System 24.1.2.2 PMux Connections The PMux is an 8-to-1 mux which determines the source for the non-inverting (also called positive) input of CT PSoC blocks (ACE00 and ACE01). More details on the CT PSoC blocks are available in this chapter, in the section titled “Continuous Time PSoC Block” on page 450. The PMux connections are described in detail in the ACExxCR1 register on page 125, bits PMux[2:0]. The numbers in Figure 24-6, which are associated with each arrow, are the corresponding PMux select line values for the data in the PMux portion of the register. The call out names in the figure show nets selected for each PMux value. Figure 24-6. PMux Connections Analog Mux Bus0 (7) (0,6) Port Inputs Port Inputs (1) (1) ACE00 (2) (5) (3) (2) ACE01 (5) (4) ASE10 24.1.2.3 Temperature Sensing Capability A temperature-sensitive voltage, derived from the bandgap sensing on the die, is buffered and available as an analog input into the continuous time block ACE01. Temperature sensing allows protection of device operating ranges for failsafe applications. Temperature sensing, combined with a long sleep timer interval (to allow the die to approximate ambient temperature), can give an approximate ambient temperature for data acquisition and battery charging applications. The user may also calibrate the internal temperature rise based on a known current consumption. The temperature sensor input to the ACE01 block is labeled VTEMP. 446 (0) (6) VTEMP (3) (4) VBG Analog Mux Bus1 (7) VBG ASE11 24.1.3 Analog Input Configuration Figure 24-8 and Figure 24-9 show the analog input configuration for the CY8C28xxx PSoC devices. For a detailed description of the I/O analog multiplexer functionality illustrated in Figure 24-8, refer to the I/O Analog Multiplexer chapter on page 525. The input multiplexer (mux) maps device inputs (package pins) to analog array columns, based on bit values in the ACE_AMX_IN and ACE_ABF_CR0 registers. Column 4 is fed by one 4-to-1 mux; column 5 is fed by one of two 4-to-1 muxes. The muxes are CMOS switches with typical resistances in the range of 2 k. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Two Column Limited Analog System Figure 24-7. Limited Two Column Analog Interconnect To Decimator Blocks ColumnInterrupt COMP0 1 CBSRC (ACE_ADCx_CR) PWM 0 PWM 1 AINT0 (ACE_CMP_CR0) 0 CompBusOutput0 IGEN0 (DEC_CR0) 1 0 PWM LUT0 (ACE_ALT_CR0) (ACE_CMP_GI_EN) CLDIS0 (ACE_CMP_CR1) 0 GIO0 CLK0 Sync ACE00 PMux PWR NMux ACE00CR1 ACE00CR2 CompBus 1 = Open ASE10 SHEN ENADC LOREN AUTO Column CLK0 GIO4 0 1 2 3 Sync Comp0Out 1 ENADC FVAL ACE_ADC0_CR ACE_ADC0_TR ASE10CR0 ACE_AMOD_CR0 CAPVAL AMOD0 PWM DIVCLKx (ACE_CLK_CR3) 1 2 4 8 ADCPWM AColumnx (ACE_CLK_CR0) To Second Analog Column ACLKx (ACE_CLK_CR1) PWM VC1 VC2 AC0 AC1 SYSCLK LOW VC3 DB23 | | DB00 HIGH ENPWM PWM_CR CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 447 Two Column Limited Analog System Figure 24-8. Two Column Limited Analog Pin Block Diagram for the CY8C28xxx (28-Pin and 44-Pin Part) 28 Pin Part P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] P3[7] P3[6] 44 Pin Part P3[5] P3[4] Array Input Configuration P3[2] P3[1] P3[0] P4[5] ACI4[1:0] ACM4 P4[3] P4[1] ACI5[1:0] ACE0MUX ACM5 ACE1MUX Analog Mux Bus P3[3] AC5 P4[4] P4[2] P4[0] Array ACE00 ACE01 ASE10 ASE11 Interface to Digital System Vdd Vss VBG Reference Generators Bandgap Microcontroller Interface (Address Bus, Data Bus, Etc.) 448 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Two Column Limited Analog System Figure 24-9. Two Column Limited Analog Pin Block Diagram for the CY8C28xxx P0[7] P0[6] 8 Pin Part P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] 16 and Higher Pin Part Array Input Configuration ACI4[1:0] ACI5[1:0] ACM4 ACE0MUX ACM5 ACE1MUX AC5 Array ACE00 ACE01 ASE10 ASE11 Interface to Digital System Vdd Vss VBG Reference Generators Bandgap Microcontroller Interface (Address Bus, Data Bus, Etc.) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 449 Two Column Limited Analog System 24.1.4 Analog Reference 24.1.5 The PSoC device is a single supply part, with no negative voltage available or applicable. The limited analog columns in CY8C28xxx PSoC devices support only one analog reference, which is the bandgap voltage VBG. This voltage is routed to the CT blocks in each analog column. VBG is available at both positive and negative inputs of each CT amplifier. DAC functions are relative to the power supply range (Vss to Vdd). The bandgap VBG reference can be used to calibrate the supply range. Single slope ADC operation relies on a calibration step, using the internal bandgap reference or other user-supplied reference. If the bandgap reference is used, the ADC gives absolute voltage conversions. For CT amplifiers configured as comparators (that is, open loop), a selected analog pin can be compared against another pin (fed from the other block), VBG, or a supply-referenced DAC voltage from the SC integrator. With the analog multiplexer bus in the CY8C28xxx PSoC devices, a Port 0 pin can be compared against another pin without using resources of the adjacent column. Continuous Time PSoC Block The CY8C28xxx Continuous Time blocks (Type ACE) are built around a low power, low offset amplifier. The CT block can be configured in two modes: As a unity gain buffer to drive to the other column or open loop as a comparator. To configure as a comparator, select any NMux choice except feedback (FB). To enable the comparator bus output, the CompBus signal must be set in the ACE0xCR1 register. See Figure 24-10. There are two discrete outputs from this block. These outputs connect to the following buses: 1. The comparator bus (CBUS), which is a digital bus that is a resource shared by all of the analog blocks in a column for that block. This output is available to system interface logic. 2. The local output bus (OUT), which is routed to the neighboring block. Figure 24-10. Analog Continuous Time Block Diagram Block Inputs + VBG Analog Mux Bus 0 OUT - PMux CBUS NMux Block Inputs Port Inputs CompBus VBG Analog Mux Bus 1 FB 24.1.6 Switched Capacitor PSoC Block The analog switched capacitor blocks accept a bit stream from either a digital block or a CT comparator. The SC block integrates this input and its output can then be connected to a CT block. The low power SC block (Type ASE) is automatically enabled whenever the CT block is powered up. Refer to the ACE0xCR2 register definition in this chapter. Figure 24-11. Analog Switch Capacitor PSoC Bloc CT Comp Bus 450 Integrator To CT Block Application Description for the SC Block The Analog Switched Capacitor (SC) blocks support DACs for comparator references. This application requires the use of one CT block. Analog-to-digital conversions can be done with a firmware-based successive approximation algorithm, using the SC block to provide a DAC reference. The integrator speed can be modified to trade off accuracy for settling time. 24.2 Swtiched Capacitor Digital Blocks 24.1.6.1 PSoC Device Distinctions The following are PSoC device distinctions for the CY8C28xxx PSoC devices. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Two Column Limited Analog System 1. The continuous time (CT) blocks of the limited analog column in the CY8C28xxx PSoC devices differ from other PSoC devices in the following ways: ❐ The CT amplifier can only be configured as unity gain or open loop (comparator). ❐ No separate low power comparator is available; however, this CT block amplifier is inherently low power and may be useful as a sleep mode comparator in many applications. ❐ The column comparator bus is always driven from the CT block. When the CT amplifier is configured in Unity Gain mode, CompBus should be set to zero and the block outputs a zero on the comparator bus. 2. In the CY8C28xxx PSoC devices, the switched capacitor (SC) block consists of a low power integrator that is enabled whenever the CT block is enabled. It can be used to create a DAC reference for a CT comparator. The only configuration of the internal state of the SC block available to the user is input and output connections, and integrator speed by way of the FCap register bit. 3. The CY8C28xxx PSoC devices can use a VC3-based control for analog-to-digital conversion. 4. For the CY8C28xxx PSoC devices, all GPIO pins can connect to the internal analog mux bus. However, there are two analog mux buses in the CY8C28xxx. The odd bits GPIOs connect to left side analog mux bus (except P0[7]). The even bits GPIOs connect to right side analog mux bus (include P0[7]). 5. The temperature sensor input (VTEMP) is connected through the ACE01 PMux. There is no special ground reference for the signal. CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F 451 Two Column Limited Analog System 24.3 Register Definitions The following registers are associated with the CY8C28xxx PSoC devices and are listed in address order within their system resource configuration. For a complete table of all analog system registers for all other PSoC devices, refer to the “Summary Table of the Analog Registers” on page 389. Each register description has an associated register table showing the bit structure for that register. Register bits that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow. 24.3.1 Summary Table for Two Column Limited Analog System Registers The following table lists the registers that are used in the CY8C28xxx PSoC devices, in address order within their system resource configuration. Note that there are no registers associated with the CY8C28xxx for the analog reference in the two column limited analog system, because there are no configuration options for that function. The bits that are grayed out are reserved bits. Reserved bits should always be written with a value of ‘0’. Table 24-5. Summary Table for Two Column Limited Analog System Registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 Access : POR Value DCLKS[0] RW : 00 DCLKS[1] RW : 00 Bit 1 ANALOG INTERFACE REGISTERS (page 453) 0,E6h DEC_CR0 ACC_IGEN[3:0] 0,E7h DEC_CR1 1,E5h ADC0_TR CAPVAL_[7:0] RW : 00 1,E6h ADC1_TR CAPVAL_[7:0] RW : 00 1,73h ACE_AMD_CR0 1,75h ACE_AMX_IN 1,76h ACE_CMP_CR0 COMP[5:4] 1,77h ACE_CMP_CR1 CLDIS[5:4] IDEC ICLKS[0] ICLKS0[3] ICLKS0[2] ICLKS0[1] ACE_IGEN[2:0] DCLKS[3] DCLKS[2] CY8C28XXX REMAPPING, PSoC BLOCK, TYPE E, REGISTERS (page 454) 1,79h ACE_CMP_GI_EN 1,7Ah ACE_ALT_CR0 1,7Bh ACE_ABF_CR0 1,7Dh ACE00CR1 1,7Eh ACE00CR2 AMOD4[3:0] ACI5[1:0] GIO5 GIO1 SEL5[1:0] AIN[5:4] GIO4 NMux[2:0] ACE_PWM_CR 1,86h ACE_ADC0_CR CMPST LOREN SHEN CBSRC 1,87h ACE_ADC1_CR CMPST LOREN SHEN CBSRC 1,89h ACE_CLK_CR0 1,8A ACE_CLK_CR1 1,8Bh ACE_CLK_CR3 ASE11CR0 RW : 00 FullRange 1,85h 1,8Fh RW : 00 RW : 00 PMux[2:0] ASE10CR0 ACE01CR1 SEL4[1:0] RW : 00 CompBus ACE_AMD_CR1 ACE01CR2 GIO0 ACE0Mux 1,83h 1,8Dh # : 00 LUT4[3:0] 1,7Fh 1,8Eh RW : 00 RW : 00 LUT5[3:0] ACE1Mux RW : 00 ACI4[1:0] PWR FVal RW : 00 RW : 00 AMOD5[3:0] HIGH[2:0] PWMEN RW : 00 AUTO ADCEN # : 00 AUTO ADCEN AColumn5[1:0] ACLK5[3:0] SYS5 CompBus RW : 00 LOW[1:0] RW : 00 DIVCLK4[1:0] RW : 00 ACLK4[3:0] DIVCLK5[1:0] NMux[2:0] SYS4 # : 00 AColumn4[1:0] RW : 00 PMux[2:0] FullRange FVal RW : 00 PWR RW : 00 RW : 00 LEGEND x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. # Access is bit specific. Refer to the Register Details chapter on page 125. 452 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *F Two Column Limited Analog System Analog Interface Registers 24.3.2 Add. 0,E6h DEC_CR0 Register Name DEC_CR0 Cols. Bit 7 4, 2 Bit 6 Bit 5 The Decimator Control Register 0 (DEC_CR0) contains control bits to access hardware support for both the Incremental ADC and the DELISG ADC. This register can only be used with four and two analog column PSoC devices. Bits 7 to 4: ACC_IGEN[3:0]. For incremental support, these bits select which column comparator bit will be gated by the output of a digital block. The output of that digital block is typically a PWM signal; the high time of which corresponds to the ADC conversion period. This ensures that the comparator output is only processed for the precise conversion time. The digital block selected for the gating function is controlled by ICLKS0 in this register, and ICLKS3, ICLKS2 and ICLKS1 bits in the DEC_CR1 register. Bit 3: ICLKS0. In conjunction with ICLKS1, ICLKS2, and ICLKS3 in the DEC_CR1 register, these bits select up to one of 16 digital blocks (depending on the PSoC device resources) to provide the gating signal for an incremental ADC conversion. 24.3.3 Address 0,E7h Bit 4 ACC_IGEN[3:0] Bit 3 ICLKS[0] Bit 2 Bit 1 ACE_IGEN[1:0] Bit 0 Access DCLKS0 RW : 00 Bits 2 and 1: ACE_IGEN[1:0]. For incremental support, these bits select which type E column comparator bit will be gated by the output of a digital block. The output of that digital block is typically a PWM signal, the high time of which corresponds to the ADC conversion period. This ensures that the comparator output is only processed for the precise conversion time. The digital block selected for the gating function is controlled by ICLKS[3:0] Bit 0: DCLKS0. The decimator requires a timer signal to sample the current decimator value to an output register that may subsequently be read by the CPU. This timer period is set to be a function of the DELSIG conversion time and may be selected from up to one of twelve digital blocks (depending on the PSoC device resources) with DCLKS0 in this register and DCLKS3, DCLKS2, and DCLKS1 in the DEC_CR1 register. If the Decimation Rate bits are set in DECx_CR this setting is overwritten For additional information, refer to the DEC_CR0 register on page 212. DEC_CR1 Register Name DEC_CR1 Cols. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 4 Bit 7 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 RW : 00 2 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 RW : 00 The Decimator Control Register 1 (DEC_CR1) is used to configure the decimator prior to using it. ter select the digital block sources for Incremental and DELSIG ADC hardware support (see the DEC_CR0 register). This register can only be used with four and two analog column PSoC devices. For additional information, refer to the DEC_CR1 register on page 213. Depending on how many analog columns your PSoC device has (see the Cols. column in the register table above), only certain bits are accessible to be read or written. Bit 6: IDEC. Any function using the decimator requires a digital block timer to sample the current decimator value. Normally, the positive edge of this signal causes the decimator output to be sampled. However, when the IDEC bit is set, the negative edge of