DC393A - Demo Manual

DEMO MANUAL DC393
LTC1564 FILTER BOARD
Evaluation Board for
LTC1564 Digitally Controlled
Antialiasing Filter and 4-Bit P.G.A.
U
DESCRIPTIO
Some key features of this demo circuit include:
• 4-bit digitally controlled 8th order lowpass filter
• fC = 10kHz to 150kHz in 10kHz steps
• 4-bit digitally controlled programmable gain amplifier
• G = 1 to 16 in 1V/V steps
• 100dB attenuation at 2.5 • fC
• Rail-to-rail input and output range
• Miniature 16-Pin SSOP package
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
This demonstration circuit allows the user to evaluate the
LTC®1564 digitally controlled antialiasing filter. The cutoff
frequency (fC) and passband gain are fully programmable
while the shape of the lowpass response is fixed. A
latching digital interface stores fC and gain settings or it
can be bypassed for control directly from the pins through
either the on-board toggle switches or using the optional
connector to control the pins externally. The LTC1564
operates from 2.7V to 10V total supply voltage (single or
split supplies) and comes in a 16 pin surface mount SSOP.
This board demonstrates proper layout, bypassing and
optional buffering to achieve best performance. Applications include DSP antialiasing and reconstruction filtering,
communications and instruments with high dynamic range,
up to 20 bits, and sampling rates to 300+ kilosamples per
second.
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TYPICAL PERFOR A CE CHARACTERISTICS A D BOARD PHOTO
Demo Circuit
Frequency Response
40
20
0
GAIN (dB)
–20
–40
–60
D
B
–80
C
–100
A
–120
–140
0.1
1
fIN/fC
10
393A TA01
A: fC = 10kHz, GAIN = 1, VIN = 1VRMS
B: fC = 10kHz, GAIN = 16, VIN = 62.5mVRMS
C: fC = 150kHz, GAIN = 1, VIN = 1VRMS
D: fC = 150kHz, GAIN = 16, VIN = 62.5mVRMS
dc393f
1
6
5
LOGIC 0
7
8
10
9
11
12
3
UP
1 0
SW2
OUT
OPOUT
4
2
1
5 4 3 2
1
5 4 3 2
1
C3
OPT
C12
OPT
R2
OPT
C11
OPT
R14
OPT
4 C2 0.1µF OPT
F3
13 RST
12 G3
11 G2
10 G1
9
3
4
5
6
7
8
EN
CS/HOLD
F3
F2
F1
F0
G PACKAGE
16-LEAD PLASTIC SSOP
14 V +
2
G0
15 AGND
1
V–
TOP VIEW
LTC1564
F2
OUT
F1
V+
V–
SGND
V–
V–
V+
8
R20 220Ω
F0
F0
7
R19 220Ω
4
3
F1
R16 220Ω
R15 220Ω
2
1
JP1
6
16 IN
C4
0.1µF
R3
0Ω
CS
R13
10k
V+
AGND
IN
U2
C7
10µF
16V
C8
10µF
16V
F0
F1
F2
9
JP4
LOGIC 1
2
R25 220Ω
R24 220Ω
R23 220Ω
R22 220Ω
LOGIC 0
RETURN
2
LOGIC 0
1 JP2 3
2 DUAL
SUPPLY
RST
C6
1µF
LOGIC 0
LOGIC 1
C5
0.1µF
R21 220Ω
V+
3 JP3 1
1
10
11
12
13
14
15
16
SINGLE
SUPPLY
G0
G1
G2
G3
CS/HOLD RST
EN
V–
OUT
LTC1564CG
F3
R12
10k
RST
LOGIC 1 LOGIC 1
ENABLE
2
3
R18 220Ω
R7
10k
V–
C10 OPT 3528
LOGIC 1
LOGIC 0
1
F2
R6
10k
OPV –
–
C1 0.1µF OPT
+ 7
R5
10k
2
3
R27
10k
5
R4
10k
U1 TBD
C9 OPT 3528
EN
R17 220Ω
LOGIC 1
F3
OPV –
R1 SGND
OPT
OPV +
OPV +
+
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0805; ALL CAPACITORS ARE IN MICROFARADS, 0805
2. SWITCHES ARE SHOWN WITH ROCKER IN “UP” POSITION, GIVING A LOGIC 1 STATE
J3
OUT
OUT
OPOUT
J2
OPOUT
OPT
AGND
+
2
LOGIC 1
0
1
G3
R8
10k
CS
1
6
R9
10k
2
G2
5
G1
R10
10k
RST
3
UP
4
G0
G0
G1
G2
G3
R11
10k
SW3
LOGIC 0
6
5
4
3
2
1
UP
1 0
SW1
R26
OPT
1
3
5
7
9
11
13
15
17
19
21
23
J4
IN
IN
393 Schem1
AGND
SGND
LOGIC 0
7
8
9
10
11
12
2 3 4 5
1
1
3
5
7
9
11
13
15
17
19
21
23
J1
2
4
6
8
10
12
14
16
18
20
22
24
IN
LOGIC 0
2
4
6
8
10
12
14
16
18
20
22
24
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W
AGND
PACKAGE A D SCHE ATIC DIAGRA
W
SGND
DEMO MANUAL DC393
LTC1564 FILTER BOARD
dc393f
DEMO MANUAL DC393
LTC1564 FILTER BOARD
PARTS LIST
REFERENCE
(2) AGND, (3) SGND,
F0–F3, G0–G3, IN, OUT,
CS, RST, EN, V +, V –,
LOGIC 0, LOGIC 1,
OPV +, OPV –, OPOUT
C1–C3, C9–C12
QUANTITY
25
DESCRIPTION
VENDOR
2501-2
1-Pin Terminal Turret, 0.094"
MILL-MAX
TELEPHONE
(516) 922-6000
TBD
Capacitor
TBD
C4, C5
2
0805ZC104MAT1A
0.1µF 10V X7R Capacitor
AVX
(843) 946-0362
C6
1
0805ZC105MAT1A
1µF 10V X7R Capacitor
AVX
(843) 946-0362
2
(408) 573-4150
C7, C8
Optional
PART NUMBER
EMK325BJ106MN
10µF 16V, 20% 1210 XR5 Capacitor
Taiyo Yuden
J1
Optional
TBD
Header
TBD
J2
Optional
TBD
BNC
TBD
J3, J4
2
112404
BNC
Connex
(805) 378-6464
JP1, JP2, JP3
3
3801S-3G2
Header, 3 Pins 1 Row 0.1"cc
Comm Con
(626) 301-4200
JP4
1
3801S-2G2
Header, 2 Pins 1 Row 0.1"cc
Comm Con
(626) 301-4200
(626) 301-4200
JP1–JP4
R1, R2, R14, R26
4
Optional
CCIJ230-G
Shunts for JP1–JP4 , 0.1"cc
Comm Con
TBD
Resistor
TBD
R3
1
CJ10-000M
0Ω 1/16W 5% Resistor
AAC
(800) 508-1521
R4–R13, R27
11
CR10-103JM
10k 1/16W 5% Resistor
AAC
(800) 508-1521
R15–R25
11
CR10-221JM
220Ω 1/16W 5% Resistor
AAC
(714) 255-9186
SW1, SW2
2
76STC04
Switch SPDT-4 FORM C
Gray Hill
(708) 354-1040
1
76STC02
Switch SPDT-2 FORM C
Gray Hill
(708) 354-1040
TBD
IC
TBD
LTC1564CGN
IC
LTC
SW3
U1
Optional
U2
1
(408) 432-1900
U
OPERATIO
Demo Board Operation and Connection Hints
When using the DC393 demo board, the following steps
should be taken to ensure proper operation for evaluating
the LTC1564. This demo board was designed for either
single or dual supply operation.
The LTC1564 has only three analog pins: input, output and
a half-supply reference voltage point, AGND. The other
pins are digital controls and power supply.
Step 1: Check the JP1 Jumper Setting. This jumper is the
digital chip enable input for the LTC1564. Install the
jumper between Pins 1 and 2 for normal operation
(EN = 0) or between pins 2 and 3 (EN = 1) for shutdown
mode with reduced supply current. The active circuitry in
the LTC1564 shuts off and its output assumes a high
impedance state. If F and G bits are latched (CS/HOLD = 1)
during the shutdown state, the latch will retain its
contents.
Step 2: Check the JP2 Jumper Setting. The LTC1564’s
CMOS-level inputs accept CMOS logic levels, either railto-rail or, alternatively, 0V and 5V when the part is operated from ±5V supplies. Jumper JP2 sets the logic 0 level
to either SGND or V –. Install the jumper between Pins 1
and 2 for logic 0 = V – or between Pins 2 and 3 for
logic 0 = SGND.
Step 3: Check the JP3 Jumper Setting. Used for selecting
single or dual power supply operation. Install the jumper
between Pins 1 and 2 for dual supply or between Pins 2
and 3 for single supply.
dc393f
3
DEMO MANUAL DC393
LTC1564 FILTER BOARD
U
OPERATIO
Step 4: Check the JP4 Jumper Setting. This jumper when
installed connects the 10k pull-up resistors to V + for all
digital inputs of the LTC1564.
Step 5: Check the SW1 Switch Positions. The four
switches labeled G3, G2, G1, G0 create a 4-bit binary word
for the LTC1564’s digital gain control (“G Code”) inputs.
G3 is the most significant bit (MSB). These switches
program the LTC1564’s passband gain through the internal latch, which passes the bits directly when the CS/HOLD
input is at logic 0. When CS/HOLD changes to logic 1, the
G switches cease to have effect and the latch retains the
previous input values. This gain control is linear in amplitude: nominal passband gain of the LTC1564 is the binary
value of the G code plus one, as shown in Table 1.
Step 6: Check the SW2 Switch Positions. The four
switches labeled F3, F2, F1, F0 create a 4-bit binary word
for the LTC1564’s digital frequency control (“F Code”)
inputs. F3 is the most significant bit (MSB). These switches
program the LTC1564’s cutoff frequency fC through the
internal latch, which passes the bits directly when the
CS/HOLD input is at logic 0. When CS/HOLD changes to
logic␣ 1, the F pins cease to have effect and the latch holds
the previous values. The F code control is the filter’s cutoff
frequency fC in 10kHz steps up to 150kHz, as summarized
in Table 2. Thus fC is proportional to the binary value of the
F code.
The frequency setting (“F”) and gain setting (“G”) are each
four-bit codes entered through the F and G digital input
pins (Table 3). Also, setting the F code to 0000 engages a
“mute” state where the filter remains fully powered but the
input pin is disconnected inside the LTC1564 and output
noise becomes even lower than in normal filter operation.
Step 7: Check the SW3 Switch Positions. The CS/HOLD
switch is the digital enable input for the internal latch
holding F and G bits. Logic 0 makes the latch transparent
so that the F and G switches directly control the filter’s
cutoff frequency and gain. Logic 1 holds the last values of
these switches prior to the transition. The RST switch is
the digital asynchronous reset input for the internal F and
G latches. Logic 0 at any time will reset these latches to
zero.
Table 1. Programming the LTC1564 Gain
G3
G2
G1
GO
(AT OUTPUT OF INTERNAL LATCH)
NOMINAL
PASSBAND GAIN
(V/V)
(dB)
MAXIMUM INPUT SIGNAL LEVEL
(VP-P)
DUAL 5V
SINGLE 5V SINGLE 3V
NOMINAL
INPUT IMPEDANCE
(k)
0
0
0
0
1
0
10
5
3
10
0
0
0
1
2
6
5
2.5
1.5
5
0
0
1
0
3
9.5
3.33
1.67
1
3.33
0
0
1
1
4
12
2.5
1.25
0.75
2.5
0
1
0
0
5
14
2
1
0.6
2
0
1
0
1
6
15.6
1.67
0.83
0.5
1.67
0
1
1
0
7
16.9
1.43
0.71
0.43
1.43
0
1
1
1
8
18.1
1.25
0.63
0.38
1.25
1
0
0
0
9
19.1
1.1
0.56
0.33
1.11
1
0
0
1
10
20
1
0.5
0.3
1
1
0
1
0
11
20.8
0.91
0.45
0.27
0.91
1
0
1
1
12
21.6
0.83
0.42
0.25
0.83
1
1
0
0
13
22.3
0.77
0.38
0.23
0.77
1
1
0
1
14
22.9
0.71
0.36
0.21
0.71
1
1
1
0
15
23.5
0.67
0.33
0.2
0.66
1
1
1
1
16
24.1
0.63
0.31
0.19
0.63
dc393f
4
DEMO MANUAL DC393
LTC1564 FILTER BOARD
U
OPERATIO
Step 8: Connecting Power Supply Lines. Electrically
clean supplies and a low impedance ground are important
for the high dynamic range and high stopband suppression available from the LTC1564. Low noise linear power
supplies are recommended. Switching supplies can be
used with sufficient filtering to prevent switching noise
coupling into the signal path, reducing dynamic range.
Step 9: Input Connection. Connect the input signal to the
IN BNC connector. The input of the LTC1564 is connected
directly to the IN BNC with an optional R26 shunt resistor
connected to SGND. Table 1 shows how the maximum
input signal level is inversely proportional to the gain of the
filter for different supplies.
Step 10: Output Connection. Connect your monitoring
device (oscilloscope, network analyzer, etc.) to the OUT
BNC connector. The output of the LTC1564 is designed to
drive nominal load of 5kΩ and 50pf. Change the series
resistor R3 from 0Ω to 500Ω for capacitances greater than
50pf. Consult the LTC1564 data sheet for more details on
output loading issues.
Table 2. Programming the LTC1564 Cutoff Frequency
F3
F2
F1
FO
(AT OUTPUT OF INTERNAL LATCH)
NOMINAL fC
(CUTOFF FREQUENCY)
0
0
0
0
0 (Mute State)
0
0
0
1
10kHz
0
0
1
0
20kHz
0
0
1
1
30kHz
0
1
0
0
40kHz
0
1
0
1
50kHz
0
1
1
0
60kHz
0
1
1
1
70kHz
1
0
0
0
80kHz
1
0
0
1
90kHz
1
0
1
0
100kHz
1
0
1
1
110kHz
1
1
0
0
120kHz
1
1
0
1
130kHz
1
1
1
0
140kHz
1
1
1
1
150kHz
Table 3. LTC1564 Digital Controls and Modes
EN RST CS/HOLD
1
1
1
1
F3 F2 Fl FO G3 G2 G1 G0
FUNCTION
1
X
X
X
X
X
X
X
X
Shutdown Mode. Filter Disabled.
Latch Holds F and G Inputs Present when Last CS/HOLD = 0
1
0
X
X
X
X
X
X
X
X
Shutdown Mode. Filter Disabled. Latch Accepts F and G Inputs
0
X
X
X
X
X
X
X
X
X
Shutdown Mode. Filter Disabled. Latch Contents (F and G) Reset to All Zeros
0
1
0
0
0
0
0
X
X
X
X
Mute Mode. Reduced Noise
0
0
X
X
X
X
X
X
X
X
X
Mute Mode. Reduced Noise
Latch Contents (F and G) Reset to All Zeros
0
1
1
Other Than 0 0 0 0
X
X
X
X
Normal Filtering Operation. Latch Holds F and G Inputs Present when Last CS/HOLD = 0
0
1
0
Other Than 0 0 0 0
X
X
X
X
Normal Filtering Operation. Filter Responds Directly to F and G Input Pins
X = Don’t Care
dc393f
5
DEMO MANUAL DC393
LTC1564 FILTER BOARD
U
W
PCB LAYOUT A D FIL
Top Silkscreen
Top Solder Paste
Top Solder Mask
dc393f
6
DEMO MANUAL DC393
LTC1564 FILTER BOARD
U
W
PCB LAYOUT A D FIL
Top Layer
Bottom Layer
dc393f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
7
DEMO MANUAL DC393
LTC1564 FILTER BOARD
U
W
PCB LAYOUT A D FIL
Bottom Solder Mask
Bottom Silkscreen
U
PC FAB DRAWI G
2.95in
C
A
HOLE CHART
A
F
B
B
B
B
F
G
B
F
B
F
F
F
B
B
F
B
F
F
F
B
B
F
B
B
G
G
G
D
D
E
D
D
G
G
G
G
2.80in
D
G
G
G
D
B
D
E
D
G
G
D
B
G
D
F
E
G
B
E
G
G
G
C
B
G
B
G
D
B
G
D
B
D
A
D
A
B
B
B
B
B
B
D
NUMBER
SYMBOL DIAMETER OF HOLES
A
0.125
4
B
0.094
26
C
0.070
2
D
0.055
15
E
0.050
4
F
0.035
65
G
0.020
36
TOTAL HOLES
152
PLATED
YES
YES
NO
YES
YES
YES
YES
NOTES: UNLESS OTHERWISE SPECIFIED
1. MATERIAL: FR4 OR EQUIVALENT EPOXY, 2 OZ COPPER CLAD
THICKNESS 0.062 ±0.006 TOTAL OF 2 LAYERS
2. FINISH: ALL PLATED HOLES 0.001 MIN/0.015 MAX COPPER PLATE
ELECTRODEPOSITED TIN-LEAD COMPOSITION
BEFORE REFLOW, SOLDER MASK OVER BARE COPPER (SMOBC)
3. SOLDER MASK: BOTH SIDES USING LPI OR EQUIVALENT
4. SILKSCREEN: USING WHITE NONCONDUCTIVE EPOXY INK
5. UNUSED SMD COMPONENTS SHOULD BE FREE OF SOLDER
6. FILL UP ALL VIAS WITH SOLDER
7. SCORING
0.017
393A FAB Dwg
dc393f
8
Linear Technology Corporation
LT/TP 0902 500 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2002
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