AD1836: Multi-Channel 96kHz Codec Preliminary Data Sheet (Rev. PrC) PDF

PRELIMINARY TECHNICAL DATA
a
Multichannel 96 kHz Codec
AD1836
Preliminary Technical Data
FEATURES
5 V Multichannel Audio System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulators with Data Directed
Scrambling
Data-Directed Scrambling ADCs and DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –92 dB THD + N, 105 dB SNR and Dynamic Range
DACs: –95 dB THD + N, 108 dB SNR and Dynamic Range
On-Chip Volume Control with “Autoramp” Function
Programmable Gain Amplifier for ADC Input
Hardware and Software Controllable Clickless Mute
Digital De-Emphasis Processing
Supports 256 fS, 512 fS, or 768 fS Master Clock
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC ® SPORT
52-Lead MQFP (PQFP) Plastic Package
APPLICATIONS
Home Theatre Systems
Automotive Audio Systems
DVD
Set-Top Boxes
Digital Audio Effects Processors
GENERAL DESCRIPTION
The AD1836 is a high-performance, single-chip codec providing three stereo DACs and two stereo ADCs using ADI’s
patented multibit sigma-delta architecture. An SPI port is
included, allowing a microcontroller to adjust volume and
many other parameters. The AD1836 operates from a 5 V
supply, with provision for a separate output supply to interface
with low-voltage external circuitry. The AD1836 is available
in a 52-lead MQFP (PQFP) package.
FUNCTIONAL BLOCK DIAGRAM
CCLK
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
CDATA CLATCH COUT
MCLK
CONTROL PORT
CLOCK
SERIAL
DATA
I/O
PORT
ALRCLK
ABCLK
ASDATA1
ASDATA2
VOLUME
VOLUME
AIN1L
ADC1L
48/96kHz
DIGITAL
FILTER
48/96kHz
AIN1R
ADC1R
48/96kHz
DIGITAL
FILTER
48/96kHz
VOLUME
VOLUME
VOLUME
AIN2L1
AIN2L2
MUX
CAPL1
PGA
ADC2L
48kHz
DIGITAL
FILTER
48kHz
ADC2R
48kHz
DIGITAL
FILTER
48kHz
VOLUME
DIGITAL
FILTER
DAC
DIGITAL
FILTER
DAC
DIGITAL
FILTER
DAC
MUX
AIN2R1
PGA
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
FILTD
CAPL2
CAPR1
AIN2R2
AOUT1
VREF
FILTR
CAPR2
PWRDWN/RESET
2
4
3
AVDD
AGND
DVDD
2
DGND
SHARC is a registered trademark of Analog Device, Inc.
REV. PrC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
PRELIMINARY TECHNICAL DATA
AD1836–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)
Ambient Temperature
Master Clock
Input Signal
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
Input Voltage HI
Input Voltage LO
5.0 V
25°C
12.288 MHz, (48 kHz fS, 256 × fS Mode)
1.000 kHz, 0 dBFS (Full Scale)
48 kHz
20 Hz to 20 kHz
20 Bits
100 pF
47 kΩ
2.4 V
0.8 V
NOTE
Performance of all channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ANALOG PERFORMANCE
Min
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution (all ADCs)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter
With A-Weighted Filter
Total Harmonic Distortion + Noise
Interchannel Isolation
Interchannel Gain Mismatch
Programmable Input Gain
Gain Step Size
Offset Error
Full-Scale Input Voltage At Each Pin (Single-Ended)
Gain Drift
Input Resistance
Input Capacitance
Common-Mode Input Volts
Typ
Max
24
Bits
102
105
–92
100
0.01
12
3
dB
dB
dB
dB
dB
dB
dB
LSB
V rms (V p-p)
ppm/°C
kΩ
pF
V
1.0 (2.8)
100
10
15
2.25
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter
With A-Weighted Filter
Total Harmonic Distortion + Noise
Interchannel Isolation
Interchannel Gain Mismatch
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
Mute Attenuation
De-Emphasis Gain Error
Full-Scale Output Voltage At Each Pin (Single-Ended)
Output Resistance At Each Pin
Common-Mode Output
105
108
–95
100
0.01(0.12)
± 3.0
0.01
150
–120
± 0.1
0.098
60
–100
± 0.1
1.0 (2.8)
115
2.25
–2–
Unit
dB
dB
dB
dB
dB (%)
%
%
dB
ppm/°C
dB
Degrees
%
dB
dB
dB
V rms (V p-p)
Ω
V
REV. PrC
PRELIMINARY TECHNICAL DATA
AD1836
DIGITAL FILTERS at 44.1 kHz
Min
Typ
Max
Unit
ADC DECIMATION FILTER
Pass Band
Pass Band Ripple
Transition Band
Stop Band
Stop Band Attenuation
Group Delay
20
± 0.0001
22
24
120
TBD
kHz
dB
kHz
kHz
dB
µs
DAC INTERPOLATION FILTER
Pass Band
Pass Band Ripple
Transition Band
Stop Band
Stop Band Attenuation
Group Delay
20
± 0.01
22
24
70
TBD
kHz
dB
kHz
kHz
dB
µs
TIMING
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
MCLK High
tMH
min
max
ns
256 × fS
512 × fS
768 × fS
MCLK Low
MCLK Period
MCLK Freq
PD/RST Low
min
min
min
4500
max
max
max
ns
ns
ns
MCLK Periods
Reset to SPI Register Write
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Hold
COUT Three-State
min
min
min
min
min
min
min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
min
min
min
max
min
min
min
min
ns
ns
ns
ns
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
min
min
min
ns
ns
ns
ns
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
tML
tMCLK
fMCLK
tPDR
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCODE
tCOD
tCOH
tCOTS
DAC SERIAL PORT
Normal Modes
tDBH
DBCLK High
DBCLK Low
tDBL
tDBP
DBCLK Period
fDB
DBCLK Freq
DLRCLK Setup
tDLS
tDLH
DLRCLK Hold
tDDS
DSDATA Setup
DSDATA Hold
tDDH
Packed 128, 256 Modes
tDBH
DBCLK High
DBCLK Low
tDBL
tDBP
DBCLK Period
fDB
DBCLK Freq
DLRCLK Setup
tDLS
tDLH
DLRCLK Hold
tDDS
DSDATA Setup
tDDH
DSDATA Hold
REV. PrC
max
max
min
max
max
min
min
min
min
–3–
PRELIMINARY TECHNICAL DATA
AD1836–SPECIFICATIONS
TIMING (continued)
Parameter
Max
Unit
Comments
ABCLK Delay High
max
ns
tABL
ABCLK Delay Low
max
ns
tALS
tABDD
tALRDD
LRCLK Delay
ASDATA Delay
ASDATA Delay
max
max
max
ns
ns
ns
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
max
ns
ADC Serial Port
Normal Modes
tABH
Min
Packed 128, 256 Modes
ABCLK Delay High
tABH
tABL
ABCLK Delay Low
max
ns
tALS
tABDD
tALRDD
LRCLK Delay
ASDATA Delay
ASDATA Delay
max
max
max
ns
ns
ns
max
ns
TDM PACKED AUX, MASTER MODE
ABCLK Delay High
tABH
tABL
ABCLK Delay Low
max
ns
tXBH
AUXBCLK Delay High
max
ns
tXBL
AUXBCLK Delay Low
max
ns
tALS
tXLS
tABDD
tALRDD
LRCLK Delay
AUXLRCLK Delay
ASDATA Delay
ASDATA Delay
max
max
max
max
ns
ns
ns
ns
tDDS
tDDH
tDDS
tDDH
tDXDD
tDXDD
AAUXDATA Setup
AAUXDATA Hold
DSDATA Setup
DSDATA Hold
DAUXDATA Delay
DAUXDATA Delay
max
max
ns
ns
ns
ns
ns
ns
min
min
min
min
–4–
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256× fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
To AUXBCLK Rising
From AUXBCLK Rising
To DBCLK Rising
From DBCLK Rising
From AUXBCLK Falling
From AUXLRCLK Changing
(Left-Justified)
REV. PrC
PRELIMINARY TECHNICAL DATA
AD1836
TIMING (continued)
Parameter
Min
TDM, PACKED AUX, SLAVE MODE
ABCLK High
tABH
tABL
ABCLK Low
tABP
ABCLK Period
ABCLK Freq
fAB
tALS
LRCLK Setup
tALH
LRCLK Hold
ASDATA Delay
tABDD
tALRDD
ASDATA Delay
tAXDS
tAXDH
tDDS
tDDH
tDXDD
tDXDD
AAUXDATA Setup
AAUXDATA Hold
DSDATA Setup
DSDATA Hold
DAUXDATA Delay
DAUXDATA Delay
Max
Unit
min
min
min
Comments
ns
ns
ns
ns
ns
ns
ns
ns
max
min
min
max
max
min
min
min
min
max
max
To ABCLK Rising
To ABCLK Rising
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
To AUXBCLK Rising
From AUXBCLK Rising
To DBCLK Rising
From DBCLK Rising
From AUXBCLK Falling
From AUXLRCLK Changing
(Left-Justified)
ns
ns
ns
ns
ns
ns
POWER SUPPLIES
Parameter
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current, Power-Down
Digital Current
Digital Current, Power-Down
Dissipation
Operation, Both Supplies
Operation, Analog Supply
Operation, Digital Supply
Power-Down, Both Supplies
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Min
Typ
Max
Unit
4.5
5
108
47
78
1.5
5.5
V
mA
mA
mA
mA
930
540
390
243
mW
mW
mW
mW
–60
–50
dB
dB
TEMPERATURE RANGE
Parameter
Min
Specifications Guaranteed
Functionality Guaranteed
Storage
–40
–65
Max
Unit
+85
+150
°C
°C
°C
25
Specifications subject to change without notice.
REV. PrC
Typ
–5–
PRELIMINARY TECHNICAL DATA
AD1836
ABSOLUTE MAXIMUM RATINGS*
DSDATA2
DVDD
ABCLK
DSDATA3
ALRCLK
MCLK
ASDATA1
ODVDD
ASDATA2
DGND
Power Supplies
Analog (AVDD)
–0.3
6.0
V
Digital (DVDD)
–0.3
6.0
V
Input Current
± 20
mA
(Except Supply Pins)
Analog Input Voltage
–0.3
AVDD + 0.3
V
(Signal Pins)
Digital Input Voltage
–0.3
DVDD + 0.3
V
(Signal Pins)
Ambient Temperature
–40
+85
°C
(Operating)
ESD Tolerance
1
kV
(Human Body Model, Method 3015.2, MIL-STD-883B)
COUT
Unit
CCLK
CLATCH
52 51 50 49 48 47 46 45 44 43 42 41 40
DVDD 1
CDATA 2
39
PIN 1
IDENTIFIER
38
PD/RST 3
OUTLP3 4
37
36
OUTLN3 5
OUTLP2 6
35
OUTLN2 7
OUTLP1 8
34
TOP VIEW
(Not to Scale)
33
32
DGND
DSDATA1
DBCLK
DLRCLK
OUTRP3
OUTRN3
OUTRP2
OUTRN2
OUTLN1 9
AVDD 10
31
AGND 11
FILTD 12
29
28
AGND
AGND
FILTR 13
27
CAPR2
30
OUTRP1
OUTRN1
CAPR1
ADC2INR2
ADC2INR1
ADC2INL1
ADC2INL2
CAPL2
CAPL1
14 15 16 17 18 19 20 21 22 23 24 25 26
ADC1INRN
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AD1836
ADC1INLN
ADC1INRP
Max
AVDD
ADC1INLP
Min
AGND
Parameter
PIN CONFIGURATION
52-Lead MQFP
ORDERING INFORMATION
Model
Temperature
Range
Package
Description
Package
Option
AD1836AS
–40 to +85°C
52-Lead MQFP
S-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1836 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–6–
WARNING!
ESD SENSITIVE DEVICE
REV. PrC
PRELIMINARY TECHNICAL DATA
AD1836
PIN FUNCTION DESCRIPTIONS
PIN
No.
Mnemonic
In/Out
Description
1, 40
2
3
4
5
6
7
8
9
10, 15
11, 14, 28, 29
12
13
16
17
18
19
20
DVDD
CDATA
PD/RST
OUTLP3
OUTLN3
OUTLP2
OUTLN2
OUTLP1
OUTLN1
AVDD
AGND
FILTD
FILTR
ADC1INLP
ADC1INLN
ADC1INRP
ADC1INRN
ADC2INL+/CAPL2
I
I
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
21
ADC2INL–/CAPL1
I
22
ADC2INL1
I
23
ADC2INL2
I
24
ADC2INR2
I
25
ADC2INR1
I
26
ADC2INR–/CAPR1
I
27
ADC2INR+/CAPR2
I
30
31
32
33
34
35
36
37
38
39, 52
41
42
43
44
45
46
47
48
49
50
51
52
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
OUTRP3
DLRCLK
DBCLK
DSDATA1
DGND
DSDATA2
DSDATA3
ABCLK
ALRCLK
MCLK
ODVDD
ASDATA1
ASDATA2
COUT
CLATCH
CCLK
DGND
O
O
O
O
O
O
I/O
I/O
I
I
I
I
O
O
I
I
O
O
O
I
I
I
Digital Power Supply. Connect to digital 5 V supply.
Serial Control Input
Power-Down Reset
DAC 3 (Left) Positive Output
DAC 3 (Left) Negative Output
DAC 2 (Left) Positive Output
DAC 2 (Left) Negative Output
DAC 1 (Left) Positive Output
DAC 1 (Left) Negative Output
Analog Power Supply. Connect to analog 5 V.
Analog Ground
Filter Capacitor Connection. Recommend 10 µF//100 nF.
Voltage Reference Filter Capacitor Connection. Recommend 10 µF//100 nF.
ADC1 Left Positive Input
ADC1 Left Negative Input
ADC1 Right Positive Input
ADC1 Right Negative Input
ADC2 Left Positive Input (Direct Mode)/ADC2 Left Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Left Negative Input (Direct Mode)/ADC2 Left Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Left Input 2 (MUX/PGA Mode)/Left Positive Input (PGA Differential Mode)
ADC2 Left Input 1 (MUX/PGA Mode)/Left Negative Input (PGA Differential Mode)
ADC2 Right Input 1 (MUX/PGA Mode)/Right Negative Input (PGA
Differential Mode)
ADC2 Right Input 2 (MUX/PGA Mode)/Right Positive Input (PGA
Differential Mode)
ADC2 Right Negative Input (Direct Mode)/ADC2 Right Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Right Positive Input (Direct Mode)/ADC2 Right Decoupling Cap
(MUX/PGA and PGA Differential Mode)
DAC 1 (Right) Negative Output
DAC 1 (Right) Positive Output
DAC 2 (Right) Negative Output
DAC 2 (Right) Positive Output
DAC 3 (Right) Negative Output
DAC 3 (Right) Positive Output
LR Clock for DACs
Bit Clock for DACs
DAC Input #1 (Input to DAC1 and DAC2)
Digital Ground
DAC Input #2 (Input to DAC3 and DAC4)
DAC Input #3 (Input to DAC5 and DAC6)
Bit Clock for ADCs
LR Clock for ADCs
Master Clock Input
Digital Output Driver Power Supply
ADC Serial Data Output #1
ADC Serial Data Output #2
Output for Control Data
Latch Input for Control Data
Control Clock Input for Control Data
Digital Ground
REV. PrC
–7–
PRELIMINARY TECHNICAL DATA
AD1836
AVDD
DVDD
2
AIN1L
MUX
AIN2R
PGA
L/R
ADC2L/R
48/96kHz
(MAX)
ODVDD
1
DECIMATION
FILTER
48/96kHz
ADCI L/R
48/96kHz
AIN1R
CAPL
AIN2L
2
DECIMATION
FILTER
48kHz (MAX)
SDOUT1
ADC
SERIAL
INTERFACE
OUTR1
OUTL2
OUTR2
OUTL3
OUTR3
ABCLK
ALRCLK
CAPR
OUTL1
SDOUT2
MCLK
DAC 1
L/R
INTERPOLATION
FILTER
VOLUME
CONTROL
DAC 2
L/R
INTERPOLATION
FILTER
VOLUME
CONTROL
DAC 3
L/R
INTERPOLATION
FILTER
VOLUME
CONTROL
DLRCLK
DAC
SERIAL
INTERFACE
DBCLK
SDIN1
SDIN2
SDIN3
RESET
CCLK
FILTR
VREF
AGND
4
SPI
CONTROL
PORT
AD1836
FILTD
DGND
2
CLATCH
CDATA
COUT
Figure 1.
FUNCTIONAL OVERVIEW
ADCs
ADC peak level information for each ADC may be read from
the SPI port through Registers 12 through 15. The data is supplied as a 10-bit word with a maximum range of 0 dB to –60 dB
and a resolution of 1 dB. The registers will hold peak information until read; after reading, the registers are reset so that new
peak information can be acquired. Refer to the register description for details of the format.
There are four ADC channels in the AD1836, configured as two
independent stereo pairs. One stereo pair is the primary ADC and
has fully differential inputs. The second pair can be programmed
to operate in one of three possible input modes (programmed
via SPI ADC Control Register 3). The ADC section may also
operate at a sample rate of 96 kHz, with only the two primary
channels active. The ADCs include an on-board digital decimation filter with 120 dB stopband attenuation and linear phase
response, operating at an oversampling ratio of 128 (for 4-channel
48 kHz operation) or 64 (for two-channel 96 kHz operation).
The voltage at the VREF pin, FILTR (~2.25 V) can be used to
bias external op amps used to buffer the input signals. This
source can be connected directly to op amp inputs but should
be buffered if it is required to drive resistive networks.
DACs
The primary ADC pair should be driven from a differential
signal source for best performance. The input pins of the primary ADC connect directly to internal switched capacitors. To
isolate the external driving op amp from the “glitches” caused
by the internal switched-capacitors, each input pin should be
isolated by using a series-connected external 100 Ω resistor
together with a 1 nF capacitor connected from each input to
ground. This capacitor must be of high quality; for example,
ceramic NPO or polypropylene film.
The AD1836 has six DAC channels arranged as three independent stereo pairs, with six fully differential analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through three
serial data input pins (one for each stereo pair) and a common
frame (DLRCLK) and bit (DBLCK) clock. Alternatively, one
of the “packed data” modes may be used to access all six channels on a single TDM data pin.
The secondary input pair can be operated in one of the following three modes:
Each set of differential output pins sits at a dc level of VREF, and
swings ± 1.4 V for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high-frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. A recommended
circuit is shown in Figure 2. Note that the use of op amps with
low slew rate or low bandwidth may cause high-frequency noise
and tones to fold down into the audio band; care should be
exercised in selecting these components.
1. Direct differential inputs (driven the same as the primary
ADC inputs described above).
2. PGA mode with differential inputs (Figure 13). In this mode,
the PGA amplifier can be programmed using the SPI port to
give an input gain of 0 to 12 dB in 3 dB steps. External
capacitors are used after the PGA to supply filtering for the
switched-capacitor inputs.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases this capacitor may be eliminated with little effect on
performance. The voltage at the VREF pin, FILTR (~2.25 V) can
be used to bias external op amps used to buffer the output signals.
3. Single-ended MUX/PGA mode. In this mode, two singleended stereo inputs are provided that can be selected using
the SPI port. Input gain can be programmed from 0 dB to
12 dB in steps of 3 dB External capacitors are used to supply
filtering for the switched-capacitor inputs.
–8–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD1836
CLATCH
CCLK
CDATA
COUT
D15
D14
D0
D9
D8
D0
Figure 2. Format of SPI Signal
Clock Signals
The master clock frequency can be selected for 256, 512, or
768 times the sample rate. The default at power-up is 256 fS.
For operation at 96 kHz, the master clock frequency should
stay at the same absolute frequency. For example, if the AD1836
is programmed in 256 × fS mode and operated in the normal
48 kHz 4-channel mode, the frequency of the master-clock
would be 256 × 48 kHz = 12.288 MHz. If the AD1836 is then
switched to 96 kHz operation (via writing to the SPI port), the
frequency of the master-clock should remain at 12.288 MHz
(which is now 128 × fS).
The internal clock used in the AD1836 is 512 × fS (48 kHz
mode) or 512 × fS (96 kHz mode). Clock doublers are used to
generate this internal master-clock from the external clocks.
Since clock-doublers have a limited range of operation, it is
recommended that the part be operated in 512 × fS mode if the
desired sampling rates are not at all close to the common audio
sampling rates for which the part was designed.
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal should not be passed through an
FPGA or other large digital chip before being applied to the
AD1836. In most cases this will induce clock jitter due to the
fact that the clock signal is sharing common power and ground
connections with other unrelated digital output signals.
The six DAC channels use a common serial bit clock to clock in
the serial data and a common left-right framing clock. The four
ADC channels output a common serial bit clock and a left-right
framing clock. The clock signals are all synchronous with the
sample rate.
RESET and Power-Down
RESET will power down the chip and set the control registers
to their default settings. After reset is deasserted, an initialization
routine will run inside the AD1836 to clear all memories to zero.
This initialization lasts for approximately 20 LRCLK intervals.
During this time it is recommended that no SPI writes occur.
DACs and for reading the ADC signal level from the internal
peak detectors. The DAC output levels may be independently
programmed by means of an internal digital attenuator adjustable in 1024 linear steps.
The SPI control port is a 4-wire serial control port. The format is
similar to the Motorola SPI format except the input data word
is 16-bits wide. Max serial bit clock frequency is 8 MHz and
may be completely asynchronous to the sample rate of the ADCs
and DACs. The following figure shows the format of the SPI
signal. Note that the CCLK should be run continuously and not
stop between SPI transactions.
Power Supply and Voltage Reference
The AD1836 is designed for 5 V supplies. Separate power supply pins are provided for the analog and digital sections. These
pins should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 µF should also be
provided on the same PC board as the codec. For critical applications, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be
isolated by means of two ferrite beads in series with the bypass
capacitor of each supply. It is important that the analog supply
be as clean as possible.
The internal voltage reference is brought out on Pin 13 (FILTR)
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 µF and 100 nF. The reference voltage may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the VREF pin should be limited to less than 50 µA.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 8 and 9 in ADC Control
Register 2, the serial mode can be changed to Right-Justified
(RJ), Left-Justified DSP (DSP) or Left-Justified (LJ). In the RJ
mode, it is necessary to set Bits 6 and 7 to define the width of
the data word.
The DAC serial data input mode defaults to I2S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1 or Packed Mode 2.
Serial Control Port
The AD1836 has an SPI-compatible control port to permit
programming the internal control registers for the ADCs and
REV. PrC
–9–
PRELIMINARY TECHNICAL DATA
AD1836
The word width defaults to 24 bits but can be changed by
reprogramming Bits 3 and 4 in DAC Control Register 1. The
packed modes accept six channels of data at the DSDATA1
input pin which is independently routed to each of the six
internal DACs.
LRCLK and BCLK signals, and the external ADCs operate in
slave mode. In the “slave” mode, the external ADCs provide the
LRCLK and BCLK signals (which must be divided down properly from the external master clock), and the AD1836 will sync
to these external clocks. See Figures 8 through 10 for details of
this mode. Figure 11 shows the internal signal-flow diagram of
the auxiliary mode.
A special “auxiliary mode” is provided to allow two external
stereo ADCs and one external stereo DAC to be interfaced to
the AD1836 to provide 8-in/8-out operation. In addition, this
mode supports glueless interface to a single SHARC DSP serial
port, allowing a SHARC DSP to access all eight channels of
analog I/O. In this special mode, many pins are redefined; see
Table I for a list of redefined pins. Two versions of this mode
are available. In the “master” mode, the AD1836 provides the
LRCLK
The following figures show the serial mode formats.
LEFT CHANNEL
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
LSB
LEFT-JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
MSB
LSB
LSB
12S MODE – 16 TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
MSB
SDATA
MSB
LSB
LSB
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE – 16 TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT f S EXCEPT FOR DSP MODE WHICH IS 2 f S
3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE
Figure 3. Stereo Serial Modes
–10–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD1836
LRCLK
128 BCLKs
BCLK
32 BCLKs
DATA
SLOT 1
LEFT 0
MSB
SLOT 2
LEFT 1
MSB–1
SLOT 3
RIGHT 0
SLOT 4
RIGHT 1
MSB–2
Figure 4. ADC Packed Mode 128
LRCLK
256 BCLKs
BCLK
32 BCLKs
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 5 SLOT 6
SLOT 4 RIGHT 0 RIGHT 1 SLOT 7
SLOT 3
MSB
MSB–1
SLOT 8
MSB–2
Figure 5. ADC Packed Mode 256
LRCLK
128 BCLKs
BCLK
DATA
20 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
LRCLK
BCLK
MSB
MSB–1
DATA
MSB–2
Figure 6. DAC Packed Mode 128
LRCLK
256 BCLKs
BCLK
DATA
32 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
LRCLK
BCLK
MSB
MSB–1
MSB–2
DATA
Figure 7. DAC Packed Mode 256
REV. PrC
–11–
SLOT 6
RIGHT 2
PRELIMINARY TECHNICAL DATA
AD1836
FSTDM
TDM INTERFACE
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA1
MSB TDM
MSB TDM
1ST
CH
8TH
CH
INTERNAL
ADC L0
INTERNAL
ADC L1
AUX_ADC L0
AUX_ADC L1
INTERNAL
ADC R0
INTERNAL
ADC R1
AUX_ADC R0
AUX_ADC R1
32
DSDATA1
TDM (IN)
DSDATA1
MSB TDM
MSB TDM
1ST
CH
8TH
CH
INTERNAL
DAC L0
INTERNAL
DAC L1
INTERNAL
DAC L2
AUX_DAC L0
INTERNAL
DAC R0
INTERNAL
DAC R1
INTERNAL
DAC R2
AUX_DAC R0
32
AUX – I2S INTERFACE
AUX
LRCLK I2S
(FROM AUX ADC#1)
RIGHT
LEFT
AUX
BCLK I2S
(FROM AUX ADC#1)
AAUXDATA1 (IN)
(FROM AUX ADC#1)
I2S – MSB LEFT
I2S – MSB RIGHT
AAUXDATA2 (IN)
(FROM AUX ADC#2)
I2S – MSB LEFT
I2S – MSB RIGHT
DAUXDATA (OUT)
(TO AUX DAC)
I2S – MSB LEFT
I2S – MSB RIGHT
NOTE:
AUX BCLK FREQUENCY IS 64 FRAME-RATE; TDM BCLK FREQUENCY IS 256 FRAME-RATE.
Figure 8. AUX-Mode Timing
–12–
REV. PrC
PRELIMINARY TECHNICAL DATA
12.288MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
TxDATA
TxCLK
RxDATA
TFS (NC)
SHARC
RxCLK
30MHz
FSYNC-TDM (RFS)
AD1836
LRCLK
ADC #1
SLAVE
ASDATA1 ALRCLK ABCLK DSDATA1
BCLK
DATA
LRCLK
MCLK
LRCLK
ADC #2
SLAVE
DLRCLK/AUXLRCLK
BCLK
DSDATA2/AAUXDATA1
DATA
DSDATA3/AAUXDATA2
MCLK
MCLK
DBCLK/AUXBCLK (64fS)
BCLK
ASDATA2/DAUXDATA
DATA
DAC
MCLK
AD1836+
MASTER
12.288MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
TxDATA
TxCLK
RxDATA
TFS (NC)
SHARC
RxCLK
30MHz
FSYNC-TDM (RFS)
Figure 9. AUX–Mode Connection to SHARC (Master Mode)
LRCLK
ADC #1
MASTER
ASDATA1 ALRCLK ABCLK DSDATA1
BCLK
DATA
LRCLK
MCLK
LRCLK
ADC #2
SLAVE
DLRCLK/AUXLRCLK
BCLK
DSDATA2/AAUXDATA1
DATA
DSDATA3/AAUXDATA2
MCLK
MCLK
DBCLK/AUXBCLK (64fS)
BCLK
ASDATA2/DAUXDATA
DATA
MCLK
AD1836+
SLAVE
Figure 10. AUX–Mode Connection to SHARC (Slave Mode)
REV. PrC
–13–
DAC
PRELIMINARY TECHNICAL DATA
AD1836
Table I. Pin Function Changes in AUX-Mode
2
I2S-Mode
Pin Name (I S/AUX-Mode)
AUX-Mode
2
ASDATA1(O)
ASDATA2(O)/DAUXDATA(O)
DSDATA1(I)
DSDATA2(I)/AAUXDATA(I)
DSDATA3(I)/AAUXDATA2(I)
ALRCLK(O)
ABCLK(O)
DLRCLK(I)/AUXLRCLK(I/O)
I S Data Out, Internal ADC1
I2S Data Out, Internal ADC2
I2S Data In, Internal DAC1
I2S Data In, Internal DAC2
I2S Data in Internal DAC3
LRCLK for Internal ADC1, 2
BCLK for Internal ADC1, 2
LRCLK In/Out Internal DACs
DBCLK(I)/AUXBCLK(I/O)
BCLK In/Out Internal DACs
ADC
AUXDATA2
SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO
RESET INTERNAL ADC COUNTER
SYNC
AUXBCLK
AUXLRCLK
TDM Data Out, to SHARC
AUX–I2S-Data Out (to Ext. DAC)
TDM Data In, from SHARC
AUX–I2S-Data in 1 (from Ext. ADC)
AUX–I2S-Data in 2 (from Ext. ADC)
TDM Frame Sync Out, to SHARC
TDM BCLK Out, to SHARC
AUX LRCLK IN/OUT, Driven by Ext. IRCLK
from ADC (in Slave Mode). In Master Mode,
Driven by Internal MCLK/512.
AUX BCLK IN/OUT, Drive by Ext. BCLK
from ADC (in Slave Mode). In Master Mode,
Driven by Internal MCLK/8.
12S
DECODE
LRCLK
ALRCLK
ABCLK
ABCLK
SPORT
ASDATA1
ASDATA1
DATA TO SHARC
4 ADCS
AUXDATA1
ASDATA1
MCLK
12S
TIMING GEN
ASDATA2/DAUXDATA
MUX
DATA TO EXT DAC
LRCLK BCLK
BCLK AND LRCLK FOR
EXT DAC COMES FROM
ADC BCLK, LRCLK.
MUST BE IN 12S MODE
AUXDATA
FROM SHARC
DSDATA1
DSDATA1
FROM EXT A/D DSDATA2/AUXDATA1
DSDATA2
FROM EXT A/D DSDATA3/AUXDATA2
DSDATA3
LRCLK
DLRCLK/AUXLRCLK
12S FORMATTER
AUXLRCLK
AUXBCLK
MUX
SPORT
BCLK
DBCLK/AUXBCLK
2 AUX
CHANNELS
6 MAIN
CHANNELS
MUX
6-CH
DAC
DAC
MASTER/SLAVE MODE,
FROM ADC SPI PORT
INDICATES MUX POSITION FOR AUX-TDM MODE
Figure 11. Extended TDM Mode Internal Flow Diagram
–14–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD1836
SPI CONTROL REGISTERS
Note: All control registers default to zero at power-up.
Serial SPI Word Format
Register Address
Read/Write
Reserved
Data Field
15..12
11
10
9..0
4 Bits
1 = Read
0 = Write
0
10 Bits
Register Addresses and Functions
Bit 15
Register Address
Bit 14
Bit 13
Bit 12
RD/WR
Bit 11
RSVD
Bit 10
Function
(Bits 9:0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAC Control 1
DAC Control 2
DAC Volume 0
DAC Volume 1
DAC Volume 2
DAC Volume 3
DAC Volume 4
DAC Volume 5
ADC 0 – Peak Level (Read Only)
ADC 1 – Peak Level (Read Only)
ADC 2 – Peak Level (Read Only)
ADC 3 – Peak Level (Read Only)
ADC Control 1
ADC Control 2
ADC Control 3
Reserved
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DAC Control Register 1
Address
RD/WR RSVD De-Emphasis Serial Mode
15, 14, 13, 12 11
0000
0
10
0
9, 8
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
7, 6, 5
2
000 = I S
001 = RJ
010 = DSP
011 = LJ
100 = Pack Mode 256
101 = Pack Mode 128
110 = Reserved
111 = Reserved
NOTES
Packed Mode: Four channels are “packed” into DSDATA1 serial input.
Packed Mode 128: Refer Figure 6.
Packed Mode 256: Refer to Figure 7.
REV. PrC
–15–
Function
Data Word
Power-Down
Width
Reset
Interpolator
Mode
Reserved
4, 3
1
0
2
00 = 24-Bits 0 = Normal
0 = 8 × (48 kHz) 0
01 = 20 Bits
1 = PWRDWN 1 = 4 × (96 kHz)
10 = 16 Bits
11 = Reserved
PRELIMINARY TECHNICAL DATA
AD1836
DAC Control Register 2
Function
Mute DAC
Address
RD/WR
Reserved
15, 14, 13, 12
11
10, 9, 8, 7, 6
5
4
3
2
1
0
0001
0
00000
0 = On
1 = Mute5
0 = On
1 = Mute4
0 = On
1 = Mute3
0 = On
1 = Mute2
0 = On
1 = Mute1
0 = On
1 = Mute0
DAC Volume Registers
Address
RD/WR
Reserved
15, 14, 13, 12
11
10
0010: DAC 0
0011: DAC 1
0100: DAC 2
0101: DAC 3
0110: DAC 4
0111: DAC 5
0
0
Function
Volume
9:0
0 to 1023 in 1024 Linear Steps
ADC Control Register 1
Address
RD/WR
RSVD
Filter
Power-Down
Function
Sample Rate
Left Gain
Right Gain
15, 14, 13, 12
11
9, 10
8
7
6
5, 4, 3
2, 1, 0
1100
0
00
0 = DC
1 = High-Pass
0 = Normal
1 = PWRDWN
0 = 48 kHz
1 = 96 kHz
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
100 = 12 dB
101 = Rsrvd
110 = Rsrvd
111 = Rsrvd
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
100 = 12 dB
101 = Rsrvd
110 = Rsrvd
111 = Rsrvd
NOTE
High-Pass Filter: 3 Hz High-Pass Filter.
ADC Control Register 2
Address
RD/WR RSVD
Master/Slave SOUT
AUX Mode
Mode
Word
Width
Right
ADC Mute
Left
Right
Left
3
2
0
15, 14, 13, 12 11
10
9
8, 7, 6
5, 4
1101
0
0 = Slave
1 = Master
000 = I2S
001 = RJ
010 = DSP
011 = LJ
100 Packed 256
101 Packed 128
110 Packed
AUX*
00 = 24 Bits 0 = On
0 = On
W/Gain
W/Gain
01 = 20 Bits 1 = Mute3 1 = Mute2 0 = On
0 = On
10 = 16 Bits
1 = Mute1 1 = Mute0
11 = Invalid
0
1
NOTES
*Note that Packed AUX mode affects the entire chip, including the DAC serial mode.
Packed Mode: Four channels are packed into ASDATA1 serial output.
Packed Mode 128: Refer Figure 4.
Packed Mode 256: Refer to Figure 5.
Packed AUX: Refer to Figures 8 to 11.
–16–
REV. PrC
PRELIMINARY TECHNICAL DATA
AD1836
ADC Control Register 3
Left Diff.
I/P Select
Right Diff.
I/P Select
Left
MUX/PGA
Enable
Function
Left
Right
MUX
MUX/PGA
I/P Select Enable
Right
MUX
I/P Select
2
1
0
0 = Direct
1 = MUX/
PGA
0 = I/P 0
1 = I/P 1
Address
RD/WR
Reserved
Clock
Mode
15, 14, 13, 12
11
10, 9, 8
7, 6
5
4
3
1110
0
000
00 = 256 × fS
01 = 512 × fS
10 = 768 × fS
0 = Differential
PGA Mode.
1 = PGA/MUX
0 = Differential
PGA Mode.
1 = PGA/MUX
Mode (SingleEnded Input)
0 = Direct
0 = I/P 0
1 = MUX/
1 = I/P 1
PGA
Mode (SingleEnded Input)
*When changing clock doubler bypass mode, other SPI bits that are written during the same SPI transaction may be lost. It is therefore recommended that a separate
transaction be used for setting CLKDBL Bypass Mode.
ADC Peak Level Data Registers
Address
RD/WR
RSVD
Peak Level Data (10 Bits)
6-Data Bits
4-Fixed Bits
15, 14, 13, 12
11
10
9..4
3..0
1000 = ADC0
1001 = ADC1
1010 = ADC2
1011 = ADC3
1
0
000000 = 0.0 dBFS
000001 = –1.0 dBFS
000010 = –2.0 dBFS
000011 = –3.0 dBFS
.
.
.
111111 = –63 dBFS
0000
The four LSBs are always zero.
AD1836
AD1836
C1
1nF
C1
1nF
CAP1L
CAP1L
GAIN SELECT
POWER-DOWN
–
MUX
LEFT
INPUT #1
VREF
250
LEFT + VE
INPUT
+
250
+
250
–
LEFT – VE
INPUT
–
GAIN SELECT
POWER-DOWN
PGA
CAP2L
CAP2L
INPUT SELECT
C2
1nF
NOTE
ADC2 SINGLE-ENDED MUX PGA INPUT MODE – LEFT CHANNEL ONLY SHOWN
CONTROL REGISTER 3 CONTENTS: 6 LSBS: SELECT INPUT #1: 11 1010
SELECT INPUT #2: 11 1111
NOTE
ADC2 DIFFERENTIAL PGA INPUT MODE – LEFT CHANNEL ONLY SHOWN
CONTROL REGISTER 3 CONTENTS: 6 LSBS: 00 1010
Figure 12. Single-Ended MUX/PGA Mode
REV. PrC
ADC2L
+
VREF
250
VREF
ADC2L
LEFT
INPUT #2
C2
1nF
–
+
Figure 13. Differential Mode
–17–
PRELIMINARY TECHNICAL DATA
AD1836
52-Lead MQFP
(S-52)
0.037 (0.95)
0.031 (0.80)
0.026 (0.65)
0.557 (14.15)
0.547 (13.90) SQ
0.537 (13.65)
0.096 (2.45)
MAX
39
27
40
26
0.307
(7.80)
REF
0.398 (10.11)
0.394 (10.00) SQ
0.390 (9.91)
TOP VIEW
(PINS DOWN)
PIN 1
52
0.010 (0.25)
MIN
14
1
0.083 (2.10)
0.079 (2.00)
0.077 (1.95)
13
0.026 (0.65)
BSC
0.009 (0.23)
0.005 (0.13)
0.015 (0.38)
0.009 (0.22)
7
0
SEATING
PLANE
DIMENSIONS PER JEDEC STANDARDS MO-112
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
–18–
REV. PrC
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