DC1843B - Demo Manual

DEMO MANUAL DC1843B
DC1842B and DC1680B
LTC4290B/LTC4271
8-Port PSE with Digital Isolation
DESCRIPTION
Demonstration kit DC1843B is an 8-port IEEE 802.3at
Type 2 power sourcing equipment (PSE) composed of a
DC1842B daughter card and DC1680B motherboard. The
kit is used for evaluation of the LTC4290B and LTC4271 PSE
chipset. Up to 8 powered devices (PDs) can be connected
and powered from this system using a single power supply.
A DC590 is connected to the DC1843 for I2C interfacing
with QuikEval™. This demonstration manual provides a
Quick Start Procedure, a DC1842B overview, a DC1680B
overview, schematics, and layout printouts. Refer to the
Layout Guide for Demonstration Circuit 1842B when
laying out the LTC4290B/LTC4271 circuit. Contact Linear
Technology for this document.
The DC1842B has increased surge protection over the
DC1842A. The DC1680B uses discrete Ethernet transformers while the DC1680A has an integrated 12-port RJ45 jack.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1843B
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
QuikEval is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
BOARD PHOTO
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DEMO MANUAL DC1843B
QUICK START PROCEDURE
Demonstration kit DC1843B includes the DC1842B
daughter card and DC1680B motherboard. The kit is set
up for evaluating the LTC4290B/LTC4271. Follow the procedure below and refer to Figures 1 through 4 for proper
equipment setup.
3. Align pin 1 of the 30-pin male connector on the DC1842B
with pin 1 of the 30-pin female connector on the
DC1680B (Figure 2). Pin 12 is polarized to assist with the
alignment. Carefully push the DC1842B straight down
until the two 30-pin connectors are flush with each other.
NOTE (DC1843B Kit): Connector J1 on the DC1680B has
four pegs blocking the unused last four pins to match the
30-pin connector of the DC1842B. Dust caps block the four
unused ports at each RJ45 connector on the DC1680B
for the 8-Port.
4.On the DC1680B, connect a supply with the positive
rail to POS and negative rail to NEG (Figure 3). Use a
power supply capable of sourcing the maximum load
expected (8 ports × 850mA ≥ 6.8A). Ramp the supply
up to 51V to 57V.
1. On the DC1842B set AUTO jumper JP1 to HI (Figure 1)
to enable AUTO pin mode.
5.Connect up to 8 PDs to ports 1-8 at the DC1680B, J4
(Figure 3).
2.On the DC1842B set MID jumper JP2 to LO (Figure 1)
to disable midspan mode.
6. The DC590 is optionally connected to the DC1680B connector J5 with a 14-pin ribbon cable (Figure 3). A GUI
for the LTC4290B/LTC4271 is brought up by QuikEval
for I2C interfacing from a PC (Figure 4).
Figure 1. DC1842 Backside. Setting AUTO and MID Jumpers
Figure 2. Inserting the DC1842 into J1 of the DC1680
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DEMO MANUAL DC1843B
QUICK START PROCEDURE
Figure 3. DC1843B Basic Setup
Figure 4. DC1843 System Setup with the DC590, DC1680, DC1842 and 51V to 57V Power Supply
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1842B OPERATION
8-Port PSE Daughter Card with Digital Isolation
Demonstration circuit 1842B (Figure 5) features the
LTC4290B/LTC4271 chipset on a compact daughter card
with digital isolation. The LTC4290B/LTC4271 chipset is
an 8-port power sourcing equipment (PSE) controller
designed for use in IEEE 802.3at Type 1 and Type 2 (high
power) compliant Power over Ethernet (PoE) systems. A
transformer isolated communication protocol replaces
expensive opto-couplers and complex isolated 3.3V supply
resulting in significant BOM cost savings. The LTC4290B/
LTC4271 chipset delivers lowest-in-industry heat dissipation by utilizing low RON external MOSFETs and 0.25Ω sense
resistors, eliminating the need for expensive heat sinks.
Advanced power management features in the LTC4290B/
LTC4271 chipset include: per port 12-bit current monitoring ADCs, DAC programmable current limit, and versatile
quick shutdown of preselected ports. PD discovery uses a
proprietary dual mode 4-point detection mechanism ensuring excellent immunity from false PD detection. Midspan
PSEs are supported with 2-event classification and a two
second backoff timer. The LTC4290B/LTC4271 includes
an I2C serial interface operable up to 1MHz.
The DC1842B demonstrates proper LTC4290B/LTC4271
board layout that is approximately the height and width
of a 2 × 4 RJ45 connector. The compact layout is made
possible by the small package size of key components. The
LTC4290B is in a 6mm × 6mm QFN, while the LTC4271 is
in a 4mm × 4mm QFN. Each port has a PSMN075-100MSE
MOSFET in a 3mm × 3mm LFPAK33 package.
The daughter card inserts in the DC1680B motherboard
through J1, a polarized 30-pin connector. Isolated 3.3V
and logic control signals are brought in on this connector. Also connected at J1 is the PoE VEE supply from the
motherboard and 8 PSE controlled outputs.
Figure 5. DC1842B 8-Port PSE Daughter Card with Digital Isolation Features the LTC4290B and LTC4271
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1842B OPERATION
Board Layout
Isolation and Power Supplies
Proper board layout is crucial for proper LTC4290B/
LTC4271 chipset operation, robustness, and accuracy.
When laying out, pay attention to parts placement, Kelvin
sensing, power paths, and copper fill. It is imperative to
follow the LTC4290B/LTC4271 Layout Guide document
when laying out the board. Contact Linear Technology
Corporation for this document.
The LTC4290B/LTC4271 chipset provides communication
across an isolation barrier through a data transformer
(Figure 6). This eliminates the need for expensive optocouplers. All digital pins reside on the digital ground reference and are isolated from the analog PoE supply. A 3.3V
supply for VDD and an isolated VEE supply are connected
to the DC1842B through the 30-pin connector.
30-PIN
CONNECTOR
VDD33
DC1842A SIDE
DC1680B SIDE
+
–
VDD33 SUPPLY
C21
0.1µF
T1
VDD33
RX–
CPD
RD–
U1
LTC4271
C23
1µF
CT(4)
U2
LTC4290
CT(3)
R14
100Ω
CND
RX+
RD+
CNA
DPD
TX–
TD–
DPA
C22
1µF
DND
R24
100Ω
+
TX
WÜRTH 7490100143
TD+
C24, 2nF
2kV
CBULK
+
–
D1
SMAJ58A
CT
R16
100Ω
+
C19
1µF
100V
R23
100Ω
CT(2)
R35
10Ω
AGND
R22
100Ω
R15
100Ω
DGND
CPA
R21
100Ω
R13
100Ω
VEE SUPPLY
TVSBULK
VEE
DNA
VEE
VEE
ISOLATION
DC1843A F06
Figure 6. DC1842B Digital and Analog Isolation
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1842B OPERATION
I2C Communication and Addressing
The LTC4271 internal registers are accessed via I2C to read
and/or write configuration, status, and interrupt registers.
The I2C lines SDAOUT, SDAIN and SCL connect to the
30-pin connector (Figure 7). Subsequently, the I2C bus
is accessed on the DC1680B.
The LTC4290B/LTC4271 chipset has an address of
(A610A3A2A1A0b), where A6, A3, A2, A1, and A0 are the
logic state of the AD6, AD3, AD2, AD1, and AD0 pins
respectively. On the DC1842B, AD0 and AD1 are tied low
with pull-down resistors. AD2, AD3 and AD6 are brought
out to the 30-pin connector (Figure 7) and set with three
switches on the DC1680B.
AGND
R30
27k
R32
220k
R31
27k
D4
GRN
XIO1
D5
GRN
XIO0
Q13A
BC846AS
Q13B
BC846AS
R33
220k
LTC4290
J2, PIN 9
XIO1
J2, PIN 10
XIO0
VEE
DC1843A F08
VEE
Figure 8. DC1842B, LTC4290B General Purpose I/O LED Indicators
R7
0Ω
SDAOUT
SDAOUT
SDAIN
VDD33
SDAIN
SCL
R28
560Ω
SCL
INT
INT
AD6
AD6
AD3
AD3
AD2
AD2
LTC4271
TO 30-PIN
CONNECTOR
LTC4271
R29
560Ω
D2
GRN
GP1
AD1
D3
GRN
GP0
GP1
J2, PIN 5
GP0
J2, PIN 6
DGND
AD0
R8
0Ω
R9
0Ω
DGND
DC1843A F09
Figure 9. DC1842B, LTC4271 General Purpose I/O LED Indicators
DC1843A F07
Figure 7. DC1842B, LTC4271 I2C and Address Connections
VDD33
I/O LED Indicators
The DC1842B features four LEDs to indicate the states
of the LTC4290B/LTC4271 chipset general purpose input
output pins. These pins are configured as inputs or outputs
via I2C. GP1 and GP0 are referenced to DGND and driven
by the LTC4271 when set as outputs (Figure 8). XIO0 and
XIO1 are referenced to VEE and are driven by the LTC4290B
when set as outputs (Figure 9). J2 provides test points
for access to these I/Os.
VDD33
JP1
LTC4271
AUTO JP2
HI
LO
MID
HI
LO
AUTO
J2, PIN 3
MID
J2, PIN 4
DGND
DC1843A F10
Figure 10. DC1842B AUTO and MID Jumpers
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1842B OPERATION
AUTO and MID Jumpers
Surge Protection
The AUTO and MID pins of the LTC4271 are set by
jumpers JP1 and JP2 respectively on the DC1842B
(Figure 10). Setting JP1 to HI enables the AUTO pin mode
in the LTC4290B/LTC4271 chipset. J2 provides test points
for access to AUTO and MID.
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components,
as shown in Figure 11, are required at the main supply,
at the LTC4270 supply pins and at each port.
In AUTO pin mode (JP1 high), the LTC4290B/LTC4271
chipset internal I2C registers default to the AUTO pin
high state after a software or hardware reset, or system
power on. The LTC4290B/LTC4271 chipset autonomously
detects, powers on and disconnects power to PDs without
the need for I2C host control.
Bulk transient voltage suppression (TVSBULK) and bulk
capacitance (CBULK) are required across the main PoE
supply and should be sized to accommodate system level
surge requirements.
Each LTC4290 requires a 10Ω, 0805 resistor (R1) in series
from supply AGND to the LTC4290 AGND pin. Across the
LTC4290 AGND pin and VEE pin are an SMAJ58A, 58V
TVS (D1) and a 1μF, 100V bypass capacitor (C19). These
components must be placed close to the LTC4290 pins.
Setting JP1 to LO disables AUTO pin mode and sets the
LTC4290B/LTC4271 chipset to a low current shutdown
mode. An I2C host controller can then be used to configure the LTC4290B/LTC4271 chipset to semi-auto mode
for controlled PSE operation or to manual mode for test
purposes.
Finally, each port requires a pair of S1B clamp diodes:
one from OUTn to supply AGND and one from OUTn to
supply VEE. The diodes at the ports steer harmful surges
into the supply rails where they are absorbed by the surge
suppressors and the VEE bypass capacitance. The layout
of these paths must be low impedance. These S1B diodes
are placed on the DC1680 mother board of the DC1843 kit.
Setting JP2 to HI enables the midspan mode detection
backoff timer in the LTC4290B/LTC4271 chipset. For
endpoint PSEs, set JP2 to LO to disable midspan mode.
For quick PSE evaluation in AUTO pin mode with
MIDSPAN disabled, set JP1 HI and JP2 LO on the DC1842B.
30-PIN
CONNECTOR
DC1842B SIDE
R35
10Ω
DC1680B SIDE
AGND
C19
1µF
100V
D1
SMAJ58A
LTC4290
VEE
C26
0.1µF
VSSK
SENSEn GATEn
S1B
PROTECTION
OUTn
Cn
0.22µF
X7R
100V
D26
B1100 RSENSEn
S1B
4 × 1.00
CBULK
OUTn
TO
PORT
OUTn
Qn
PSM075-100MSE
VEE
+
S1B
VEE
TVSBULK
VEE
DC1843A F11
Figure 11. DC1842B, 1 of 8 Port Outputs. Surge Protection
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B OPERATION
Demonstration circuit 1680B is configured as an 8-Port,
IEEE802.3at Type 1 and Type 2 PoE PSE motherboard in
the DC1843B kit. This board accepts various PSE daughter
cards featuring Linear Technology PSE controllers. The
DC1680B is capable of powering up to 8 PDs.
Ethernet ports. Additional pegs are placed in the last 4
pins of connector J1 to block off the unused pins when
the DC1842B daughter card is inserted.
Daughter Card Insertion Precautions
Refer to Figure 12 and Figure 13 for the following user
features.
When inserting or removing the daughter card into the
DC1680B, verify all supplies and LEDs are off. Push the
card straight down for insertion or pull straight up for
removal to avoid bending the connector pins. Follow the
instructions in the Quick Start Procedure for alignment.
VEE Supply
Connect a power supply for VEE with the positive rail to POS
and negative rail to NEG as shown in Figure 3 of the Quick
Start Procedure. Set the voltage within the range in Table 1
depending on whether the application is a Type 1 or Type 2.
Choose a power supply rating and set the current limit
high enough to provide power for the maximum number of
PDs connected and to meet each PD power requirements.
Table 1. DC1843B VEE Power Range for Type 1 and Type 2 PSEs
PSE TYPE
V EE SUPPLY
RANGE
MAX DELIVERED
PORT POWER
POWER
SUPPLY*
Type 1
45V to 57V
13W
200W
Type 2
51V to 57V
25.5W
400W
*Recommended DC1843B power supply minimum to avoid drooping in
a worst-case scenario with ILIM current at all 8 ports.
PD Connection
PDs are connected using an Ethernet cable to any of the
8 ports at the 2×6, RJ45 connector J4 on the DC1680B
(Figure 3). Test points for port outputs OUT1 through
OUT8 are provided.
8-Port Configuration
The DC1680B is configured for an 8-port PSE motherboard
for the DC1843B kit. Four RJ45 dust caps at J3 and four
dust caps at J4 are inserted to block off the four unused
DC1680B USER FEATURES
Onboard 3.3V Supply
The DC1680B has an onboard VDD33 digital supply generated from the VEE supply. DGND is a negative voltage
referenced to AGND. If an external 3.3V supply is to be
used, contact Linear Technology Applications for proper
connection.
VEE and VDD33 LED Indicators
LEDs for VEE and VDD33 indicate if voltage is present at
these supplies. Verify these LEDs are off before inserting
or removing the daughter card.
Digital Connections
The DC1680B has connections for I2C control from a
host controller. The DC590 is optionally connected to
the DC1680B at J5 through a 14-pin ribbon cable. The
QuikEval software will automatically detect the DC1680B
and open the LTC4271 GUI. A second 14-pin ribbon cable
can be connected to J6 for I2C expansion to another
DC1680B board with slight board modifications. Contact
Linear Technology Applications for instructions.
Digital test points include SCL, SDA, DGND, INT, MSD,
and RESET. I2C address pin AD6, AD3, and AD2 are set
with a 3-bit switch SW3.
Midspan PSE
The DC1843B can be configured as a midspan PSE.
Upstream switch data comes in to J3. Data and PoE go
out to a PD at J4. Set both MID and AUTO pins logic high.
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B OPERATION
MSD and RESET Pushbuttons
Pushbutton switch SW1, when pressed, pulls the RESET
pin of the daughter card logic low. The PSE controller is
then held inactive with all ports off and all internal registers
reset to their power-up states. When SW1 is released,
RESET is pulled high, and the PSE begins normal operation.
Pushbutton switch SW2 when pressed pulls the maskable
shutdown input (MSD) pin of the daughter card logic low.
When pressed, all ports that have their corresponding mask
bit set in the mconfig register of the PSE controller will be
shutdown. These ports must then be manually re-enabled
via I2C or by resetting the PSE.
Figure 12. DC1680B Connections and Supply LEDs
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B OPERATION
Interrupt LED
Port 1 Through 8 Power LED Indicators
A red LED indicates when the INT line is pulled logic low
by the daughter card. When the interrupt is cleared (high)
via I2C servicing, the LED is turned off.
Each PSE port has a green LED indicator to show when
PoE power is present at the port. The LEDs are driven by
the respective port OUT voltage.
Figure 13. DC1680B Address Switch, Pushbutton Switches, INT LED, and Port Power LEDs
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1843B SYSTEM
DC1843B System Setup
Figure 14 shows a basic DC1843B system setup. The
DC1842B daughter card is inserted in the 30-pin connector J1 on the DC1680B motherboard. A power supply is
connected to VEE with banana cables. The DC590 connects
with a 14-pin ribbon cable to the DC1680B and to a PC via
USB. On the PC, a GUI communicates with the board. At
the PSE output, PDs are connected. A sample PD demo
board is shown in Figure 14.
Figure 14. DC1680B and DC1842B System Setup with Power Supply, DC590 and PD Demo Board
Table 2. DC1843 Kit Versions
VERSION
FEATURES
DC1843A
DC1680A: Motherboard with Integrated Magjack
DC1842A: 8-Port PSE Daughter Card
DC1843B
DC1680B: Motherboard with Discrete Ethernet Transformers
DC1842B: 8-Port PSE Daughter Card with Increased Surge Protection
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1842B LAYOUT
Top Assembly
Layer 1: Top Layer
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1842B LAYOUT
Layer 2: VEE Plane 1
Layer 3: VEE Plane 2
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1842B LAYOUT
Layer 4: Bottom Layer
Bottom Assembly
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B LAYOUT
Top Assembly
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B LAYOUT
Layer 1: Top Layer
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B LAYOUT
Layer 2: AGND, CGND Plane 1
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B LAYOUT
Layer 3: SIG, AGND, CGND Plane 2
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B LAYOUT
Layer 4: SIG, AGND, CGND Plane 3
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B LAYOUT
Layer 5: SIG, AGND, CGND Plane 4
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B LAYOUT
Layer 6: Bottom Layer
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DEMO MANUAL DC1843B
DEMONSTRATION CIRCUIT 1680B LAYOUT
Bottom Assembly
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A
B
C
XIO1
XIO0
R27
OPT
VEE
C19
1uF
100V
1206
10
0805
R35
R34
12k
1206
1/2W
OPT
SMAJ58A
D1
20
XIO1
11
XIO0
6
CAP2
25
AGND
VEE
REQUIRED SURGE
COMPONENTS (BULK 58V
TVS and BULK CAPACITANCE)
ON MOTHER BOARD.
BZT52C5V6-7-F
D31
OPT
R33
220k
C25
0.1uF
Q13B
BC846AS
VEE
5
R31
27k
0805
D5
GRN
XIO0
C20
1uF
19
VEE
T1
WURTH, 7490100143
C23
1uF
VDD33
2
NOTE 1, 2
D26
B1100
C26
1
4 X 1.00
RA1-RA4
0.1uF
R13
100
100
R21
R22
100
D68
OPT
0.22uF
X7R
100V
0805
G1 VEE
R1
0
C1
R15
100
100
R23
R2
0
J2-2
J2-1
R16
100
VEE
D69
OPT
0.22uF
X7R
100V
0805
C2
100
R24
4 X 1.00
4 X 1.00 PSMN075-100MSE
RC1-RC4
PSMN075-100MSE
G2
RB1-RB4 Q2
Q1
R14
100
R9
0
1
R10
0
C21
0.1uF
3
5
4
AD2
AD3
AD6
AD0
AD1
G3
R3
0
2KV
1808
C24
2.2nF
VEE
D70
OPT
0.22uF
X7R
100V
0805
C3
VEE
C22
1uF
R11
0
Q4
G4
R4
0
AUTO
J2-3
D71
OPT
0.22uF
X7R
100V
0805
C4
LTC4290
U2
LTC4271
VEE
4 X 1.00
3
HI
LO
JP1
AUTO
U1
SDAOUT
SDAIN
SCL
INT#
4 X 1.00 PSMN075-100MSE
RE1-RE4
PSMN075-100MSE
RD1-RD4
Q3
1. ALL SENSE RESISTORS TIE TO VEE AT ONE COMMON POINT.
2. VSSK CONNECTS TO THE COMMON SENSE RESISTOR VEE POINT THROUGH AN ISOLATED KELVIN SENSE TRACE.
3. ONE S1B PROTECTION DIODE FROM VEE TO OUTn AND ONE S1B PROTECTION DIODE FROM OUTn TO AGND SHOWN ON MOTHER BOARD.
4. ALL RESISTORS AND CAPACITORS ARE 0603.
5. OPTIONAL REPLACE R1- R8 WITH 10 OHMS AND D68 - D75 WITH BAT41JFILM FOR INCREASED SURGE PROTECTION.
NOTE: UNLESS OTHERWISE SPECIFIED
R26
OPT
J2-9
J2-10
R30
27k
0805
D4
GRN
XIO1
VEE
R32
220k
Q13A 2
BC846AS
2
1
1
6
2
1
3
4
D
1
2
13
DNC
7
NC
5
4
12
VSSK
10
CAP1
1
VEE
30
VEE
33
VEE
40
VEE
35
NC
34
NC
32
NC
31
NC
41
20
VDD33
12
VDD33
CPD
8
9
RXRD8
CT(3)CT(4)
7
S1
38
CNA
39
CPA
SENSE1
2
G1
GATE1
3
O1
CND
9
25
S2 13
OUT1
1
2
DGND
11
RX+
12
N/C
13
N/C
6
RD+
5
N/C
4
N/C
4
G2
SENSE2
DPD
10
14
TX-
2
15
2
TD-
3
37
DPA
GATE2
AD0
5
OUT2
1
2
O2
AD1
CT(2)
CT
16
TX+
TD+
1
36
DNA
16
SDAOUT
4
AD2
11
DND
AD3
7
G3
SENSE3
S3 14
AD6
GATE3
8
O3
OUT3
1
2
15
INT
18
SCL
17
SDAIN
S4 15
SENSE4
9
G4
GATE4
10
O4
OUT4
1
2
2
G5
VEE
D72
OPT
0.22uF
X7R
100V
0805
C5
MID
J2-4
JP2
MID
HI
LO
3
4 X 1.00
PSMN075-100MSE
RF1-RF4
Q5
R5
0
3
2
VDD33
G6
VEE
D73
OPT
0.22uF
X7R
100V
0805
C6
Q7
D2
GRN
GP1
R28
560
G7
R7
0
VEE
D74
OPT
0.22uF
X7R
100V
0805
C7
4 X 1.00
D3
GRN
GP0
R29
560
4 X 1.00 PSMN075-100MSE
RH1-RH5
PSMN075-100MSE
RG1-RG4
Q6
R6
0
RESET#
MSD#
2
1
2
1
3
1
22
G5
SENSE5
S5 16
21
1
MID
6
AUTO
GATE5
21
O5
OUT5
1
2
RESET
14
S6 17
SENSE6
24
G6
GATE6
22
GP1
24
MSD
23
O6
OUT6
1
2
23
GP0
S7 18
SENSE7
27
G7
GATE7
26
O7
OUT7
1
2
J2-5
J2-6
Q8
G8
R8
0
VEE
D75
OPT
0.22uF
X7R
100V
0805
C8
GP1
GP0
PSMN075-100MSE
S8 19
SENSE8
29
G8
GATE8
28
O8
OUT8
1
2
5
2
2
NOTE 5
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
CUSTOMER NOTICE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2mm, 30 PIN CONNECTOR
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
OUT7
OUT8
OUT5
OUT6
OUT3
OUT4
VEE
SCL
SDAIN
SDAOUT
INT#
RESET#
OUT1
OUT2
VDD33
AD2
AD3
AD6
MSD#
DILIAN R.
APP ENG.
SCALE = NONE
KIM T.
APPROVALS
PCB DES.
1
REV
1
DESCRIPTION
DILIAN R.
APPROVED
REVISION HISTORY
REBUILD WITH CHANGE
DATE
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
08-18-15
DATE:
N/A
SIZE
DEMO CIRCUIT 1842B
1
SHEET 1
LTC4290BIUJ, LTC4271IUF
Tuesday, August 18, 2015
IC NO.
1
OF 1
REV.
8-PORT PSE DAUGHTER CARD WITH DIGITAL ISOLATION
TITLE: SCHEMATIC
TECHNOLOGY
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
VEE
S1B
OUTn
S1B
REQUIRED S1B DIODE PROTECTION
SHOWN ON MOTHER BOARD.
See NOTE 3
__
ECO
A
B
C
D
DEMO MANUAL DC1843B
DC1842B SCHEMATIC DIAGRAM
dc1843bfa
23
A
B
C
D
OPT
J2
1
2
OUT9
OUT5
OUT1
NEG
RE9
10M
RD9
2M
RE5
10M
RD5
2M
RE1
10M
RD1
2M
1
1
1
KEY-575
J8
MOLEX-50-84-1020
MAIN SUPPLY IN
KEY-575
+
OUT2
5
V_LED
Q9
Si2343CDS
OUT10
RL9
1.5k
PORT9
LED9
GREEN
Q5
Si2343CDS
OUT6
V_LED
RL5
1.5k
PORT5
LED5
GREEN
V_LED
E27
VEE
D2
S5BC
ANALOG CONNECTIONS
D5
1.5SMC62A
D4
1.5SMC62A
D3
S5BC
R7
20k
1206
VEE
LED15
ORANGE
C10
1uF,100V
1210
1
1
RE10
10M
1
RD10
2M
RE6
10M
RD6
2M
RE2
10M
RD2
2M
V_LED
OUT7
OUT3
Q10
Si2343CDS
OUT11
RL10
1.5k
PORT10
LED10
GREEN
V_LED
Q6
Si2343CDS
RL6
1.5k
PORT6
LED6
GREEN
V_LED
Q2
Si2343CDS
RL2
1.5k
PORT2
LED2
GREEN
1
1
RE11
10M
1
RD11
2M
RE7
10M
RD7
2M
RE3
10M
RD3
2M
Q3
Si2343CDS
V_LED
OUT8
OUT4
Q11
Si2343CDS
OUT12
RL11
1.5k
PORT11
LED11
GREEN
V_LED
Q7
Si2343CDS
RL7
1.5k
PORT7
LED7
GREEN
V_LED
4
R5
100k
0805
PORT3
LED3
GREEN
RL3
1.5k
1
Q13
ZXTP19100CGTA
0805
R20
1k
D1
MMSZ4691T1G
1
1
RE12
10M
1
RD12
2M
RE8
10M
RD8
2M
RE4
10M
RD4
2M
VEE
R8-R11
3.9k
1206
C3
1uF
Q4
Si2343CDS
V_LED
Q12
Si2343CDS
RL12
1.5k
PORT12
LED12
GREEN
V_LED
Q8
Si2343CDS
RL8
1.5k
PORT8
LED8
GREEN
V_LED
SHDN
IN
2
GND
3
BYP
OUT
LT1761ES5-3.3
U5
R12-R15
3.9k
1206
PORT4
LED4
GREEN
RL4
1.5k
3
1
Q14
ZXTP19100CGTA
V_LED
R23
OPT
0805
R21
1k 1
0805
R22
OPT
0805
POLARITY PROTECTION DIODE, TVS, FUSES TO BE INCLUDED
OPTIONAL PORT LED DRIVERS
Q1
Si2343CDS
RL1
1.5k
PORT1
LED1
GREEN
10A, 0154010
LITTELFUSE
F2
C1
47uF,100V
10A, 0154010
LITTELFUSE
1
2
1
2
1
2
AGND
E22
1
2
F1
1
2
1
2
J7
3
2
4
4
5
INT
SCL
SDA
RESET
MSD
8
10
12
14
7
9
11
13
1000pF,2KV
1808
1000pF,2KV
1808
1000pF,2KV
1808
C7
C8
C9
R6
5.1k
A2
VSS
SCL
SDA
4
3
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
2
AGND
1
OUT7
OUT8
OUT5
OUT6
OUT3
OUT4
OUT1
OUT2
SW3
219-3MST
2
OUT11
OUT12
3
E17
E16
E14
E11
E9
E1
E2
E15
E13
E12
E8
INT#
RESET#
VEE
(NC)
(SDAOUT)
SCL
SDAIN
MSD#
VDD33
AD2
AD3
AD6
E5
HI
E20
DGND
REBUILD WITH CHANGE
ADDRESS
OUT9
OUT10
6
5
4
1
DESCRIPTION
TECHNOLOGY
SCALE = NONE
J1
1
SHEET
DEMO CIRCUIT 1680B
Friday, September 04, 2015
IC NO.
1
OF
4
2
REV.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
12-PORT IEEE802.3at PSE MOTHER BOARD
DATE:
N/A
SIZE
DILIAN R. TITLE: SCHEMATIC
KIM T.
APPROVALS
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DATE
09-04-15
SAMTEC
MMS-134-02-T-SV
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DILIAN R.
APPROVED
REVISION HISTORY
E23 E24 E25 E26
2
REV
1. ALL RESISTORS AND CAPACITORS ARE 0603.
2. INSTALL SHUNTS AS SHOWN.
LO
ECO
NOTE: UNLESS OTHERWISE SPECIFIED
CUSTOMER NOTICE
EEGND
A1
WP
TP1
A0
VCC
1
14
12
10
8
6
4
2
HD2X7-079-MOLEX
J6
I2C EXPANSION
13
11
9
7
5
3
1
R4
OPT C13
0.1uF
VDD33
VDD33
LED13
GREEN
R1
470
0805
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
APP ENG.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
WP
5
6
7
8
U4
C2
0.1uF
24LC025-I/ST
HD2X7-079-MOLEX
TO DC590
6
5
2
4
J5
INT
LED14
RED
R2
470
0805
DIGITAL CONNECTIONS
R16 R17
OPT OPT
R3
OPT C14
0.1uF
VDD33
SW2
MSD
DGND
E19
C12
1uF
VDD33
E18
C11
1uF
3
1
SW1
RESET
D31
DDZ9688
1000pF,2KV
1808
REP2
5.1k
REP1
5.1k
C5
10uF
0805
VDD33
C6
E10
E6
E7
E4
E3
R19
0
C4
0.01uF
R18
0
1
2
2
1
2
3
1
2
4
3
2
4
ON
POS
51V - 57V
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
1
2
2
3
3
2
1
24
2MM, 34 PIN CONNECTOR
5
A
B
C
D
DEMO MANUAL DC1843B
DC1680B SCHEMATIC DIAGRAM
dc1843bfa
A
B
C
D
11
1 12
2 13
3 14
4
15
5 16
6 17
7 18
8
1
1 2
2 3
3 4
4
5
5 6
6 7
7 8
8
121
122
123
124
125
126
127
128
129
SS-73100-046F
J3M
1
2
3
4
5
6
7
8
9
SS-73100-046F
J3A
A
DATA IN
SS-73100-046F
J3B
B
DATA IN
RJ45
5
CA1
1000pF
2kV
1808
CA2
1000pF
2kV
1808
RR1
RQ1
RP1
RO1
RR2
RQ2
RP2
RO2
16
OUT1
VEE
23
2
22
3
24
20
75 1
21
5
19
17
75 4
6
8
18
14
9
75 7
11
13
15
WE, 749022017
T1
75 10
12
VEE
23
OUT2
24
22
2
20
3
75 1
21
5
19
17
18
16
75 4
6
8
75 7
9
14
13
11
WE, 749022017
T2
15
12
75 10
DN1
S1B
DP1
S1B
DN2
S1B
DP2
S1B
4
RZ1
RY1
RX1
RW1
RZ2
RY2
RX2
RW2
4
75
75
75
75
75
75
75
75
CZ1 0.01uF
100V 0805
CY1 0.01uF
100V 0805
CX1 0.01uF
100V 0805
CW1 0.01uF
100V 0805
CZ2 0.01uF
100V 0805
CY2 0.01uF
100V 0805
CX2 0.01uF
100V 0805
CW2 0.01uF
100V 0805
J4L
CB1
1000pF
2kV
1808
121
122
123
124
125
126
127
128
129
J4K
J4M
SS-73100-046F
1
2
3
4
5
6
7
8
9
3
31
1 32
2 33
3 34
4
35
5 36
6 37
7 38
8
21
1 22
2 23
3 24
4
25
5 26
6 27
7 28
8
SS-73100-046F
J3C
C
DATA IN
SS-73100-046F
J3D
D
DATA IN
LOWER ROW
SS-73100-046F
101
102 1
103 2
104 3
4
105
106 5
107 6
108 7
8
DATA/PoE OUT
PORT 1
SS-73100-046F
111
112 1
113 2
114 3
4
115
116 5
117 6
118 7
8
PORT 2
DATA/PoE OUT
CB2
1000pF
2kV
1808
3
UPPER ROW
SHIELD
RJ45
SHIELD
RJ45
RJ45
RJ45
RJ45
CA3
1000pF
2kV
1808
CA4
1000pF
2kV
1808
16
CUSTOMER NOTICE
OUT3
VEE
23
2
22
24
20
3
75 1
21
5
19
17
75 4
6
8
18
14
9
75 7
11
13
15
WE, 749022017
T3
75 10
12
VEE
23
OUT4
24
22
2
20
3
75 1
21
5
19
17
18
16
75 4
6
8
75 7
9
14
13
11
WE, 749022017
T4
15
12
75 10
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
DP4
S1B
RZ3
RY3
RX3
RW3
RZ4
RY4
RX4
RW4
75
75
75
75
75
75
75
75
SCALE = NONE
1
SHEET
DEMO CIRCUIT 1680B
Friday, September 04, 2015
IC NO.
2
OF
4
2
REV.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
CB3
1000pF
2kV
1808
J4I
SS-73100-046F
81
82 1
83 2
84 3
4
85
86 5
87 6
88 7
8
PORT 3
DATA/PoE OUT
CB4
1000pF
2kV
1808
J4J
SS-73100-046F
91
92 1
93 2
94 3
4
95
96 5
97 6
98 7
8
PORT 4
12-PORT IEEE802.3at PSE MOTHER BOARD
DATE:
N/A
SIZE
1
DATA/PoE OUT
TECHNOLOGY
CZ3 0.01uF
100V 0805
CY3 0.01uF
100V 0805
CX3 0.01uF
100V 0805
CW3 0.01uF
100V 0805
CZ4 0.01uF
100V 0805
CY4 0.01uF
100V 0805
CX4 0.01uF
100V 0805
CW4 0.01uF
100V 0805
DILIAN R. TITLE: SCHEMATIC
KIM T.
APPROVALS
DN3
S1B
DP3
S1B
DN4
S1B
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
APP ENG.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
RR3
RQ3
RP3
RO3
RR4
RQ4
RP4
RO4
2
RJ45
RJ45
5
A
B
C
D
DEMO MANUAL DC1843B
DC1680B SCHEMATIC DIAGRAM
dc1843bfa
25
A
B
C
D
51
1 52
2 53
3 54
4
55
5 56
6 57
7 58
8
41
1 42
2 43
3 44
4
45
5 46
6 47
7 48
8
SS-73100-046F
J3E
E
DATA IN
SS-73100-046F
J3F
F
DATA IN
RJ45
RJ45
5
CA5
1000pF
2kV
1808
CA6
1000pF
2kV
1808
RR5
RQ5
RP5
RO5
RR6
RQ6
RP6
RO6
16
OUT5
VEE
23
2
22
3
24
20
5
75 1
21
19
17
75 4
6
8
18
14
9
75 7
11
13
15
WE, 749022017
T5
75 10
12
VEE
23
OUT6
24
22
3
2
20
75 1
21
5
19
17
75 4
6
8
18
16
9
75 7
14
11
13
15
WE, 749022017
T6
75 10
12
DN5
S1B
DP5
S1B
DN6
S1B
DP6
S1B
4
RZ5
RY5
RX5
RW5
RZ6
RY6
RX6
RW6
4
75
75
75
75
75
75
75
75
CZ5 0.01uF
100V 0805
CY5 0.01uF
100V 0805
CX5 0.01uF
100V 0805
CW5 0.01uF
100V 0805
CZ6 0.01uF
100V 0805
CY6 0.01uF
100V 0805
CX6 0.01uF
100V 0805
CW6 0.01uF
100V 0805
J4H
CB5
1000pF
2kV
1808
J4G
71
1 72
2 73
3 74
4
75
5 76
6 77
7 78
8
61
1 62
2 63
3 64
4
65
5 66
6 67
7 68
8
SS-73100-046F
J3G
G
DATA IN
SS-73100-046F
J3H
H
DATA IN
3
LOWER ROW
SS-73100-046F
61
62 1
63 2
64 3
4
65
66 5
67 6
68 7
8
PORT 5
DATA/PoE OUT
SS-73100-046F
71
72 1
73 2
74 3
4
75
76 5
77 6
78 7
8
PORT 6
DATA/PoE OUT
CB6
1000pF
2kV
1808
3
UPPER ROW
RJ45
RJ45
RJ45
RJ45
CA7
1000pF
2kV
1808
CA8
1000pF
2kV
1808
16
9
CUSTOMER NOTICE
2
3
75 1
5
6
75 4
8
OUT7
16
VEE
23
24
22
20
21
19
17
18
14
9
75 7
11
13
15
WE, 749022017
T7
75 10
12
VEE
23
OUT8
24
22
2
20
3
75 1
21
5
19
17
75 4
6
8
18
14
11
75 7
15
13
75 10
WE, 749022017
T8
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
DP8
S1B
RZ7
RY7
RX7
RW7
RZ8
RY8
RX8
RW8
CZ8 0.01uF
100V 0805
CY8 0.01uF
100V 0805
CX8 0.01uF
100V 0805
CW8 0.01uF
100V 0805
75
75
75
SCALE = NONE
1
SHEET
DEMO CIRCUIT 1680B
Friday, September 04, 2015
IC NO.
3
OF
4
2
REV.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
CB7
1000pF
2kV
1808
J4E
SS-73100-046F
41
42 1
43 2
44 3
4
45
46 5
47 6
48 7
8
PORT 7
DATA/PoE OUT
12-PORT IEEE802.3at PSE MOTHER BOARD
DATE:
N/A
SIZE
J4F
SS-73100-046F
51
52 1
53 2
54 3
4
55
56 5
57 6
58 7
8
PORT 8
DATA/PoE OUT
1
CB8
1000pF
2kV
1808
TECHNOLOGY
CZ7 0.01uF
100V 0805
CY7 0.01uF
100V 0805
CX7 0.01uF
100V 0805
75 CW7 0.01uF
100V 0805
75
75
75
75
DILIAN R. TITLE: SCHEMATIC
KIM T.
APPROVALS
DN7
S1B
DP7
S1B
DN8
S1B
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
APP ENG.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
RR7
RQ7
RP7
RO7
RR8
RQ8
RP8
RO8
12
2
RJ45
26
RJ45
5
A
B
C
D
DEMO MANUAL DC1843B
DC1680B SCHEMATIC DIAGRAM
dc1843bfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
A
B
C
D
91
1 92
2 93
3 94
4
95
5 96
6 97
7 98
8
81
1 82
2 83
3 84
4
85
5 86
6 87
7 88
8
SS-73100-046F
J3I
I
DATA IN
SS-73100-046F
J3J
J
DATA IN
RJ45
RJ45
5
CA9
1000pF
2kV
1808
CA10
1000pF
2kV
1808
RR9
RQ9
RP9
RO9
RR10
RQ10
RP10
RO10
16
VEE
23
OUT9
24
22
3
2
20
75 1
21
5
19
17
75 4
6
8
18
14
9
75 7
11
13
15
WE, 749022017
T9
75 10
12
VEE
23
OUT10
24
22
3
2
20
75 1
21
5
19
17
75 4
6
8
18
16
9
75 7
14
11
13
15
WE, 749022017
T10
75 10
12
DN9
S1B
DP9
S1B
DN10
S1B
DP10
S1B
4
RZ9
RY9
RX9
RW9
RZ10
RY10
RX10
RW10
4
75
75
75
75
CZ9 0.01uF
100V 0805
CY9 0.01uF
100V 0805
CX9 0.01uF
100V 0805
CW9 0.01uF
100V 0805
75 CZ10 0.01uF
100V 0805
75 CY10 0.01uF
100V 0805
75 CX10 0.01uF
100V 0805
75 CW10 0.01uF
100V 0805
J4D
CB9
1000pF
2kV
1808
J4C
111
1 112
2 113
3 114
4
115
5 116
6 117
7 118
8
101
1 102
2 103
3 104
4
105
5 106
6 107
7 108
8
SS-73100-046F
J3K
K
DATA IN
SS-73100-046F
J3L
L
DATA IN
3
LOWER ROW
SS-73100-046F
21
22 1
23 2
24 3
4
25
26 5
27 6
28 7
8
PORT 9
DATA/PoE OUT
SS-73100-046F
31
32 1
33 2
34 3
4
35
36 5
37 6
38 7
8
PORT 10
DATA/PoE OUT
CB10
1000pF
2kV
1808
3
UPPER ROW
RJ45
RJ45
RJ45
RJ45
CA11
1000pF
2kV
1808
CA12
1000pF
2kV
1808
16
9
CUSTOMER NOTICE
2
75 1
3
5
6
75 4
8
OUT11
16
VEE
23
24
22
20
21
19
17
18
14
9
75 7
11
13
15
WE, 749022017
T11
75 10
12
VEE
23
OUT12
24
22
2
20
3
75 1
21
5
19
17
75 4
6
8
18
14
11
75 7
15
13
75 10
WE, 749022017
T12
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
RZ11
RY11
RX11
RW11
RZ12
RY12
RX12
RW12
SCALE = NONE
1
SHEET
DEMO CIRCUIT 1680B
Friday, September 04, 2015
IC NO.
4
OF
4
2
REV.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
CB11
1000pF
2kV
1808
J4A
SS-73100-046F
1
2 1
3 2
4 3
4
5
6 5
7 6
8 7
8
PORT 11
DATA/PoE OUT
12-PORT IEEE802.3at PSE MOTHER BOARD
DATE:
N/A
SIZE
J4B
SS-73100-046F
11
12 1
13 2
14 3
4
15
16 5
17 6
18 7
8
PORT 12
DATA/PoE OUT
1
CB12
1000pF
2kV
1808
TECHNOLOGY
75 CZ11 0.01uF
100V 0805
75 CY11 0.01uF
100V 0805
75 CX11 0.01uF
100V 0805
75 CW11 0.01uF
100V 0805
75 CZ12 0.01uF
100V 0805
75 CY12 0.01uF
100V 0805
75 CX12 0.01uF
100V 0805
75 CW12 0.01uF
100V 0805
DILIAN R. TITLE: SCHEMATIC
KIM T.
APPROVALS
DN11
S1B
DP11
S1B
DN12
S1B
DP12
S1B
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
APP ENG.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
RR11
RQ11
RP11
RO11
RR12
RQ12
RP12
RO12
12
2
RJ45
RJ45
5
A
B
C
D
DEMO MANUAL DC1843B
DC1680B SCHEMATIC DIAGRAM
dc1843bfa
27
DEMO MANUAL DC1843B
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
dc1843bfa
28 Linear Technology Corporation
LT 1215 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2012
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