8321E183236

GS8321E18/32/36E-250/225/200/166/150/133
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
165-Bump FP-BGA
Commercial Temp
Industrial Temp
Features
Functional Description
ct
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
DCD Pipelined Reads
The GS8321E18/32/36E is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
De
sig
Applications
The GS8321E18/32/36E is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
n—
Di
sco
nt
inu
ed
Pr
od
u
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Ne
w
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positiveedge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
No
t
Re
co
m
me
nd
ed
for
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.05 12/2007
Core and Interface Voltages
The GS8321E18/32/36E operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
285
330
5.5
5.5
205
235
250
290
6.0
6.0
195
225
215
255
6.5
6.5
185
210
200
235
7.0
7.0
175
200
190
220
7.5
7.5
165
190
165
195
8.5
8.5
155
175
mA
mA
ns
ns
mA
mA
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BB
NC
E3
BW
ADSC
ADV
A
A
A
B
NC
A
E2
NC
BA
CK
GW
G
ADSP
A
NC
B
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPA
C
D
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
D
E
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
E
F
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
F
G
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
G
H
FT
MCL
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
J
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
J
K
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
K
L
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
L
M
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
M
N
DQPB
NC
P
NC
NC
R
LBO
A
me
nd
ed
for
Ne
w
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
1
De
sig
165 Bump BGA—x18 Commom I/O—Top View (Package E)
VSS
NC
A
NC
VSS
VDDQ
NC
NC
N
A
A
TDI
A1
TDO
A
A
A
A
P
A
A
TMS
A0
TCK
A
A
A
A
R
Re
co
m
VDDQ
No
t
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.05 12/2007
2/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
165 Bump BGA—x32 Common I/O—Top View (Package E)
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
A
NC
B
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
D
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
E
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
F
DQC
DQC
VDDQ
VDD
VSS
VSS
G
DQC
DQC
VDDQ
VDD
VSS
H
FT
MCL
NC
VDD
J
DQD
DQD
VDDQ
K
DQD
DQD
L
DQD
M
A
B
NC
NC
C
VDDQ
DQB
DQB
D
VDD
VDDQ
DQB
DQB
E
VSS
VDD
VDDQ
DQB
DQB
F
VSS
VSS
VDD
VDDQ
DQB
DQB
G
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
J
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
K
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
L
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
M
N
NC
NC
P
NC
NC
R
LBO
A
me
nd
ed
for
Ne
w
n—
Di
sco
nt
inu
ed
Pr
od
u
NC
De
sig
ct
1
VSS
NC
A
NC
VSS
VDDQ
NC
NC
N
A
A
TDI
A1
TDO
A
A
A
A
P
A
A
TMS
A0
TCK
A
A
A
A
R
Re
co
m
VDDQ
No
t
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.05 12/2007
3/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
165 Bump BGA—x36 Common I/O—Top View (Package E)
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
A
NC
B
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
C
DQPC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
D
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
E
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
F
DQC
DQC
VDDQ
VDD
VSS
VSS
G
DQC
DQC
VDDQ
VDD
VSS
H
FT
MCL
NC
VDD
J
DQD
DQD
VDDQ
K
DQD
DQD
L
DQD
M
A
B
NC
DQPB
C
VDDQ
DQB
DQB
D
VDD
VDDQ
DQB
DQB
E
VSS
VDD
VDDQ
DQB
DQB
F
VSS
VSS
VDD
VDDQ
DQB
DQB
G
VSS
VSS
VSS
VDD
NC
NC
ZZ
H
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
J
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
K
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
L
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
M
N
DQPD
NC
P
NC
NC
R
LBO
A
me
nd
ed
for
Ne
w
n—
Di
sco
nt
inu
ed
Pr
od
u
NC
De
sig
ct
1
VSS
NC
A
NC
VSS
VDDQ
NC
DQPA
N
A
A
TDI
A1
TDO
A
A
A
A
P
A
A
TMS
A0
TCK
A
A
A
A
R
Re
co
m
VDDQ
No
t
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.05 12/2007
4/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
GS8321E18/32/36E 165-Bump BGA Pin Description
Type
Description
A 0, A 1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
DQA
DQB
DQC
DQD
I/O
BA , BB , BC , BD
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC
—
No Connect
CK
I
BW
I
Byte Write—Writes all enabled bytes; active low
GW
I
Global Write Enable—Writes all bytes; active low
E1
I
Chip Enable; active low
E3
I
E2
I
G
I
ADV
I
ADSC, ADSP
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep mode control; active high
FT
I
LBO
I
TMS
I
TDI
I
TDO
O
TCK
I
MCL
—
VDD
I
VSS
I
n—
Di
sco
nt
inu
ed
Pr
od
u
Data Input and Output pins
Clock Input Signal; active high
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
De
sig
Burst address counter advance enable; active l0w
me
nd
ed
for
Ne
w
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect Low
Core power supply
I/O and Core Ground
Re
co
m
VDDQ
ct
Symbol
Output driver power supply
No
t
I
Rev: 1.05 12/2007
5/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
GS8321E18/32/36 Block Diagram
Register
D
Q
A0
A0
D0
Q0
A1
D1
Q1
Counter
Load
n—
Di
sco
nt
inu
ed
Pr
od
u
A1
ct
A0–An
A
LBO
ADV
Memory
Array
D
Q
36
Register
D
D
Q
BB
36
D
Ne
w
D
Q
Register
Q
36
36
me
nd
ed
for
D
36
Register
E1
D
Q
4
Re
co
m
FT
G
No
t
Power Down
32
36
Parity
Encode
Register
D
ZZ
4
Register
BD
Q
Register
D
Q
Q
De
sig
D
BC
Register
4
Register
Q
Q
Register
GW
BW
BA
Register
ADSC
ADSP
D
CK
Q
4
Parity
Compare
36
0
DQx1–DQx9
NC
NC
Control
Note: Only x36 version shown for simplicity.
Rev: 1.05 12/2007
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
GS8321E18/32/36E 165-Bump BGA Pin Description
Type
Description
A 0, A 1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA , BB , BC , BD
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC
—
No Connect
CK
I
BW
I
Byte Write—Writes all enabled bytes; active low
GW
I
Global Write Enable—Writes all bytes; active low
E1
I
Chip Enable; active low
E3
I
E2
I
G
I
ADV
I
Burst address counter advance enable; active l0w
ADSC, ADSP
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep mode control; active high
FT
I
LBO
I
TMS
I
TDI
I
TDO
O
TCK
I
MCL
—
VDD
I
VSS
I
VDDQ
I
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
Clock Input Signal; active high
Chip Enable; active low
Chip Enable; active high
De
sig
Output Enable; active low
Flow Through or Pipeline mode; active low
Ne
w
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
me
nd
ed
for
Scan Test Data Out
Scan Test Clock
Must Connect Low
Core power supply
I/O and Core Ground
No
t
Re
co
m
Output driver power supply
Rev: 1.05 12/2007
7/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Pin
Name
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
State
Function
L
Linear Burst
H
Interleaved Burst
n—
Di
sco
nt
inu
ed
Pr
od
u
Mode Name
ct
Mode Pin Functions
L
Flow Through
H or NC
Pipeline
L or NC
Active
Standby, IDD = ISB
H
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
me
nd
ed
for
Note:
The burst counter wraps to initial state on the 5th clock.
Ne
w
1st address
A[1:0] A[1:0] A[1:0] A[1:0]
De
sig
A[1:0] A[1:0] A[1:0] A[1:0]
No
t
Re
co
m
BPR 1999.05.18
Rev: 1.05 12/2007
8/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Write No Bytes
H
L
H
H
H
H
1
Write byte a
H
L
L
Write byte b
H
L
H
Write byte c
H
L
H
Write byte d
H
L
H
Write all bytes
H
L
L
Write all bytes
L
X
X
ct
Function
n—
Di
sco
nt
inu
ed
Pr
od
u
Byte Write Truth Table
H
H
H
2, 3
L
H
H
2, 3
H
L
H
2, 3, 4
H
H
L
2, 3, 4
L
L
L
2, 3, 4
X
X
X
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.05 12/2007
9/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Synchronous Truth Table
W
DQ3
X
X
High-Z
L
X
X
High-Z
L
X
X
X
High-Z
X
L
X
X
X
High-Z
X
X
X
L
X
X
High-Z
H
L
L
X
X
X
Q
H
L
H
L
X
F
Q
H
L
H
L
X
T
D
X
X
H
H
L
F
Q
X
X
X
H
L
F
Q
X
X
H
H
L
T
D
E1
E2
E3
X
H
X
L
L
X
X
X
H
L
None
X
L
Deselect Cycle, Power Down
None
X
L
Deselect Cycle, Power Down
None
X
L
Deselect Cycle, Power Down
None
X
L
Deselect Cycle, Power Down
None
X
H
Read Cycle, Begin Burst
External
R
L
Read Cycle, Begin Burst
External
R
L
Write Cycle, Begin Burst
External
W
L
Read Cycle, Continue Burst
Next
CR
X
Read Cycle, Continue Burst
Next
CR
H
Write Cycle, Continue Burst
Next
CW
X
Write Cycle, Continue Burst
Next
CW
Read Cycle, Suspend Burst
Current
Read Cycle, Suspend Burst
Current
Write Cycle, Suspend Burst
Current
Write Cycle, Suspend Burst
Current
De
sig
Deselect Cycle, Power Down
ADSP ADSC
ADV
ct
Operation
n—
Di
sco
nt
inu
ed
Pr
od
u
State
Address Diagram
Used
Key
X
X
X
H
L
T
D
X
X
X
H
H
H
F
Q
H
X
X
X
H
H
F
Q
X
X
X
H
H
H
T
D
H
X
X
X
H
H
T
D
me
nd
ed
for
Ne
w
H
No
t
Re
co
m
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.05 12/2007
10/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Simplified State Diagram
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
X
Deselect
W
R
X
R
R
First Write
CR
X
CR
Ne
w
De
sig
CW
First Read
me
nd
ed
for
W
X
R
R
Burst Write
Burst Read
X
CR
CW
CR
Re
co
m
Simple Burst Synchronous Operation
Simple Synchronous Operation
W
No
t
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.05 12/2007
11/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Simplified State Diagram with G
ct
X
W
R
W
X
n—
Di
sco
nt
inu
ed
Pr
od
u
Deselect
R
R
First Write
CR
First Read
CW
X
CR
W
Burst Write
me
nd
ed
for
X
Ne
w
De
sig
CW
W
R
CR
CW
R
W
Burst Read
X
CW
CR
No
t
Re
co
m
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.05 12/2007
12/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
–0.5 to 4.6
VI/O
Voltage on I/O Pins
VIN
Voltage on Other Input Pins
IIN
Input Current on Any Pin
IOUT
Output Current on Any I/O Pin
PD
Package Power Dissipation
TSTG
Storage Temperature
TBIAS
Temperature Under Bias
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Symbol
V
–0.5 to VDDQ +0.5 (≤ 4.6 V max.)
V
–0.5 to VDD +0.5 (≤ 4.6 V max.)
V
+/–20
mA
+/–20
mA
1.5
W
–55 to 125
o
–55 to 125
o
C
C
De
sig
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Parameter
Symbol
Min.
Typ.
Max.
Unit
3.3 V Supply Voltage
Ne
w
Power Supply Voltage Ranges
VDD3
3.0
3.3
3.6
V
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
me
nd
ed
for
2.5 V Supply Voltage
Notes
No
t
Re
co
m
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.05 12/2007
13/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
2.0
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.8
V
1
VDDQ I/O Input High Voltage
VIHQ
2.0
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.8
V
1,3
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
ct
VDDQ3 Range Logic Levels
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Parameter
Symbol
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V
1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
–0.3
—
0.3*VDD
V
1,3
De
sig
Min.
Ne
w
VDDQ2 Range Logic Levels
VILQ
me
nd
ed
for
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
2
Ambient Temperature (Industrial Range Versions)
TA
–40
25
85
°C
2
Re
co
m
Parameter
No
t
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.05 12/2007
14/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
50% tKC
VDD + 2.0 V
VSS
n—
Di
sco
nt
inu
ed
Pr
od
u
50%
ct
50%
VDD
VSS – 2.0 V
50% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
6
7
pF
AC Test Conditions
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output load
me
nd
ed
for
Output reference level
Ne
w
Parameter
De
sig
Note:
These parameters are sample tested.
VDDQ/2
Fig. 1
Output Load 1
DQ
No
t
Re
co
m
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
50Ω
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
Rev: 1.05 12/2007
15/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
Rev: 1.05 12/2007
OH
DD
–100 uA
–1 uA
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
IIN2
1 uA
1 uA
1 uA
100 uA
1 uA
Max
OH2
OH3
OL
Output High Voltage
Output Low Voltage
OL
OH
OL
DDQ
DDQ
OUT
Output Disable, V
= 0 to V
–1 uA
1 uA
meI
I = –8 mA, V
= 2.375 V
Vn
1.7 V
—
d
V
I = –8 mA, V
= 3.135 V
2.4 V
—
ed
V
I = 8 mA
for
—
0.4 V
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
Output High Voltage
Output Leakage Current
FT, SCD, ZQ Input Current
Re
co
m
–1 uA
–1 uA
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
IIN1
ZZ Input Current
No
t
–1 uA
VIN = 0 to VDD
IIL
Min
Input Leakage Current
(except mode pins)
Test Conditions
Symbol
Parameter
DC Electrical Characteristics
ct
GS8321E18/32/36E-250/225/200/166/150/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
16/35
© 2003, GSI Technology
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
GS8321E18/32/36E-250/225/200/166/150/133
Rev: 1.05 12/2007
17/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Operating Currents
Operating
Current
Test Conditions
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
Symbol
0
to
70°C
Pipeline
IDD
IDDQ
280
50
290
50
245
45
255
45
215
40
Flow
Through
IDD
IDDQ
210
25
220
25
200
25
210
25
IDD
260
25
270
25
225
25
Mode
(x32/
x36)
Pipeline
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
—
—
IDD
0
to
70°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
225
40
200
35
210
35
190
30
200
30
170
25
190
20
200
20
180
20
190
20
170
20
180
20
160
15
235
25
195
20
205
20
180
20
190
20
170
20
180
20
150
15
–40
to
85°C
0
to
70°C
-150
–40
to
85°C
Flow
Through
IDDQ
190
15
200
15
180
15
190
15
170
15
180
15
160
15
170
15
150
15
160
15
140
15
Pipeline
ISB
40
50
40
50
40
50
40
50
40
50
40
Flow
Through
ISB
40
50
40
50
40
50
40
50
40
50
40
Pipeline
IDD
75
80
75
80
70
75
70
75
65
70
60
Flow
Through
IDD
65
70
65
70
60
65
60
65
55
60
50
Ne
w
ZZ ≥ VDD – 0.2 V
IDDQ
–40
to
85°C
-166
De
sig
(x18)
Standby
Current
-200
n—
Di
sco
nt
inu
ed
Pr
od
u
Parameter
-225
ct
-250
No
t
Re
co
m
me
nd
ed
for
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Rev: 1.05 12/2007
18/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
AC Electrical Characteristics
Clock Cycle Time
-250
-225
-200
-166
-150
Max
Min
Max
Min
Max
Min
Max
tKC
5.5
—
6.0
—
6.5
—
7.0
—
Clock to Output Valid
tKQ
—
5.5
—
6.0
—
6.5
—
Clock to Output Invalid
tKQX
3.0
—
3.0
—
3.0
—
Clock to Output in Low-Z
tLZ1
3.0
—
3.0
—
3.0
Setup time
tS
1.5
—
1.5
—
Hold time
tH
0.5
—
0.5
Clock HIGH Time
tKH
1.3
—
1.3
Clock LOW Time
tKL
1.5
—
1.5
Clock to Output in
High-Z
tHZ1
1.5
2.5
1.5
G to Output Valid
tOE
—
2.5
—
G to output in Low-Z
tOLZ1
0
—
G to output in High-Z
tOHZ1
—
2.5
ZZ setup time
tZZS2
5
ZZ hold time
tZZH2
1
tZZR
20
ZZ recovery
Unit
Min
Max
Min
Max
7.5
—
8.5
—
ns
7.0
—
7.5
—
8.5
ns
3.0
—
3.0
—
3.0
—
ns
—
3.0
—
3.0
—
3.0
—
ns
1.5
—
1.5
—
1.5
—
1.5
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
—
1.3
—
1.3
—
1.5
—
1.7
—
ns
—
1.5
—
1.5
—
1.7
—
2
—
ns
2.7
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
2.7
—
3.2
—
3.5
—
3.8
—
4.0
ns
0
—
0
—
0
—
0
—
0
—
ns
—
2.7
—
3.0
—
3.0
—
3.0
—
3.0
ns
—
5
—
5
—
5
—
5
—
5
—
ns
—
1
—
1
—
1
—
1
—
1
—
ns
—
20
—
20
—
20
—
20
—
20
—
ns
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
Min
-133
ct
Symbol
me
nd
ed
for
Flow
Through
Parameter
No
t
Re
co
m
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.05 12/2007
19/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Pipeline Mode Timing (DCD)
Read A
Cont
Deselect Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Cont
tKC
CK
ADSP
tS
ADSC initiated read
tH
ADSC
tS
tH
ADV
tS
tH
Ao–An
A
B
C
tS
GW
tS
tH
BW
Ba–Bd
tS
tH
tS
E2 and E3 only sampled with ADSC
tH
tH
G
me
nd
ed
for
E2
E3
tS
tOE
Hi-Z
tOHZ
Q(A)
tKQ
tH
D(B)
tHZ
tLZ
tKQX
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
No
t
Re
co
m
DQa–DQd
Deselected with E1
Ne
w
E1
De
sig
tH
tS
tS
n—
Di
sco
nt
inu
ed
Pr
od
u
tKL
tKH
Deselect Deselect
ct
Begin
Rev: 1.05 12/2007
20/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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Flow Through Mode Timing (DCD)
Read A
Cont
Deselect Write B
Read C
tKH
tKC
CK
ADSP
tS
tH
ADSC
initiated read
ADSC
tH
tS
tS
ADV
tS
tH
A
B
C
tS
tH
tS
tH
BW
Ba–Bd
tS
tH
tS
tH
E2
tS
tH
E3
E2 and E3 only sampled with ADSP and ADSC
Re
co
m
G
Deselected with E1
E1 masks ADSP
me
nd
ed
for
E1
Ne
w
tH
tS
tH
De
sig
GW
E1 masks ADSP
tH
tS
tOE
tKQ
tOHZ
Q(A)
tKQX
tHZ
tLZ
D(B)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
No
t
DQa–DQd
Deselect
Fixed High
tS
tH
Ao–An
Read C+1 Read C+2 Read C+3 Read C
n—
Di
sco
nt
inu
ed
Pr
od
u
tKL
ct
Begin
Rev: 1.05 12/2007
21/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
De
sig
ADSC
tZZS
me
nd
ed
for
Ne
w
ZZ
tZZR
tZZH
Application Tips
Re
co
m
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
No
t
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
Rev: 1.05 12/2007
22/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
JTAG Pin Descriptions
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Test Data In
TDO
Test Data Out
n—
Di
sco
nt
inu
ed
Pr
od
u
TDI
ct
Pin
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Ne
w
De
sig
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
me
nd
ed
for
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
No
t
Re
co
m
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.05 12/2007
23/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
·
·
·
·
·
·
·
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inu
ed
Pr
od
u
·
ct
JTAG TAP Block Diagram
Boundary Scan Register
·
1
·
·
108
0
0
Bypass Register
2 1 0
Instruction Register
TDI
TDO
ID Code Register
·
· ··
2 1 0
De
sig
31 30 29
Control Signals
TMS
Test Access Port (TAP) Controller
Ne
w
TCK
No
t
Die
Revision
Code
Re
co
m
ID Register Contents
GSI Technology
JEDEC Vendor
ID Code
I/O
Configuration
Not Used
Presence Register
me
nd
ed
for
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x36
X
X
x18
X
X
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
1
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
1
Rev: 1.05 12/2007
24/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Tap Controller Instruction Set
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Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
0
Run Test Idle
1
Select DR
1
Select IR
0
0
1
De
sig
Shift DR
Ne
w
1
me
nd
ed
for
1
0
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
1
Update DR
1
Capture IR
0
0
Pause IR
1
Exit2 IR
0
1
0
0
Update IR
1
0
No
t
Re
co
m
1
Capture DR
0
1
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
Rev: 1.05 12/2007
25/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
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ct
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
De
sig
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
Ne
w
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
me
nd
ed
for
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
No
t
Re
co
m
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.05 12/2007
26/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
JTAG TAP Instruction Set Summary
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
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ct
Instruction
1
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
BYPASS
111
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
1
Rev: 1.05 12/2007
27/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
JTAG Port Recommended Operating Conditions and DC Characteristics
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
VIHJ3
2.0
VDD3 +0.3
V
1
3.3 V Test Port Input Low Voltage
VILJ3
–0.3
0.8
V
1
2.5 V Test Port Input High Voltage
VIHJ2
0.6 * VDD2
VDD2 +0.3
V
1
VILJ2
–0.3
0.3 * VDD2
V
1
IINHJ
–300
1
uA
2
IINLJ
–1
100
uA
3
IOLJ
–1
1
uA
4
VOHJ
1.7
—
V
5, 6
VOLJ
—
0.4
V
5, 7
VOHJC
VDDQ – 100 mV
—
V
5, 8
VOLJC
—
100 mV
V
5, 9
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Parameter
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
me
nd
ed
for
Ne
w
De
sig
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Input high level
Input low level
Re
co
m
Input slew rate
Conditions
VDD – 0.2 V
JTAG Port AC Test Load
DQ
0.2 V
50Ω
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
No
t
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.05 12/2007
28/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTS
TMS
tTKQ
TDO
tTH
tTS
JTAG Port AC Electrical Characteristics
De
sig
Parallel SRAM input
n—
Di
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inu
ed
Pr
od
u
TDI
ct
tTH
tTS
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
50
—
ns
TCK Low to TDO Valid
tTKQ
—
20
ns
TCK Low Pulse Width
TDI & TMS Set Up Time
tTKH
20
—
ns
tTKL
20
—
ns
tTS
10
—
ns
tTH
10
—
ns
Re
co
m
TDI & TMS Hold Time
me
nd
ed
for
TCK High Pulse Width
Ne
w
Parameter
No
t
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: [email protected]
Rev: 1.05 12/2007
29/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
Ø0.10 M C
Ø0.25 M C A B
Ø0.40~0.60 (165x)
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
1.0
14.0
Ne
w
1.0
10.0
15±0.05
0.20(4x)
No
t
Re
co
m
0.36~0.46
1.50 MAX.
SEATING PLANE
C
B
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
me
nd
ed
for
0.20 C
A
De
sig
17±0.05
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
11 10 9 8 7 6 5 4 3 2 1
Rev: 1.05 12/2007
30/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
TA3
250/5.5
C
165 BGA
225/6
C
DCD Pipeline/Flow Through
165 BGA
200/6.5
C
GS8321E18E-166
DCD Pipeline/Flow Through
165 BGA
166/7
C
2M x 18
GS8321E18E-150
DCD Pipeline/Flow Through
165 BGA
150/7.5
C
2M x 18
GS8321E18E-133
DCD Pipeline/Flow Through
165 BGA
133/8.5
C
1M x 32
GS8321E32E-250
DCD Pipeline/Flow Through
165 BGA
250/5.5
C
1M x 32
GS8321E32E-225
DCD Pipeline/Flow Through
165 BGA
225/6
C
1M x 32
GS8321E32E-200
DCD Pipeline/Flow Through
165 BGA
200/6.5
C
1M x 32
GS8321E32E-166
DCD Pipeline/Flow Through
165 BGA
166/7
C
1M x 32
GS8321E32E-150
DCD Pipeline/Flow Through
165 BGA
150/7.5
C
1M x 32
GS8321E32E-133
DCD Pipeline/Flow Through
165 BGA
133/8.5
C
1M x 36
GS8321E36E-250
DCD Pipeline/Flow Through
165 BGA
250/5.5
C
1M x 36
GS8321E36E-225
DCD Pipeline/Flow Through
165 BGA
225/6
C
1M x 36
GS8321E36E-200
DCD Pipeline/Flow Through
165 BGA
200/6.5
C
1M x 36
GS8321E36E-166
DCD Pipeline/Flow Through
165 BGA
166/7
C
1M x 36
GS8321E36E-150
DCD Pipeline/Flow Through
165 BGA
150/7.5
C
1M x 36
GS8321E36E-133
DCD Pipeline/Flow Through
165 BGA
133/8.5
C
2M x 18
GS8321E18E-250I
DCD Pipeline/Flow Through
165 BGA
250/5.5
I
2M x 18
GS8321E18E-225I
DCD Pipeline/Flow Through
165 BGA
225/6
I
2M x 18
GS8321E18E-200I
DCD Pipeline/Flow Through
165 BGA
200/6.5
I
2M x 18
GS8321E18E-166I
DCD Pipeline/Flow Through
165 BGA
166/7
I
2M x 18
GS8321E18E-150I
DCD Pipeline/Flow Through
165 BGA
150/7.5
I
Type
Package
2M x 18
GS8321E18E-250
DCD Pipeline/Flow Through
165 BGA
2M x 18
GS8321E18E-225
DCD Pipeline/Flow Through
2M x 18
GS8321E18E-200
2M x 18
No
t
Re
co
m
me
nd
ed
for
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
Part Number1
ct
Speed2
(MHz/ns)
Org
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8321E18E-166IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 12/2007
31/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
2M x 18
GS8321E18E-133I
DCD Pipeline/Flow Through
165 BGA
133/8.5
I
1M x 32
GS8321E32E-250I
DCD Pipeline/Flow Through
165 BGA
250/5.5
I
1M x 32
GS8321E32E-225I
DCD Pipeline/Flow Through
165 BGA
225/6
I
1M x 32
GS8321E32E-200I
DCD Pipeline/Flow Through
165 BGA
200/6.5
I
1M x 32
GS8321E32E-166I
DCD Pipeline/Flow Through
165 BGA
166/7
I
1M x 32
GS8321E32E-150I
DCD Pipeline/Flow Through
165 BGA
150/7.5
I
1M x 32
GS8321E32E-133I
DCD Pipeline/Flow Through
165 BGA
133/8.5
I
1M x 36
GS8321E36E-250I
DCD Pipeline/Flow Through
165 BGA
250/5.5
I
1M x 36
GS8321E36E-225I
DCD Pipeline/Flow Through
165 BGA
225/6
I
1M x 36
GS8321E36E-200I
DCD Pipeline/Flow Through
165 BGA
200/6.5
I
1M x 36
GS8321E36E-166I
DCD Pipeline/Flow Through
165 BGA
166/7
I
1M x 36
GS8321E36E-150I
DCD Pipeline/Flow Through
165 BGA
150/7.5
I
1M x 36
GS8321E36E-133I
DCD Pipeline/Flow Through
165 BGA
133/8.5
I
2M x 18
GS8321E18GE-250
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
C
2M x 18
GS8321E18GE-225
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
225/6
C
2M x 18
GS8321E18GE-200
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
C
2M x 18
GS8321E18GE-166
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
166/7
C
2M x 18
GS8321E18GE-150
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
C
2M x 18
GS8321E18GE-133
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
133/8.5
C
1M x 32
GS8321E32GE-250
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
C
1M x 32
GS8321E32GE-225
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
225/6
C
1M x 32
GS8321E32GE-200
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
C
1M x 32
GS8321E32GE-166
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
166/7
C
1M x 32
GS8321E32GE-150
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
C
n—
Di
sco
nt
inu
ed
Pr
od
u
De
sig
Ne
w
me
nd
ed
for
Re
co
m
ct
Org
No
t
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8321E18E-166IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 12/2007
32/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
1M x 32
GS8321E32GE-133
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
133/8.5
C
1M x 36
GS8321E36GE-250
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
C
1M x 36
GS8321E36GE-225
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
225/6
C
1M x 36
GS8321E36GE-200
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
C
1M x 36
GS8321E36GE-166
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
166/7
C
1M x 36
GS8321E36GE-150
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
C
1M x 36
GS8321E36GE-133
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
133/8.5
C
2M x 18
GS8321E18GE-250I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
I
2M x 18
GS8321E18GE-225I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
225/6
I
2M x 18
GS8321E18GE-200I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
I
2M x 18
GS8321E18GE-166I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
166/7
I
2M x 18
GS8321E18GE-150I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
I
2M x 18
GS8321E18GE-133I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
133/8.5
I
1M x 32
GS8321E32GE-250I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
I
1M x 32
GS8321E32GE-225I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
225/6
I
Ne
w
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
ct
Org
No
t
Re
co
m
me
nd
ed
for
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8321E18E-166IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 12/2007
33/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
1M x 32
GS8321E32GE-200I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
I
1M x 32
GS8321E32GE-166I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
166/7
I
1M x 32
GS8321E32GE-150I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
I
1M x 32
GS8321E32GE-133I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
133/8.5
I
1M x 36
GS8321E36GE-250I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
250/5.5
I
1M x 36
GS8321E36GE-225I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
225/6
I
1M x 36
GS8321E36GE-200I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
200/6.5
I
1M x 36
GS8321E36GE-166I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
166/7
I
1M x 36
GS8321E36GE-150I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
150/7.5
I
1M x 36
GS8321E36GE-133I
DCD Pipeline/Flow Through
RoHS-compliant 165 BGA
133/8.5
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Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8321E18E-166IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 12/2007
34/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8321E18/32/36E-250/225/200/166/150/133
36Mb Sync SRAM Datasheet Revision History
New
Page;Revisions;Reason
• Creation of new datasheet
8321Exx_r1
ct
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Content
• Added parity bit designators to x18 and x36 pinouts
• Removed address pin numbers (except 0 and 1)
• Corrected “E” package thickness to 1.4 mm
8321Exx_r1_01;
8321Exx_r1_02
Content/Format
• Updated format
• Added variation information to package mechanical
8321Exx_r1_02;
8321Exx_r1_03
Content
8321Exx_r1_03;
8321Exx_r1_04
Content
8321Exx_r1_04;
8321Exx_r1_05
Content
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8321Exx_r1; 8321Exx_r1_01
• RoHS-compliant information added
• Updated Truth Tables (pg. 9, 10)
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• Removed Preliminary banner due to production status
• Updated mechanical drawing
Rev: 1.05 12/2007
35/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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