DC1029B - Demo Manual

DEMO MANUAL DC1029B
LTC2928
Multichannel Power Supply
Sequencer and Supervisor
DESCRIPTION
Demonstration circuit 1029B is for evaluating the performance of the LTC®2928 Multichannel Power Supply
Sequencer and Supervisor.
The LTC2928 sequences and monitors up to four power
channels in power-up and power-down, and it monitors
those outputs in the steady state. Sequencing is accomplished by controlling the power supply enable inputs or
N-channel MOSFET gates with the LTC2928 outputs. Supervisory functions include undervoltage and overvoltage
monitoring, and capturing the output state information in
the event of a system fault.
Inherent fault detection circuitry can detect:
nn
nn
nn
System controller command errors
nn
Externally commanded faults
nn
Sequencing faults
The board is populated with nineteen jumpers for selection
of the LTC2928 operation options and with twelve LEDs
for displaying:
nn
nn
nn
Stalled supplies (during sequencing)
Supplies with the output voltage not satisfying the
undervoltage or overvoltage conditions
The undervoltage status in the steady state
CMP1 (D5) – CMP4 (D8)
The LTC2928 controlling outputs states
EN1 (D1) – EN4 (D4)
The state signals of the ON pin (#16), the RST
pin (#21), the OV pin (#20), and the FLT pin (#19).
Design files for this circuit board are available at
http://www.linear.com/demo/DC1029B
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
PERFORMANCE SUMMARY
SYMBOL
PARAMETER
Specifications are at TA = 25°C
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
VCC Input Supply Range
2.9
6.0
V
VHVCC
HVCC Input Supply Range
7.2
12.0
16.5
V
VON
ON Threshold Voltage
VON Rising
0.985
1.0
1.15
V
VMON(TH)
Voltage Monitor Reset Threshold Voltage
VSEL = VCC
VEN
Enable Pin Voltage Output in ON State
IEN(UP)
Enable Pin Pull-Up Current
Enable Pin ON, VEN ≤ VCC + 4V
tSTMR
Sequence Timer Period, STMR
CSTMR = 0.022µF
tPTMR
Power Good Timer Period
tRTMR
Reset Timer
V1
V2
V3
V4
V1 Internal and External Input
V2 Internal and External Input
V3 Internal and External Input
V4 Internal and External Input
TPV1
TPV2
TPV3
TPV4
V1 Time Position
V2 Time Position
V3 Time Position
V4 Time Position
0.492
0.500
0.508
V
VCC + 4.5
VCC + 5.5
VCC + 6
V
–7.5
–10
–12.5
µA
161
190
220
ms
CPTMR = 2.2µF
7.33
8.80
10.27
s
CRTMR = 0.047μF
156.7
188.0
219.3
ms
2.5
1.5
1.8
3.3
V
V
V
V
1
3
5
7
dc1029bf
1
DEMO MANUAL DC1029B
OPERATING PRINCIPLES
A single LTC2928 can control four positive supplies or
three positive and one negative.
Each supply timing position in the sequence can be any one
of eight available time positions. Refer to the data sheet
for the external resistor values for setting the sequence
time position.
Power is applied to the LTC2928 through either the VCC
pin (2.9V to 6V) or the HVCC pin (7.2V to 16.5V).
Each one of the four enable outputs (EN1, EN2, EN3, EN4)
provides a (VCC + 4.5V) signal to control a MOSFET gate
or a power supply enable input.
The LTC2928 monitors four supply thresholds per supply
(sequence-up, sequence-down, undervoltage, overvoltage) during a full LTC2928 operation cycle. A full operation
cycle includes two transient phases (sequence-up and
sequence-down) and one monitor (steady state) phase.
The time intervals between adjacent supplies’ enable or
disable signal is set by the value of the sequence timer
capacitor with a timing scale factor of 8670ms/µF. The
sequencing-up interval is equal to the sequencing-down
interval.
2
The power good timer period defines the maximum time
allowed by any input supply to reach its undervoltage
threshold (in power-up) or drop to its sequencing-down
threshold (in power-down). This period is set by a power
good timer capacitor with a timing scale factor of 4000ms/µF.
During the sequence-up phase, supply monitor inputs are
expected to cross their sequence-up threshold (which may
be different from their undervoltage threshold). Any supply
monitor input failing to cross its sequence-up threshold
will stall the process and a sequence-up fault is generated.
During the sequence-down phase, supply monitor inputs
are expected to cross their sequence-down threshold
(which can be different from their undervoltage threshold)
within the selected power good time. Any supply monitor
input failing to cross its sequence-down threshold will stall
the process and generate a sequence-down fault.
Refer to the LTC2928 data sheet for sequencing threshold
selection by biasing the SQT1 and SQT2 pins.
dc1029bf
DEMO MANUAL DC1029B
QUICK START PROCEDURE
For fast evaluation of LTC2928 performance, the board contains four low drop out regulators (LDO): LT1761ES-2.5,
LT1761ES-1.5, LT1761ES-1.8, LT1761ES-3.3, and a push
button with control circuitry for ON control signal generation. LDO outputs are +2.5V, +1.5V, 1.8V, and +3.3V. Each
LDO has an enable input, and works as a power supply.
Demonstration circuit 1029B is easy to set up to evaluate
the performance of the LTC2928 with the on-board supplies. Refer to Figure 1 for the proper circuit connection.
For the load resistors R1, R2, R3, and R4 use 51Ω 1W
resistors. Connect four scope probes to the load resistors
R1, R2, R3, and R4.
Place jumpers in the following positions:
JP1 (OPERATION)
LAST
JP2 (ON)
INT_ON
JP3 (V1)
INT
JP4 (V3)
INT
JP5 (V2)
INT
JP6 (V4)
INT
JP7 (SQT1)
GND
JP8 (VSEL)
ALL POSITIVE
JP9 (RT1 Control)
TIME POSITION
JP10 (SQT2)
GND
JP11 (V1 POLARITY)
V1_POS
JP12 (MS1)
GND
JP13 (RT2 Control)
TIME POSITION
JP14 (OVA CONFIG)
32%
JP15 (MS2)
GND
JP16 (RT3 Control)
TIME POSITION
JP17 (VCC Select)
LOW VCC
JP18 (RDIS)
OPEN
JP19 (RT4 Control)
TIME POSITION
1.With the +5V power supply off, connect the supply to
the 5V_AUX and GND turrets.
2. Turn the +5V supply on and after that switch the ON control signal from low to high by pressing the button S1.
3. The power-up output voltages should correlate with the
transient shown in Figure 3 (power-up phase). Acceptable tolerance in the sequence timing is ±20%.
4.Press the button PB (S1) to change the ON signal
from high to low and observe the output voltages. The
power-down output voltages should correlate with the
transient shown in Figure 3. (power-down phase). Acceptable tolerance in the sequence timing is ±20%.
5.Turn the +5V power supply off and connect four external power supply terminals with DC1029 as shown
in Figure 2. Use external power supplies with output
voltages +2.5V, +1.5V, +1.8V, and +3.3V. Leave output
loads as in previous experiments or replace them with
3W resistors 2.5Ω, 1.5Ω, 2Ω, and 3Ω accordingly to
have current in each rail around 1A.
6.Change jumpers V1 (JP1), V2 (JP2), V3 (JP3), and V4
(JP4) positions from INT to EXT.
7.Turn-on all five power supplies. Pushing the button
PB (S1) changes the ON signal from low to high and
after the power-up transient completes, press PB (S1)
a second time to initiate the power-down. The output
voltage sequence timing should be similar to the timing
with the internal power supplies.
8.The DC1029B could be used for the original customer
design. Based on the sequence timing and threshold
parameters define all the optional components’ values,
replace them on the board and verify design performance. Contact LTC Field Applications Engineers to
get help in the designing or verifying your circuit with
a special tool.
dc1029bf
3
DEMO MANUAL DC1029B
QUICK START PROCEDURE
Figure 1. Demo Circuit 1029 Connections for Operation with Internal Supplies
4
dc1029bf
DEMO MANUAL DC1029B
QUICK START PROCEDURE
Figure 2. Demo Circuit 1029 Connections for Operation with External Supplies
dc1029bf
5
DEMO MANUAL DC1029B
QUICK START PROCEDURE
Figure 3. Power-Up and Power-Down Transients
6
dc1029bf
A
B
C
5
ON
RDIS
MS2
MS1
SQT2
SQT1
RT4
RT3
RT2
RT1
REF
V1
EN1
OVA
V2
3
V1
4
2
EN1
7
8
9
10
11
12
RT2
RT3
RT4
SQT1
SQT2
MS1
ON
RDIS
MS1
SQT2
SQT1
RT4
RT3
RT2
RT1
REF
NC
V1
EN1
OVA
36
U1
LTC2928CUHF
CAS
3
JP1
VCC
OPERATION
1
LAST
2
NOT LAST
E1
CAS
6
RT1
MS2
5
REF
4
1
OVA
38
13
V2
4
37
V2
14
RDIS
15
CAS
16
MS2
EN2
35
CMP2
34
CMP1
ON
33
CMP4
NC
17
EN4
V4
EN3
3
VCC
C3
1uF
25V
C4
1uF
25V
CUSTOMER NOTICE
E2
DONE#
20
21
22
23
24
HVCC
STMR
26
25
PTMR
27
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
3
C1
0.022uF
2
IC NO.
DATE
1
SHEET
1
OF
5
1
REV.


 www.linear.com


Oct 20, 2015




MODIFY DATE: 

SIZE
FLT#
OV#
RST#
VSEL
TECHNOLOGY
FLT#
OV#
RST#
Vlad Ostrerov TITLE: SCHEMATIC

SCALE = NONE
APP ENG.
PCB DES.
APPROVALS
0.047uF
C5
C2 2.2uF
VSEL
V4
EN4
RTMR
EN4
28
EN3
V4
29
V3
CMP3
CMP4
CMP1
CMP2
EN2
1
Vlad Ostrerov
EN3
V3
CMP3
CMP4
CMP1
CMP2
EN2
Replaced obsolete LED's
REVISION HISTORY
DESCRIPTION
APPROVED
30
B
2
31

ECO REV
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
R1
3.3K
OV#
RST#
VCC
HVCC
GND
VSEL
STMR
PTMR
RTMR
V3
32
CMP3
DONE#
18
FLT#
19
D
5
A
B
C
D
DEMO MANUAL DC1029B
SCHEMATIC DIAGRAM
dc1029bf
7
A
B
C
E4
ON
EN1
ON
5
Q9
2N7002
D9
ON
GRN
R11
300
Q2
2N7002
Q1
2N7002
EN2
D2
EN2
YEL
R3
300
D1
EN1
YEL
R2
300
RESET
E5
EN3
RST#
D10
RESET
RED
R12
1.5K
Q3
2N7002
D3
EN3
YEL
R4
300
4
EN4
4
OV#
OVERVOLTAGE
E6
Q4
2N7002
D4
EN4
YEL
R5
300
5V_AUX
FAULT
E7
FLT#
3
D12
FAULT
RED
R14
1.5K
5V_AUX
CMP2

D11
OVERVOLTAGE
RED
R13
1.5K
CMP1
Q5
2N7002
D5
CMP1
ORN
R6
300
3
Q6
2N7002
D6
CMP2
ORN
R7
300
0.1uF
C6
CMP3
PB
S1
VCC
PB
VIN
C7
4700pF
2
1
U2
LTC2950CTS8-1
CMP4

C8
4700pF
KILL
8
6
5
2
SCALE = NONE
ON
R10
10K
JP2
ON
E3
ON
EXT_ON
INT_ON
1
SHEET
2
OF
5
1
REV.


 www.linear.com


3
2
1
FLT#
OV#
RST#
ON
CMP4
CMP3
CMP2
CMP1
EN4
EN3
EN2
EN1
1




IC NO.
MODIFY DATE: 

SIZE
R39
10K
VCC
FLT#
OV#
RST#
ON
CMP4
CMP3
CMP2
CMP1
EN4
EN3
EN2
EN1
TECHNOLOGY
APP ENG. Vlad Ostrerov TITLE: SCHEMATIC
PCB DES.
INT
EN/EN
Q8
2N7002
D8
CMP4
ORN
R9
300
5V_AUX
APPROVALS
Q7
2N7002
D7
CMP3
ORN
R8
300
2
GND
4
ONT
3
OFFT
8
7
D
5
A
B
C
D
DEMO MANUAL DC1029B
SCHEMATIC DIAGRAM
dc1029bf
A
B
C
D
5
E16
EN2
E10
EN1
5
EN2
EN1
C11
TBD
C9
TBD
100
R21
100
R15
E18
V2_MON
E14
V2_FET
E12
V1_MON
V2_MON
R23
182K
1%
R17
88.7K
1%
Q12
IRL3704ZSPBF
V2_FET
V1_MON
Q10
IRL3704ZSPBF
V1_FET
R20
49.9K
1%
R25
49.9K
1%
V2
3
2
1
V1_POL
V1
3
JP5
V2
INT
V2
EXT
V2_INT
V1_POL
V1
EXT
V1_INT
JP3
V1
1
INT
2
3
E17
EN4
E11
EN3
EN4
EN3
EN4
EN3
C12
TBD
C10
TBD
4
3


EN2
EN1
E8
V1_FET
4
R16
100
R22
100
V4_MON

2
SCALE = NONE
APP ENG. Vlad Ostrerov
PCB DES.
R18
118K
1%
TECHNOLOGY
V4
EXT
1
SHEET
3
OF
5
1
REV.


 www.linear.com


1


IC NO.


MODIFY DATE: 

SIZE
V3
EXT
V4_INT
JP6
V4
INT
R26
49.9K
1%
V4
3
2
1
R19
49.9K
1%
V3
3
V3_INT
JP4
V3
1
INT
2
TITLE: SCHEMATIC
261K
1%
R24
Q13
IRL3704ZSPBF
V4_FET
V3_MON
Q11
IRL3704ZSPBF
V3_FET
APPROVALS
E19
V4_MON
E15
V4_FET
E13
V3_MON
E9
V3_FET
2
A
B
C
D
DEMO MANUAL DC1029B
SCHEMATIC DIAGRAM
dc1029bf
9
10
A
B
C
D








5
5
RT4
RT3
RT2
RT1
RT4
R34
3.40K
1%
RT3
R32
9.53K
1%
RT2
R30
24.3K
1%
RT1
R27
95.3K
1%
VCC
VCC
VCC
VCC
FORCE OFF
TIME POSITION
FORCE OFF
FORCE OFF
4
FORCE OFF
JP19
RT4 CONTROL
1
FORCE ON
2
TIME POSITION
3
4
JP16
RT3 CONTROL
1
FORCE ON
2
TIME POSITION
3
4
JP13
RT2 CONTROL
1
FORCE ON
2
TIME POSITION
3
4
3
JP9
RT1 CONTROL
1
FORCE ON
2
4
4
E20
VCC IN
LOW Vcc:2.9V-6V
HVcc:8V-16.5V
OVA
REF
V1
ALL POSITIVE
(Opt)
R29
3
VCC
V1_NEG
JP11
V1_POLARITY
1
V1_POS
2
3
2
V1_NEG
R33
5.1K
3
LOW VCC 3
2
JP17
VCC Select
1
LOW VCC(2.9V to 6V)
HVCC(8V to 16.5V)

2
SCALE = NONE
APP ENG. Vlad Ostrerov
PCB DES.
APPROVALS
JP18
RDIS
GND
OPEN
VCC
GND
OPEN
VCC
GND
OPEN
VCC
GND
OPEN
VCC
GND
OPEN
VCC
1
SHEET
4
OF
5
1
REV.


 www.linear.com


4
3
2
1
4
3
JP15
MS2
JP12
MS1
4
3
2
JP10
SQT2
1
4
3
2
JP7
SQT1
1
1


IC NO.


MODIFY DATE: 

SIZE
RDIS
VCC
TECHNOLOGY
RDIS
TITLE: SCHEMATIC


MS2
MS2
VCC
4
3
2


MS1
2
1
VCC
VCC
SQT2
SQT1
(Opt)
<32%
32%
MS1
SQT2
SQT1
VCC
1
6



2
R31
4
5
2 >32%
3
1
JP14
OVA CONFIG ABOVE UV
HVCC
HVCC
R_GND
R28
TBD
R_VCC
REF
V1
V1_POL
VSEL
VCC
OVA
VIN
V1_POL
VSEL
VCC JP8
VSEL
1

3
A
B
C
D
DEMO MANUAL DC1029B
SCHEMATIC DIAGRAM
dc1029bf
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5
E25
SHDN1.5
B
E24
EXTERNAL
SHDN2.5
A
5V_AUX
E30
GND
3
E31
GND
JP20
SUPPLIES SELECTION
1
LOCAL ON BOARD
2
E21
5V_AUX
C
D
E32
GND
E33
GND
C16
10uF
6.3V
C13
10uF
6.3V
E34
GND
R36
10K
R35
10K
3
1
3
1
SHDN
IN
U4
LT1761ES5-1.5
SHDN
IN
U3
LT1761ES5-2.5
GND
2
GND
2
BYP
OUT
BYP
4
3
4
5
4
5
V1_INT
C17
0.01uF
V2_INT
C14
0.01uF
C18
10uF
6.3V
C15
10uF
6.3V
E26
V2_INT
E22
V1_INT
3
V2_INT
V1_INT
SHDN3.3
E29
SHDN1.8
E28

OUT
4
C22
10uF
6.3V
C19
10uF
6.3V
3
1
3
1
SHDN
IN
U6
LT1761ES5-3.3
SHDN
IN

2
SCALE = NONE
APP ENG. Vlad Ostrerov
PCB DES.
APPROVALS
R38
10K
R37
10K
U5
LT1761ES5-1.8
2
GND
2
BYP
OUT
BYP
OUT
4
5
4
5
V4_INT
C23
0.01uF
V4_INT

 www.linear.com


E27
V4_INT
V3_INT
1
SHEET
5
OF
5
1
REV.

C24
10uF
6.3V
C21
10uF
6.3V
E23
V3_INT
1


IC NO.


MODIFY DATE: 

SIZE
V3_INT
C20
0.01uF
TECHNOLOGY
TITLE: SCHEMATIC
GND
2
5
A
B
C
D
DEMO MANUAL DC1029B
SCHEMATIC DIAGRAM
dc1029bf
11
DEMO MANUAL DC1029B
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application
engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
12 Linear Technology Corporation
dc1029bf
LT 1215 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2015
Similar pages