Data Sheet

NXP Semiconductors
Data sheet: Advance Information
Document Number: MC12XS6D1
Rev. 2.0, 5/2016
17 mOhm and 7.0 mOhmhigh-side
switches
The 12XS6 is the latest SMARTMOS achievement in automotive lighting drivers.
It belongs to an expanding family, which helps to control and diagnose
incandescent lamps and light-emitting diodes (LEDs), with enhanced precision.
It combines flexibility through daisy chainable SPI 5.0 MHz, extended digital and
analog feedbacks, safety, and robustness.
Output edge shaping helps to improve electromagnetic performance. To avoid
shutting off the device upon inrush current, while still being able to closely track
the load current, a dynamic overcurrent threshold profile is featured. Current of
each channel can be sensed with a programmable sensing ratio. Whenever
communication with the external microcontroller is lost, the device enters a fail
operation mode, but remains operational, controllable, and protected.
This new generation of high-side switch products family facilitates ECU design
due to compatible MCU software and PCB foot prints for each device variant.
Features
• Quad or penta high-side switches with high transient capability
• 16-bit 5.0 MHz SPI control of overcurrent profiles, channel control including
PWM duty cycles, output-on and -off open load detections, thermal shutdown
and prewarning, and fault reporting
• Output current monitoring with programmable synchronization signal and
battery voltage feedback
• Limp home mode
• External smart power switch control
• Operating voltage is 7.0 V to 18 V with sleep current < 5.0 µA, extended mode
from 6.0 V to 28 V
• -16 V reverse polarity and ground disconnect protections
• Compatible PCB foot print and SPI software driver among the family
12XS6D1
High-side switches
EK SUFFIX (PB-FREE)
98ASA00367D
54-PIN SOIC-EP
EK SUFFIX (PB-FREE)
98ASA00368D
32-PIN SOIC-EP
Applications
• Low-voltage automotive exterior lighting
• Halogen lamps
• Incandescent bulbs
• Light-emitting diodes (LEDs)
• HID Xenon ballasts
VBAT
VBAT
VBAT
VCC
07XS6517
5.0 V
Regulator
GND
VCC
Main
MCU
GND
SO
CSB
SCLK
SI
RSTB
CLK
A/D1
TRG1
PORT
PORT
PORT
PORT
PORT
A/D2
VBAT
VCC
SI
CP
CSB
OUT1
SCLK
SO
OUT2
RSTB
CLK
OUT3
CSNS
SYNCB
OUT4
LIMP
IN1
OUT5
IN2
IN3
IN4
GND OUT6
VBAT OUT
Smart Power
CSNS GND
IN
Figure 1. Triple 7.0 m and dual 17 m high-side simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
1
Orderable parts
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided
on the web. To determine the orderable part numbers for this device, go to http://www.nxp.com and perform a part number search for the
following device numbers.
Table 1. Orderable part variations
Part number
Notes
Temperature
(TA)
SOIC54 pins
exposed pad
MC07XS6517BEK
MC17XS6500BEK
MC17XS6400EK
Package
(1)
-40 °C to 125 °C
SOIC32 pins
exposed pad
OUT1
RDS(on)
OUT2
RDS(on)
OUT3
RDS(on)
OUT4
RDS(on)
OUT5
RDS(on)
OUT6
17 m
17 m
7.0 m
7.0 m
7.0 m
Yes
17 m
17 m
17 m
17 m
17 m
Yes
17 m
17 m
17 m
17 m
No
Yes
Notes
1. To order parts in tape and reel, add the R2 suffix to the part number.
MC12XS6D1
2

NXP Semiconductors
Table of Contents
1
2
3
4
5
6
7
8
9
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Relationship between ratings and operating requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 Supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General IC functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6 SPI interface and configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Self-protected high-side switches description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Power supply functional block description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3 Communication interface and device control functional block description and application information . . . . . . . . . . . . . . . 54
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.2 EMC and EMI considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.3 Robustness considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.4 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.5 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.1 Marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.2 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
MC12XS6D1

NXP Semiconductors
3
2
Internal block diagram
CP
VCC
Power
Supply
Oscillator
UVF
Thermal
Prewarning
OTS1
Temperature
Shutdown
SI
SPIF
Fault
Management
OC1
OLON1
OLOFF1
Charge
Pump
Selectable
Slope Control
Selectable Overcurrent
Protection
Selectable OpenLoad
Detection
Selectable
Current Sensing
LIMP
OUT1
IN1
Output Voltage
Monitoring
OUT1 Channel
OUT1
PWM Module
OUT2 Channel
IN4
Logic
VCC
WAKEB OR
RSTB
Clock Failure
Detection
CLK
CSNS
OUT3 Channel
OUT3
OUT4
OUT4Channel
Channel
OUT4
OUT5 Channel
OUT5/
NC
VCC
CSNS
SYNCB
Selectable
Delay
VBAT_PROTECTED
Selectable
Analog
Feedback
OUT2
Smart Power
Switch Drive
IN3
Power channels
IN2
CLKF
SPI Control
OTW1
OTW2
SCLK
Reference
PWM Clock
Limp Home Control
Battery
Clamp
CPF
SPI
RSTB
A to D Convertion
Undervoltage
Detection
OVF
SO
CSB
Reverse
Battery
Protection
VBAT_PROTECTED
VS
Power-on
Reset
VBAT
OUT6
VBAT_PROTECTED
Control die
Temperature
Monitoring
Battery
Voltage
Monitoring
GND
Figure 2. 12XS6 simplified internal block diagram (penta/quad)
MC12XS6D1
4

NXP Semiconductors
3
Pin connections
3.1
Pinout diagram
Transparent top view
CP
RSTB
CSB
1
32
CLK
2
31
LIMP
3
30
IN4
SCLK
SI
4
29
IN3
5
28
IN2
VCC
SO
6
27
IN1
7
26
CSNS SYNCB
OUT6
8
25
CSNS
VBAT
33
GND
9
24
GND
OUT2
OUT2
OUT4
10
23
OUT1
11
22
OUT1
12
21
OUT3
OUT4
OUT4
13
20
OUT3
14
19
OUT3
NC
15
18
OUT5/NC
NC
16
17
OUT5/NC
Figure 3. Pinout diagram for 32 pin SOIC-EP package
Transparent top view - stamped version
Transparent top view - etched version
NC
NC
CP
RSTB
CSB
SCLK
SI
VCC
SO
OUT6
GND
OUT2
OUT2
OUT4
OUT4
OUT4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
18
19
20
21
22
23
24
25
26
27
55
VBAT
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
NC
NC
CLK
LIMP
IN4
IN3
IN2
IN1
CSNS SYNCB
CSNS
GND
OUT1
OUT1
OUT3
OUT3
OUT3
37
36
35
34
33
32
31
30
29
28
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
NC
NC
CP
RSTB
CSB
SCLK
SI
VCC
SO
OUT6
GND
OUT2
OUT2
OUT4
OUT4
OUT4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
18
19
20
21
22
23
24
25
26
27
55
VBAT
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
NC
NC
CLK
LIMP
IN4
IN3
IN2
IN1
CSNS SYNCB
CSNS
GND
OUT1
OUT1
OUT3
OUT3
OUT3
37
36
35
34
33
32
31
30
29
28
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
OUT5
Figure 4. Pinout diagram for 54 pin SOIC-EP package
MC12XS6D1

NXP Semiconductors
5
3.2
Pin definitions
Table 2. 12XS6 pin definitions
Pin number
Pin number
Pin name
32 SOIC-EP 54 SOIC-EP (2)
Pin function
Formal name
Definition
1
3
CP
Internal supply
Charge-pump
This pin is the connection for an external capacitor for charge pump use
only.
2
4
RSTB
SPI
Reset
This input pin is used to initialize the device configuration and fault
registers, as well as place the device in a low-current sleep mode. This pin
has a passive internal pull-down.
3
5
CSB
SPI
Chip select
This input pin is connected to a chip select output of a master
microcontroller (MCU). When this digital signal is high, SPI signals are
ignored. Asserting this pin low starts an SPI transaction. The transaction is
indicated as completed when this signal returns to high level. This pin has
a passive internal pull-up to VCC through a diode
4
6
SCLK
SPI
Serial clock
This input pin is connected to the MCU providing the required bit shift clock
for SPI communication. This pin has an passive internal pull-down.
5
7
SI
SPI
Serial input
This pin is the data input of the SPI communication interface. The data at
the input are sampled on the positive edge of the SCLK. This pin has a
passive internal pull-down.
6
8
VCC
Power supply
MCU power
supply
This pin is a power supply pin for internal logic, the SPI I/Os and the OUT6
driver.
7
9
SO
SPI
Serial output
This output pin is connected to the SPI serial data Input pin of the MCU or
to the SI pin of the next device of a daisychain of devices. The SPI changes
on the negative edge of SCLK. When CSB is high, this pin is highimpedance.
8
10
OUT6
Output
External solid
state
This output pin controls an external smart power switch by logic level. This
pin has a passive internal pull-down.
9 and 24
11 and 14
GND
Ground
Ground
These pins are the ground for the logic and analog circuitries of the device.
For ESD and electrical parameter accuracy purpose, the ground pins must
be shorted on the board.
10 to 11
12 to 13
OUT2
Output
Channel #2
Protected high-side power output pins to the load.
12 to 14
14 to 16
OUT4
Output
Channel #4
Protected high-side power output pins to the load.
15, 16
1, 2, 18 to 27,
53, 54
NC
N/A
Not connected
These pins are not connected. It is recommended to connect these pint to
ground
17 to 18
28 to 37
OUT5
Output
Channel #5
Protected high-side power output pins to the load. This channel is not
connected for the quad version 17XS6400. It is recommended to connect
those pins to ground for this device.
19 to 21
39 to 41
OUT3
Output
Channel #3
Protected high-side power output pins to the load.
22 to 23
42 to 43
OUT1
Output
Channel #1
Protected high-side power output pins to the load.
25
45
CSNS
Feedback
Current sense
This pin reports an analog value proportional to the designated OUT[1:5]
output current or the temperature of the exposed pad or the battery
voltage. It is used externally to generate a ground-referenced voltage for
the microcontroller (MCU). Current recopy and analog voltage feedbacks
are SPI programmable.
26
46
CSNS
SYNCB
Feedback
Current sense
synchronization
This open drain output pin allows synchronizing the MCU A/D conversion.
This pin requires an external pull-up resistor to VCC.
27
47
IN1
Input
Direct input #1
This input wakes up the device. This input pin is used to directly control
corresponding channel in Fail mode. During normal mode the control of the
outputs by the control inputs is SPI programmable.This pin has a passive
internal pull-down.
28
48
IN2
Input
Direct input #2
This input wakes up the device. This input pin is used to directly control
corresponding channel in fail mode. During normal mode the control of the
outputs by the control inputs is SPI programmable.This pin has a passive
internal pull-down.
MC12XS6D1
6

NXP Semiconductors
Table 2. 12XS6 pin definitions (continued)
Pin number
Pin number
Pin name
32 SOIC-EP 54 SOIC-EP (2)
Pin function
Formal name
Definition
29
49
IN3
Input
Direct input #3
This input wakes up the device. This input pin is used to directly control
corresponding channel in fail mode. During normal mode the control of the
outputs by the control inputs is SPI programmable.This pin has a passive
internal pull-down.
30
50
IN4
Input
Direct input #4
This input wakes up the device. This input pin is used to directly control
corresponding channel in fail mode. During normal mode the control of the
outputs by the control inputs is SPI programmable.This pin has a passive
internal pull-down.
31
51
LIMP
Input
Limp home
The Fail mode can be activated by this digital input. This pin has a passive
internal pull-down.
This pin is an input/output pin. It is used to report the device sleep-state
information. It is also used to apply reference PWM clock which is divided
by 28 in normal operating mode. This pin has a passive internal pull-down.
This exposed pad connects to the positive power supply and is the source
of operational power for the device.
32
52
CLK
Input/output
Device mode
feedback
Reference
PWM clock
33
55
VBAT
Power supply
Battery power
supply
Notes
2. Pins 17 and 38 are omitted.
MC12XS6D1

NXP Semiconductors
7
4
General product characteristics
4.1
Relationship between ratings and operating requirements
The analog portion of device is supplied by the voltage applied to the VBAT exposed pad. Thereby the supply of internal circuitry (logic in
case of a VCC disconnect, charge pump, gate drive,...) is derived from the VBAT pin.
In case of a reverse battery:
Fatal range
Reverse
protection
Probable
permanent
failure
Degraded operating Normal operating
range
range
V
40
V
18
32
V
V
7.
0
-1
6
V
Un
5. de
5 rv
V o
l
ta
ge
• the internal supply rail is protected (max. -16 V)
• the output drivers (OUT1:OUT4/5) are switched on, to reduce the power consumption in the drivers when using incandescent bulbs
Degraded operating
range
- Reduced performance Full performance - Reduced performance
- Full protection but
- Full protection but
accuracy not
accuracy not
guaranteed
guaranteed
- no PMW feature for
UV to 6.0 V
Potential failure
Fatal range
- Reduced performance
- Probable failure in
case of short-circuit
Probable
permanent
failure
Fatal range
40
V
-1
6V
Operating range
Accepted industry
standard practices
Probable
permanent failure
Fatal range
Probable
permanent failure
Correct operation
Handling conditions (power off)
Fatal range
Probable
permanent failure
Not operating range
Degraded operating
range
Normal operating
range
Reduced
performance
Full performance
Degraded operating
range
V
0
7.
5.
5
V
V
4.
5
-0
.
6
V
VC
(2 C
.0 PO
V R
to
4.
0
V)
Figure 5. Ratings vs. operating requirements (VBAT pin)
The device’s digital circuitry is powered by the voltage applied to the VCC pin. If VCC is disconnected, the logic part is supplied by the
VBAT pin. The output driver for SPI signals, CLK pin (wake feedback), and OUT6 are supplied by the VCC pin only. This pin must be
protected externally in case of a reverse polarity, and in case of a high-voltage disturbance.
Fatal range
Probable
Reduced performance permanent failure
Operating range
Figure 6. Ratings vs. operating requirements (VCC pin)
MC12XS6D1
8

NXP Semiconductors
4.2
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Electrical ratings
VBAT
VBAT voltage range
-16
40
V
VCC
VCC logic supply voltage
-0.3
7.0
V
VIN
Digital input voltage
• IN1:IN4 and LIMP
• CLK, SI, SCLK, CSB, and RSTB
-0.3
-0.3
40
20
V
(3)
VOUT
Digital output voltage
• SO, CSNS, SYNC, OUT6, CLK
-0.3
20
V
(3)
ICL
Negative digital input clamp current
–
5.0
mA
(4)
Power channel current
• 7.0 mchannel
• 17 m channel
–
–
11
5.5
A
(5)
–
–
–
–
200
100
100
50
mJ
(6)
-8000
-2000
-750
-500
+8000
+2000
+750
+500
V
(7)
IOUT
Power channel clamp energy capability
• 7.0 m channel - Initial TJ = 25 °C
• 7.0 m channel - Initial TJ = 150 °C
• 17 m channel - Initial TJ = 25 °C
ECL
• 17 m channel - Initial TJ = 150 °C
VESD
ESD voltage
• Human body model (HBM) - VBAT, power channel, and GND pins
• Human body model (HBM) - all other pins
• Charge device model (CDM) - corner pins
• Charge device model (CDM) - all other pins
Notes
3. Exceeding voltage limits on those pins may cause a malfunction or permanent damage to the device.
4. Maximum current in negative clamping for IN1:IN4, LIMP, RSTB, CLK, SI, SO, SCLK, and CSB pins.
5. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
6. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 , VBAT = 14 V). Refer to Output clamps on page 38 section.
7.
ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the charge device model.
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9
4.3
Thermal characteristics
Table 4. Thermal ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Operating temperature
• Ambient
• Junction
-40
-40
+125
+150
°C
TSTG
Storage temperature
-55
+ 150
°C
TPPRT
Peak package reflow temperature during reflow
–
260
°C
(8) (9)
–
2.5
°C/W
(10)
Thermal ratings
TA
TJ
Thermal resistance and package dissipation ratings
RJB
Junction-to-board
RJA
Junction-to-ambient, natural convection, four-layer board (2s2p)
• RJA - 54 SOIC-EP
• RJA - 32 SOIC-EP
RJC
Junction-to-case (case top surface)
(11) (12)
–
–
17.4
19.4
°C/W
–
10.6
°C/W
(13)
Notes
8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
9. NXP’s package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and
moisture sensitivity levels (MSL), Go to www.nxp.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all
orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
10. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
11. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
12. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
13. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
4.4
Operating conditions
This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted.
Table 5. Operating conditions
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Min.
Max.
Unit
7.0
18
V
–
–
28
40
V
Reverse battery
-16
–
V
Functional operating supply voltage - Device is fully functional. All features are
operating.
4.5
5.5
V
Functional operating supply voltage - Device is fully functional. All features are
operating.
VBAT
VCC
Overvoltage range
• Jump start
• Load dump
Notes
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4.5
Supply currents
This section describes the current consumption characteristics of the device.
Table 6. Supply currents
Characteristics noted under conditions 4.5 V  VCC  5.5 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Ratings
Min.
Typ.
Max.
Unit
Notes
Sleep mode measured at VPWR = 12 V
• TA = 25 °C
• TA = 125 °C
–
–
1.2
10
5.0
30
µA
(14) (15)
Operating mode measured at VPWR = 18 V
–
7.0
8.0
mA
(15)
Sleep mode measured at VCC = 5.5 V
–
0.05
5.0
µA
Operating mode measured at VPWR = 5.5 V (SPI frequency 5.0 MHz)
–
2.8
4.0
mA
VBAT current consumptionS
IQVBAT
IVBAT
VCC current consumptionS
IQVCC
IVCC
Notes
14. With the OUT1:OUT4/5 power channels grounded.
15. With the OUT1:OUT4/5 power channels opened.
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5
General IC functional description and application
information
5.1
Introduction
The 12XS6 is the latest achievement in automotive drivers for all types of centralized automotive lighting applications. It is an evolution of
the successful 12XS3 by providing improved features of a complete family of devices using NXP's latest and unique technologies for the
controller and the power stages.
It consists of a scalable family of devices with different RDS(on) and different number of outputs, compatible in terms of software driver and
package footprint. It allows diagnosing the light-emitting diodes (LEDs) with an enhanced current sense precision with synchronization
pin. It combines flexibility through daisy chainable SPI 5.0 MHz, extended digital and analog feedbacks, safety, and robustness. It
integrates an enhanced PWM module with 8-bit duty cycle capability and PWM frequency prescaler per power channel.
5.2
Features
The main attributes of the 12XS6 are:
• Dual, triple, quad, or penta high-side switches with overload, overtemperature, and undervoltage protection
• Control output for one external smart power switch
• 16-bit SPI communication interface with daisy chain capability
• Dedicated control inputs for use in fail mode
• Analog feedback pin with SPI programmable multiplexer and sync signal
• Channel diagnosis by SPI communication
• Advanced current sense mode for LED usage
• Synchronous PWM module with external clock, prescaler and multiphase feature
• Excellent EMC behavior
• Power net and reverse polarity protection
• Ultra low-power mode
• Scalable and flexible family concept
• Board layout compatible SOIC54 and SOIC32 package with exposed pad
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5.3
Block diagram
The choice of multi-die technology in an SOIC exposed pad package, including a low cost vertical trench FET power die associated with
smart power control die, lead to an optimized solution.
12XS6 - Functional block diagram
Power supply
MCU interface and device control
SPI interface
Parallel control inputs
MCU
interface
Self-protected
high-side
switches
OUT[x]
PWM controller
Supply
MCU interface and output control
Self-protected high-side switches
Figure 7. Functional block diagram
5.3.1
Self-protected high-side switches
OUT1: OUT4/5 are the output pins of the power switches. The power channels are protected against various kinds of short-circuits, and
have active clamp circuitry which may be activated when switching off inductive loads. Many protective and diagnostic functions are
available.
5.3.2
Power supply
The device operates with supply voltages from 5.5 V to 40 V (VBAT), but is full spec. compliant only between 7.0 V and 18 V. The VBAT
pin supplies power to the internal regulator, analog, and logic circuit blocks. The VCC pin (5.0 V typ.) supplies the output register of the
serial peripheral interface (SPI). Consequently, the SPI registers cannot be read without presence of VCC. The employed IC architecture
guarantees a low quiescent current in sleep mode.
5.3.3
MCU interface and device control
In normal mode the power output channels are controlled by the embedded PWM module, which is configured by the SPI register settings.
For bidirectional SPI communication, VCC has to be in the authorized range. Failure diagnostics and configuration are also performed
through the SPI port. The reported failure types are: open load, short-circuit to battery, severe short-circuit to ground, overcurrent,
overtemperature, clock-fail, and under and overvoltage. The device allows driving loads at different frequencies up to 400 Hz.
5.4
Functional description
The device has four fundamental operating modes: sleep, normal, fail, and power off. It possesses multiple high-side switches (power
channels) each of which can be controlled independently:
• In normal mode by SPI interface. A second supply voltage (VCC) is required for bidirectional SPI communication
• In fail mode by the corresponding direct inputs IN1:IN4. The OUT5 for the penta version and the OUT6 are off in this mode
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13
5.5
Modes of operation
The operating modes are based on the signals:
• wake = (IN1_ON) OR (IN2_ON) OR (IN3_ON) OR (IN4_ON) OR (RSTB). More details in the Logic I/O plausibility check section
• fail = (SPI_fail) OR (LIMP). More details in the Loss of communication interface section
The following chapters provide information for a five output device. (do not consider OUT5 for the quad version.)
Sleep
wake = [0]
wake = [0]
wake = [1]
(VBAT < VBATPOR) and
(VCC < VCCPOR)
(VBAT < VBATPOR) and
(VCC < VCCPOR)
Fail
(VBAT > VBATPOR) or
(VCC > VCCPOR)
Power
off
(VBAT < VBATPOR) and
(VCC < VCCPOR)
fail = [0] and valid watchdog toggle
Normal
fail = [1]
Figure 8. General IC operating modes
5.5.1
Power off mode
The power off mode is applied when VBAT and VCC are below the power on reset threshold (VBAT POR, VCC POR). No functionality is
available, but the device is protected by the clamping circuits In power off. Refer to Supply voltages disconnection.
5.5.2
Sleep mode
The sleep mode is used to provide ultra low-current consumption. During sleep mode:
• the component is inactive and all outputs are disabled
• the outputs are protected by the clamping circuits
• the pull-up/pull-down resistors are present
Sleep mode is the default mode of the device after applying the supply voltages (VBAT or VCC) prior to any wake-up condition (wake = [0]).
Wake-up from sleep mode is provided by the wake signal.
5.5.3
Normal mode
The normal mode is the regular operating mode of the device. The device is in normal mode, when the device is in the wake state
(wake = [1]) and no fail condition (fail = [0]) is detected.
During normal mode:
• the power outputs are under control of the SPI
• the power outputs are controlled by the programmable PWM module
• the power outputs are protected by the overload protection circuit
• the control of the power outputs by SPI programming
• the digital diagnostic feature transfers status of the smart switch via the SPI
• the analog feedback output (CSNS and CSNS SYNC) can be controlled by the SPI
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The channel control (CHx) can be summarized:
• CH1:4 controlled by ONx or iINx (if it is programmed by the SPI)
• CH5:6 controlled by ONx
• Rising CHx by definition means starting overcurrent window for OUT1:5
5.5.4
Fail mode
The device enters the fail mode, when:
• the LIMP input pin is high (logic [1])
• or a SPI failure is detected
During fail mode (wake = [1] & fail = [1]):
• the OUT1:OUT4 outputs are directly controlled by the corresponding control inputs (IN1:IN4)
• the OUT5:OUT6 are turned off
• the PWM module is not available
• while no SPI control is feasible, the SPI diagnosis is functional (depending on the fail mode condition):
• SO reports the content of SO register defined by SOA0 to three bits
• the outputs are fully protected in case of an overload, overtemperature, and undervoltage
• no analog feedback is available
• the max. output overcurrent profile is activated (OCLO and window times)
• in case of an overload condition or undervoltage, the autorestart feature controls the OUT1:OUT4 outputs
• in case of an overtemperature condition, OCHI1 detection, or severe short-circuit detection, the corresponding output is latched
OFF until a new wake-up event
The channel control (CHx) can be summarized:
• CH1:4 controlled by iINx, while the overcurrent windows are controlled by IN_ONx
• CH5:6 are off
5.5.5
Mode transitions
After a wake-up:
• a power on reset is applied and all SPI SI and SO registers are cleared (logic[0])
• the faults are blanked during tBLANKING
The device enters in normal mode after start-up if following sequence is provided:
• VBAT and VCC power supplies must be above their undervoltage thresholds (sleep mode)
• generate wake-up event (wake =1) setting RSTB from 0 to 1
The device initialization is completed after 50 µsec (typ). During this time, the device is robust in case VBAT interrupts higher than
150 nsec. The transition from “normal mode” to “fail mode” is executed immediately when a fail condition is detected. During the transition,
the SPI SI settings are cleared and the SPI SO registers are not cleared.
When the fail mode condition is a:
• LIMP input, WD toggle timeout, WD toggle sequence, or a SPI modulo 16 error, the SPI diagnosis is available during fail mode
• SI/SO stuck to static level, the SPI diagnosis is not available during fail mode
The transition from “fail mode” to “normal mode” is enabled when:
• the fail condition is removed and
• two SPI commands are sent within a valid watchdog cycle (first WD=[0] and then WD=[1])
During this transition:
• all SPI SI and SO registers are cleared (logic[0])
• the DSF (device status flag) in the registers #1:#7 and the RCF (register clear flag) in the device status register #1 are set (logic[1])
To delatch the RCF diagnosis, a read command of the quick status register #1 must be performed.
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15
5.6
SPI interface and configurations
5.6.1
Introduction
The SPI is used to:
• control the device in case of normal mode
• provide diagnostics in case of normal and fail mode
The SPI is a 16-bit full-duplex synchronous data transfer interface with daisy chain capability.
The interface consists of four I/O lines with 5.0 V CMOS logic levels and termination resistors:
• The SCLK pin clocks the internal shift registers of the device
• The SI pin accepts data into the input shift register on the rising edge of the SCLK signal
• The SO pin changes its state on the rising edge of SCLK and reads out on the falling edge
• The CSB enables the SPI interface:
• with the leading edge of CSB, the registers loads
• while CSB is logic [0], SI/SO data shifts
• with the trailing edge of the CSB signal, SPI data latches into the internal registers
• when CSB is logic [1], the signals at the SCLK and SI pins are ignored and SO is high-impedance
When the RSTB input is:
• low (logic [0]), the SPI and the fault registers are reset. The wake state then depends on the status of the input pins
(IN_ON1:IN_ON4)
• high (logic[1]), the device is in wake status and the SPI is enabled
The functionality of the SPI is checked by a plausibility check. During a SPI failure, the device enters fail mode.
5.6.2
SPI input register and bit descriptions
The first nibble of the 16-bit data word (D15:D12) serves as address bits.
Register
name
SI address
#
8
D15
D14
SI data
D13
4-Bit address
D12
D11
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
11-Bit address
11 bits (D10:D1) are used as data bits.
The D11 bit is the WD toggle bit. This bit has to be toggled with each write command.
When the toggling of the bit is not executed within the WD timeout, a SPI fail is detected.
All register values are logic [0] after a reset. The predefined value is off/inactive unless otherwise noted.
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Register
SI address
#
D15
D14
SI data
D13
D12
D11
D10
D9
D8
SYNC
EN0
Initialisation 1
0
0
0
0
0
WD
WD SEL
SYNC
EN1
initialisation 2
1
0
0
0
1
WD
OCHI
THERMAL
OCHI
TRANSIENT
CH1 control
2
0
0
1
0
WD
PH11
PH01
ON1
CH2 control
3
0
0
1
1
WD
PH12
PH02
ON2
CH3 control
4
0
1
0
0
WD
PH13
PH03
CH4 control
5
0
1
0
1
WD
PH14
CH5 control
6
0
1
1
0
WD
PH15
CH6 control
7
0
1
1
1
WD
PH16
output
control
8
1
0
0
0
WD
PSF5
Global PWM
control
over current
control
input enable
prescaler
settings
9-1
1
0
0
1
WD
0
D7
D6
D5
D4
D3
D2
D1
D0
SOA3
SOA2
SOA1
SOA0
OCHI
OD2
OCHI
OD1
PWM
sync
OTW
SEL
MUX1
MUX0
OCHI
OD5
OCHI
OD4
SOA
MODE
OCHI
OD3
PWM71
PWM61
PWM51
PWM41
PWM31
PWM21
PWM11
PWM01
PWM72
PWM62
PWM52
PWM42
PWM32
PWM22
PWM12
PWM02
ON3
PWM73
PWM63
PWM53
PWM43
PWM33
PWM23
PWM13
PWM03
PH04
ON4
PWM74
PWM64
PWM54
PWM44
PWM34
PWM24
PWM14
PWM04
PH05
ON5
PWM75
PWM65
PWM55
PWM45
PWM35
PWM25
PWM15
PWM05
PH06
ON6
PWM76
PWM66
PWM56
PWM46
PWM36
PWM26
PWM16
PWM06
PSF4
PSF3
PSF2
PSF1
ON6
ON5
ON4
ON3
ON2
ON1
GPWM
EN5
GPWM
EN4
GPWM
EN3
GPWM
EN2
GPWM
EN1
GPWM4
GPWM3
GPWM2
GPWM1
GPWM0
X
MUX2
NO HID1 NO HID0
X
X
X
GPWM
EN6
9-2
1
0
0
1
WD
1
X
X
GPWM7
GPWM6
GPWM5
10-1
1
0
1
0
WD
0
OCLO5
OCLO4
OCLO3
OCLO2
OCLO1 ACM EN5 ACM EN4 ACM EN3 ACM EN2
10-2
1
0
1
0
WD
1
NO
OCHI5
NO
OCHI4
NO
OCHI3
NO
OCHI2
NO
OCHI1
SHORT
OCHI5
SHORT
OCHI4
SHORT
OCHI3
SHORT
OCHI2
ACM
EN1
SHORT
OCHI1
11
1
0
1
1
WD
0
X
X
INEN14
INEN04
INEN13
INEN03
INEN12
INEN02
INEN11
INEN01
12-1
1
1
0
0
WD
0
PRS15
PRS05
PRS14
PRS04
PRS13
PRS03
PRS12
PRS02
PRS11
PRS01
12-2
1
1
0
0
WD
1
X
X
X
X
X
X
X
X
PRS16
PRS06
OL control
13-1
1
1
0
1
WD
0
OLON
DGL5
OLON
DGL4
OLON
DGL3
OLON
DGL2
OLLED control
13-2
1
1
0
1
WD
1
res
res
res
res
OLON
DGL1
OLLED
TRIG
OLOFF
EN5
OLLED
EN5
OLOFF
EN4
OLLED
EN4
OLOFF
EN3
OLLED
EN3
OLOFF
EN2
OLLED
EN2
OLOFF
EN1
OLLED
EN1
increment /
decrement
14
1
1
1
0
WD
INCR
SGN
INCR15
INCR05
INCR14
INCR04
INCR13
INCR03
INCR12
INCR02
INCR11
INCR01
testmode
15
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
#0
MUX2
0
0
0
0
1
1
1
1
MUX1
0
0
1
1
0
0
1
1
SYNC
EN1
0
0
1
1
MUX0
0
1
0
1
0
1
0
1
SYNC
EN0
0
1
0
1
PH 1x
0
0
1
1
PH 0x
0
1
0
1
WD #0~#14 = watchdog toggle bit
SOA0 ~ SOA3
SOA MODE
MUX0 ~ MUX2
SYNC EN0~ SYNC EN1
WD SEL
OTW SEL
PWM SYNC
OCHI ODx
NO HIDx
OCHI THERMAL
OCHI TRANSIENT
PWM0x ~ PWM7x
PH0x ~ PH1x
ONx
PSFx
GPWM ENx
GPWM1 ~ GPWM7
ACM ENx
OCLOx
SHORT OCHIx
NO OCHIx
INEN0x ~ INEN1x
PRS0x ~ PRS1x
OLOFF ENx
OLON DGLx
OLLED ENx
OLLED TRIG
INCR SGN
INCR0x ~ INCR1x
#0
#0
#0
#0
#0
#1
#1
#1
#1
#1
#1
#2~#7
#2~#7
#2~#8
#8
#9-1
#9-2
#10-1
#10-1
#10-2
#10-2
#11
#12
#13-1
#13-1
#13-2
#13-2
#14
#14
= address of next SO data word
= single read address of next SO data word
= CSNS multiplexer setting
= SYNC delay setting
= watchdog timeout select
= over temperature warning threshold selection
= reset clock module
= OCHI window on load demand
= HID outputs selection
= OCHI1 level depending on control die temperature
= OCHIx levels adjusted during OFF-to-ON transition
= PWM value (8Bit)
= phase control
= channel on/off incl. OCHI control
= pulse skipping feature for power output channels
= global PWM enable
= global PWM value (8Bit)
= advanced current sense mode enable
= OCLO level control
= use short OCHI window time
= start with OCLO threshold
= input enable control
= pre scaler setting
= OL load in off state enable
= OL ON deglitch time
= OL LED mode enable
= trigger for OLLED detetcion in 100% d.c.
= PWM increment / decrement sign
= PWM increment / decrement setting
#0
#2~#7
#11
0
1
#12
#1
NO HID1 NO HID0
0
0
0
1
1
0
1
1
HID Selection
available for all channels
available for channel 3 only
available for channels 3 and 4 only
unavailable for all channels
ONx
#14
#14
CSNS
off
OUT1 current
OUT2 current
OUT3 current
OUT4 current
OUT5 current
VBAT monitor
control die temp.monitor
Sync status
sync off
valid
trig0
trig1/2
Phase
0°
90°
180°
270°
INx=0
GPWM
INEN1x INEN0x
OUTx
PWMx
ENx
x
x
x
OFF
x
individual
0
ON
0
0
global
1
ON
individual
0
OFF
0
1
global
1
OFF
individual
0
OFF
1
0
global
1
OFF
individual
0
ON
1
1
global
1
ON
PRS 1x PRS 0x PRS divider
0
0
/4
25Hz .... 100Hz
0
1
/2
50Hz .... 200Hz
x
/1
100Hz .... 400Hz
1
INCR SGN
increment/decrement
0
decrement
1
increment
INCR 1x INCR 0x increment/decrement
0
0
no increment/decrement
4 LSB
0
1
8 LSB
0
1
1
1
16 LSB
INx=1
OUTx
PWMx
OFF
x
individual
ON
global
ON
individual
ON
global
ON
individual
ON
global
ON
global
ON
individual
ON
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17
5.6.3
SPI output register and bit descriptions
The first nibble of the 16-bit data word (D12:D15) serves as address bits. All register values are logic [0] after a reset, except DSF and
RCF bits. The predefined value is off/inactive unless otherwise noted.
#2~#6
QSFx
#1
= qu ick s ta tu s (OC o r OTW or OTS or OLON or OLOFF)
C LKF
#1
= PWM clo ck fail flag
0
0
0
n o ove rcu rrent
R CF
#1
= reg ister c lea r fla g
0
0
1
OC H I1
#1
= ch arge pum p fl ag
C PF
OLF
OVLF
D SF
OC 2x
O C1x
OC 0x ove r cur re nt st atus
0
1
0
OC H I2
#1 ~# 7 = op en lo ad flag (wi red or of all OL s ign als )
0
1
1
OC H I3
#1 ~# 7 = ov er loa d fl ag (wire d or of all OC a nd OTS sig nal s)
1
0
0
OC LO
#1 ~# 7 = de vic e status flag ( UVF or OVF or CP F or R CF or CL KF o r TM F)
1
0
1
OC H IOD
1
1
0
S SC
1
1
1
n ot u sed
FM #1 ~# 8 = fail m ode fla g
OLOFFx #2 ~# 6 = op en lo ad in o ff state status b it
OLON x #2 ~# 6 = op en lo ad in o n state status b it
OTWx #2 ~# 6 = ov er te mp eratur e wa rnin g bit
OTS x #2 ~# 6 = ov er te mp eratur e shu td own bit
#9
D EVID 2 DEV ID1 D EVID 0 dev ic e type
0
0
0
P enta3 /2
0
0
1
P enta0 /5
Qu ad2 /2
iLIM P
#7
= status o f LIM P i npu t after de gli tc her (re ported i n rea l tim e)
0
1
0
SPIF
#7
= SPI fa il flag
0
1
1
Qu ad0 /4
U VF
#7
= un der v oltag e fla g
1
0
0
Trip le1 /2
OVF
#7
= ov er vo lta ge flag
1
0
1
Trip le0 /3
TMF
#7
= testmo de a ctiva ti on flag
1
1
0
re s
OU Tx
#8
= status o f VB AT/2 c omp arato r (re po rte d in rea l ti me)
1
1
1
re s
iIN x
#8
= status o f INx p in after de glitc her (re ported i n real tim e)
TOGGLE
#8
= status o f INx _ON s ign als (IN 1_O N or IN2 _ON o r IN 3_ON or IN 4_ ON)
D EVID0 ~ DE VID 2
#9
= de vic e ty pe
D EVID3 ~ DE VID 4
#9
= de vic e fa mil y
D EVID5 ~ DE VID 7
#9
= de sig n status (in cre men te d nu mbe r)
MC12XS6D1
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NXP Semiconductors
5.6.4
Timing diagrams
RSTB
VIH
10 % VCC
VIL
tWRST
tCS
tENBL
CSB
90 % VCC
VIH
10 % VCC
VIL
tRSI
tWSCLKh
tLEAD
tLAG
VIH
90 % VCC
SCLK
10 % VCC
tSI(SU)
VIL
tWSCLKl
tFSI
tSI(H)
SI
VIH
90 % VCC
10 % VCC
Don’t Care
Must be Valid
Don’t Care
VIL
tSOEN
SO
Don’t Care
Must be Valid
tSODIS
Tri-stated
Tri-stated
VIH
VIL
Figure 9. Timing requirements during SPI communication
tFSI
tRSI
VOH
90 % VCC
50 %
SCLK
10 % VCC
VOL
VOH
10 % VCC
SO
VOL
tRSO
Low to High
tVALID
tFSO
SO
High To Low
VOH
90 % VCC
10 % VC
VOL
Figure 10. Timing diagram for serial output (SO) data communication
MC12XS6D1
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NXP Semiconductors
19
5.6.5
Electrical characterization
Table 7. Electrical characteristics
Characteristics noted under conditions 4.5 V  VCC  5.5 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
SPI signals CSB, SI, SO, SCLK, SO
fSPI
SPI clock frequency
0.5
–
5.0
MHz
VIH
Logic input high state level (SI, SCLK, CSB, RSTB)
3.5
–
–
V
Logic input high state level for wake-up (RSTB)
3.75
–
–
V
–
–
0.85
V
VIH(WAKE)
VIL
Logic input low state level (SI, SCLK, CSB, RSTB)
VOH
Logic output high state level (SO)
VCC - 0.4
–
–
V
VOL
Logic output low state level (SO)
–
–
0.4
V
Logic input leakage current in inactive state (SI = SCLK = RSTB = [0]
and CSB = [1])
-0.5
–
+0.5
µA
Logic output tri-state leakage current (SO from 0 V to VCC)
-10
–
+1.0
µA
Logic input pull-up/pull-down resistor
25
–
100
k
Logic input capacitance
–
–
20
pF
7.5
10
12.5
µs
SO rising and falling edges with 80 pF
–
–
20
ns
tWCLKh
Required high state duration of SCLK (required setup time)
80
–
–
ns
tWCLKl
Required low state duration of SCLK (required setup time)
80
–
–
ns
tCS
Required duration from the rising to the falling edge of CSB (required
setup time)
1.0
–
–
µs
tRST
Required low state duration for reset RSTB
1.0
–
–
µs
tLEAD
Falling edge of CSB to rising edge of SCLK (required setup time)
320
–
–
ns
tLAG
Falling edge of SCLK to rising edge of CSB (required setup lag time)
100
–
–
ns
tSI(SU)
SI to falling edge of SCLK (required setup time)
20
–
–
ns
tSI(H)
Falling edge of SCLK to SI (required hold time of the SI signal)
20
–
–
ns
tRSI
SI, CSB, SCLK, Max. rise time allowing operation at maximum fSPI
–
20
50
ns
tFSI
SI, CSB, SCLK, Max. fall time allowing operation at maximum fSPI
–
20
50
ns
tSO(EN)
Time from falling edge of CSB to reach low-impedance on SO (access
time)
–
–
60
ns
tSO(DIS)
Time from Rising Edge of CSB to Reach Tri-state on SO
–
–
60
ns
IIN
IOUT
RPULL
CIN
tRST_DGL
tSO
RSTB deglitch time
(16)
Notes
16. Parameter is derived from simulations.
MC12XS6D1
20

NXP Semiconductors
6
Functional block requirements and behaviors
6.1
Self-protected high-side switches description and application
information
6.1.1
Features
Up to five power outputs are foreseen to drive automotive light applications. The outputs are optimized for driving automotive bulbs, but
also HID ballasts, LEDs, and other primarily resistive loads. The smart switches are controlled by use of high sophisticated gate drivers.
The gate drivers provide:
• output pulse shaping
• output protections
• active clamps
• output diagnostics
6.1.2
Output pulse shaping
The outputs are controlled with a closed loop active pulse shaping to provide the best compromise between:
• low switching losses
• low EMC emission performance
• minimum propagation delay time
Depending on the programming of the prescaler setting register #12-1, #12-2, the switching speeds of the outputs are adjusted to the
output frequency range of each channel. The edge shaping must be designed according the following table:
divider
factor
PWM freq. (Hz)
PWM period (ms)
d.c. range (hex)
d.c. range (LSB)
min.
max.
min.
max.
min.
max.
min.
max
min. on/off
duty cycle
time (s)
4
25
100
10
40
03
FB
4
252
156
2
50
200
5
20
07
F7
8
248
156
1
100
400
2.5
10
07
F7
8
248
78
The edge shaping provides full symmetry for rising and falling transition:
• the slopes for the rising and falling edge are matched to provide the best EMC emission performance
• the shaping of the upper edges and the lower edges are matched to provide the best EMC emission performance
• the propagation delay time for the rising edge and the falling edge is matched to provide true duty cycle control of the output duty
cycle error, < 1 LSB at max. frequency
• a digital regulation loop is used to minimize the duty cycle error of the output signal
MC12XS6D1
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NXP Semiconductors
21
Figure 11. Typical power output switching (slow and fast slew rate)
6.1.2.1
SPI control and configuration
For optimized control of the outputs, a synchronous clock module is integrated. The PWM frequency and output timing during normal mode
are generated from the clock input (CLK) by the integrated PWM module. In case of clock fail (very low frequency, very high frequency),
the output duty cycle is 100 %.
Each output (OUT1:OUT6) can be controlled by an individual channel control register:
Register
CHx control
SI address
#
2-7
D15
D14
SI data
D13
channel address
D12
D11
D10
D9
D8
WD
PH1x
PH0x
Onx
D7
D6
D5
D4
D3
D2
D1
D0
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
x
x
x
x
x
x
x
x
Where:
• PH0x:PH1x: phase assignment of the output channel x
• ONx: on/off control including overcurrent window control of the output channel x
• PWM0x:PWM7x: 8-bit PWM value individually for each output channel x
The ONx bits are duplicated in the output control register #8 to control the outputs with either the CHx control register or the output control
register. The PRS1x:PRS0x prescaler settings can be set in the prescaler settings register #12-1 and #12-2. The following changes of the
duty cycle are performed asynchronous (with positive edge of CSB signal):
• turn on with 100 % duty cycle (CHx = ON)
• change of duty cycle value to 100 %
• turn off (CHx = OFF)
• phase setting (PH0x:PH1x)
• prescaler setting (PRS1x:PRS0x)
A change in phase setting or prescaler setting during CHx = on may cause an unwanted long on-time. Therefore it is recommended to
turn off the output(s) before execution of this change. The following changes of the duty cycle are performed synchronous (with the next
PWM cycle):
• turn on with less than 100 % duty cycle (OUTx = ONx)
• change of duty cycle value to less than 100 %
A change of the duty cycle value can be achieved by a change of the:
• PWM0x: PWM7x bits in individual channel control register #2:#7
• GPWM EN1: GPWM EN6 bits (change between individual PWM and global PWM settings) in global PWM control register #9-1
• incremental/decremental register #14
MC12XS6D1
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
NXP Semiconductors
The synchronization of the switching phases between different devices is provided by the PWM SYNC bit in the initialization 2 register #1.
On a SPI write into initialization 2 register (#1):
• initialization when the bit D1 (PWM SYNC) is logic[1], all counters of the PWM module are reset with the positive edge of the CSB,
i.e. the phase synchronization is performed immediately within one SPI frame. It could help to synchronize different 12XS6 devices
in the board
• when the bit D1 is logic[0], no action is executed
The switching frequency can be adjusted for the corresponding channel as described in the following table:
CLK freq. (kHz)
prescaler setting
min.
max.
25.6
102.4
PWM freq. (Hz)
PRS1x
PRS0x
divider
factor
0
0
4
25
100
slow
0
1
2
50
200
slow
1
X
1
100
400
fast
min.
max.
PWM resolution)
slew rate
(Bit)
(steps)
8
256
No PWM feature is provided in case of:
• Fail mode
• clock input signal failure
6.1.2.2
Global PWM control
In addition to the individual PWM register, each channel can be assigned independently to a global PWM register. The setting is controlled
by the GPWM EN bits inside the global PWM control register #9-1. When no control by direct input pin is enabled and the GPWM EN bit is:
• low (logic[0]), the output is assigned to individual PWM (default status)
• high (logic[1]), the output is assigned to global PWM
The PWM value of the global PWM channel is controlled by the global PWM control register #9-2.
Table 8. Global PWM register
ONx
INEN1x
INEN0x
GPWM ENx
0
x
x
0
0
0
1
1
1
1
INx = 0
INx = 1
CHx
PWMx
CHx
PWMx
x
off
x
off
x
0
on
individual
on
individual
1
on
global
on
global
1
0
off
individual
on
individual
0
1
off
global
on
global
0
on
individual
on
global
1
on
global
on
individual
When a channel is assigned to global PWM, the switching phase the prescaler and the pulse skipping are according the corresponding
output channel setting.
6.1.2.3
Incremental PWM control
To reduce the control overhead during soft start/stop of bulbs (e.g. theatre dimming), an incremental PWM control feature is implemented.
With the incremental PWM control feature the PWM values of all internal channels OUT1:OUT4/5 can be incremented or decremented
with one SPI frame.
The incremental PWM feature is not available for:
• the global PWM channel
• the external channel OUT6
The control is according the increment/decrement register #14:
• INCR SGN: sign of incremental dimming (valid for all channels)
• INCR 1x, INCR 0x increment/decrement
MC12XS6D1
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NXP Semiconductors
23
INCR SG N increm ent/decre me nt
0
de creme nt
1
incre ment
INCR 1x INCR 0x incre ment/decreme nt
0
0
n o i ncrement/d ecre me nt
0
1
1
0
8
1
1
16
4
This feature limits the duty cycle to the rails (00 resp. FF) to avoid any overflow.
6.1.2.4
Pulse skipping
Due to the output pulse shaping feature and the resulting switching delay time of the smart switches, duty cycles close to 0 % resp. 100 %
can not be generated by the device. Therefore the pulse skipping feature (PSF) is integrated to interpolate this output duty cycle range in
normal mode.
The pulse skipping provides a fixed duty cycle pattern with eight states to interpolate the duty cycle values between F7 (Hex) and FF (Hex).
The range between 00 (Hex) and 07 (Hex) is not considered to be provided.
The pulse skipping feature:
• is available individually for the power output channels (OUT1:OUT5)
• is not available for the external channel (OUT6)
The feature is enabled with the PSF bits in the output control register #8. When the corresponding PSF bit is:
• low (logic[0]), the pulse skipping feature is disabled on this channel (default status)
• high (logic[1]), the pulse skipping feature is enabled on this channel
hex
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
.
.
.
.
03
02
01
00
PWM duty cycle
dec
[%]
256
100,00%
255
99,61%
254
99,22%
253
98,83%
252
98,44%
251
98,05%
250
97,66%
249
97,27%
96,88%
248
96,48%
247
96,09%
246
245
95,70%
.
.
.
.
.
.
.
.
4
1,56%
3
1,17%
2
0,78%
1
0,39%
S0
FF
F7
F7
F7
F7
F7
F7
F7
pulse skipping frame
S1 S2 S3 S4 S5 S6
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF F7 FF FF
FF F7 FF F7 FF FF
FF F7 FF F7 FF F7
F7 F7 FF F7 FF F7
F7 F7 FF F7 F7 F7
F7 F7 F7 F7 F7 F7
S7
FF
FF
FF
FF
FF
FF
FF
FF
MC12XS6D1
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
NXP Semiconductors
6.1.2.5
Input control
Up to four dedicated control inputs (IN1:IN4) are foreseen to:
• wake-up the device
• fully control the corresponding output in case of fail mode
• control the corresponding output in case of normal mode
The control during normal mode is according the INEN0x and INEN1x bits in the input enable register #11 and according the logic table
in Table 8. An input deglitcher is provided at each control input to avoid high frequency control of the outputs. The internal signal is called
iINx. The channel control (CHx) can be summarized:
• Normal mode:
• CH1: 4 controlled by ONx or INx (if it is programmed by the SPI)
• CH5: 6 controlled by ONx
• Rising CHx by definition means starting overcurrent window for OUT1:5
• Fail mode:
• CH1: 4 controlled by iINx, while the overcurrent windows are controlled by IN_ONx
• CH5: 6 are off
Even so, the input thresholds are logic level compatible, the input structure of the pins is able to withstand battery voltage levels (max.40 V)
without damage. External current limit resistors (i.e. 1.0 k:10 k) can be used to handle reverse current conditions. The inputs have an
integrated pull-down resistor.
6.1.2.6
Electrical characterization
Table 9. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
RDS(on)
On-resistance, drain-to-source for 7.0 m power channel
• TJ = 25 °C
• TJ = 150 °C
• TJ = 25 °C, VBAT = -12 V
• TJ = 150 °C, VBAT = -12 V
–
–
–
–
6.0
–
–
–
–
12.9
13
18.7
RDS(on)
On-resistance, drain-to-source for 17 m power channel
• TJ = 25 °C
• TJ = 150 °C
• TJ = 25 °C, VBAT = -12 V
• TJ = 150 °C, VBAT = -12 V
–
–
–
–
15
–
–
–
–
30.9
31
43.5
Sleep mode output leakage current (output shorted to GND) per
channel
• TJ = 25 °C, VBAT = 12 V
• TJ = 125 °C, VBAT = 12 V
• TJ = 25 °C, VBAT = 35 V
• TJ = 125 °C, VBAT = 35 V
–
–
–
–
–
–
–
–
0.5
5.0
5.0
25
Operational output leakage current in off-state per channel
• TJ = 25 °C, VBAT = 18 V
• TJ = 125 °C, VBAT = 18 V
–
–
–
–
10
20
4.0
8.0
8.0
–
–
–
252
248
248
Unit
Notes
Power outputs OUT1:OUT5
ILEAK SLEEP
IOUT
OFF
PWM
Output PWM duty cycle range (measured at VOUT = VBAT/2)
• Low frequency range (25 Hz to 100 Hz)
• Medium frequency range (50 Hz to 200 Hz)
• High frequency range (100 Hz to 400 Hz)
m
m
µA
µA
LSB
MC12XS6D1

NXP Semiconductors
25
Table 9. Electrical characteristics (continued)
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Min.
Typ.
Max.
Unit
Notes
Rising and falling edges slew rate at VBAT = 14 V (measured from
VOUT = 2.5 V to VBAT - 2.5 V)
• Low frequency range
• Medium frequency range
• High frequency range
0.25
0.25
0.55
0.42
0.42
0.84
0.6
0.6
1.25
V/µs
(17)
SR
Rising and falling edges slew rate matching at VBAT = 14 V (SRr/SRf)
0.9
1.0
1.1
tDLY
Turn-on and turn-off delay times at VBAT = 14 V
• Low frequency range
• Medium frequency range
• High frequency range
20
20
10
70
70
30
120
120
50
Turn-on and turn-off delay times matching at VBAT = 14 V
• Low frequency range
• Medium frequency range
• High frequency range
-20
-20
-10
0.0
0.0
0.0
20
20
10
Shutdown delay time in case of fault
0.5
2.5
4.5
µs
25.6
–
102.4
kHz
SR
tDLY
tOUTPUT SD
Characteristic
(17)
µs
(17)
µs
(17)
Reference PWM clock
fCLK
Clock Input Frequency Range
Notes
17. With nominal resistive load: 2.5  and 5.0  respectively for 7.0 m and 17 m channel.
6.1.3
Output protections
The power outputs are protected against fault conditions in normal and fail mode in case of:
• overload conditions
• harness short-circuit
• overcurrent protection against ultra-low resistive short-circuit conditions due to a smart overcurrent profile and severe short-circuit
protection
• overtemperature protection including overtemperature warning
• under and overvoltage protections
• charge pump monitoring
• reverse battery protection
In case a fault condition is detected, the corresponding output is commanded off immediately after the deglitch time tFAULT SD. The turn
off in case of a fault shutdown (OCHI1, OCHI2, OCHI3, OCLO, OTS, UV, CPF, OLOFF) is provided by the FTO feature (fast turn off). The
FTO:
• does not use edge shaping
• is provided with high slew rate to minimize the output turn-off time tOUTPUT SD, in regards to the detected fault
• uses a latch which keeps the FTO active during an undervoltage condition (0 < VBAT < VBAT UVF)
MC12XS6D1
26

NXP Semiconductors
Figure 12. Power output switching in nominal operation and in case of a fault
Normal mode
In case of a fault condition during normal mode:
• the status is reported in the quick status register #1 and the corresponding channel status register #2:#6
To restart the output:
• the channel must be restarted by writing the corresponding on bit in the channel control register #2:#6 or output control register #8
MC12XS6D1

NXP Semiconductors
27
OLOFF
(Ioutx > I oloff thres) or (t > t oloff)
OUTx = 1
(OLOFF ENx = 1)
(rewrite CHx=1) & (tochi1+tochi2< t <tochi1+tochi2+tochi3)
(rewrite CHx=1) & (tochi1< t <tochi1+tochi2)
off
[(set CHx=1) & (fault x=0)] or
[(rewrite CHx=1) & (t<tochi1)]
OCHI1
OCHI2
OUTx = HSONx
OUTx = HSONx
OUTx = off
(t>tochi1 + tochi2)
& (fault x=0)
(t > tochi1) & (fault x=0)
OCHI3
OUTx = HSONx
(CHx=0) or (fault x=1)
(CHx=0) or (fault x=1)
(CHx=0) or (fault x=1)
(OCLOx=1) & (OCHI ODx=1)
(NO OCHIx=1) & (fault x=0)
(NO OCHIx =1) & (fault x=0)
(CHx=0) or (fault x=1)
OCLO
OUTx = HSONx
[(rewrite CHx=1) & (t>tochi1+tochi2+tochi3)] or
[(set CHx=1) & (NO OCHIx=1)]
[(t > tochi1+tochi2+tochi3) & (fault x=0)] or
[(NO OCHIx=1) & (fault x=0)]
Definitions of key logic signals
(fault x):= (UV) or (OCHI1x) or (OCHI2x) or (OCHI3x) or (OCLOx) or (OTx) or (SSCx)
(set CHx=1):= [(ONx=0) then (ONx=1)] or [(iINx=0) then (iINx=1)]
(rewrite CHx=1):= (rewrite ONx=1) after (fault x=1)
SSCx:= severe short circuit detection
tochi2 is depending on NO_HID settings and output current during OCHI2 state
Figure 13. Output control diagram in normal mode
MC12XS6D1
28
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NXP Semiconductors
Fail mode
In an overcurrent (OCHI2, OCHI3, OCLO) or undervoltage is detected, the restart is controlled by the autorestart feature.
I threshold
I OCHI2
I OCHI3
driver turned off in case of
fault_fail x ( = OC or UV)
event during autorestart
driver turned on again with
OCHI2 after fault_fail x
I OCLO
In case of successful autorestart
(no fault_fail x event)
OCLO remains active
tOCHI2
time
t AUT ORESTART
Figure 14. Autorestart in fail mode
During overtemperature (OTSx), severe short-circuit (SSCx), or OCHI1 overcurrent, the corresponding output enters the latch off state
until the next wake-up cycle or mode change.
(INx_ON=0)
auto
restart
autorestart x=1
OC_fail x=0
OUTx=off
(UV =1)
(UV =1) or
(OCLOx=1)
(UV =1) or
(OCHI3x=1)
(UV=0) &
(t > t autorestart)
(UV =1) or
(OCHI2x=1)
(t > tochi1+tochi2)
& (autorestart=1)
(INx_ON=1)
off
OCHI1
OUTx=off
autorestart x=0
OUTx=iINx
OCHI2
(t > tochi1)
OUTx=iINx
(t > tochi1+tochi2)
& (autorestart x=0)
OCHI3
(t >tochi1+
tochi2+ tochi3)
OUTx=iINx
OCLO
OUTx=iINx
(INx_ON=0)
(INx_ON=0)
(INx_ON=0)
(OTSx=1) or
(SSCx=1)
(INx_ON=0)
(OTSx=1) or
(SSCx=1) or
(OCHI1x=1)
Definitions of key signals
iINx:= external Inputs IN1~IN4 after deglitcher
SSCx := severe short circuit detection
latch
OFF
(OTSx=1) or
(SSCx=1)
(OTSx=1) or
(SSCx=1)
OUTx=off
tochi2 is depending on output current during OCHI2 state
Figure 15. Output control diagram in fail mode
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29
6.1.3.1
Overcurrent protections
Each output channel is protected against overload conditions by use of a multilevel overcurrent shutdown.
current
IOCHI1
IOCHI2
Overcurrent threshold profile
IOCHI3
IOCLO
Lamp current
tOCHI1
tOCHI2
tOCHI3
Figure 16. Transient overcurrent profile
The current thresholds and the threshold window times are fixed for each type of power channel. When the output is in PWM mode, the
clock for the OCHI time counters (tOCHI1:tOCHI3) is gated (logic AND) with the referring output control signal:
• the clock for the tOCHI counter is activated when the output = [1] respectively CHx = 1
• the clock for the tOCHI counter is stopped when the output = [0] respectively CHx = 0
current
IOCHI1
IOCHI2
IOCHI3
IOCLO
time
cumulative
tOCHI1
cumulative
tOCHI2
cumulative
tO CHI3
Figure 17. Transient overcurrent profile in PWM mode
This strategy counts the OCHI time only when the bulb is actually heated up. The window counting is stopped in case of UV, CPF, and
OTS. A severe short-circuit protection (SSC) is implemented to limit the power dissipation in normal and fail modes, in case of severe
short-circuit event. This feature is active only for a very short period of time, during off-to-on transition. The load impedance is monitored
during the output turn-on.
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Normal mode
The enabling of the high current window (OCHI1:OCHI3) is dependent on CHx signal. When no control input pin is enabled, the control
of the overcurrent window depends on the on bits inside channel control registers #2:#7 or the output control register #8. When the
corresponding CHx signal is:
• toggled (turn off and then on), the OCHI window counter resets and the full OCHI windows is applied
current
IOCHI1
Overcurrent threshold profile
IOCHI2
IOCHI3
OCLO fault detection
IOCLO
Channel current
time
ON bit =0
ON bit =1
Figure 18. Resetable overcurrent profile
• rewritten (logic [1]), the OCHI window time is proceeding without reset of the OCHI counter
current
OCLO fault detection
I OCLO
time
ON bit =1 rewriting
Figure 19. Overcurrent level fixed to OCLO
Fail mode
The enabling of the high current window (OCHI1:OCHI3) is dependent on INx_ON toggle signal. The enabling of output (OUT1:5) is
dependent on CHx signal.
6.1.3.1.1
Overcurrent control programming
A set of overcurrent control programming functions are implemented to provide a flexible and robust system behavior:
HID ballast profile (NO_HID)
A smart overcurrent window control strategy is implemented to turn on an HID ballast, even in the case of a long power on reset time.
When the output is in 100 % PWM mode (including PWM clock failure in normal mode and iINx = 1 in fail mode), the clock for the OCHI2
time counter is divided by 8, when no load current is demanded from the output driver:
• the clock for the tOCHI2 counter is divided by 8 when the open load signal is high (logic[1]), to accommodate the HID ballast while
in power on reset mode
• the clock for the tOCHI2 counter is connected directly to the window time counter when the open load signal is low (logic[0]), to
accommodate the HID demanding load current from the output
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31
current
IOCHI1
IOCHI2
Overcurrent threshold profile
IOCHI3
IOCLO
Channel current
tOCHI1
8 x tOCHI2
tOCHI3
time
Figure 20. HID ballast overcurrent profile
This feature extends the OCHI2 time, depending on the status of the HID ballast, and ensures to bypass even a long power on reset time
of HID ballast. Nominal tOCHI2 duration is up to 64 ms (instead of 8.0 ms). This feature is automatically active at the beginning of smart
overcurrent window, except for OCHI on demand as described by the following. The functionality is controlled by the NO_HID1 and
NO_HID0 bits inside the initialization #2 register. When the NO_HID1 and NO_HID0 bits are respectively:
• [0 0]: smart HID feature is available for all channels (default status and during fail mode)
• [0 1]: smart HID feature is available for channel 3 only
• [1 0]: smart HID feature is available for channels 3 and 4 only
• [1 1]: smart HID feature is not available for any channel
OCHI on demand (OCHI OD)
In some instances, a lamp might be de-powered when its supply is interrupted by the opening of a switch (as in a door), or by disconnecting
the load (as in a trailer harness). In these cases, the driver should be tolerant of the inrush current occurring when the load is reconnected.
The OCHI on demand feature allows such control individually for each channel through the OCHI ODx bits inside the Initialization #2
register. When the OCHI ODx bit is:
• low (logic[0]), the channel operates in its normal, default mode. After end of OCHI window timeout the output is protected with an
OCLO threshold
• high (logic[1], the channel operates in the OCHI on demand mode and uses the OCHI2 and OCHI3 windows and times after an
OCLO event
To reset the OCHI ODx bit (logic[0]) and change the response of the channel, first change the bit in the Initialization #2 register and then
turn the channel off. The OCHI ODx bit is also reset after an overcurrent event at the corresponding output. The fault detection status is
reported in the quick status register #1 and the corresponding channel status registers #2:#6, as presented in Figure 21.
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NXP Semiconductors
current
solid line: nominal operation
dotted lines: fault conditions
OCHI2 fault reported
IOCHI2
OCHI3 fault reported
IOCHI3
OCLO fault reported
IOCLO
OCHI OD fault reported
tOCHI2
tOCHI3
time
Figure 21. OCHI on demand profile
OCLO threshold setting
The static overcurrent threshold can be programmed individually for each output in two levels to adapt low duty cycle dimming and a
variety of loads. The CSNS recopy factor and OCLO threshold depend on OCLO and ACM settings. The OCLO setting is controlled by
the OCLOx bits inside the overcurrent control register #10-1. When the OCLOx bit is
• low (logic[0]), the output is protected with the higher OCLO threshold (default status and during fail mode)
• high (logic[1]), the lower OCLO threshold is applied
Short OCHI
The length of the OCHI windows can be shortened by a factor of 2, to accelerate the availability of the CSNS diagnosis and to reduce the
potential stress inside the switch during an overload condition. The setting is controlled individually for each output by the SHORT OCHIx
bits inside the overload control register #10-2. When the SHORT OCHIx bit is:
• low (logic[0]), the default OCHI window times are applied (default status and during fail mode)
• high (logic[1]), the short OCHI window times are applied (50 % of the regular OCHI window time)
No OCHI
The switch on process of an output can be done without an OCHI window, to accelerate the availability of the CSNS diagnosis. The setting
is controlled individually for each channel by the no OCHIx bits inside the overcurrent control register #10-2. When the no OCHIx bit is:
• low (logic[0]), the regular OCHI window is applied (default status and during fail mode)
• high (logic[1]), the turn on of the output is provided without OCHI windows
The NO OCHI bit is applied in real time. The OCHI window is left immediately when the no OCHI is high (logic[1]). The overcurrent
threshold is set to OCLO when:
• the no OCHIx bit is set to logic [1] while CHx is on or
• CHx turns on if no OCHIx is already set
Thermal OCHI
To minimize the electro-thermal stress inside the device in case of a short-circuit, the OCHI1 level can be automatically adjusted in regards
to the control die temperature. The functionality is controlled for all channels by the OCHI thermal bit inside the initialization 2.
When the OCHI thermal bit is:
• low (logic[0]), the output is protected with default OCHI1 level
• high (logic[1]), the output is protected with the OCHI1 level reduced by RTHERMAL OCHI = 15 % (typ.) when the control die
temperature is above TTHERMAL OCHI = 63 °C (typ.)
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Transient OCHI
To minimize the electro-thermal stress inside the device in case of a short-circuit, the OCHIx levels can be dynamically evaluated during
the off-to-on output transition. The functionality is controlled for all channels by the OCHI transient bit inside the initialization 2 register.
When the OCHI TRANSIENT bit is:
• low (logic[0]), the output is protected with default OCHIx levels
• high (logic[1]), the output is protected with an OCHIx levels depending on the output voltage (VOUT):
• OCHIx level reduced by RTRANSIENT OCHI = 50 % typ. for 0 < VOUT < VOUT DETECT (VBAT/2 typ.)
• Default OCHIx level for VOUT DETECT < VOUT
If the resistive load is less than VBAT/IOCHI1, the overcurrent threshold is exceeded before output reaches VBAT/2, and the output current
reaches IOCHI1. The output is then switched off at much lower and safer currents. When the load has significant series inductance, the
output current transition falls behind voltage with LLOAD/RLOAD constant time. The intermediate overcurrent threshold could not reach and
the output current continues to rise up to OCHIx levels.
6.1.3.1.2
Electrical characterization
Table 10. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power outputs OUT1:OUT5
IOCHI1
High overcurrent level 1 for 7.0 m power channel
• TJ = -40 °C and 25 °C
• TJ = 150 °C
100
96
111
106
126.5
126.5
A
IOCHI2
High overcurrent level 2 for 7.0 m power channel
• TJ = -40 °C and 25 °C
• TJ = 150 °C
61.2
60
70
69
77.5
77.5
A
IOCHI3
High overcurrent level 3 for 7.0 m power channel
34
39
43.5
A
IOCLO
Low overcurrent for 7.0 m power channel
• High level
• Low level
17.6
8.8
21.9
10.8
26.4
13.2
A
Low overcurrent for 7.0 m power channel in ACM mode
• High level
• Low level
8.8
4.4
10.8
5.5
13.2
6.6
A
IOCHI1
High overcurrent level 1 for 17 m power channel
• TJ = -40 °C and 25 °C
• TJ = 150 °C
42
40
48
46
54.4
54.4
A
IOCHI2
High overcurrent level 2 for 17 m power channel
24.5
28.2
32.2
A
IOCHI3
High overcurrent level 3 for 17 m power channel
14.8
17.3
19.5
A
IOCLO
Low overcurrent for 17 m power channel
• High level
• Low level
8.8
4.4
10.8
5.3
13.2
6.6
A
Low overcurrent for 17 m power channel in ACM mode
• High level
• Low level
4.4
2.2
5.3
2.6
6.6
3.3
A
RTRANSIENT OCHI
High overcurrent ratio 1
0.45
0.5
0.55
RTHERMAL OCHI
High overcurrent ratio 2
0.835
0.85
0.865
TTHERMAL OCHI
Temperature threshold for IOCHI1 level adjustment
50
63
70
IOCLO ACM
IOCLO ACM
°C
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NXP Semiconductors
Table 10. Electrical characteristics (continued)
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power outputs OUT1:OUT5 (continued)
tOCHI1
High overcurrent time 1
• Default value
• Short OCHI option
1.5
0.75
2.0
1.0
2.5
1.25
ms
tOCHI2
High overcurrent time 2
• Default value
• Short OCHI option
6.0
3.0
8.0
4.0
10
5.0
ms
tOCHI3
High overcurrent time 3
• Default value
• Short OCHI option
48
24
64
32
80
40
ms
Minimum severe short-circuit detection
• 7.0 m power channel
• 17 m power channel
5.0
10
–
–
–
–
m
tFAULT SD
Fault deglitch time
• OCLO and OCHI OD
• OCHI1:3 and SSC
1.0
1.0
2.0
2.0
3.0
3.0
µs
tAUTO
RESTART
Fault autorestart time in fail mode
48
64
80
ms
tBLANKING
Fault blanking time after wake-up
–
50
100
µs
RSC MIN
(18)
Notes
18. Guaranteed by test mode.
6.1.3.2
Overtemperature protection
A dedicated temperature sensor is located on each power transistor, to protect the transistors and provide SPI status monitoring. The
protection is based on a two stage strategy. When the temperature at the sensor exceeds the:
• selectable overtemperature warning threshold (TOTW1, TOTW2), the output stays on and the event is reported in the SPI
• overtemperature threshold (TOTS), the output is switched off immediately after the deglitch time tFAULT SD and the event is reported
in the SPI after the deglitch time tFAULT SD
6.1.3.2.1
Overtemperature warning (OTW)
In case of an overtemperature warning:
• the output remains in current state
• the status is reported in the quick status register #1 and the corresponding channel status register #2:#6
The OTW threshold can be selected by the OTW SEL bit inside the initialization 2 register #1. When the bit is:
• low (logic[0]), the high overtemperature threshold is enabled (default status)
• high (logic[1]), the low overtemperature threshold is enabled
To delatch the OTW bit (OTWx):
• the temperature has to drop below the corresponding overtemperature warning threshold
• a read command of the corresponding channel status register #2:#6 must be performed
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35
6.1.3.2.2
Overtemperature shutdown (OTS)
During an overtemperature shutdown:
• the corresponding output is disabled immediately after the deglitch time tFAULT SD
• the status is reported after tFAULT SD in the quick status register #1 and the corresponding channel status register #2:#6
To restart the output after an overtemperature shutdown event in normal mode:
• the overtemperature condition must be removed, and the channel must be restarted by a write command of the on bit in the
corresponding channel control register #2:#6, or in the output control register #8
To delatch the diagnosis:
• the overtemperature condition must be removed
• a read command of the corresponding channel status register #2:#6 must be performed
To restart the output after an overtemperature shutdown event in fail mode:
• a mode transition is needed. Refer to Mode transitions on page 15
6.1.3.2.3
Electrical characterization
Table 11. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power outputs OUT1:OUT5
TOW
Overtemperature warning
• TOW1 level
• TOW2 level
100
120
115
135
130
150
°C
(19)
TOTS
Overtemperature shutdown
155
170
185
°C
(19)
Fault deglitch time
• OTS
2.0
5.0
10
µs
tFAULT SD
Notes
19. Guaranteed by test mode.
6.1.3.3
6.1.3.3.1
Undervoltage and overvoltage protections
Undervoltage
During an undervoltage condition (VBATPOR < VBAT < VBAT UVF), all outputs (OUT1:OUT5) are switched off immediately after deglitch time
tFAULT SD. The undervoltage condition is reported after the deglitch time tFAULT SD:
• in the device status flag (DSF) in the registers #1:#7
• in the undervoltage flag (UVF) inside the device status register #7
Normal mode
The reactivation of the outputs is controlled by the microcontroller. To restart, the output the undervoltage condition must be removed and:
• a write command of the on bit must be performed in the corresponding channel control register #2:#6 or in the output control register
#8
To delatch the diagnosis:
• the undervoltage condition must be removed
• a read command of the device status register #7 must be performed
Fail mode
When the device is in fail mode, the restart of the outputs is controlled by the autorestart feature.
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6.1.3.3.2
Overvoltage
The device is protected against overvoltage on VBAT. During:
• jump start condition, the device may be operated, but with respect to the device limits
• load dump condition (VBAT LD MAX = 40 V) the device does not conduct energy to the loads
The overvoltage condition (VBAT > VBAT OVF) is reported in the:
• device status flag (DSF) in the registers #1:#7
• overvoltage flag (OVF) inside the device status register #7
To delatch the diagnosis:
• the overvoltage condition must be removed
• a read command of the device status register #7 must be performed
During an overvoltage (VBAT > VBAT HIGH), the device is not “short-circuit” proof.
6.1.3.3.3
Electrical characterization
Table 12. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Battery undervoltage
5.0
5.25
5.5
V
Battery undervoltage hysteresis
200
350
500
mV
Battery overvoltage
28
30
32
V
VBAT OVF HYS
Battery overvoltage hysteresis
0.5
1.0
1.5
V
VBAT LD MAX
Battery load dump voltage (2.0 min at 25 °C)
40
–
–
V
VBAT HIGH
Maximum battery voltage for short-circuit protection
32
–
–
V
tFAULT SD
Fault deglitch time
• UV and OV
2.0
3.5
5.5
µs
Notes
Battery VBAT
VBAT UVF
VBAT UVF HYS
VBAT OVF
6.1.3.4
Charge pump protection
The charge pump voltage is monitored in order to protect the smart switches in case of:
• power up
• failure of external capacitor
• failure of charge pump circuitry
During power up, when the charge pump voltage has not yet settled to its nominal output voltage range, the outputs can not be turned on.
Any turn on command during this phase is executed immediately after settling of the charge pump. When the charge pump voltage is not
within its nominal output voltage range:
• the power outputs are disabled immediately after the deglitch time tFAULT SD
• the failure status is reported after tFAULT SD in the device status flag DSF in the registers #1:#7 and the CPF in the quick status
register #1
• Any turn on command during this phase is executed including the OCHI windows immediately after the charge pump output voltage
has reached its valid range
To delatch the diagnosis:
• the charge pump failure condition must be removed
• a read command of the quick status register #1 is necessary
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6.1.3.4.1
Electrical characterization
Table 13. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Charge pump capacitor range (ceramic type X7R)
47
–
220
nF
VCP MAX
Maximum charge pump voltage
–
–
16
V
tFAULT SD
Fault deglitch time
• CPF
–
4.0
6.0
µs
Notes
Charge pump CP
CCP
6.1.3.5
Reverse battery protection
The device is protected against reverse polarity of the VBAT line. In reverse polarity condition:
• the output transistors OUT1:5 are turned on in order to prevent the device from thermal overload
• the OUT6 pin is pulled down to GND. An external current limit resistor must be added in series with OUT6 pin
• no output protection is available in this condition
6.1.4
Output clamps
6.1.4.1
Negative output clamp
In case of an inductive load (L), the energy is dissipated after the turn-off inside the N-channel MOSFET. When tCL (=Io x L/VCL) > 1.0 ms,
the turn-off waveform can be simplified with a rectangle as shown in Figure 22.
Output Current
Io
time
Output Voltage
tCL
VBAT
time
time
VCL
Figure 22. Simplified negative output clamp waveform
The energy dissipated in the N-channel MOSFET is: ECL = 1/2 x L x Io² x (1+ VBAT/|VCL|). In the case of tCL < 1.0 ms, contact the factory
for guidance.
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6.1.4.2
Battery clamp
The device is protected against dynamic overvoltage on the VBAT line by means of an active gate clamp, which activates the output
transistors in order to limit the supply voltage (VDCCLAMP). In case of an overload on an output the corresponding switch is turned off,
which leads to high voltage at VBAT with an inductive VBAT line. The maximum VBAT voltage is limited at VDCCLAMP by active clamp circuitry
through the load.
In case of an open load condition, the positive transient pulses (acc. ISO 7637/pulse 2 and inductive battery line) is handled by the
application. In case of negative transients on the VBAT line (acc. ISO7637-2/pulse 1), the energy of the pulses are dissipated inside the
load, or must be drained by an external clamping circuit, during a high ohmic load.
6.1.4.3
Electrical characterization
Table 14. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
41
–
50
V
-20.5
-21
–
–
-17.5
-18
Notes
Battery VBAT
VDCCLAMP
Battery clamp voltage
Power outputs OUT1:OUT5
VCL
6.1.5
Negative power channel clamp voltage
• 7.0 m
• 17 m
V
Digital diagnostics
The device offers several modes for load status detection in on state and off state through the SPI.
6.1.5.1
Open load detections
6.1.5.1.1
Open load in on state
Open load detection during on state is provided for each power output (OUT1:OUT5), based on the current monitoring circuit. The
detection is activated automatically when the output is in on state. The detection threshold is dependent on:
• the OLLED EN bits inside the OLLED control register #13-2
The detection result is reported in:
• the corresponding QSFx bit in the quick status register #1
• the global open load flag OLF (registers #1:#7)
• the OLON bit of the corresponding channel status registers #2:#6
To delatch the diagnosis:
• the open load condition must be removed
• a read command of the corresponding channel status register #2:#6 must be performed
When an open load has been detected, the output remains in on state. The deglitch time of the open load in on state can be controlled
individually for each output to be compliant with different load types. The setting is dependent on the OLON DGL bits inside the open load
control register #13-1:
• low (logic[0]) the deglitch time is tOLON DGL = 64 µs typ (bulb mode)
• high (logic[1]) the deglitch time is tOLON DGL = 2.0 ms typ (converter mode)
The deglitching filter is reset whenever output falls low and is only active when the output is high.
6.1.5.1.2
Open load in on state for LED
For detection of small load currents (e.g. LED) in on state of the switch a special low current detection mode is implemented by using the
OLLED EN bit. The detection principle is based on a digital decision during regular switch off of the output. Thereby a current source
(IOLLED) is switched on and the falling edge of the output voltage is evaluated by a comparator at VBAT - 0.75 V (typ).
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Figure 23. Open load in on state diagram for LED
The OLLED fault is reported when the output voltage is above VBAT - 0.75 V after 2.0 ms off-time or at each turn-on command in case of
off-time < 2.0 ms. The detection mode is enabled individually for each channel with the OLLED EN bits inside the LED control register
#13-2. When the corresponding OLLED EN bit is:
• low (logic[0]), the standard open load in on state (OLON) is enabled
• high (logic[1]), the OLLED detection is enabled
The detection result is reported in:
• the corresponding QSFx bit in the quick status register #1
• the global open load flag OLF (register #1:#7)
• the OLON bit of the corresponding channel status register #2:#6
When an open load has been detected, the output remains in the on state. When output is in PWM operation:
• the detection is performed at the end of the on time of each PWM cycle
• the detection is active during the off time of the PWM signal, up to 2.0 ms max.
The current source (IOLLED) is disabled after “no OLLED” detection or after 2.0 ms.
hson_1
128*DCLOCK (prescaler = ‘0’)
En_OLLed_1
OUT_1
VBAT-0.75
OUT_high
check
Analog Comparator output
TimeOut = 2.0 msec
1 : olled detected
0 : no olled detected
Figure 24. Open load in on state for LED in PWM operation (off time > 2.0 ms)
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NXP Semiconductors
hson_1
128*DCLOCK (prescaler=‘0’)
En_OLLed_1
OUT_1
VBAT-0.75
OUT_high
check
Analog Comparator output
1 : olled detected
0 : no olled detected
TimeOut = 2.0 msec
Figure 25. Open load in on state for LED in PWM operation (off time < 2.0 ms)
When output is in fully on operation (100 % PWM):
• the detection on all outputs is triggered by setting the OLLED TRIG bit inside the LED control register #13-2
• at the end of detection time, the current source (IOLLED) is disabled 100 µsec (typ.) after the output reactivation
OLLED TRIG 1
Note: OLLED TRIG bit is reset after the detection
ONoff & PWM
FF
hson_1
En_OLLed_1
100 sec
100 sec
VBAT-0.75
OUT_1
check
OUT_high
Analog Comparator output
Check
Precision ~ 9600 ns
TimeOut = 2.0 msec
1 : olled detected
0 : no olled detected
Figure 26. Open load in on state for LED in fully on operation
The OLLED TRIG bit is reset after the detection. To delatch the diagnosis:
• a read command of the corresponding channel status register #2:#6 must be performed
A false “open” result could be reported in the OLON bit:
• for high duty cycles, the PWM off-time becomes too short
• for capacitive load, the output voltage slope becomes too slow
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41
6.1.5.1.3
Open load in off state
An open load in off state detection is provided individually for each power output (OUT1:OUT5). The detection is enabled individually for
each channel by the OLOFF EN bits inside the open load control register #13-1. When the corresponding OLOFF EN is:
• low (logic[0]), the diagnosis mode is disabled (default status)
• high (logic[1]), the diagnosis mode is started for tOLOFF. It is not possible to restart any OLOFF or disable the diagnosis mode during
active OLOFF state
This detection can be activated independently for each power output (OUT1:OUT5). When it is activated, it is always activated
synchronously for all selected outputs (with positive edge of CSB). When the detection is started, the corresponding output channel is
turned on with a fixed overcurrent threshold of IOLOFF threshold. When this overcurrent threshold is:
• reached within the detection timeout tOLOFF, the output is turned off and the OLOFF EN bit is reset. No OCLOx and no OLOFFx is
reported
• not reached within the detection timeout tOLOFF, the output is turned off after tOLOFF and the OLOFF EN bit is reset. The OLOFFx
is reported
The overcurrent behavior as commanded by the overcurrent control settings (NO OCHIx, OCHI ODx, SHORTOCHIx, OCLOx, and ACM
ENx) is not be affected by applying the OLOFF ENx bit. The same is true for the output current feedback and the current sense
synchronization. The detection result is reported in:
• the corresponding QSFx bit in the quick status register #1
• the global open load flag OLF (register #1:#7)
• the OLOFF bit of the corresponding channel status register #2:#6
To delatch the diagnosis, a read command of the corresponding channel status register #2:#6 must be performed. In case of any fault
during tOLOFF (OTS, UV, CPF,), the open load in off state detection is disabled and the output(s) is (are) turned off after the deglitch time
tFAULT SD. The corresponding fault is reported in the SPI SO registers.
6.1.5.1.4
Electrical characterization
Table 15. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Open load current threshold in on state
• 7.0 m power channel at TJ = -40 °C
• 7.0 m power channel at TJ = 25 °C and 125 °C
• 17 m power channel at TJ = -40 °C
• 17 m power channel at TJ = 25 °C and 125 °C
50
100
30
50
200
200
100
100
350
300
160
150
Output PWM duty cycle range for open load detection in on state
• Low frequency range (25 Hz to 100 Hz)
• Medium frequency range (100 Hz to 200 Hz)
• High frequency range (200 Hz to 400 Hz)
18
18
17
–
–
–
–
–
–
Open load current threshold in on state/OLLED mode
2.0
4.0
5.0
mA
Maximum open load detection time/OLLED mode with 100 % duty
cycle
1.5
2.0
2.6
ms
Open load detection time in off state
0.9
1.2
1.5
ms
Fault deglitch time
• OLOFF
• OLON with OLON DGL = 0
• OLON with OLON DGL = 1
2.0
48
1.5
3.3
64
2.0
5.0
80
2.5
µs
ms
ms
0.77
0.385
1.1
0.55
1.43
0.715
A
Notes
Power outputs OUT1:OUT5
IOL
PWM OLON
IOLLED
tOLLED100
tOLOFF
tFAULT SD
IOLOFF
Open load current threshold in off state
• 7.0 m power channel
• 17 m power channel
mA
LSB
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6.1.5.2
Output shorted to VBAT in off state
A short to VBAT detection during off state is provided individually for each power output OUT1:OUT5, based on an output voltage
comparator referenced to VBAT/2 (VOUT DETECT) and an external pull-down circuitry. The detection result is reported in the OUTx bits of
the I/O status register #8 in real time. In case of UVF, the OUTx bits are undefined.
6.1.5.2.1
Electrical characterization
Table 16. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
0.42
0.5
0.58
VBAT
Notes
Power outputs OUT1:OUT5
VOUTDETECT
6.1.5.3
Output voltage comparator threshold
SPI fault reporting
Protection and monitoring of the outputs during normal mode is provided by digital switch diagnosis via the SPI. The selection of the SO
data word is controlled by the SOA0:SOA3 bits inside the initialization 1 register #0. The device provides two different reading modes,
depending on the SOA MODE bit. When the SOA MODE bit is:
• low (logic[0]), the programmed SO address is used for a single read command. After the reading, the SO address returns to quick
status register #1 (default state)
• high (logic[1]), the programmed SO address is used for the next and all further read commands until a new programming
The “quick status register” #1 provides one glance failure overview. As long as no failure flag is set (logic[1]), no control action by the
microcontroller is necessary.
Register
quick
address
SO address
SO data
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
FM
DSF
OVLF
OLF
CPF
RCF
CLKF
QSF5
QSF4
QSF3
QSF2
QSF1
• FM: fail mode indication. This bit is also present in all other SO data words, and indicates the fail mode by a logic[1]. When the
device is in normal mode, the bit is logic[0]
• global device status flags (D10:D8): These flags are also present in the channel status registers #2:#6, the device status register
#7, and are cleared when all fault bits are cleared by reading the registers #2:#7
• DSF = device status flag (RCF, or UVF, or OVF, or CPF, or CLKF, or TMF). UVF and TMF are also reported in the device status
register #7
• OVLF = over load flag (wired OR of all OC and OTS signals)
• OLF = open load flag
• CPF: charge pump flag
• RCF: registers clear flag: this flag is set (logic[1]) when all SI and SO registers are reset
• CLKF: clock fail flag. Refer to Logic I/O plausibility check on page 55
• QSF1:QSF5: channel quick status flags (QSFx = OC0x, or OC1x, or OC2x, or OTWx, or OTSx, or OLONx, or OLOFFx)
The SOA address #0 is also mapped to register #1 (D15:D12 bits report logic [0001]). When a fault condition is indicated by one of the
quick status bits (QSF1:QSF5, OVLF, OLF), the detailed status can be evaluated by reading of the corresponding channel status registers
#2:#6.
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43
Register
SO address
SO data
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
CH1 status
2
0
0
1
0
FM
DSF
OVLF
OLF
res
CH2 status
3
0
0
1
1
FM
DSF
OVLF
OLF
CH3 status
4
0
1
0
0
FM
DSF
OVLF
CH4 status
5
0
1
0
1
FM
DSF
CH5 status
6
0
1
1
0
FM
DSF
D6
D5
D4
D3
D2
D1
D0
OTS1 OTW1 OC21
OC11
OC01
OLON
OLOFF1
1
res
OTS2 OTW2 OC22
OC12
OC02
OLON
OLOFF2
2
OLF
res
OTS3 OTW3 OC23
OC13
OC03
OLON
OLOFF3
3
OVLF
OLF
res
OTS4 OTW4 OC24
OC14
OC04
OLON
OLOFF4
4
OVLF
OLF
res
OTS5 OTW5 OC25
OC15
OC05
OLON
OLOFF5
5
• OTSx: overtemperature shutdown flag
• OTWx: overtemperature warning flag
• OC0x:OC2x: overcurrent status flags
• OLONx: open load in on state flag
• OLOFFx: open load in off state flag
The most recent OC fault is reported by the OC0x:OC2x bits, if a new OC occurs before an old OC on the same output that was read.
#2~ #6
OC2x
0
OC1x OC0x over current status
0
0
no ov erc urrent
0
0
1
OCHI1
0
1
0
OCHI2
0
1
1
OCHI3
1
0
0
OCLO
1
0
1
OCHIOD
1
1
0
SSC
1
1
1
not us ed
When a fault condition is indicated by one of the global status bits (FM, DSF), the detailed status can be evaluated by reading of the device
status registers #7:
Register
device
status
SO address
SO data
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7
0
1
1
1
FM
DSF
OVLF
OLF
res
res
res
TMF
OVF
UVF
SPIF
iLMP
• TMF: test mode activation flag. Test mode is used for manufacturing testing only. If this bit is set to logic [1], the MCU must reset
the device
• OVF: overvoltage flag
• UVF: undervoltage flag
• SPIF: SPI fail flag
• iLIMP (real time reporting after the tIN_DGL, not latched)
The I/O status register #8 can be used for system test, fail mode test and the power down procedure:
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NXP Semiconductors
Register
I/O status
SO address
SO data
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
8
1
0
0
0
FM
res
TOGG
LE
iIN4
iIN3
iIN2
iIN1
D4
D3
D2
D1
D0
OUT5 OUT4 OUT3 OUT2 OUT1
The register provides the status of the control inputs, the toggle signal, and the power outputs state in real time (not latched).
• Toggle = status of the 4 input toggle signals (IN1_ON, or IN2_ON, or IN3_ON, or IN4_ON), reported in real time
• iINx = status of iINx signal (real time reporting after the tIN_DGL, not latched)
• OUTx = status of output pins OUTx (the detection threshold is VBAT/2) when undervoltage condition does not occur
The device can be clearly identified by the device ID register #9 when the battery voltage is within its nominal range:
Register
device ID
SO address
SO data
#
D15
D14
D13
D12
D11
D10
D9
D8
9
1
0
0
1
X
X
X
X4
D7
D6
D5
D4
D3
D2
D1
D0
DEVID DEVID DEVID DEVID DEVID DEVID DEVID DEVID
7
6
5
4
3
2
1
0
The register delivers DEVIDx bits = 40hex for the 07XS6517. During undervoltage condition (UVF = 1), DEVIDx bits report 00hex.
6.1.6
Analog diagnostics
The analog feedback circuit (CSNS) is implemented to provide load and device diagnostics during normal mode. During fail and sleep
modes, the analog feedback is not available. The routing of the integrated multiplexer is controlled by MUX0:MUX2 bits inside the
initialization 1 register #0.
6.1.6.1
Output current monitoring
The current sense monitor provides a current proportional to the current of the selected output (OUT1:OUT5). CSNS output delivers
1.0 mA full scale range current source reporting channel 1:5 current feedback (IFSR).
ICSNS
1.0 mA
ICSNS / IOUT = 1.0 mA / (100 % FSR) typ
Note: FSR value depends on SPI setting
IOUT
0 mA
1 % FSR
100 % FSR
Figure 27. Output current sensing
The feedback is suppressed during OCHI window (t < tOCHI1 + tOCHI2 + tOCHI3) and only enabled during low overcurrent shutdown
threshold (OCLO). During PWM operation, the current feedback circuit (CSNS) delivers current only during the on time of the output
switch. Current sense settling time, tCSNS(SET), varies with current amplitude. Current sense valid time, tCSNS(VAL), depends on the PWM
frequency (see Electrical characterization on page 50).
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45
An advanced current sense mode (ACM) is implemented in order to diagnose LED loads in normal mode and to improve current sense
accuracy for low current loads. In the ACM mode, the offset sign of current sense amplifier is toggled on every CSNS SYNCB rising edge.
The error amplifier offset contribution to the CSNS error can be fully eliminated from the measurement result by averaging each two
sequential current sense measurements. The ACM mode is enabled with the ACM ENx bits inside the ACM control register #10-1. When
the ACM ENx bit is:
• low (logic[0]), ACM disabled (default status and during fail mode)
• high (logic[1]), ACM enabled
In ACM mode:
• the precision of the current recopy feature (CSNS) is improved, especially at low output currents by averaging CSNS reporting on
sequential PWM periods
• the current sense full scale range (FSR) is reduced by a factor of two
• the overcurrent protection threshold OCLO is reduced by a factor of two
Figure 28 describes the timings between the selected channel current and the analog feedback current. Current sense validation time
pertains to stabilization time needed after turn on. Current sense settling time pertains to the stabilization time needed after the load current
changes while the output is continuously on or when another output signal is selected.
HSONx
tDLY(ON)
tDLY(OFF)
IOUTx
tCSNS(VAL)
tCSNS(SET)
time
time
CSNS
+/- 5% of new value
time
Figure 28. Current sensing response time
Internal circuitry limits the voltage of the CSNS pin when its sense resistor is absent. This feature prevents damage to other circuitry
sharing that electrical node, such as a microcontroller pin, for example. Several 12XS6 may be connected to one shared CSNS resistor.
6.1.6.2
Battery voltage monitoring
The VBAT monitor provides a voltage proportional to the battery supply tab. The CSNS voltage is proportional to the VBAT voltage as shown
in Figure 29.
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NXP Semiconductors
VCSNS
5.0 V
VCSNS / VBAT = ¼ typ
VBAT
0V
VBATPOR
20 V
Figure 29. Battery voltage reporting
6.1.6.3
Temperature monitoring
The average temperature of the control die is monitored by an analog temperature sensor. The CSNS pin can report the voltage of this
sensor.
The chip temperature monitor output voltage is independent of the resistor connected to the CSNS pin, provided the resistor is within the
min/max range of 5.0 k to 50 k. Temperature feedback range, TFB, -40 °C to 150 °C.
VCSNS
VCSNS / TJ = VFBS
VFB
-40°C
25°C
150°C
TJ
Figure 30. Temperature reporting
6.1.6.4
Analog diagnostic synchronization
A current sense synchronization pin is provided to simplify the synchronous sampling of the CSNS signal. The CSNS SYNCB pin is an
open drain requiring an external 5.0 k (min.) pull-up resistor to VCC. The CSNS SYNC signal is:
• available during normal mode only
• behavior depends on the type of signal selected by the MUX2:MUX0 bits in the initialization 1 register #0. This signal is either a
current proportional to an output current or a voltage proportional to temperature or the battery voltage
Current sense signal
When a current sense signal is selected:
• the pin delivers a recopy of the output control signal during on phase of the PWM defined by the SYNC EN0, SYNC EN1 bits inside
the initialization 1 register #0
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47
SYNC EN1
SYNC EN0
Setting
Behavior
0
0
OFF
0
1
VALID
CSNS SYNC is active (low) when CSNS is valid. During switching the output of MUXMUX, the CSNS SYNC
is inactive (high)
1
0
TRIG0
As in setting VALID, but after a change of the MUX, the CSNS SYNC is inactive (high) until the next PWM cycle
is started
1
1
TRIG1/2
Pulses (active low) from the middle of the CSNS pulse to its end are generated. Switching phases (output and
MUX) and the time from the MUX switching to the next middle of the CSNS pulse are blanked (high)
CSNS SYNC is inactive (high)
.
OUT1
time
OUT2
CSNS
SYNCB
CSNS SYNC\ CSNS SYNC\ blanked
active (low)
time
tDLY(ON)+tCSNS(SET)
time
change of CSNS MUX
from OUT1 to OUT2
OUT1 for
CSNS selected
OUT2 for CSNS selected
Figure 31. CSNS SYNCB valid setting
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NXP Semiconductors
OUT1
time
OUT2
CSNS SYNC\ blanked until
rising edge of the 1st
complete PWM cycle
CSNS
SYNC\
time
change of CSNS MUX
from OUT1 to OUT2
OUT1 for
CSNS selected
time
OUT2 for CSNS selected
Figure 32. CSNS SYNCB TRIG0 setting
OUT1
time
CSNS
SYNC\
CSNS SYNC\
active (low)
OUT2
CSNS SYNC\ blanked until 1rst valid edge
generated in the middle of the OUT2 pulse
time
change of CSNS MUX
from OUT1 to OUT2
OUT1 for
CSNS selected
time
OUT2 for CSNS selected
Figure 33. CSNS SYNCB TRIG1/2 setting
• the CSNS SYNCB pulse is suppressed during OCHI and during off phase of the PWM
• the CSNS SYNCB is blanked during settling time of the CSNS multiplexer and ACM switching by a fixed time of tDLY(ON) +
tCSNS(SET)
• when a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50 % duty cycle at a fixed period of 6.5 ms
• when the output is programmed with 100 % PWM, the CSNS SYNCB delivers a logic[0] a high pulse with the length of 100 µs (typ.)
during the PWM counter overflow for TRIG0 and TRIG1/2 settings, as shown in Figure 34
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49
OUT1
time
OUT2
time
CSNS
SYNC\
tDLY(ON)+tCSNS(SET)
time
change of CSNS MUX
from OUT1 to OUT2
OUT1 for
CSNS selected
OUT2 for CSNS selected
Figure 34. CSNS SYNCB when the output is programmed with 100 %
• In case of output fault, the CSNS SYNCB signal for current sensing does not deliver a trigger signal until the output is enabled again
Temperature signal or VBAT monitor signal
When a voltage signal (average control die temperature or battery voltage) is selected:
• the CSNS SYNCB delivers a signal with 50 % duty cycle and the period of the lowest prescaler setting (fCLK/1024)
• and a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50 % duty cycle at a fixed period of 6.5 ms (tSYNC DEFAULT)
6.1.6.5
Electrical characterization
Table 17. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Current sense resistor range
5.0
–
50
k
Current sense leakage current when CSNS is disabled
-1.0
–
+1.0
µA
VCS
Current sense clamp voltage
6.0
–
8.0
V
IFSR
Current sense full scale range for 7.0 m power channel
• High OCLO and ACM = 0
• Low OCLO and ACM = 0
• High OCLO and ACM = 1
• Low OCLO and ACM = 1
–
–
–
–
22
11
11
5.5
–
–
–
–
-11
-14
-20
-29
–
–
–
–
+11
+14
+20
+29
Notes
Current sense CSNS
RCSNS
ICSNS LEAK
ACC ICSNS
Current sense accuracy for 9.0 V < VBAT < 18 V for 7.0 m power channel
• IOUT = 80 % FSR
• IOUT = 25 % FSR
• IOUT = 10 % FSR
• IOUT = 5.0 % FSR
A
%
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Table 17. Electrical characteristics (continued)
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Current sense CSNS (continued)
ACC ICSNS 1 CAL
Current sense accuracy for 9.0 V < VBAT < 18 V with one calibration point
at 25 °C for 50 % FSR and VBAT = 14 V for 7.0 m power channel
• IOUT = 80 % FSR
• IOUT = 25 % FSR
• IOUT = 10 % FSR
• IOUT = 5.0 % FSR
ACC ICSNS 2 CAL
Current sense accuracy for 9.0 V < VBAT < 18 V with two calibration points
at 25 °C for 2.0 % and 50 % FSR and VBAT = 14 V for 7.0 m power
channel
• IOUT = 80 % FSR
• IOUT = 25 % FSR
• IOUT = 10 % FSR
• IOUT = 5.0 % FSR
ICSNSMIN
IFSR
ACC ICSNS
Minimum current sense reporting for 7.0 m
• 9.0 V < VBAT < 18 V
Current sense full scale range for 17 m power channel
• High OCLO and ACM = 0
• Low OCLO and ACM = 0
• High OCLO and ACM = 1
• Low OCLO and ACM = 1
Current sense accuracy for 9.0 V < VBAT < 18 V for 17 m power channel
• IOUT = 80 % FSR
• IOUT = 25 % FSR
• IOUT = 10 % FSR
• IOUT = 5.0 % FSR
ACC ICSNS 1 CAL
Current sense accuracy for 9.0 V < VBAT < 18 V with one calibration point
at 25 °C for 2.0 % or 50 % FSR and VBAT = 14 V for 17 m power channel
• IOUT = 80 % FSR
• IOUT = 25 % FSR
• IOUT = 10 % FSR
• IOUT = 5.0 % FSR
ACC ICSNS 2 CAL
Current sense accuracy for 9.0 V < VBAT < 18 V with two calibration points
at 25 °C for 2.0 % and 50 % FSR and VBAT = 14 V for 17 m power
channel
• IOUT = 80 % FSR
• IOUT = 25 % FSR
• IOUT = 10 % FSR
• IOUT = 5.0 % FSR
ICSNSMIN
VBAT
ACC VBAT
Minimum current sense reporting for 17 m
• 9.0 V < VBAT < 18 V
Battery voltage feedback range
Battery feedback precision
• Default (for 07XS6517 and 17XS6500)
• Default (for 17XS6400)
• 1 calibration point at 25 °C and VBAT = 12 V, for 7.0 V < VBAT < 20 V
• 1 calibration point at 25 °C and VBAT = 12 V, for 6.0 V < VBAT < 7.0 V
TFB
Temperature feedback range
(24) (22)
-7.0
-7.0
-20
-29
–
–
–
–
+7.0
+7.0
+20
+29
%
(24) (22)
-6.0
-6.0
-8.0
-12
–
–
–
–
+6.0
+6.0
+8.0
+12
–
–
1.0
–
–
–
–
11
5.5
5.5
2.75
–
–
–
–
%
(20) (23)
%
A
(20)
-11
-14
-20
-29
–
–
–
–
+11
+14
+20
+29
%
(20) (22)
-7.0
-7.0
-20
-29
–
–
–
–
+7.0
+7.0
+20
+29
%
(20) (22)
-6.0
-6.0
-8.0
-12
–
–
–
–
+6.0
+6.0
+8.0
+12
%
–
–
1.0
%
VBATMAX
–
20
V
-5.0
-6.0
-1.5
-2.2
–
–
–
–
+5.0
+6.0
+1.5
+2.2
-40
–
150
(20) (23)
(22)
%
°C
(21)
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51
Table 17. Electrical characteristics (continued)
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Temperature feedback voltage at 25 °C
–
2.31
–
V
Temperature feedback thermal coefficient
–
7.72
–
mV/°C
-15
-5.0
–
–
+15
+5.0
°C
–
–
–
–
–
–
40
260
10
Notes
Current sense CSNS (continued)
VFB
COEF VFB
ACCTFB
tCSNS(SET)
Temperature feedback voltage precision
• Default
• 1 calibration point at 25 °C and VBAT = 7.0 V
Current sense settling time
• Current sensing feedback for IOUT from 75 % FSR to 50 % FSR
• Current sensing feedback for IOUT from 10 % FSR to 1.0 % FSR
Temperature and battery voltage feedback
tCSNS(VAL)
tSYNC DEFAULT
Current sense valid time
Current sensing feedback
• Low/medium frequency range for IOUT > 20 % FSR
• Low/medium frequency range for IOUT < 20 % FSR
• High frequency range for IOUT > 20 % FSR
(22)
(22)
(21)
µs
(24)
• High frequency range for IOUT < 20 % FSR
Temperature voltage feedback
Battery voltage feedback
10
70
5.0
70
–
–
–
–
–
–
–
–
150
300
75
300
10
15
Current sense synchronization period for PWM clock failure
4.8
6.5
8.2
ms
5.0
–
–
k
–
–
0.4
V
-1.0
–
+1.0
µA
µs
Current sense synchronization CSNS SYNCB
RCSNS SYNC
VOL
IOUT MAX
Notes
20.
21.
22.
23.
24.
Pull-up current sense synchronization resistor range
Current sense synchronization logic output low state level at 1.0 mA
Current sense synchronization leakage current in tri-state (CSNS SYNC
from 0 to 5.5 V)
Precision either OCLO and ACM setting.
Parameter is derived mainly from simulations.
Parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process variations.
Error of 100 % without calibration for all modes and 50 % with 1 calibration point done at 25 °C in ACM mode (70 % in non-ACM).
Tested at 5.0 % of final value at VBAT = 14 V, current step from 0 A to 2.8 A (or 5.6 A). Parameter guaranteed by design at 1.0 % of final value.
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6.2
Power supply functional block description and application
information
6.2.1
Introduction
The device is functional when wake = [1] with supply voltages from 5.5 V to 40 V (VBAT), but is fully specification compliant only between
7.0 V and 18 V. The VBAT pin supplies power to the internal regulator, analog, and logic circuit blocks. The VCC pin (5.0 V typ.) supplies
the output register of the serial peripheral interface (SPI) and the OUT6 driver. Consequently, the SPI registers cannot be read without
presence of VCC. The employed IC architecture guarantees a low quiescent current in sleep mode (wake = [0]).
6.2.2
Wake state reporting
The CLK input/output pin is also used to report the wake state of the device to the microcontroller as long as RSTB is logic [0].
When the device is in:
• “wake state” and RSTB is inactive, the CLK pin reports a high signal (logic[1])
• “sleep mode” or the device is wake by the RSTB pin, the CLK is an input pin
6.2.2.1
Electrical characterization
Table 18. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
VCC - 0.6
–
–
V
Notes
Clock input/output CLK
VOH
6.2.3
6.2.3.1
Logic output high state level (CLK) at 1.0 mA
Supply voltages disconnection
Loss of VBAT
In case of a VBAT disconnection (VBAT < VBAT POR) the device behavior depends on VCC voltage value:
• VCC < VCC POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults are cleared
• VCC > VCC POR: all registers and faults are maintained. OUT1:5 are shut off immediately. The on/off state of OUT6 depends on the
current SPI configuration. SPI reporting is available when VCC remains within its operating voltage range (4.5 V to 5.5 V)
The wake-up event is not reported to the CLK pin. The clamping structures (battery clamp, negative output clamp) are available to protect
the device. No current is conducted from VCC to VBAT. An external current path must be available to drain the energy from an inductive
load, in case a battery disconnection occurs when an output is on.
6.2.3.2
Loss of VCC
In case of a VCC disconnection, the device behavior depends on VBAT voltage:
• VBAT < VBAT POR: the device enters the power off mode. All outputs are shut off immediately. All registers and faults are cleared
• VBAT > VBAT POR: the SPI is not available. Therefore, the device enters WD timeout
The clamping structures (battery clamp, negative output clamp) are available to protect the device. No current is conducted from VBAT to
VCC.
6.2.3.3
Loss of device GND
During loss of ground, the device cannot drive the loads, therefore the OUT1:OUT5 outputs are switched off and the OUT6 voltage is
pulled up. The device must not be damaged by this failure condition. For protection of the digital inputs series resistors (1.0 k typ) can
be provided externally in order to limit the current to ICL.
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6.2.3.4
Electrical characterization
Table 19. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Battery VBAT
VBAT POR
Battery power on reset
2.0
3.0
4.0
V
VCC POR
VCC power on reset
2.0
3.0
4.0
V
Maximum ground shift between GND pin and load grounds
-1.5
–
+1.5
V
VCC
Ground GND
VGND SHIFT
6.3
Communication interface and device control functional block
description and application information
6.3.1
Introduction
In normal mode, the power output channels are controlled by the embedded PWM module, which is configured by the SPI register settings.
For bidirectional SPI communication, VCC has to be in the authorized range. Failure diagnostics and configuration are also performed
through the SPI port. The reported failure types are: open load, short-circuit to battery, severe short-circuit to ground, overcurrent,
overtemperature, clock fail, and under and overvoltage. For direct input control, the device must be in Fail-safe mode. VCC is not required
and this mode can be forced by the LIMP input pin.
6.3.2
Fail mode input (LIMP)
The fail mode of the component can be activated by the LIMP direct input. The fail mode is activated when the input is logic [1]. In fail
mode, the channel power outputs are controlled by the corresponding inputs. Even though the input thresholds are logic level compatible,
the input structure of the pins are able to withstand battery voltage level (max. 40 V) without damage. External current limit resistors (i.e.
1.0 k:10 k) can be used to handle reverse current conditions. The direct inputs have an integrated pull-down resistor. The LIMP input
has an integrated pull-down resistor. The status of the LIMP input can be monitored by the LIMP IN bit inside the device status register #7.
6.3.2.1
Electrical characterization
Table 20. Electrical characteristics
Characteristics noted under conditions 4.5 V  VBAT  5.5 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Fail mode input LIMP
VIH
Logic input high state level
3.5
–
–
V
VIL
Logic input low state level
–
–
1.5
V
IIN
Logic input leakage current in inactive state (LIMP = [0])
-0.5
–
+0.5
µA
Logic input pull-down resistor
25
–
100
k
Logic input capacitance
–
–
20
pF
RPULL
CIN
(25)
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Table 20. Electrical characteristics
Characteristics noted under conditions 4.5 V  VBAT  5.5 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Logic input high state level
3.5
–
–
V
Logic input high state level for wake-up
3.75
–
–
V
–
–
1.5
V
-0.5
–
+0.5
µA
Logic input pull-down resistor
25
–
100
k
Logic input capacitance
–
–
20
pF
Notes
Direct inputs IN1:IN4
VIH
VIH(WAKE)
VIL
Logic input low state level
IIN
Logic input leakage current in inactive state (forced to [0])
RPULL
CIN
(25)
Notes
25. Parameter is derived mainly from simulations.
6.3.3
6.3.3.1
MCU communication interface protections
Loss of communication interface
If a SPI communication error occurs, the device is switched into fail mode. A SPI communication fault is detected if:
• the WD bit is not toggled with each SPI message or
• WD timeout is reached or
• protocol length error (modulo 16 check)
The SI stuck to static levels during CSB period and VCC fail (SPI not functional) are indirectly detected by a WD toggle error. The SPI
communication error is reported in:
• SPI failure flag (SPIF) inside the device status register #7 in the next SPI communication
As long as the device is in fail mode, the SPIF bit retains its state. The SPIF bit is delatched during the transition from fail-to-normal modes.
6.3.3.2
Logic I/O plausibility check
The logic and signal I/O are protected against fatal mistreatment by a signal plausibility check, according following table:
I/O
Signal check strategy
IN1 ~ IN4
frequency above limit (low pass filter)
LIMP
frequency above limit (low pass filter)
RSTB
frequency above limit (low pass filter)
CLK
frequency above limit (low pass filter)
The LIMP and IN1:IN4 have an input symmetrically deglitch time tIN_DGL = 200 µs (typ). If the LIMP input is set to logic [1] for a delay
longer than 200 µs typ, the device is switched into fail mode (internal signal called iLIMP).
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LIMP
tIN_DGL
200µs typ.
tIN_DGL
200µs typ.
time
iLIMP
time
Figure 35. LIMP and iLIMP signal
If the INx input is set to logic [1] for a delay longer than 200 µs (typ.), the corresponding channel is controlled by the direct signal (internal
signal called iINx).
INx
tIN_DGL
tIN_DGL
iINx
tIN_DGL
tIN_DGL
tIN_DGL
time
tIN_DGL
200µs typ.
ttoggle
1024ms typ.
ttoggle
time
INx_ON
time
Figure 36. IN, iIN and IN_ON signal
The RSTB has an input deglitch time tRST_DGL = 10 µs (typ.) for the falling edge only. The CLK has an input symmetrically deglitch time
tCLK_DGL = 2.0 µs (typ). Due to the input deglitcher (at the CLK input) a very high input frequency leads to a clock fail detection. The CLK
fail detection (clock input frequency detection fCLK LOW) is started immediately with the positive edge of RSTB signal. If the CLK frequency
is below fCLK LOW limit, the output state depends on the corresponding CHx signal. As soon as the CLK signal is valid, the output duty
cycle depends on the corresponding SPI configuration. To delatch the CLK fail diagnosis:
• the clock failure condition must be removed
• a read command of the quick status register #1 must be performed
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6.3.3.3
Electrical characterization
Table 21. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
SPI watchdog timeout
• WD SEL = 0
• WD SEL = 1
24
96
32
128
40
160
ms
Input toggle time for IN1:IN4
768
1024
1280
ms
Input deglitching time
• LIMP and IN1:IN4
• CLK
• RST\
150
1.5
7.5
200
2.0
10
250
2.5
12.5
Clock low frequency detection
50
100
200
Notes
Logic I/O LIMP IN1:IN4 CLK
tWD
tTOGGLE
tDGL
fCLOCK LOW
6.3.4
µs
Hz
External smart power control (OUT6)
The device provides a control output to drive an external smart power device in normal mode only. The control is according to the channel
6 settings in the SPI input data register.
• The protection and current feedback of the external SMARTMOS device are under the responsibility of the microcontroller
• The output delivers a 5.0 V CMOS logic signal from VCC
The output is protected against overvoltage. An external current limit resistor (i.e. 1.0 k:10 k) must be used to handle negative output
voltage conditions. The output has an integrated pull-down resistor to provide a stable off condition in sleep mode and fail mode. In case
of a ground disconnection, the OUT6 voltage is pulled up. External components are mandatory to define the state of external smart power
device and to limit possible reverse OUT6 current (i.e. resistor in series).
6.3.4.1
Electrical characterization
Table 22. Electrical characteristics
Characteristics noted under conditions 7.0 V  VBAT  18 V, - 40 C  TA  125 C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
–
–
5.0
µs
5.0
10
20
k
Notes
External smart power output OUT6
tOUT6 RISE
OUT6 rising edge for 100 pF capacitive load
ROUT6 DWN
OUT6 Pull-down resistor
VOH
Logic output high state level (OUT6)
VCC - 0.6
–
–
V
VOL
Logic output low state level (OUT6)
–
–
0.6
V
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7
Typical applications
7.1
Introduction
The 12XS6 is the latest achievement in automotive drivers for all types of centralized automotive lighting applications.
7.1.1
Application diagram
VBAT RIGHT
20V
5V Regulator
VBAT
VCC
10µ
10n…100n
GND
VCC
SO
SI
CS\
CS\
SCLK
VCC
VCC Clamp
100n
100n
5k
SO
10n
OUT2
RST\
RST\
CLK
CLK
A/D1
Parking Light
10n
OUT3
Flasher
10n
Low Beam
CSNS
10k
TRIG1
GND
OUT1
SCLK
Main MCU SI
GND
VCC VBAT CP
SYNC\
A/D2
LIMP
A/D3
IN1
10n
OUT4
10n
OUT5
Fog Light
10n
High Beam
IN2
1k
1k
5k
IN3
OUT6
IN4
VBAT
IN
1k
GND
OUT
10n
Smart Power
Spare
CSNS GND
1k
CSNS
GND
IN4
IN3
OUT6
IN
IN2
OUT5
SYNC\
CLK
10n
IN3
GND
Low Beam
OUT3
10n
RST\
Watchdog IN2
IN4
Spare
10n
Fog Light
OUT4
CSNS
IN1
OUT
10n
LIMP
LIMP
VBAT
High Beam
IN1
VBAT
GND
Smart Power
1k
1k
SO
1k
SCLK
1k
CS\
1k
SI
Flasher
OUT2
10n
Parking Light
OUT1
10n
VCC VBAT CP
1k
100n
10n…100n
20V
100n
VBAT LEFT
Figure 37. Typical automotive front lighting (featuring 07XS6517)
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7.1.2
Application instructions
7.1.3
Bill of materials
Table 23. 12XS6 Bill of materials (26)
Signal
Location
Mission
Value
VBAT
close to 12XS6
eXtreme Switch
improve emission and immunity performances
100 nF (X7R 50 V)
CP
close to 12XS6
eXtreme Switch
charge pump tank capacitor
100 nF (X7R 50 V)
VCC
close to 12XS6
eXtreme Switch
improve emission and immunity performances
10 to 100 nF (X7R 16 V)
OUT1:OUT4/5
close to output
connector
sustain ESG gun and fast transient pulses improve emission and immunity
performances
10 to 22 nF (X7R 50 V)
CSNS
close to MCU
output current sensing
CSNS
5.0 k (1.0 %)
10 k (1.0 %) and 10 nF (X7R
16 V)
close to MCU
low pass filter removing noise
CSNS SYNCB
N/A
pull-up resistor for the synchronization of A/D conversion
IN1:IN4
N/A
sustain high-voltage
1.0 k (1.0 %)
OUT6
N/A
sustain reverse battery
1.0 k (1.0 %)
5.0 k (1.0 %)
To increase fast transient pulses robustness
VBAT
close to connector
sustain pulse #1 in case of LED loads or without loads
VBAT
close to 12XS6
eXtreme Switch
sustain pulse #2 without loads
20 V zener diode and diode in series
per battery line
additional 10 µF (X7R 50 V)
To sustain 5.0 V voltage regulator failure mode
VCC
close to 5.0 V
voltage regulator
prevent high-voltage application on the MCU
5.0 V zener diode and a bipolar
transistor
Notes
26. NXP does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables.
While NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
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7.2
EMC and EMI considerations
7.2.1
EMC/EMI tests
This paragraph gives EMC/EMI performances. Further generic design recommendations can be found on the NXP website www.nxp.com.
Table 24. EMC/EMI Performances
Test
Signals
Conditions
VPWR
Conducted emission
Conducted immunity
7.2.2
150  method
Global pins: VBAT and OUT1:OUT5
Local pins: VCC, CP, and CSNS
outputs off
outputs on
in PWM
Global pins: VBAT and OUT1:OUT5
Local pins: VCC
Standard
Criteria
CISPR25
Class 5
IEC 61967-4
150  method
Global pins: 12-K level for 
VBAT pin - 11-L for OUT1: 5 pins
Local pins: 10-J level
IEC 62132-4
Class A related to the outputs state
and the analog diagnostics (20 %)
30 dBm for Global pins
12 dBm for Local pins
Fast transient pulse tests
This paragraph gives the device performances.against fast transient disturbances.
Table 25. Fast transient capability on VBAT
Test
Conditions
Pulse 1
Criteria
ISO 7637-2
Class A
outputs loaded with lamps 
other cases with external transient voltage suppressor
Pulse 2a
Pulse 3a/3b
outputs loaded
outputs unloaded
Pulse 5b (40 V)
7.3
Standard
Robustness considerations
The short-circuit protections embedded in 12XS6 are preferred to conventional current limitations, to minimize the thermal overstress
within the device in case of an overload condition. The junction temperature elevation is drastically reduced to a value which does not
affect the device’s reliability. Moreover, the availability of the lighting is guaranteed in fail mode by the unlimited autorestart feature.
The chapter 12 of AEC-Q100 specification published by the automotive electronics council presents turn-on into short-circuit condition. It
is not enough, because the short-circuit event can also occur in on-state. The test plan at TA = 70 °C is presented in Table 26. The tests
are performed on 30 parts from three engineering lots (total 90 pieces).
Table 26. 12XS6 repetitive short-circuit test results at TA = 70 °C
Short-circuit case
Battery voltage
Turn-on into short-circuit
condition
16 V
Supply line
0.3 m/2.5 mm²
5.0 m/2.5 mm²
Short-circuit in on-state
(27)
14 V
0.3 m/2.5 mm²
5.0 m/2.5 mm²
On-state overload 95 % of min
OCHI1/2/3 levels
16 V
0.3 m/6.0 mm²
Load line
5.0 m/1.0 mm²
0.3 m/1.0 mm²
5.0 m/1.0 mm²
0.3 m/1.0 mm²
0.3 m/6.0 mm²
7.0 m output cycle
without failure
17 m output cycle
without failure
500 k
500 k
500 k
500 k
500 k
500 k
500 k
500 k
500 k
500 k
500 k
500 k
500 k
500 k
Notes
27. The channel was loaded in the on-state with 100 mA.
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7.4
PCB layout recommendations
This new generation of high-side switch products family facilitates ECU design thanks to compatible MCU software and PCB foot print for
each device variant. The PCB Copper layer is similar for all devices in the 12XS6 family, only the solder Stencil opening is different.
Figure 38 shows superposition of SOIC54 (in black) and SOIC32 packages (in blue). To keep pin-to-pin compatibility in the same PCB
footprint, pin 1 of the SOIC32 package must be located at pin 3 of the SOIC54 package.
Figure 38. PCB copper layer and solder stencil opening recommendations
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7.5
Thermal information
This section provides thermal information.
7.5.1
Thermal transient
Figure 39. Transient thermal response curve
7.5.2
R/C thermal model
Contact the local field application engineer (email: [email protected]).
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8
Packaging
8.1
Marking information
Device markings indicate information on the week and year of manufacturing. The date is coded with the last four characters of the nine
character build information code (e.g. “CTKAH1229”). The date is coded as four numerical digits where the first two digits indicate the year
and the last two digits indicate the week. For instance, the date code “1229” indicates the 29th week of the year 2012.
8.2
Package mechanical dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number.
Table 27. Package Outline
Package
Suffix
32-Pin SOICEP
EK
98ASA00368D
Package Outline Drawing Number
54-Pin SOICEP
EK
98ASA00367D
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9
Revision history
Revision
Date
1.0
12/2014
2.0
5/2016
Description of changes
•
Initial release
•
Updated 98A packages per PCN 17161
•
Updated document format and style
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How to Reach Us:
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Home Page:
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Web Support:
http://www.nxp.com/support
products herein.
based on the information in this document. NXP reserves the right to make changes without further notice to any
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular
purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,
and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each
customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor
the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the
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Document Number: MC12XS6D1
Rev. 2.0
5/2016
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