DC200A - Demo Manual

DEMO MANUAL DC200
HIGH SPEED ADC
LTC1416 (400ksps) and
LTC1419 (800ksps) 14-Bit
A/D Converter Demo Board
DESCRIPTIO
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The LTC 1416/LTC1419 are, respectively, 2µs, 400ksps
and 1µs, 800 ksps sampling A/D converters. The LTC1416
draws 70mW and the LTC1419 draws 150mW. The
LTC1416/LTC1419 demo board provides the user with a
way to evaluate the LTC1416 and LTC1419 high speed
A/D converters. In addition, the LTC1416/LTC1419 demo
board is intended to illustrate the layout and bypassing
techniques required to obtain optimum performance from
these parts. The LTC1416/LTC1419 demo board is designed to be easy to use and requires only ±7V to ±15V
supplies, a conversion-start signal and an analog input
signal (single-ended or differential). As shown in the
Board Photo, the LTC1416/LTC1419 are very space efficient solutions for A/D users. By combining a 14-bit A/D,
sample-and-hold and reference into a single SSOP package, all the data acquisition circuitry, including the bypass
capacitors, can be placed in an area of only 0.5 inch2.
This manual describes how to use the demo board.
Included are timing diagrams, power supply requirements
and analog input range information. Additionally, a sche-
matic, parts list, drawings and dimensions of all the PC
board layers are included. An explanation of the layout and
bypass strategies used in this board is also included, so
that anyone designing a PC board using the LTC1416/
LTC1419 will be able to get the maximum performance
from the device. The LTC1416/LTC1419 are intended for
applications in telecommunications, digital signal processing, imaging, or any high speed, high resolution data
acquisition application. Gerber files for this circuit board
are available. Call the LTC factory.
Some key features of this demo board include:
• Proven 400ksps (LTC1416) and 800ksps (LTC1419)
14-bit ADC surface mount layout
• Actual ADC footprint is only 0.5 inch2 including
bypass capacitors
• 80dB SINAD and 90dB THD at 200kHz (LTC1416) and
80dB SINAD and 86dB THD at 400kHz (LTC1419)
inputs
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL PERFOR A CE CHARACTERISTICS A D BOARD PHOTO
4096 Point FFT of LTC1419 Demo Board
Component Side
0
–10
–20
MAGNITUDE (dB)
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
100
200
300
400
FREQUENCY (kHz)
500
600
DC200 TA01
DC200 BdPhoto
1
J7
J5
VLOGIC
RD
SHDN
JP5B
JP5A
2
3
3
R20
1M
HC14
U7B
C13
22µF
10V
C11
1000pF
R15
51Ω
D15
SS12
R16
51Ω
CS
HC14
U7A
C8
1µF
10V
JP2
JP5C
1
JP4
DGND
R19
51Ω
R18
10k
VOUT
LT1121-5
GND TABGND
2
4
VIN
U2
R17
10k
1
4
+
C4
0.1µF
C12
0.1µF
C9
10µF
10V
VCC
VSS
C3
0.1µF
U3
V+
LT®1363
2 7
–
6
3 +
8
1
V– 4
VCC
R14
20Ω
VOUT
VCC
C2
22µF
10V
JP3
VCC
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5%
2. ALL CAPACITOR VALUES IN µF, 25V, 20% AND IN pF, 50V, 10%
3. THIS DEMO CIRCUIT IS AVAILABLE IN A LOW POWER
VERSION LTC1416, DEMO NUMBER DC200A-L
CLK
A–
A+
AGND
J2
J4
GND
+VIN
J3
7V TO
15V
C5
10µF
10V
VSS
C14
0.1µF
14
5
26
27
28
21
22
23
24
25
4
3
2
1
C10
10µF
10V
C15
0.1µF
J1
–7V TO
–15V 2
7
VCC
U7G
HC14
GND
14
VLOGIC
DGND
AGND
VSS
DVDD
AVDD
SHDN
RD
CONVST
CS
BUSY
REFCOMP
VREF
AIN–
AIN
+
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
B11
B10
8
9
13
HC14
U7F
20 B00
19 B01
18 B02
17 B03
16 B04
15 B05
13 B06
12 B07
11 B08
10 B09
B12
B13
7
6
U1
79L05
1
IN
OUT
GND
5
D14
SS12
U4
LTC1419/LTC1416
–VIN
DATA READY
+
VLOGIC
VSS
C1
22µF
10V
12
B[00:13]
+
2
1
LTC1416CG
LTC1419CG
TOP VIEW
1
B06
B07
B08
B09
B10
B11
B12
B13
B05
B04
B03
5
9
8
7
6
5
4
3
2
11
1
9
8
7
6
5
4
3
B01
B02
2
B00
11
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
6
HC14
12
13
14
15
16
17
18
19
12
13
14
15
16
17
18
C16
15pF
R21
1k
Q7
D7
U7C
Q6
Q5
D5
D6
Q4
Q3
Q2
Q1
Q0
D4
D3
D2
D1
D0
0E
U6
74HC574
D7
D6
D5
D4
D3
D2
D1
D0
0E
U5
74HC574
19
15 B5
16 B4
17 B3
18 B2
19 B1
20 B0
21 SHDN
22 RD
D06
D07
D08
D09
D10
D11
D12
D13
D05
D04
D03
D02
D01
D00
23 CONVST
24 CS
25 BUSY
26 VSS
27 DVDD
28 +AVDD
G PACKAGE
28-LEAD PLASTIC SSOP
DGND 14
B7 12
B6 13
B9 10
B8 11
B11 8
B10 9
B13 6
B12 7
REFCOMP 4
AGND 5
AIN– 2
VREF 3
AIN
+
9
HC14
U7D
11
8
HC14
U7E
D[00:13]
10
D13
RDY
D13
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D13
D12
D11
J6-12
J6-11
J6-14
JP1
LED
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
DM124 SCHEM
DGND
DGND
RDY
D13
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
HEADER
18-PIN
J6-18
J6-17
J6-16
J6-15
J6-2
J6-1
J6-4
J6-3
J6-6
J6-5
J6-8
J6-7
J6-10
J6-9
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
J6-13
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0 1.2k
LTC1416/LTC1419 Demonstration Board Features Analog Input Signal Buffer, 400ksps/800ksps, Parallel Data Output 14-bit ADC,
Data Latches and LED Binary Data Display. Latched Conversion Data is Available on the 18-Pin Header, J6
DEMO MANUAL DC200
HIGH SPEED ADC
U
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PACKAGE AND SCHEMATIC DIAGRAMS
DEMO MANUAL DC200
HIGH SPEED ADC
PARTS LIST
REFERENCE
DESIGNATOR
C1, C2
C3, C4, C12, C14, C15
C5, C9
C8
C10
C11
C13
C16
D0 to D13
D14, D15
J1, J2, J3
J4, J5, J7
J6
JP1
JP2, JP3, JP4
JP5
R0 to R13
R14
R15, R16
R17, R18
R19
R20
R21
U1
U2
U3
U4
U5, U6
U7
QUANTITY
2
5
2
1
1
1
1
1
14
2
3
3
1
1
3
1
14
1
2
2
1
1
1
1
1
1
1
2
1
4
4
4
PART NUMBER
DESCRIPTION
VENDOR
TAJC226M010R
08053C104MAT1A
1206ZG106ZAT1A
0603ZG105ZAT1A
TAJB106M010R
06033A102KAT1A
1210ZG226ZAT1A
08055A150KAT1A
LN1251C-(TR)
SS12-PKG11
575-4
112404
PZC09DFAN
PZC02SAAN
JL-100-25-T
PZC03DFAN
CR10-122JM
CR10-200JM
RR0816Q510D
CR10-103JM
CR10-510JM
CR10-105JM
CR10-102JM
MC79L05ACDR1
LT1121CST-5
LT1363CS8
LTC1416CG
MC74HC574ADW
MC74HC14AD
SSC02SYAN
22uF 10V 20% Tantalum Capacitor
0.1uF 25V 20% X7R Capacitor
10uF 10V Y5V Capacitor
1uF 10V Y5V Capacitor
10uF 10V 20% Tantalum Capacitor
1000pF 25V 10% NPO Capacitor
22uF 10V Y5V Capacitor
15pF 50V 10% NPO Capacitor
2.1V 15mA Red SMT LED
20V 1A SMA Schottky Diode
Standard Banana Jack Connector
50Ω BNC, PCB-Vertical Connector
18-Pin 2-Row 0.100cc Header Connector
2-Pin 0.100cc 0.025sq Jumper
0.100cc 22-AWG Wire Jumper
6-Pin 2-Row 0.100cc 0.025sq Jumper
1.2k 1/10W 5% Chip Resistor
20Ω 1/10W 5% Chip Resistor
51Ω 1/16W 0.5% Thin Film Chip Resistor
10k 1/10W 5% Chip Resistor
51Ω 1/10W 5% Chip Resistor
1M 1/10W 5% Chip Resistor
1k 1/10W 5% Chip Resistor
79L05 –5V SO-8 Regulator IC
5V SOT-224 Regulator IC
SO-8 Op Amp IC
SSOP-28 14-Bit ADC IC
SOL-20 Flip-Flop Octal D IC
SO-14 Hex-Inv Schmitt IC
0.100cc Shunt
#4-40 1/4" Screw
Nylon Hex #4-40 1/2" Standoff
AVX
AVX
AVX
AVX
AVX
AVX
AVX
AVX
Panasonic
General Inst
Keystone
Connex
Sullins
Sullins
Samtec
Sullins
TAD
TAD
Thin Film Tech
TAD
TAD
TAD
TAD
Motorola
LTC
LTC
LTC
Motorola
Motorola
Sullins
Any
Keystone
1902C
TELEPHONE
207-282-5111
803-946-0362
803-946-0362
803-946-0362
207-282-5111
803-946-0362
803-946-0362
803-946-0362
201-348-5217
516-847-3000
718-956-8900
805-378-6464
760-744-0125
760-744-0125
800-726-8329
760-744-0125
714-255-9123
714-255-9123
507-625-8445
714-255-9123
714-255-9123
714-255-9123
714-255-9123
602-655-3005
408-432-1900
408-432-1900
408-432-1900
602-655-3005
602-655-3005
800-726-8329
718-956-8900
QUICK START GUIDE
This demonstration board is easily set up for evaluating
the LTC1416/LTC1419. Follow the procedure below for
proper operation.
1. Connect a –7V to –15V supply (J1), 7V to 15V supply
(J3), 0V or ground (J2), input test signal generator
(J4) and conversion clock source (J7) to the board as
shown in Figure 1. As delivered, the board is configured for a ±2.5V input referenced to ground (JP2 and
JP4 are shorted). Differential inputs can be converted
by removing the shorting connector on JP4. The
demonstration board also includes an LT1363 input
buffer amplifier operating with a gain of 1. The input
signal can be buffered by removing the shorting
connector from JP2 and placing it on JP3.
2. The LTC1416/LTC1419 demo board includes an input
filter with a cutoff frequency of 1.56MHz. For lower
input frequencies, best results are obtained by using
an optional filter. The TTE J3449-100k-500-20 is a
3
DEMO MANUAL DC200
HIGH SPEED ADC
QUICK START GUIDE
100kHz lowpass filter and works well for frequencies
below 100kHz. At the Nyquist frequency of 200kHz,
the TTE LE1182T-200k-400-720B 200kHz lowpass or
TTE Q70T-200k-30k-400-720B 200kHz bandpass
filters work well. The signal generator and filter should
produce < – 96dB THD.
3. Adjust the magnitude of the input signal to within
10mV of negative and positive full scale. This ensures
that the maximum SINAD is achieved without the risk
of overdriving the input and producing unwanted
distortion. The conversion clock frequency can be set
within the range of 0kHz to 400kHz.
4. The conversion results can be observed in several
ways. The onboard LEDs indicate the state of each
data bit. This is useful for giving a preliminary indication that the conversions are taking place and verifying
results when converting DC signals. The 14-bit parallel output data is available on header J6. This allows
monitoring of each bit and can be connected to a logic
analyzer, DSP or oscilloscope. The data format is
two’s complement. Offset binary format is also available by using D13 instead of D13.
5. Dynamic performance can be measured by using an
FFT-based analyzer. By synchronizing the analog input signal’s frequency to the conversion rate, or using
a windowing function, accurate SINAD, THD or other
dynamic characteristics can be evaluated.
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OPERATIO
OPERATING THE BOARD
Powering the Board
To use the demo board, apply ±7V to ±15V at 200mA to
the banana jacks J1 and J3, and 0V (GND) to J2. Be careful
to observe the correct polarity. Internal regulators provide
±5V to the LTC1416/LTC1419. An LT1121-5 regulator
(U2) provides 5V for analog and digital circuitry; – 5V is
provided for the A/D and buffer by the MC79L05 regulator
(U1).
The Analog Input
The LTC1416/LTC1419 have a unique feature not found on
previous ADCs: differential inputs with good common
mode rejection from DC to over 10MHz. Although this
feature is extremely valuable for rejecting noise and measuring differential signals, the board can also be used to
evaluate the LTC1416/LTC1419 in single-ended mode
(with the “–” input grounded). This board allows evaluation in either mode.
Differential (bipolar) analog signals are applied to the
LTC1416/LTC1419 demo board using BNC connectors J4
(noninverting + input) and J5 (inverting – input). The
analog signal input range is ±2.5V.
4
The LTC1416/LTC1419 AIN+ (noninverting) and AIN–
(inverting) inputs have a common mode range of VSS to
VDD. The full-scale differential between the signals applied
to AIN+ and AIN– is ±2.5V. For example, when a 1.5V signal
is applied to the AIN– input, the negative-to-positive fullscale input range of AIN+ is –1V to 4V, corresponding to
an output code of 1000 0000 0000 to 0111 1111 1111.
The demo board is delivered with jumpers JP2 and JP4
closed. This configures the board for a ±2.5V input signal
centered around ground and applied to J4 ( AIN+).
The board includes a recommended lowpass filter (R15
and R16, and C11) across the differential inputs. With the
component values shown, the cutoff frequency (fS) is:
1
= 1.56MHz
2π(102Ω)(1000pF)
These values can be altered to meet other circuit and input
signal requirements. For lower bandwidth input signals,
increase the value of C11. For undersampling applications
that take advantage of the input circuitry’s wide bandwidth, decrease the capacitance of C11.
The best way to observe the performance of the LTC1416/
LTC1419 is to drive it directly from a low impedance signal
source. However, since some applications involve high
DEMO MANUAL DC200
HIGH SPEED ADC
U
OPERATIO
output impedance sources, the board also has provisions
for an onboard LT1363 high speed operational amplifier.
The LT1363, operating as a noninveting buffer, provides
the LTC1416/LTC1419 with a fast settling, low impedance
signal that allows the input voltage to settle fully between
conversions. The buffer is recommended if the source
impedance of the input signal is greater than 930Ω. The
LT1363 demonstrates how to properly drive the LTC1416/
LTC1419. When using the LT1363, open JP2 and close
JP4 and JP3.
Optimum performance is achieved using a signal source
that has low output impedance, is low noise and has low
distortion. Signal generators, such as the B & K Type 1051
Sine Generator, give excellent results. Further, this
generator can be configured to operate referenced to a
master clock signal, as shown in Figure 1.
Applying the Conversion Start Signal
A conversion is initiated by a falling edge on the CONVST
input (BNC J7). The CONVST input uses TTL or CMOS
levels. As shown in Figure 2, CONVST should remain low
until the conversion is completed or returned high within
420ns of the negative going edge, as shown in Figure 3.
During a conversion, transitions on the CONVST input can
cause errors in the DOUT output.
The LTC1416/LTC1419 DOUT word can be acquired with a
logic analyzer. Conversion data can be stored on a disk and
easily transferred to a PC by using a logic analyzer that has
a PC compatible floppy drive (such as an HP1663A). Once
the data is transfered to a PC, use programs such as
MathCAD or Excel to calculate FFTs. Use the FFTs to obtain
LTC1416/LTC1419 AC specifications, such as signal-tonoise ratio and total harmonic distortion.
REFERENCE
FREQUENCY
IN
BRUEL & KJAER
TYPE 1051 SINE
GENERATOR
VIN
J4
LTC1416/
LTC1419
14-BIT A/D
DEMO BOARD
REFERENCE
FREQUENCY
OUT
HEWLETT PACKARD
HP3326A
GENERATOR
CLOCK
J7
J6
1-14
DOUT
HEWLETT PACKARD
HP1663A
LOGIC
ANALYZER
CLK
CONVST
DC200 F01
Figure 1. Typical Setup for LTC1419 Demo Board
CONVST
BUSY
Reading the Output Data
The ADC data outputs are buffered by the two 74HC574
latches and are available on connector J6. The latches
drive the LEDs and connector J6. In a practical circuit,
latches are not required unless the ADC is tied to a noisy
data bus. (Refer to the LTC1416 or LTC1419 data sheet for
details on different digital interface modes.)
The output data format of the LTC1416/LTC1419 is two’s
complement. The data can be converted to offset binary by
using D13 instead of D13. Offset binary is used when an
FFT is to be performed on the sampled data. A Data Ready
line (J6, Pin 16) is provided to latch the DOUT word. DOUT
is valid on the rising edge of Data Ready. Two ground lines
are provided on the connector and should be connected to
the receiving system.
DATA READY
DC200 F02
Figure 2. Timing Diagram
<420ns
>40ns
GOOD
CONVST
BUSY
DATA READY
DC200 F03
Figure 3. Alternative Timing Diagram
5
DEMO MANUAL DC200
HIGH SPEED ADC
U
OPERATIO
LEDs D0 to D13 provide a visual display of the LTC1416/
LTC1419 digital output word. D0 and D13 display the logic
state of the LSB and MSB, respectively. Remove jumper
JP1 to disable the LEDs, reducing supply consumption up
to 37mA.
plane efficiency, especially for the analog ground plane,
it is important to minimize plane-breaking traces.
POWER SUPPLY CONNECTIONS AND BYPASSING
LAYOUT
Analog and digital positive supply pins, AVDD and DVDD
respectively, are connected at the device and to the 5V
supply with a single trace. The negative supply pin (VSS)
is connected to the –5V supply. The best performance
is achieved by careful attention to proper bypassing.
Bypass AVDD and DVDD together to the analog ground
plane with a 10µF monolithic ceramic capacitor. Bypass
VSS to the analog ground plane with its own 10µF monolithic ceramic capacitor.
A well-designed printed circuit board layout incorporating
the LTC1416/LTC1419 uses separate analog and digital
ground planes. Except for connecting them near U4’s Pin
14, completely isolate the ground planes from each other.
Additionally, they should not overlap if they are on different printed circuit board layers. Connecting the LTC1416/
LTC1419 analog (AGND) and digital (DGND) pins to the
analog ground plane ensures the lowest noise operation.
The internal voltage reference requires a 22µF monolithic
ceramic capacitor connected between the REFCOMP pin
and the analog ground plane. This bypass capacitor is
necessary because the LTC1416/LTC1419 internal reference requires a bypass capacitor of at least 1µF for stable
operation. Reference noise can be reduced even further by
using a 1µF monolithic ceramic capacitor connected
between the VREF pin and the analog ground plane.
The demonstration board layout (section titled “PCB Layout and Film”) shows the best way to configure and
connect the ground planes. To ensure maximum ground
As with all high accuracy, high resolution circuits, the
best performance is achieved by minimizing the lead
lengths of the bypass capacitors.
Driving CS, RD and SHDN Pins
Jumpers for SHDN, RD and CS (JP5A to JP5C) are shorted
for normal operation. The jumpers can be removed and
these lines externally driven if desired. See the LTC1416 or
LTC1419 data sheet for details on driving these lines.
Table 1. Functional Description of User-Configurable Jumpers
6
JUMPER
JUMPER NAME
JUMPER CONNECTION
JP1
LED Enable
JP2
AIN+
JP3
Noninverting Input Buffer Bypass
JP4
AIN–
JP5A
SHDN
JP5B
RD
Shorted for Normal Operation. Open to Externally Drive the RD Pin
JP5C
CS
Shorted for Normal Operation. Open to Externally Drive the CS Pin
Shorting Enables LED Operation. Opening Disables LED Operation
Shorted for Unbuffered Operation. Open When Using the Noninverting Input
Buffer. See JP3
Open for Normal Operation. Short for Buffered Input Signals and Open JP2
Shorted for Single-Ended Operation. Open for Differential Input Signals
Shorted for Normal Operation. Open to Externally Drive the SHDN Pin
with a Logic Low for Shutdown Mode or with a Logic High for Normal Operation
DEMO MANUAL DC200
HIGH SPEED ADC
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OPERATIO
Table 2. Input and Output Pin Functional Description
INPUT/OUTPUT PIN
FUNCTION
INPUT/OUTPUT PIN
FUNCTION
E1
AGND (Mounting Hole)
J6-2
D13 (MSB)
E2
DGND (Mounting Hole)
J6-3
D10
E3
DGND (Mounting Hole)
J6-4
D11
E4
DGND (Mounting Hole)
J6-5
D08
J1
Negative Supply Voltage:
–7V to –15V at 100mA
J6-6
D09
J6-7
D06
J2
Supply Ground
J6-8
D07
J3
Positive Supply Voltage:
7V to 15V at 100mA
J6-9
D04
J4
AIN+ , Noninverting Input:
±2.5V, Referenced to AIN– .
Input Voltage Range:
VSS to AVDD (DVDD)
J6-10
D05
J6-11
D02
J6-12
D03
J6-13
D00
J6-14
D01
J6-15
D13 (MSB)
J6-16
RDY Output (End of Conversion)
J5
J6-1
AIN– , Inverting Input:
±2.5V, Referenced to AIN+ .
Input Voltage Range:
VSS to AVDD (DVDD)
D12
J6-17, 18
J7
Digital Ground
Convert Start: 0V to 5V
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PCB LAYOUT A D FIL
E2
E2
E1
E1
E3
E3
E4
E4
DC200 1419 SLK
DC200 1416 SLK
LTC1416 Component Side Silkscreen
LTC1419 Component Side Silkscreen
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
7
DEMO MANUAL DC200
HIGH SPEED ADC
U
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PCB LAYOUT A D FIL
DC200 COMP
DC200 SLD
Solder Side
Component Side
U
PC FAB DRAWI G
3.500
0.200
NOTES: UNLESS OTHERWISE SPECIFIED
1. WORKMANSHIP SHALL BE IN ACCORDANCE WITH IPC-A-600E
2. ALL DIMENSIONS ARE IN INCHES, ±0.003
FINISHED HOLE SIZES ARE +0.003/–0
3. FINISHED MATERIAL IS FR4, 0.062" THICK, 2 OZ Cu, 2 LAYERS
PLATED HOLE WALL THICKNESS IS 0.001 MINIMUM
INTERNAL LAYERS ARE 1 OZ Cu
4. PROCESS/PLATING SMOBC
5. SOLDERMASK BOTH SIDES USING GLOSSY GREEN LPI
6. SILKSCREEN COMPONENT SIDE USING WHITE NONCONDUCTIVE INK
0.200
B
B
A
A
A
E
C
G
D
G
G
G
F
HOLE CHART FOR SINGLE IMAGE
G
G
3.500
G
G
D
E
G
E
8
G
DIAMETER
NUMBER
OF HOLES
PLATED
A
0.209
3
YES
B
0.120
4
YES
C
0.070
2
NO
D
0.052
15
YES
E
0.040
26
YES
F
0.031
6
YES
0.015
52
YES
TOTAL HOLES
108
G
D
B
G
B
SYMBOL
C
Linear Technology Corporation
dc200f LT/TP 0798 500 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1998
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