Freescale Semiconductor
Advance Information
Document Number: MC07XSC200
Rev. 2.0, 9/2013
Dual High Side Switch
(7.0 mOhm)
07XSC200
The 07XSC200 is one in a family of devices designed for low-voltage
lighting or factory automation applications. Its two low RDS(ON)
MOSFETs (dual 7.0 m) can control two separate 55 W / 28 W bulbs,
and/or Xenon modules, and/or LEDs, and/or DC low voltage motors.
Programming, control and diagnostics are accomplished using a 16-bit
SPI interface. Its output with selectable slew rate improves
electromagnetic compatibility (EMC) behavior. Additionally, each
output has its own parallel input or SPI control for pulse-width
modulation (PWM) control if desired. The 07XSC200 allows the user to
program via the SPI, the fault current trip levels and duration of
acceptable inrush. The device has Fail-safe mode to provide fail-safe
functionality of the outputs in case of MCU damaged.
The 07XSC200 is packaged in a Pb-free power-enhanced 32 pins
SOIC package with exposed tab.
This device is powered by SMARTMOS technology.
Features
• Dual 7.0 m max high side switch (at 25 °C)
• Operating voltage range of 6.0 to 20 V with sleep current < 5.0 µA,
extended mode from 4.0 to 28 V
• 8.0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with
daisy chain capability
• PWM module using external clock or calibratable internal oscillator
with programmable outputs delay management
• Smart overcurrent shutdown compliant to huge inrush current,
severe short-circuit, overtemperature protections with time limited
auto-retry, and Fail-safe mode, in case of MCU damage
• Output OFF or ON OpenLoad detection compliant to bulbs or LEDs
and short to battery detection. Analog current feedback with
selectable ratio and board temperature feedback.
VDD
VDD
VDD
EK SUFFIX PB-FREE
98ASA00368D
32-PIN EXPOSED PAD SOIC
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC07XSC200EK
- 40 to 125 °C
32 SOIC
VPWR
07XSC200
VDD
I/O
MCU
HIGH SIDE SWITCH
I/O
FSB
WAKE
SO
SI
SCLK
SCLK
CSB
CSB
SO
SI
I/O
I/O
RSTB
CLOCK
I/O
IN0
I/O
IN1
A/D
VPWR
GND
HS1
HS0
LOAD
LOAD
CSNS
FSI
GND
Figure 1. 07XSC200 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2013. All rights reserved.
1
Internal Block Diagram
VDD
IUP
VPWR
VDD Failure
Detection
Internal
Regulator
POR
Over/Undervoltage
Protections
VPWR
Voltage Clamp
Charge
Pump
VREG
CSB
SCLK
Selectable Slew Rate
Gate Driver
IDWN
Selectable Overcurrent
Detection
SO
SI
RSTB
WAKE
FSB
IN0
HS0
Severe Short-circuit
Detection
Logic
Short to VPWR
Detection
Overtemperature
Detection
IN1
CLOCK
OpenLoad
Detections
HS0
RDWN IDWN
RDWN
HS1
Calibratable
Oscillator
PWM
Module
HS1
Overtemperature
Prewarning
VREG
Selectable Output
Current Recopy
Temperature
Feedback
FSI
Programmable
Watchdog
Analog MUX
VDD
GND
CSNS
Figure 2. 07XSC200 Simplified Internal Block Diagram
07XSC200
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
Pin Connections
2.1
Pinout Diagram
Transparent top View
RSTB
CSB
SCLK
SI
VDD
SO
GND
VPWR
HS1
HS1
HS1
HS1
HS1
HS1
HS1
HS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
VPWR
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WAKE
FSB
IN1
IN0
CLOCK
CSNS
FSI
GND
HS0
HS0
HS0
HS0
HS0
HS0
HS0
HS0
Figure 3. 07XSC200 Pin Connection
2.2
Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 22.
Table 1. 07XSC200 Pin Definitions
Pin
Number
Pin Name
Pin
Function
Formal Name
Definition
1
RSTB
Input
Reset (Active Low)
This input pin is used to initialize the device configuration and fault registers, as
well as place the device in a low current Sleep mode.
2
CSB
Input
Chip Select (Active
Low)
This input pin is connected to a chip select output of a master microcontroller
(MCU).
3
SCLK
Input
Serial Clock
This input pin is connected to the MCU providing the required bit shift clock for
SPI communication.
4
SI
Input
Serial Input
This is a command data input pin connected to the SPI Serial Data Output of
the MCU or to the SO pin of the previous device of a daisy chain of devices.
5
VDD
Input
Digital Drain Voltage
(Power)
6
SO
Output
Serial Output
This output pin is connected to the SPI serial data input pin of the MCU or to the
SI pin of the next device of a daisy chain of devices.
7, 25
GND
Ground
Ground
Those pins are the ground for the logic and analog circuitry of the device. These
pins must be shorted to board level.
This is an external voltage input pin used to supply power to the SPI circuit.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
Table 1. 07XSC200 Pin Definitions (continued)
Pin
Number
Pin Name
Pin
Function
8, 33
VPWR
Power
9 to 16
HS1
Output
High Side Output
Protected 7.0 m high side power output pin to the load. Those pins must be
shorted at board level.
26
FSI
Input
Fail-safe Input
The value of the resistance connected between this pin and ground determines
the state of the outputs after a watchdog time-out occurs.
27
CSNS
Output
Output Current
Monitoring
This pin is used to output a current proportional to the designated HS0-1 output.
28
CLOCK
Input
Reference Clock
This pin is used to apply a reference clock used to control the outputs in PWM
mode through embedded PWM module.
29
IN0
Input
Direct Input 0
This input pin is used to directly control the output HS0.
30
IN1
Input
Direct Input 1
This input pin is used to directly control the output HS1.
31
FSB
Output
Fault Status (Active
Low)
This is an open drain configured output requiring an external pull-up resistor to
VDD for fault reporting.
32
WAKE
Input
Wake
This pin is used to input a Logic [1] signal so as to enable the watchdog timer
function.
Formal Name
Definition
Positive Power Supply Pin 8 is a positive supply for quiet and accurate control. Pin 33 is a power supply
for the high current switch. These pins must be shorted at board level.
Connecting a heatsink to pin 33 guarantees optimal heat-evacuation
properties.
07XSC200
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
Electrical Characteristics
3.1
Maximum Ratings
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
VPWR Supply Voltage Range
V
VPWR(SS)
• Load Dump at 25 °C (400 ms)
41
• Maximum Operating Voltage
28
• Reverse Battery
-18
VDD Supply Voltage Range
VDD
-0.3 to 5.5
V
(4)
-0.3 to VDD + 0.3
V
WAKE Input Clamp Current
ICL(WAKE)
2.5
mA
CSNS Input Clamp Current
ICL(CSNS)
2.5
mA
Input / Output Voltage
HS [0:1] Voltage
V
VHS[0:1]
• Positive
41
• Negative
-24
Output Current per Channel
• Nominal Continuous Current
A
IHS[0:1]
(1)
26
• Short-circuit Transient Current
116
• Reverse Continuous Current(1)
-26
High Side Breakdown Voltage
VPWR - VHS
47
V
ECL [0:1]
100
mJ
• Human Body Model (HBM) for HS[0:1], VPWR and GND
VESD1
± 8000
• Human Body Model (HBM) for other pins
VESD2
± 2000
VESD3
± 750
VESD4
± 500
HS[0,1] Output Clamp Energy using single pulse method(2)
ESD Voltage(3)
• Charge Device Model (CDM)
Corner Pins (1, 27, 28, 57)
All Other Pins
V
Notes
1. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using board thermal resistance is required.
2. Active clamp energy using single-pulse method (L = 2.0 mH, RL = 0 , VPWR = 14 V, TJ = 150 C initial).
3.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM)
(CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
4.
Input / Output pins are: IN[0:1], CLOCK, RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
• Ambient
TA
- 40 to 125
• Junction (5)
TJ
- 40 to 150
Storage Temperature
TSTG
- 55 to 150
• Junction to Case
RJC
4.0
• Junction to Ambient(6)
RJA
35
TSOLDER
260
Unit
THERMAL RATINGS
Operating Temperature
C
C
THERMAL RESISTANCE
Thermal Resistance
Peak Pin Reflow Temperature During Solder
C/ W
Mounting(7)
C
Notes
5. To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not
exceed 125C.
6. Device mounted on a 2s2p test board per JEDEC JESD51-2. 20 °C/W of RθJA can be reached in a real application case (4 layers board).
7.
Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
07XSC200
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
3.2
Static Electrical Characteristics
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
• Fully Operational
6.0
–
20
• Extended mode(8)
4.0
–
28
41
47
53
–
6.5
20
Unit
POWER INPUTS
Battery Supply Voltage Range
Battery Clamp Voltage(9)
VPWR Operating Supply Current
VPWR(CLAMP)
IPWR(ON)
• Outputs commanded ON, HS[0 : 1] open, IN[0:1] > VIH
VPWR Supply Current
V
mA
mA
IPWR(SBY)
• Outputs commanded OFF, OFF Open-load Detection Disabled, HS[0 : 1]
shorted to the ground with VDD = 5.5 V
WAKE > VIH or RSTB > VIH and IN[0:1] < VIL
Sleep State Supply Current
V
VPWR
–
6.5
7.5
A
IPWR(SLEEP)
VPWR = 12 V, RSTB = WAKE = CLOCK = IN[0:1] < VIL, HS[0 :1] shorted to
ground
• TA = 25 °C
–
1.0
5.0
• TA = 85 °C
–
–
30
3.0
–
5.5
• No SPI Communication
–
1.6
2.2
• 8.0 MHz SPI Communication(10)
–
5.0
–
VDD Supply Voltage
VDD(ON)
VDD Supply Current at VDD = 5.5 V
IDD(ON)
V
mA
VDD Sleep State Current at VDD = 5.5 V
IDD(SLEEP)
–
–
5.0
A
Overvoltage Shutdown Threshold
VPWR(OV)
28
32
36
V
Overvoltage Shutdown Hysteresis
VPWR(OVHYS)
0.2
0.8
1.5
V
Undervoltage Shutdown Threshold(11)
VPWR(UV)
3.3
3.9
4.3
V
VPWR and VDD Power on Reset Threshold
VSUPPLY(POR)
0.5
–
0.9
VPWR(UV)
Recovery Undervoltage Threshold
VPWR(UV)_UP
3.4
4.1
4.5
V
VDD(FAIL)
2.2
2.5
2.8
V
VDD Supply Failure Threshold (for VPWR > VPWR(UV))
Notes
8. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 to 6.0 V voltage range, the device is only
protected with the thermal shutdown detection.
9. Measured with the outputs open.
10. Typical value guaranteed per design.
11. Output will automatically recover with time limited auto-retry to instructed state when VPWR voltage is restored to normal as long as the
VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is
supplied by VPWR and assumes that the external VDD supply is within specification.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
• VPWR = 4.5 V
–
–
25.2
• VPWR = 6.0 V
• VPWR = 10 V
–
–
11.2
–
–
7.0
• VPWR = 13 V
–
–
7.0
• VPWR = 4.5 V
–
–
42.8
• VPWR = 6.0 V
• VPWR = 10 V
–
–
19.1
–
–
11.9
• VPWR = 13 V
–
–
11.9
–
–
10.5
–
–
14
RSHORT_01
21
47
75
OCHI1_0
89.9
114.8
139.8
OCHI2_0
67
83.7
100.4
OC1_0
48
61.2
74.4
OC2_0
42
53.2
64.4
OC3_0
35.2
44.6
54
Unit
OUTPUTS HS0 TO HS1
HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 25 C)
HS[0,1] Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 150 C)
HS[0,1] Output Source-to-Drain ON Resistance (IHS = -5.0 A, VPWR= -18 V)(12)
HS[0,1] Maximum Severe Short-circuit Impedance Detection
m
RDS_01(ON)
RSD_01(ON)
• TA = 25 C
• TA = 150 C
(13)
m
RDS_01(ON)
m
HS[0,1] Output Overcurrent Detection Levels (6.0 V < VHS[0:1] < 20 V)
• 28W bit = 0
• 28W bit = 1
m
A
OC4_0
28.8
36.4
44
OCLO4_0
21
26.6
32.1
OCLO3_0
13.3
18.4
23.5
OCLO2_0
11.3
14.2
17.1
OCLO1_0
7.4
9.3
11.2
OCHI1_1
44.9
57.4
69.9
OCHI2_1
33.5
41.9
50.2
OC1_1
24
30.6
37.2
OC2_1
20.8
26.5
32.1
OC3_1
17.6
22.3
27
OC4_1
14.4
18.2
22
OCLO4_1
6.1
7.6
9.0
OCLO3_1
6.1
7.6
9.0
OCLO2_1
6.1
7.6
9.0
OCLO1_1
2.7
4.9
7.0
Notes
12. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
13.
Short-circuit impedance calculated from HS[0:1] to GND pins. Value guaranteed per design.
07XSC200
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 TO HS1 (CONTINUED)
HS[0,1] Current Sense Ratio (6.0 V < VHS[0:1] < 20 V, CSNS < 5.0 V)(14)
–
• 28W bit = 0
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1
• 28W bit = 1
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1
HS[0,1] Current Sense Ratio (CSR0) Accuracy
(6.0 V < VHS[0:1] < 20 V) with 28W bit = 0
CSR0_0
–
1/10700
–
CSR1_0
–
1/63600
–
CSR0_1
–
1/5350
–
CSR1_1
–
1/31800
–
%
CSR0_0_ACC
25 and 125 C
• IHS[0:1] = 12.5 A
-15
–
15
• IHS[0:1] = 5.0 A
-22
–
22
• IHS[0:1] = 3.0 A
-27
–
27
• IHS[0:1] = 1.5 A
-30
–
30
• IHS[0:1] = 12.5 A
-20
–
20
• IHS[0:1] = 5.0 A
-27
–
27
-30
–
30
-40
–
40
-40 C
• IHS[0:1] = 3.0 A
• IHS[0:1] = 1.5 A
HS[0,1] Current Recopy Accuracy with one calibration point
(6.0 V < VHS[0:1] < 20 V) with 28W bit = 0(15)
(CAL)
• IHS[0:1] = 5.0 A
HS[0,1] Current Sense Ratio (CSR0) Accuracy
(6.0 V < VHS[0:1] < 20 V) with 28W bit = 1
%
CSR0_0_ACC
-5.0
–
5.0
%
CSR0_1_ACC
25 and 125 C
• IHS[0:1] = 3.0 A
-25
–
25
• IHS[0:1] = 1.5 A
-30
–
30
• IHS[0:1] = 3.0 A
-30
–
30
• IHS[0:1] = 1.5 A
-40
–
40
-40 C
HS[0,1] Current Recopy Accuracy with one calibration point
(6.0 V < VHS[0:1] < 20 V) with 28W bit = 1(15)
(CAL)
• IHS[0:1] = 3.0 A
HS[0,1] CSR0 Current Recopy Temperature Drift
(6.0 V < VHS[0:1] < 20 V) with 28W bit = 0(16)
• IHS[0:1] = 5.0 A
%
CSR0_1_ACC
-5.0
–
5.0
(CSR0_0)/(T)
%/C
–
–
0.04
Notes
14. Current sense ratio = ICSNS / IHS[0:1]
15.
16.
Based on statistical analysis. It is not production tested.
Based on statistical data: delta(CSR0)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No
production tested.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 TO HS1 (CONTINUED)
HS[0,1] Current Sense Ratio (CSR1) Accuracy
(6.0 V < VHS[0:1] < 20 V) with 28W bit = 0
%
CSR1_0_ACC
25 and 125 C
• IHS[0:1] = 12.5 A
-20
–
20
• IHS[0:1] = 75 A
-17
–
17
• IHS[0:1] = 12.5 A
-28
–
28
• IHS[0:1] = 75 A
-25
–
25
-40 C
HS[0,1] Current Recopy Accuracy with one calibration point
(6.0 V < VHS[0:1] < 20 V) with 28W bit = 0(17)
(CAL)
• IHS[0:1] = 12.5 A
HS[0,1] Current Sense Ratio (CSR1) Accuracy
(6.0V < VHS[0:1] < 20V) with 28W bit = 1
%
CSR1_0_ACC
-5.0
–
5.0
%
CSR1_1_ACC
25 and 125 C
• IHS[0:1] = 12.5 A
-20
–
20
• IHS[0:1] = 37.5 A
-17
–
17
• IHS[0:1] = 12.5 A
-28
–
28
• IHS[0:1] = 75 A
-25
–
25
-40 C
HS[0,1] Current Recopy Accuracy with one calibration point
(6.0 V < VHS[0:1] < 20 V) with 28W bit = 1(17)
%
CSR1_1_ACC
(CAL)
• IHS[0:1] = 12.5 A
-5.0
–
5.0
VDD+0.25
–
VDD+1.0
IOLD(OFF)
30
–
100
A
OFF OpenLoad Fault Detection Voltage Threshold
VOLD(THRES)
2.0
3.0
4.0
V
ON OpenLoad Fault Detection Current Threshold
IOLD(ON)
80
330
660
mA
Current Sense Clamp Voltage
VCL(CSNS)
• CSNS Open; IHS[0:1] = 5.0 A with CSR0 ratio
OFF OpenLoad Detection Source Current(18)
ON OpenLoad Fault Detection Current Threshold with LED
IOLD(ON_LED)
• VHS[0:1] = VPWR - 0.75 V
Output Short to VPWR Detection Voltage Threshold
5.0
10
VOSD(THRES)
V
VPWR-1.2 VPWR-0.8 VPWR-0.4
VCL
• 0.5 A < IHS[0:1] < 5.0 A, Output programmed OFF
Output Overtemperature Shutdown for 4.5 V < VPWR < 28 V
mA
2.5
• Output programmed OFF
Output Negative Clamp Voltage
V
TSD
V
- 22
–
-16
155
175
195
C
Notes
17. Based on statistical analysis. It is not production tested.
18. Output OFF OpenLoad Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open-load condition when the specific output is commanded OFF. Pull-up current is measured for VHS = VOLD(THRES)
07XSC200
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VIH
2.0
–
VDD+0.3
V
VIL
-0.3
–
0.8
V
IDWN
5.0
–
20
A
IUP
5.0
–
20
A
CSO
–
–
20
pF
RDWN
125
250
500
k
CIN
–
4.0
12
pF
18
25
32
- 2.0
–
- 0.3
CONTROL INTERFACE
Input Logic High Voltage(19)
Input Logic Low
Voltage(19)
(22)
Input Logic Pull-down Current (SCLK, SI)
Input Logic Pull-up Current (CSB)
SO, FSB Tri-state
(23)
Capacitance(20)
Input Logic Pull-down Resistor (RSTB, WAKE, CLOCk and IN[0:1])
Input Capacitance
(20)
Wake Input Clamp
Voltage(21)
VCL(WAKE)
• ICL(WAKE) < 2.5 mA
Wake Input Forward Voltage
VF(WAKE)
• ICL(WAKE) = -2.5 mA
SO High-state Output Voltage
V
VDD-0.4
–
–
–
–
0.4
- 2.0
0.0
2.0
–
0.0
1.0
10
Infinite
–
VSOL
• IOL = -1.0 mA
SO, CSNS and FSB Tri-state Leakage Current
V
VSOH
• IOH = 1.0 mA
SO and FSB Low-state Output Voltage
V
V
A
ISO(LEAK)
• CSB = VIH and 0 V < VSO < VDD, or FSB = 5.5 V, or CSNS = 0.0 V
FSI External Pull-down Resistance(24)
• Watchdog Disabled
k
RFS
• Watchdog Enabled
Notes
19. Upper and lower logic threshold voltage range applies to SI, CSB, SCLK, FSB, IN[0:1], CLOCK and WAKE input signals. The WAKE and
RSTB signals may be supplied by a derived voltage referenced to VPWR.
20.
21.
22.
Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CLOCK and WAKE. This parameter is guaranteed by process monitoring but is not
production tested.
The current must be limited by a series resistance when using voltages > 7.0 V.
Pull-down current is with VSI > 1.0 V and VSCLK > 1.0 V.
23.
Pull-up current is with VCSB < 2.0 V. CSB has an active internal pull-up to VDD.
24.
In Fail-safe HS[0:1] depends respectively on IN[0:1]. FSI has an active internal pull-up to VREG ~ 3.0 V.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
3.3
Dynamic Electrical Characteristics
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
0.15
0.3
0.6
0.07
0.15
0.3
0.3
0.6
1.2
0.15
0.3
0.6
0.07
0.15
0.3
0.3
0.6
1.2
Unit
POWER OUTPUT TIMING HS0 TO HS1
Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0] = 00)(25)
SRR_00
• VPWR = 14 V
Output Rising Slow Slew Rate (low speed slew rate / SR[1:0] = 01)(25)
SRR_01
• VPWR = 14 V
Output Falling Fast Slew Rate (high speed slew rate / SR[1:0] = 10)(25)
V/s
SRF_10
• VPWR = 14 V
HS[0:1] Outputs Turn-ON and OFF Delay Times(26)(27)
V/s
SRF_01
• VPWR = 14 V
Output Rising Fast Slew Rate (high speed slew rate / SR[1:0] = 10)(25)
V/s
SRF_00
• VPWR = 14 V
Output Falling Slow Slew Rate (low speed slew rate / SR[1:0] = 01)(25)
V/s
SRR_10
• VPWR = 14 V
Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0] = 00)(25)
V/s
V/s
s
t DLY_12
VPWR = 14 V for medium speed slew rate (SR[1:0] = 00)
• tDLY(ON)
80
130
180
• tDLY(OFF)
40
90
140
0.8
1.0
1.2
Driver Output Matching Slew Rate (SRR /SRF)
SR
• VPWR = 14 V @ 25 °C and for medium speed slew rate (SR[1:0] = 00)
HS[0:1] Driver Output Matching Time (t DLY(ON) - t DLY(OFF))
• VPWR = 14 V, f PWM = 240 Hz, PWM duty cycle = 50%, @ 25 °C for
medium speed slew rate (SR[1:0] = 00)
t RF_01
s
0
50
100
Notes
25. Rise and Fall Slew Rates measured across a 5.0 resistive load at high side output = 30% to 70% (see Figure 4, page 19).
26. Turn-ON delay time measured from rising edge of any signal (IN[0 : 1] and CSB) that would turn the output ON to VHS[0 : 1] = VPWR / 2
with RL = 5.0 resistive load.
27.
Turn-OFF delay time measured from falling edge of any signal (IN[0 : 1] and CSB) that would turn the output OFF to VHS[0 : 1] = VPWR / 2
with RL = 5.0 resistive load.
07XSC200
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Fault Detection Blanking Time(28)
tFAULT
1.0
5.0
20
s
Time(29)
tDETECT
–
7.0
30
s
t CNSVAL
–
70
100
s
t WDTO
217
310
400
ms
TOLD(LED)
105
150
195
ms
POWER OUTPUT TIMING HS0 TO HS1 (continued)
Output Shutdown Delay
CSNS Valid Time
(30)
Watchdog Time-out
(31)
ON OpenLoad Fault Cyclic Detection Time with LED
Notes
28. Time necessary to report the fault to FSB pin.
29. Time necessary to switch-off the output in case of OT or OC or SC or UV fault detection (from negative edge of FSB pin to HS voltage =
50% of VPWR
30.
Time necessary for CSNS to be within ±5% of the targeted value (from HS voltage = 50% of VPWR to ±5% of the targeted CSNS value).
31.
For FSI open, the Watchdog time-out delay measured from the rising edge of RSTB, to HS[0,1] output state depend on the corresponding
input command.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
tOC1_00
4.40
6.30
8.02
tOC2_00
1.62
2.32
3.00
tOC3_00
2.10
3.00
3.90
tOC4_00
2.88
4.12
5.36
tOC5_00
4.58
6.56
8.54
tOC6_00
10.16
14.52
18.88
tOC7_00
73.2
104.6
134.0
tOC1_01
1.10
1.57
2.00
tOC2_01
0.40
0.58
0.75
tOC3_01
0.52
0.75
0.98
tOC4_01
0.72
1.03
1.34
tOC5_01
1.14
1.64
2.13
tOC6_01
2.54
3.63
4.72
tOC7_01
18.2
26.1
34.0
tOC1_10
2.20
3.15
4.01
tOC2_10
0.81
1.16
1.50
tOC3_10
1.05
1.50
1.95
tOC4_10
1.44
2.06
2.68
tOC5_10
2.29
3.28
4.27
tOC6_10
5.08
7.26
9.44
tOC7_10
36.6
52.3
68.0
tOC1_11
8.8
12.6
16.4
tOC2_11
3.2
4.6
21.4
tOC3_11
4.2
6.0
7.8
tOC4_11
5.7
8.2
10.7
tOC5_11
9.1
13.1
17.0
Unit
POWER OUTPUT TIMING HS0 TO HS1 (continued)
HS[0,1] Output Overcurrent Time Step for 28W bit = 0
OC[1:0] = 00 (slow by default)
OC[1:0]=01 (fast)
OC[1:0]=10 (medium)
OC[1:0]=11 (very slow)
ms
tOC6_11
20.3
29.0
37.7
tOC7_11
146.4
209.2
272.0
07XSC200
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
tOC1_00
3.4
4.9
6.4
tOC2_00
1.1
1.6
2.1
tOC3_00
1.4
2.1
2.8
tOC4_00
2.0
2.9
3.8
tOC5_00
3.4
4.9
6.4
tOC6_00
8.5
12.2
15.9
tOC7_00
62.4
89.2
116.0
tOC1_01
0.86
1.24
1.61
tOC2_01
0.28
0.40
0.52
tOC3_01
0.36
0.52
0.68
tOC4_01
0.51
0.74
0.96
tOC5_01
0.78
1.12
1.46
tOC6_01
2.14
3.06
3.98
tOC7_01
20.2
22.2
28.9
tOC1_10
1.7
2.5
3.3
tOC2_10
0.5
0.8
1.0
tOC3_10
0.7
1.0
1.3
tOC4_10
1.0
1.5
2.0
tOC5_10
1.7
2.5
3.3
tOC6_10
4.2
6.1
6.0
tOC7_10
31.2
44.6
58.0
tOC1_11
6.8
9.8
12.8
tOC2_11
2.2
3.2
16.7
tOC3_11
2.9
4.2
5.5
tOC4_11
4.0
5.8
7.6
tOC5_11
6.8
9.8
12.8
Unit
POWER OUTPUT TIMING HS0 TO HS1 (continued)
HS[0,1] Output Overcurrent Time Step for 28W bit = 1
OC[1:0] = 00 (slow by default)
OC[1:0] = 01 (fast)
OC[1:0] = 10 (medium)
OC[1:0] = 11 (very slow)
ms
tOC6_11
17.0
24.4
31.8
tOC7_11
124.8
178.4
232.0
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
tBC1_00
242
347
452
tBC2_00
126
181
236
tBC3_00
140
200
260
tBC4_00
158
226
294
tBC5_00
181
259
337
tBC6_00
211
302
393
tBC1_01
121
173
226
tBC2_01
63
90
118
tBC3_01
70
100
130
tBC4_01
79
113
147
tBC5_01
90
129
169
tBC6_01
105
151
197
tBC1_10
484
694
1904
tBC2_10
252
362
472
tBC3_10
280
400
520
tBC4_10
316
452
588
tBC5_10
362
518
674
tBC6_10
422
604
786
tBC1_00
291
417
542
tBC2_00
156
224
292
tBC3_00
178
255
332
tBC4_00
208
298
388
tBC5_00
251
359
467
tBC6_00
314
449
584
tBC1_01
146
209
272
tBC2_01
78
112
146
tBC3_01
88
127
166
tBC4_01
101
145
189
tBC5_01
126
180
234
tBC6_01
226
324
422
tBC1_10
583
834
1085
tBC2_10
312
448
582
tBC3_10
357
510
665
tBC4_10
417
596
775
tBC5_10
501
717
933
tBC6_10
628
898
1170
Unit
POWER OUTPUT TIMING HS0 TO HS1 (continued)
HS[0,1] Bulb Cooling Time Step for 28W bit = 0
CB[1:0] = 00 or 11 (medium)
CB[1:0] = 01 (fast)
ms
CB[1:0] = 10 (slow)
HS[0,1] for 28W bit = 1
CB[1:0] = 00 or 11 (medium)
CB[1:0] = 01 (fast)
CB[1:0] = 10 (slow)
07XSC200
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
PWM MODULE TIMING
Input PWM Clock Range on CLOCK
Input PWM Clock Low Frequency Detection Range on
fCLOCK
7.68
–
30.72
kHz
CLOCK(33)
fCLOCK(LOW)
1.0
2.0
4.0
kHz
(33)
fCLOCK(HIGH)
100
–
400
kHz
(32)
fPWM
31.25
–
781
Hz
AFPWM(CAL)
-10
–
+10
%
fPWM(0)
84
120
156
Hz
t CSB(MIN)
14
20
26
s
t CSB(MAX)
140
200
260
s
Input PWM Clock High Frequency Detection Range on CLOCK
Output PWM Frequency Range using external clock on CLOCK
Output PWM Frequency Accuracy using Calibrated
Oscillator(32)
Default Output PWM Frequency using Internal Oscillator
CSB Calibration Low Minimum Time Detection Range
CSB Calibration Low Maximum Tine Detection Range
(33)
Output PWM Duty Cycle Range for fPWM = 1.0 kHz for high speed slew rate
RPWM_1k
10
–
94
%
Output PWM Duty Cycle Range for fPWM = 400
Hz(33)
RPWM_400
6.0
–
98
%
Output PWM Duty Cycle Range for fPWM = 200
Hz(33)
RPWM_200
5.0
–
98
%
tIN
175
250
325
ms
tAUTO
105
150
195
ms
TOTWAR
110
125
140
°C
TFEED
1.15
1.20
1.25
V
DTFEED
-3.5
-3.7
-3.9
mV/°C
INPUT TIMING
Direct Input Toggle Time-out
AUTO-RETRY TIMING
Auto-retry Period
TEMPERATURE ON THE GND FLAG
Thermal Prewarning Detection(34)
Analog Temperature Feedback at TA = 25 °C with RCSNS = 2.5 k
Analog Temperature Feedback Derating with RCSNS = 2.5 k(35)
Notes
32. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].
33. The PWM ratio is measured at VHS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty cycle
100%) and fully-off (duty cycle 0%). For values outside this range, a calibration is needed between the PWM duty cycle programming
and the PWM on the output with RL = 5.0 resistive load.
34.
35.
Typical value guaranteed per design.
Value guaranteed per statistical analysis.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 20 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f SPI
–
–
8.0
MHz
t WRSTB
10
–
–
s
SPI INTERFACE CHARACTERISTICS(36)
Maximum Frequency of SPI Operation
Required Low State Duration for
RSTB(37)
Rising Edge of CSB to Falling Edge of CSB (Required Setup Time)
(38)
t CSB
–
–
1.0
s
(38)
t ENBL
–
–
5.0
s
Falling Edge of CSB to Rising Edge of SCLK (Required Setup
Time)(38)
t LEAD
–
–
500
ns
Required High State Duration of SCLK (Required Setup Time)
(38)
t WSCLKh
–
–
50
ns
(38)
t WSCLKl
–
–
50
ns
t LAG
–
–
60
ns
t SI (SU)
–
–
37
ns
t SI (HOLD)
–
–
49
ns
–
–
13
–
–
13
t RSI
–
–
13
ns
Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CSB (Required Setup
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup
(39)
Time)(39)
SO Rise Time
Time)(38)
t RSO
• CL = 80 pF
SO Fall Time
ns
t FSO
• CL = 80 pF
SI, CSB, SCLK, Incoming Signal Rise Time(39)
SI, CSB, SCLK, Incoming Signal Fall Time
(39)
ns
t FSI
–
–
13
ns
Time from Falling Edge of CSB to SO
Low-impedance(40)
t SO(EN)
–
–
60
ns
Time from Rising Edge of CSB to SO
High-impedance(41)
t SO(DIS)
–
–
60
ns
Notes
36.
37.
38.
39.
40.
41.
Parameters guaranteed by design.
RSTB low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 07XSC200 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double
pulsing.
Time required for output status data to be available for use at SO. 1.0 kon pull-up on CSB.
Time required for output status data to be terminated at SO. 1.0 kon pull-up on CSB.
07XSC200
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
3.4
Timing Diagrams
IN[0:1]
High logic level
Low logic level
Time
or
CSB
High logic level
Low logic level
Time
VHS[0:1]
VPWR
RPWM
50%VPWR
Time
t DLY(ON)
VHS[0:1]
70% VPWR
t DLY(OFF)
SR F
SR R
30% VPWR
Time
Figure 4. Output Slew Rate and Time Delays
IOCH1
IOCH2
Load
Current
IOC1
IOC2
IOC3
IOC4
IOCLO4
IOCLO3
IOCLO2
IOCLO1
Time
t OC1
t OC2
t OC3
t OC4
t OC5
t OC6
t OC7
Figure 5. Overcurrent Shutdown Protection
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
IOCH1
IOCH2
IOC1
IOC2
IOC3
IOC4
IOCLO4
IOCLO3
IOCLO2
IOCLO1
t BC3
tB C1
t BC2
t BC4
tB C5
Previous OFF duration
(tOFF)
tB C6
Figure 6. Bulb Cooling Management
VIH
VIH
RSTB
RSTB
10%
0.2
VDDVDD
tWRSTB
VIL
VIL
TwRSTB
tENBL
TCSB
t CSB
TENBL
VIH
VIH
90%
VDD
0.7VDD
CSB
CSB
0.7VDD
10%
VDD
t WSCLKH
TwSCLKh
tTlead
LEAD
VIL
VIL
t RSI
TrSI
t LAG
90%
VDD
0.7VDD
SCLK
SCLK
Tlag
VIH
VIH
10% VDD
0.2VDD
VIL
VIL
t SI(SU)
TSIsu
SI
SI
Don’t Care
90%
0.7 VDD
VDD
0.2VDD
10%
VDD
t WSCLKl
TwSCLKl
t SI(HOLD)
TSI(hold)
tTfSI
FSI
VIH
VIH
Valid
Don’t Care
Valid
Don’t Care
VIH
VIL
Figure 7. Input Timing Switching Characteristics
07XSC200
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
tFSI
tRSI
TrSI
TfSI
VOH
VOH
90%
VDD
3.5V
50%
SCLK
SCLK
1.0V VDD
10%
VOL
VOL
t SO(EN)
TdlyLH
SO
SO
90%
VDD
0.7 VDD
0.210%
VDDVDD
VOH
VOH
VOL
VOL
Low-to-High
Low
to High
TrSO
t RSO
VALID
tTVALID
SO
TfSO
t FSO
SO
VOH
VOH
VDD
VDD
High to Low 0.790%
High-to-Low
0.2VDD
10% VDD
TdlyHL
VOL
VOL
t SO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
4
Functional Description
4.1
Introduction
The 07XSC200 is one in a family of devices designed for low-voltage lighting applications. Its two low RDS(ON) MOSFETs (dual
7.0 m) can control two separate 55 W / 28 W bulbs and/or Xenon modules.
Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate
improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for
pulse-width modulation (PWM) control if desired. The 07XSC200 allows the user to program via the SPI, the fault current trip
levels and duration of acceptable lamp inrush. The device has fail-safe mode to provide fail-safe functionality of the outputs in
case of MCU damaged.
4.2
Functional Pin Description
4.2.1
Output Current Monitoring (CSNS)
The Current Sense pin provides a current proportional to the designated HS0 : HS1 output or a voltage proportional to the
temperature on the GND flag. That current is fed into a ground-referenced resistor (2.5 k typical) and its voltage is monitored
by an MCU's A/D. The output type is selected via the SPI. This pin can be tri-stated through the SPI.
4.2.2
Direct Inputs (IN0, IN1)
Each IN input wakes the device. The IN0 : IN1 high side input pins are also used to directly control HS0 : HS1 high side output
pins. If the outputs are controlled by PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with
CMOS levels, and they have a passive internal pull-down, RDWN.
4.2.3
Fault Status (FSB)
This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault
condition is detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin.
4.2.4
WAKE (WAKE)
The WAKE input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10 k
typ). This input has a passive internal pull-down, RDWN.
4.2.5
PWM Clock (CLOCK)
The clock input wakes the device. The PWM frequency and timing are generated from clock input by the PWM module. The clock
input frequency is the selectable factor 27 = 128. This input has a passive internal pull-down, RDWN.
4.2.6
RESET (RSTB)
The RESET input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the
device in a low-current sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin
has a passive internal pull-down, RDWN.
07XSC200
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.2.7
Chip Select (CSB)
The CSB pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is
capable of transferring information to, and receiving information from, the MCU. The 07XSC200 latches in data from the Input
Shift registers to the addressed registers on the rising edge of CSB. The device transfers status information from the power output
to the Shift register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from
a logic [1] to a logic [0] state only when SCLK is a logic [0]. CSB has an active internal pull-up from VDD, IUP.
4.2.8
Serial Clock (SCLK)
The SCLK pin clocks the internal shift registers of the 07XSC200 device. The serial input (SI) pin accepts data into the input shift
register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on
the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CSB makes any transition. For
this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CSB logic [1] state). SCLK
has an active internal pull-down. When CSB is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (highimpedance) (see Figure 10, page 26). SCLK input has an active internal pull-down, IDWN.
4.2.9
Serial Input (SI)
This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial
data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 07XSC200 are configured and
controlled using a 5-bit addressing scheme described in Table 9, page 36. Register addressing and configuration are described
in Tables 10, page 36. SI input has an active internal pull-down, IDWN.
4.2.10 Digital Drain Voltage (VDD)
This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device
goes to Fail-safe mode.
4.2.11 Ground (GND)
These pins are the ground for the device.
4.2.12 Positive Power Supply (VPWR)
This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the
backside surface mount tab of the package.
4.2.13 Serial Output (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin
is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the
key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting
descriptions are provided in Table 22, page 42.
4.2.14 High Side Outputs (HS0, HS1)
Protected 7.0 m high side power outputs to the load.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
4.2.15 Fail-safe Input (FSI)
This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog time-out
feature.
When the FSI pin is opened, the watchdog circuit is enabled. After a watchdog time-out occurs, the output states depends on
IN[0:1].
When the FSI pin is connected to GND, the watchdog circuit is disabled. The output states depends on IN[0:1] in case of VDD
Failure condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]).
4.3
Functional Internal Block Description
07XSC200 - Functional Block Diagram
Power Supply
MCU Interface & Output Control
Self-protected
High Side
Switches
HS0 - HS1
SPI Interface
Parallel Control Inputs
MCU
Interface
PWM Controller
Supply
MCU Interface & Output Control
Self-protected High Side Switches
Figure 9. Functional Block Diagram
4.3.1
Power Supply
The 07XSC200 is designed to operate from 4.0 to 28 V on the VPWR pin. Characteristics are provided from 6.0 to 20 V for the
device. The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for Serial
Peripheral Interface (SPI) communication to configure and diagnose the device. This IC architecture provides a low quiescent
current sleep mode. Applying VPWR and VDD to the device will place the device in the Normal mode. The device will transit to
Fail-safe mode in case of failures on the SPI or/and on VDD voltage.
4.3.2
High Side Switches: HS0–HS1
These pins are the high side outputs controlling lamps located for the front of vehicle, such as 65 W/55 W bulbs and Xenon-HID
modules. N-channel MOSFETs with 7.0 m RDS(ON) are self-protected and present extended diagnostics to detect bulb outage
and a short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive battery line.
When driving DC motor or solenoid loads demand multiple switching, an external recirculation device must be used to maintain
the device in its Safe Operating Area.
07XSC200
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.3.3
MCU Interface and Output Control
In Normal mode, each bulb is controlled directly from the MCU through the SPI. A pulse width modulation control module allows
improvement of lamp lifetime with bulb power regulation (PWM frequency range from 100 to 400 Hz) and addressing the dimming
application (day running light). An analog feedback output provides a current proportional to the load current or the temperature
of the board. The SPI is used to configure and to read the diagnostic status (faults) of high side outputs. The reported fault
conditions are: OpenLoad, short-circuit to battery, short-circuit to ground (overcurrent and severe short-circuit), thermal
shutdown, and under/overvoltage.
In Fail-safe mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
5
Functional Device Operation
5.1
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI),
Serial Output (SO), Serial Clock (SCLK), and Chip Select (CSB).
The SI / SO pins of the 07XSC200 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the
most significant bit (MSB) first. All inputs are compatible with 5.0 or 3.3 V CMOS logic levels.
CSB
CSB
CS
SCLK
SI
SO
D15
D14
D13
D12
D11
D10
D9
OD15 OD14 OD13 OD12 OD11 OD10 OD9
D8
OD8
D7
OD7
D6
OD6
D5
OD5
D4
D3
OD4
OD3
D2
OD2
D1
D0
OD1 OD0
Notes 1. RSTB is a logic [1] state during the above operation.
D15is: D0
to the
most
ordered entry of data into the device.
NOTES: 1. 2.RSTB
in arelate
logic H state
during
therecent
above operation.
OD15
: OD0
relate
thetofirst
16 bits
ofordered
ordered
fault
and status
data
out IC
of the device.
device.
2. 3.DO,
D1, D2,
... , and
D15to
relate
the most
recent
entry
of program
data into
the LUX
Figure 10. Single 16-Bit Word SPI Communication
5.2
Operational Modes
The 07XSC200 has four operating modes: Sleep, Normal, Fail-safe and Fault. Table 5 and Figure 12 summarize details
contained in succeeding paragraphs.
The Figure 11 describes an internal signal called IN_ON[x] depending on IN[x] input.
IN[x]
tIN
IN_ON[x]
Figure 11. IN_ON[x] internal signal
The 07XSC200 transits to operating modes according to the following signals:
• wake-up = RSTB or WAKE or IN_ON[0] or IN_ON[1] or CLOCK_ON,
• fail = (VDD Failure and VDD_FAIL_en) or (Watchdog time-out and FSI input not shorted to ground),
• fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis).
07XSC200
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 5. 07XSC200 Operating Modes
Mode
wake-up
fail
fault
Comments
Sleep
0
x
x
Device is in Sleep mode. All outputs are OFF.
Normal
1
0
0
Device is currently in Normal mode. Watchdog
is active if enabled.
Fail-safe
1
1
0
Device is currently in Fail-safe mode due to
watchdog time-out or VDD Failure conditions.
The output states are defined with the RFS
resistor connected to FSI.
Fault
1
X
1
Device is currently in fault mode. The faulted
output(s) is (are) OFF. The safe auto-retry
circuitry is active to turn-on again the output(s).
x = Don’t care.
(fail=0) and (wake-up=1) and (fault=0)
Sleep
(wake-up=0)
(wake-up=1) and
(fail=1)
and (fault=0)
(wake-up=1)
and (fault=1)
(wake-up=0)
(fail=1) and
(wake-up=1)
and (fault=1)
Fail-safe
Fault
(fail=1) and
(wake-up=1)
and (fault=0)
(wake-up=0)
(fail=0) and
(wake-up=1)
and (fault=1)
Normal
(fail=0) and
(wake-up=1)
and (fault=0)
(fail=0) and (wake-up=1) and (fault=0)
(fail=1) and (wake-up=1) and (fault=0)
Figure 12. Operating Modes
5.2.1
Sleep Mode
The 07XSC200 is in Sleep mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 0,
• fail = X,
• fault = X.
This is the Default mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state
of the device when the WAKE and RSTB, CLOCK_ON and IN_ON[0:1] are logic [0]. In the Sleep mode, the output and all unused
internal circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the
device are as if set to logic [0].
In the event of an external VPWR supply disconnect, an unexpected current consumption may sink on the VDD supply pin (In
Sleep state). This current leakage is about 70 mA instead of 5.0 µA and it may impact the device reliability. The device recovers
its normal operational mode once VPWR is reconnected.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
To avoid this unexpected current leakage on the VDD supply pin, maintain the device in Normal mode with RSTB pin set to
logic[1]. This will allow diagnosis of the battery disconnection event through UV fault reporting in SPI. Then, apply 0 V on the VDD
supply pin to switch the device to Sleep state.
5.2.2
Normal Mode
The 07XSC200 is in Normal mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = 0,
• fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:1] are under control, as defined by the hson signal:
hson[x] = (((IN[x] and DIR_dis[x]) or On bit[x]) and PWM_en) or (On bit [x] and Duty_cycle[x] and PWM_en).
In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below:
fault_control[x] = ((IN_ON[x] and DIR_dis[x]) and PWM_en) or (On bit [x]).
5.2.2.1
Programmable PWM Module
The outputs HS[0:1] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from CLOCK input pin or from the internal clock is the factor 27 (128) of the output PWM frequency
(CLOCK_sel bit). The outputs HS[0:1] can be controlled in the range of 5.0 to 98% with a resolution of 7 bits of duty cycle
(Table 6). The state of other IN pin is ignored.
Table 6. Output PWM Resolution
On bit
Duty cycle
Output state
0
X
OFF
1
0000000
PWM (1/128 duty cycle)
1
0000001
PWM (2/128 duty cycle)
1
0000010
PWM (3/128 duty cycle)
1
n
PWM ((n+1)/128 duty cycle)
1
1111111
fully ON
The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC
behavior of the light module (Table 7).
Table 7. Output PWM Switching Delay
Delay bits
Output delay
000
no delay
001
16 PWM clock periods
010
32 PWM clock periods
011
48 PWM clock periods
100
64 PWM clock periods
101
80 PWM clock periods
110
96 PWM clock periods
111
112 PWM clock periods
07XSC200
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
The clock frequency from CLOCK is permanently monitored in order to report a clock failure in case the frequency is out a
specified frequency range (from fCLOCK(LOW) to fCLOCK(HIGH)). In case of clock failure, no PWM feature is provided, the On bit
defines the outputs state and the CLOCK_fail bit reports [1].
5.2.2.2
Calibratable Internal Clock
The internal clock can vary as much as 30 percent corresponding to typical fPWM(0) output switching period.
Using the existing SPI inputs and the precision timing reference already available to the MCU, the 07XSC200 allows clock period
setting within 10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration
pulse is provided by the MCU. The pulse is sent on the CSB pin after the SPI word is launched. At the moment, the CSB pin
transitions from logic [1] to [0] until from logic [0] to [1] determines the period of internal clock with a multiplicative factor of 128.
CS
SI
CALR
SI command
ignored
Internal
clock duration
In case a negative CSB pulse is outside a predefined time range (from t CSB(MIN) to t CSB(MAX)), the calibration event will be ignored
and the internal clock will be unaltered or reset to the default value (fPWM(0)), if this was not calibrated before.
The calibratable clock is used, instead of the clock from CLOCK input, when CLOCK_sel is set to [1].
5.2.3
Fail-safe Mode
The 07XSC200 is in Fail-safe mode when:
• VPWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
• fault = 0.
5.2.3.1
Watchdog
If the FSI input is not grounded, the watchdog time-out detection is active when either the WAKE or IN_ON[0:1] or RSTB input
pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance
limiting the internal clamp current according to the specification.
The watchdog time-out is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled
within the minimum watchdog time-out period (WDTO), the device will operate normally.
5.2.3.2
Fail-safe Conditions
If an internal watchdog time-out occurs before the WD bit for FSI open (Table 8) or in case of VDD failure condition (VDD<
VDD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to logic [1]
(see fail-safe to normal mode transition paragraph) and VDD is within the normal voltage range.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
Table 8. SPI Watchdog Activation
Typical RFSI ()
Watchdog
0 (shorted to ground)
Disabled
(open)
Enable
During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default
value (except POR bit) and fault protections are fully operational.
The Fail-safe mode can be detected by monitoring the NM bit is set to [0].
5.2.4
Normal & Fail-safe Mode Transitions
Transition Fail-safe to Normal mode
To leave the Fail-safe mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit
set to logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (autoretry included).
Moreover, the device can be brought out of the Fail-safe mode due to watchdog time-out issue by forcing the FSI pin to logic [0].
Transition Normal to Fail-safe mode
To leave the Normal mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into
Fail-safe mode (auto-retry included).
5.2.5
Fault Mode
The 07XSC200 is in Fault mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = X,
• fault=1.
This device indicates the faults below as they occur by driving the FSB pin to logic [0] for RSTB input is pulled up:
• Overtemperature fault,
• Overcurrent fault,
• Severe short-circuit fault,
• Output(s) shorted to VPWR fault in OFF state,
• OpenLoad fault in OFF state,
• Overvoltage fault (enabled by default),
• Undervoltage fault.
The FSB pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit,
overtemperature and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled).
Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI
communication.
The OpenLoad fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x])
and the FS pin.
5.2.6
Start-up Sequence
The 07XSC200 enters in Normal mode after start-up if following sequence is provided:
• VPWR and VDD power supplies must be above their undervoltage thresholds,
• generate wake-up event (wake-up=1) from 0 to 1 on RSTB. The device switches to normal mode with SPI register content is
reset (as defined in Table 10 and Table 22). All features of the 07XSC200 will be available after 50 s typical, and all SPI
registers are set to default values (set to logic [0]).
• toggle WD bit from 0 to 1.
And, in case the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
07XSC200
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
• apply PWM clock on CLOCK input pin after maximum 200s (min. 50s).
If the correct start-up sequence is not provided, the PWM function is not guaranteed.
5.3
Protection and Diagnostic Features
5.3.1
Protections
Over-temperature Fault
The 07XSC200 incorporates over-temperature detection and shutdown circuitry for each output structure.
Two cases need to be considered when the output temperature is higher than TSD:
• If the output command is ON: the corresponding output is latched OFF. FSB will be also latched to logic [0]. To delatch the
fault and be able to turn ON again the outputs, the failure condition must disappear and the auto-retry circuitry must be active,
or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or
the VSUPPLY(POR) condition, if VDD = 0.
• If the output command is OFF: FSB will go to logic [0] till the corresponding output temperature are below TSD.
For both cases, the fault register OT[0:1] bit into the status register will be set to [1]. The fault bits will be cleared in the status
register after a SPI read command.
5.3.1.1
Overcurrent Fault
The 07XSC200 incorporates output shutdown in order to protect each output structure against resistive short-circuit condition.
This protection is composed by eight predefined current levels (time dependent) to fit Xenon-HID manners by default or, 55 W
or 28 W bulb profiles, selectable separately by Xenon bit and 28W bits (as illustrated Figure 14, page 39).
In the first turn-on, the lamp filament is cold and the current will be huge. fault_control signal transition from logic [0] to [1] or an
auto-retry define this event. In this case, the overcurrent protection will be fitted to inrush current, as shown in Figure 5. This
overcurrent protection is programmable: OC[1:0] bits select overcurrent slope speed and OCHI1 current step can be removed in
case the OCHI bit is set to [1].
Over-current thresholds
fault_control
hson
signal
hson
PWM
In Steady state, the wire harness will be protected by OCLO2 current level by default. Three other DC overcurrent levels are
available: OCLO1 or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits.
If the load current level ever reaches the overcurrent detection level, the corresponding output will latch the output OFF and FSB
will be also latched to logic [0]. To delatch the fault and be able to turn ON again the corresponding output, the failure condition
must disappear and the auto-retry circuitry must be active or the corresponding output must be commanded OFF and then ON
(toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
The SPI fault report (OC[0:1] bits) is removed after a read operation.
In Normal mode using internal PWM module, the 07XSC200 incorporates also a cooling bulb filament management if OC_mode
and Xenon are set to logic [1]. In this case, the firstt step of multi-step overcurrent protection will depend to the previous OFF
duration, as illustrated in Figure 6. The following figure illustrates the current level will be used in function to the duration of
previous OFF state (toff). The slope of cooling bulb emulator is configurable with OCOFFCB[1:0] bits.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
Depending on toff
depending to toff
Over-current thresholds
Cooling
toff
fault_control
hson
signal
hson
PWM
5.3.1.2
Severe Short-circuit Fault
The 07XSC200 provides output shutdown to protect each output in case of a severe short-circuit during of the output switching.
If the short-circuit impedance is below RSHORT, the device will latch the output OFF, FSB will go to logic [0] and the fault register
SC[0:1] bit will be set to [1]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear
and the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or
VSUPPLY(POR) condition if VDD = 0.
The SPI fault report (SC[0:1] bits) is removed after a read operation.
5.3.1.3
Overvoltage Fault (Enabled by Default)
By default, the overvoltage protection is enabled. The 07XSC200 shuts down all outputs and FSB will go to logic [0] during an
overvoltage fault condition on the VPWR pin (VPWR > VPWR(OV)). The outputs remain in the OFF state until the overvoltage
condition is removed (VPWR < VPWR(OV) - VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and
cleared after either a valid SPI read.
The overvoltage protection can be disabled through the SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any
overvoltage condition (VPWR > VPWR(OV)). This overvoltage diagnosis, as a warning, is removed after a read operation, if the fault
condition disappears. The HS[0:1] outputs are not commanded in RDS(ON) above the OV threshold.
5.3.1.4
Undervoltage Fault
The output(s) will latch off at some battery voltage below VPWR(UV). As long as the VDD level stays within the normal specified
range, the internal logic states within the device will remain (configuration and reporting).
In the case where battery voltage drops below the undervoltage threshold (VPWR < VPWR(UV)), the outputs will turn off, FSB will
go to logic [0], and the fault register UV bit will be set to [1].
Two cases need to be considered when the battery level recovers (VPWR > VPWR(UV)_UP):
• If outputs command are low, FSB will go to logic [1] but the UV bit will remain set to 1 until the next read operation (warning
report).
• If the output command is ON, FSB will remain at logic [0]. To delatch the fault and be able to turn ON again the outputs, the
failure condition must disappear and the auto-retry circuitry must be active or the corresponding output must be commanded
OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when
VPWR was within the normal voltage range, are guaranteed if VDD is within the operational voltage range or until VSUPPLY(POR) if
VDD = 0. Any new OT fault is detected (VDD failure included) and reported through SPI above VPWR(UV). The output state is
not changed as long as the VPWR voltage does not drop any lower than 3.5 V typical.
All latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if:
• VDD < VDD(FAIL) with VPWR in nominal voltage range,
• VDD and VPWR supplies is below VSUPPLY(POR) voltage value.
07XSC200
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
(fault_control=0)
(OpenloadOFF=1
or ShortVpwr=1
or OV=1)
(fault_control=1 and OV=0)
OFF
if hson=0
ON
(fault_control=0 or OV=1)
(fault_control=0)
(OpenloadOFF=1
or ShortVpwr=1
or OV=1)
(OpenloadON=1)
(SC=1)
if hson=1
(Retry=1)
Latched
OFF
(count=16)
(SC=1)
(OpenloadON=1)
(after Retry Period and OV=0)
Auto-retry
(OV=1)
OFF
Auto-retry
ON
if hson=1
(OpenloadOFF=1
or ShortVpwr=1
or OV=1)
(Retry=1)
=> count=count+1
(fault_control=0)
Figure 13. Auto-retry State Machine
5.3.2
Auto-retry
The auto-retry circuitry is used to reactivate the output(s) automatically in case of overcurrent or overtemperature or undervoltage
failure conditions to provide a high availability of the load.
Auto-retry feature is available in Fault mode. It is activated in case of internal retry signal is set to logic [1]:
retry[x] = OC[x] or OT[x] or UV.
The feature retries to switch-on the output(s) after one auto-retry period (tAUTO) with a limitation in term of number of occurrence
(16 for each output). The counter of retry occurrences is reset in case of Fail-safe to Normal or Normal to Fail-safe mode
transitions. At each auto-retry, the overcurrent detection will be set to default values in order to sustain the inrush current.
The Figure 13 describes the auto-retry state machine.
5.3.3
Diagnostic
Output Shorted to VPWR Fault
The 07XSC200 incorporates output shorted to VPWR detection circuitry in OFF state. Output shorted to VPWR fault is detected if
output voltage is higher than VOSD(THRES) and reported as a fault condition when the output is disabled (OFF). The output shorted
to VPWR fault is latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The
OS[0:1] and OL_OFF[0:1] fault bits are set in the status register and FSB pin reports in real time the fault. If the output shorted
to VPWR fault is removed, the status register will be cleared after reading the register.
The open output shorted to VPWR protection can be disabled through SPI (OS_DIS[0:1] bit).
OpenLoad Faults
The 07XSC200 incorporates three dedicated OpenLoad detection circuitries on the output to detect in OFF and in ON state.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
5.3.3.1
OpenLoad Detection in Off State
The OFF output OpenLoad fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current
source (IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output OpenLoad fault is latched
into the status register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:1] fault bit
is set in the status register. If the OpenLoad fault is removed (FSB output pin goes to high), the status register will be cleared
after reading the register.
The OFF output OpenLoad protection can be disabled through SPI (OLOFF_DIS[0:1] bit).
5.3.3.2
OpenLoad Detection in On State
The ON output OpenLoad current thresholds can be chosen by the SPI to detect a standard bulbs or LEDs (OLLED[0:1] bit set
to logic [1]). In the case where load current drops below the defined current threshold OLON bit is set to logic [1], the output stays
ON and FSB is not disturbed.
5.3.3.3
OpenLoad Detection in On State For Led
OpenLoad for LEDs only (OLLED[0:1] set to logic [1]) is detected periodically each t OLLED (fully-on, D[6:0]=7F). To detect OLLED
in fully-on state, the output must be ON at least t OLLED.
To delatch the diagnosis, the condition should be removed and the SPI read operation is needed (OL_ON[0:1] bit). The ON output
open-load protection can be disabled through the SPI (OLON_DIS[0:1] bit).
5.3.3.4
Analog Current Recopy and Temperature Feedbacks
The CSNS pin is an analog output reporting a current proportional to the designed output current or a voltage proportional to the
temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s
bits).
In case the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot.
The maximum current is 2.0 mA, typical. The typical value of external CSNS resistor connected to the ground is 2.5 k.
The current recopy is not active in Fail-safe mode.
5.3.3.5
Temperature Prewarning Detection
In Normal mode, the 07XSC200 provides a temperature prewarning reported via the SPI, in case the temperature of the GND
flag is higher than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI
command is needed.
5.3.4
Active Clamp ON VPWR
The device provides an active gate clamp circuit in order to limit the maximum transient VPWR voltage at VPWR(CLAMP). In case
of an overload on an output, the corresponding output is turned off, which leads to high voltage at VPWR with an inductive VPWR
line. When the VPWR voltage exceeds VPWR(CLAMP) threshold, the turn-off on the corresponding output is deactivated and all
HS[0:1] outputs are switched ON automatically to demagnetize the inductive battery line.
5.3.5
Reverse Battery on VPWR
The output survives the application of reverse voltage as low as -18 V. Under these conditions, the ON resistance of the output
is two times higher than a typical ohmic value in forward mode. No additional passive components are required except on the
VDD current path.
07XSC200
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
5.3.6
Ground Disconnect Protection
In the event the 07XSC200 ground is disconnected from load ground, the device protects itself and safely turns OFF the output,
regardless of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 k resistor needs to be added
between the MCU and each digital input pin to ensure the device turns off, during a ground disconnect and to prevent this pin
from exceeding maximum ratings.
5.3.7
5.3.7.1
Loss of Supply Lines
Loss of VDD
If the external VDD supply is disconnected (or not within specification: VDD < VDD(FAIL), with the VDD_FAIL_en bit set to logic [1]),
all SPI register content is reset.
The outputs can still be driven by the direct inputs IN[0 : 1] if VPWR is within specified voltage range. The 07XSC200 uses the
battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing Fail-safe device
operation with no VDD supplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF
OpenLoad circuitry are fully operational, with default values corresponding to all SPI bits are set to logic [0]. No current is
conducted from VPWR to VDD.
5.3.7.2
Loss of VPWR
If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features
are provided for RSTB to set to logic [1] under VDD in nominal conditions. This fault condition can be diagnosed with UV fault in
SPI STATR_s registers. The SPI pull-up and pull-down current sources are not operational. The previous device configuration
is maintained. No current is conducted from VDD to VPWR.
5.3.7.3
Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < VSUPPLY(POR)), all SPI
register contents are reset, with default values corresponding to all SPI bits set to logic [0] and all latched faults reset.
5.3.8
EMC Performances
All following tests are performed on the Freescale evaluation board in accordance with the typical application schematic.
The device is protected in the event of positive and negative transients on the VPWR line (per ISO 7637-2).
The 07XSC200 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level
for immunity tests.
5.4
Logic Commands and Registers
5.4.1
Serial Input Communication
SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15
and ending with the LSB, D0 (Table 9). Each incoming command message on the SI pin can be interpreted using the following
bit assignments: the MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bit D13. The next four
bits, D14 -D12: D10, are used to select the command register. The remaining nine bits, D8 : D0, are used to configure and control
the outputs and their protection features.
Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to
confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is
not 16 bits will be ignored.
The 07XSC200 has defined registers, which are used to configure the device and to control the state of the outputs. Table 10
summarizes the SI registers.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
Table 9. SI Message Bit Assignment
Bit Sig
SI Msg Bit
Message Bit Description
MSB
D15
Watchdog in: toggled to satisfy watchdog requirements.
D13
Register address bit used in some cases for output selection (Table 11).
D14, D12 : D10
Not used (set to logic [0]).
D9
LSB
Register address bits.
Used to configure the inputs, outputs, and the device protection features and SO status content.
D8:D0
Table 10. Serial Input Address and Configuration Bit Map
SI
Register D15 D1 D1 D1 D1 D1 D9
4 3 2 1 0
SI Data
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
SOA4
SOA3
SOA2
SOA1
SOA0
ON_s
PWM6_s
PWM3_s
PWM2_s
PWM1_s
PWM0_s
0
STATR_ WDI X
s
N
X
0
0
0
0
PWMR_ WDI 1
s
N
A
0
0
1
0 28W_s
CONFR WDI 1
0_s
N
A
0
1
0
0
0
0
CONFR WDI 1
1_s
N
A
0
1
1
0
0
0
OCR_s WDI 1
N
A
1
0
0
0
Xenon
_s
VDD_ PWM_en CLOCK_s TEMP_en CSNS_e
el
n
FAIL_
en
Retry_
unlimited_
s
BC1_s
BC0_s
PWM5_s PWM4_s
DIR_dis_
s
SR1_s
SR0_s
DELAY2_s DELAY1_ DELAY0_
s
s
Retry_dis OS_dis_s OLON_dis OLOFF_di OLLED_e CSNS_rati
_s
_s
s_s
n_s
o_s
OC1_s
OC0_s
OCHI_s
OLCO1_s
OLCO0_ OC_mode
s
_s
CSNS1
CSNS0
X
OV_dis
GCR
WDI 0
N
0
1
0
1
0
CALR
WDI 0
N
0
1
1
1
0
1
0
1
0
1
1
0
1
1
0
X
X
X
0
0
0
0
0
0
0
0
0
0
Register
state
after
RST=0
or
VDD(FAIL)
or
VSUPPLY
0
0
(POR)
condition
x = Don’t care.
s = Output selection with the bit A as defined in Table 11.
07XSC200
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
5.4.2
Device Register Addressing
The following section describes the possible register addresses (D[14:10]) and their impact on device operation.
5.4.2.1
Address XX000 — Status Register (STATR_s)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device
operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to
the device status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR
and CALR registers (Refer to Serial Output Communication (Device Status Return Data).
5.4.2.2
Address A1A0001— Output PWM Control Register (PWMR_s)
The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is
independently selected for configuration based on the state of the D13 bit (Table 11).
Table 11. Output Selection
A (D13)
HS Selection
0
HS0 (default)
1
HS1
A logic [1] on bit D8 (28W_s) selects the 28 W overcurrent protection profile: the overcurrent thresholds are divided by 2, and the
inrush and cooling responses are dedicated to 28 W lamps for HS[0,1] outputs.
Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also
pulled down). Bits D6:D0 set the output PWM duty cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 6.
5.4.2.3
Address A1A0010— Output Configuration Register (CONFR0_S)
The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output “s” is
independently selected for configuration based on the state of the D14 : D13 bits (Table 11).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D5 will disable
the output from direct control (in this case, the output is only controlled by the On bit).
D4:D3 bits (SR1_s and SR0_s) are used to select the high or medium or low speed slew rate for the selected output, the default
value [00] corresponds to the medium speed slew rate (Table 12).
Table 12. Slew Rate Speed Selection
SR1_s (D4)
SR0_s (D3)
Slew Rate Speed
0
0
medium (default)
0
1
low
1
0
high
1
1
Not used
Incoming message bits D2 : D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as
shown Table 7, (only available for PWM_en bit is set to logic [1]).
5.4.2.4
Address A1A0011 — Output Configuration Register (CONFR1_s)
The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output “s”
is independently selected for configuration based on the state of the D14 : D13 bits (Table 11).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the auto-retry counter for the selected output, the default value [0]
corresponds to enable auto-retry feature with time limitation.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
A logic [1] on bit D5 (RETRY_dis_s) disables the auto-retry for the selected output, the default value [0] corresponds to enable
this feature.
A logic [1] on bit D4 (OS_dis_s) disables the output hard shorted to VPWR protection for the selected output, the default value [0]
corresponds to enable this feature.
A logic [1] on bit D3 (OLON_dis_s) disables the ON output OpenLoad detection for the selected output, the default value [0]
corresponds to enable this feature (Table 13).
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF output OpenLoad detection for the selected output, the default value [0]
corresponds to enable this feature.
A logic [1] on bit D1 (OLLED_en_s) enables the ON output OpenLoad detection for LEDs for the selected output, the default value
[0] corresponds to ON output OpenLoad detection is set for bulbs (Table 13).
Table 13. ON OpenLoad Selection
OLON_dis_s (D3)
OLLED_en_s
(D1)
0
0
enable with bulb
threshold (default)
0
1
enable with LED
threshold
1
X
disable
ON OpenLoad detection
A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio on the CSNS pin for the corresponding output. The default value [0] is
the low ratio (Table 14).
Table 14. Current Sense Ratio Selection
5.4.2.5
CSNS_high_s (D0)
Current Sense Ratio
0
CRS0 (default)
1
CRS1
Address A1A0100 — Output Overcurrent Register (OCR)
The OCR_s register allows the MCU to configure corresponding output overcurrent protection through the SPI. Each output “s”
is independently selected for configuration based on the state of the D14 : D13 bits (Table 11).
A logic [1] on bit D8 (Xenon_s) disables enables the Xenon 55 W or 28 W bulb overcurrent profile, as described Figure 14.
07XSC200
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
Xenon bit set to logic [0]:
IOCH1
IOCH2
IOC1
IOC2
IOCLO4
IOCLO3
IOCLO2
IOCLO1
t OC1
t OC3 t OC4 t OC5
t OC2
t OC6
Time
t OC7
Xenon bit set to logic [1]:
IOCH1
IOCH2
IOC1
IOC2
IOC3
IOC4
IOCL4
IOCL3
IOCL2
IOCL1
t OC1 t OC3 t OC4 t OC5
t OC2
t OC6
Time
t OC7
Figure 14. Overcurrent Profile Depending on Xenon bit
D[7:6] bits allow to MCU to programmable bulb cooling curve and D[5:4] bits inrush curve for selected output, as shown Table 15
and Table 16.
Table 15. Cooling Curve Selection
BC1_s (D7)
BC0_s (D6)
Profile Curves Speed
0
0
medium (default)
0
1
slow
1
0
fast
1
1
medium
Table 16. Inrush Curve Selection
OC1_s (D5)
OC0_s (D4)
Profile Curves Speed
0
0
slow (default)
0
1
fast
1
0
medium
1
1
very slow
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during tOC1, as shown Figure 15.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
IOCH1
IOCH2
IOC1
IOC2
IOC3
IOC4
IOCL4
IOCL3
IOCL2
IOCL1
t OC1 t OC3 t OC4 t OC5
t OC2
t OC6
t OC7
Time
Figure 15. Overcurrent Profile with OCHI bit set to ‘1’
The wire harness is protected by one of four possible current levels in steady state, as defined in Table 17.
Table 17. Output Steady State Selection
OCLO1 (D2) OCLO0 (D1)
Steady State Current
0
0
OCLO2 (default)
0
1
OCLO3
1
0
OCLO4
1
1
OCLO1
Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 18.
Table 18. Overcurrent Mode Selection
OC_mode_s (D0)
Overcurrent Mode
0
only inrush current management (default)
1
inrush current and bulb cooling
management
Address 00101 — GLObal configuration regIster (GCR)
The GCR register allows the MCU to configure the device through the SPI.
Bit D8 allows the MCU to enable or disable the VDD failure detector. A logic [1] on VDD_FAIL_en bit allows switch of the outputs
HS[0:1] with PWMR register device in Fail-safe mode in case of VDD < VDD(FAIL).
Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:1]
with PWMR register (the direct input states are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 19.
Table 19. PWM Module Selection
PWM_en (D7) CLOCK_sel (D6)
PWM module
0
X
PWM module disabled (default)
1
0
PWM module enabled with external
clock from CLOCK
1
1
PWM module enabled with
internal calibrated clock
Bits D5:D4 allow the MCU to select one of two analog feedback on CSNS output pin, as shown in Table 20.
07XSC200
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 20. CSNS Reporting Selection
TEMP_en (D5) CSNS_en (D4)
CSNS reporting
0
0
CSNS tri-stated (default)
X
1
current recopy of selected output (D3:2]
bits)
1
0
temperature on GND flag
Table 21. Output Current Recopy Selection
CSNS1 (D3)
CSNS0 (D2)
CSNS reporting
1
0
HS0
1
1
HS1
The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value).
5.4.2.6
Address 00111 — Calibration Register (CALR)
The CALR register allows the MCU to calibrate internal clock, as explained in Figure 13.
5.4.3
Serial Output Communication (Device Status Return Data)
When the CSB pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new
message data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a CSB transition, is
dependent upon the previously written SPI word.
Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked
into the SI pin since the CSB pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as
message verification.
A valid message length is determined following a CSB transition of [0] to [1]. If there is a valid message length, the data is latched
into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault
status register is now able to accept new fault status information.
SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4,
OD3, OD2, OD1, and OD0. The value of the previous bit SOA3 will determine which output the SO information applies to for the
registers which are output specific; viz., Fault, PWMR, CONFR0, CONFR1, and OCR registers.
Note that the SO data will continue to reflect the information for each output that was selected during the most recent STATR
write until changed with an updated STATR write.
The output status register correctly reflects the status of the STATR-selected register data at the time that the CSB is pulled to a
logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following
exception:
• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid
SPI communication never occurred
• The VPWR voltage is below 4.0 V, the status must be ignored by the MCU
5.4.4
Serial Output Bit Assignment
The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 22,
summarizes SO returned data for bits OD15 : OD0.
•
•
•
•
Bit OD15 is the MSB; it reflects the state of the watchdog bit from the previously clocked-in message
Bits OD14:OD10 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message
Bit OD9 is set to logic [1] in Normal mode (NM)
The contents of bits OD8 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained
in the paragraphs following Table 22
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
Table 22. Serial Output Bit Map Description
Previous
STATR
SO Returned Data
S
O
A
4
S
O
A
3
S
O
A
2
S
O
A
1
S
O OD OD OD OD OD OD O
OD8 OD7
A 15 14 13 12 11 10 D9
0
STATR
1
_s
A
0
0
0
WDI SO SOA SOA SO
N
A4
3
2
A1
SO
A0
N
M
POR
PWMR
_s
1
A
0
0
1
WDI SO SOA SOA SO
N
A4
3
2
A1
SO
A0
N
M
28W ON_ PWM
_s
s
6_s
CONF
R0_s
1
A
0
1
0
WDI SO SOA SOA SO
N
A4
3
2
A1
SO
A0
N
M
X
X
CONF
R1_s
1
A
0
1
1
WDI SO SOA SOA SO
N
A4
3
2
A1
SO
A0
N
M
X
X
OCR_s 1
GCR
0
A
0
1
1
UV
OD6
OD5
OD4
OD3
OD2
OD1
OD0
OV
OLON
_s
OLOF
F_s
OS_s
OT_s
SC_s
OC_s
PWM PWM
5_s
4_s
PWM3_s
PWM2_s
DIR_d SR1_
is_s
s
SR0_s
X
PWM1_s PWM0_s
DELAY2_s DELAY1 DELAY0
_s
_s
Retry_ Retry_ OS_di OLON_dis OLOFF_dis OLLED_ CSNS_r
_s
_s
en_s
atio_s
unlimit dis_s s_s
ed_s
BC0_ OC1_ OC0_
s
s
s
OCHI_s
OCLO1_s
VDD PW CLOC TEMP CSNS
_en
_en
CSNS1
CSNS0
X
OV_dis
0
0
WDI SO SOA SOA SO
N
A4
3
2
A1
SO
A0
N Xeno BC1
M n_s
_s
0
WDI SO SOA SOA SO
1
N
A4
3
2
A1
SO
A0
N _FAI M_e K_sel
M L_e
n
OCLO0_ OC_mod
s
e_s
n
DIAGR
0
0
0
1
1
1
WDI SO SOA SOA SO
N
A4
3
2
A1
SO
A0
N
M
X
X
X
X
X
X
CLOCK_fail
CAL_fail
OTW
DIAGR
1
0
1
1
1
1
WDI SO SOA SOA SO
N
A4
3
2
A1
SO
A0
N
M
X
X
X
X
IN1
IN0
X
X
WD_en
DIAGR
2
1
0
1
1
1
WDI SO SOA SOA SO
N
A4
3
2
A1
SO
A0
N
M
X
X
X
X
X
X
0
1
0
0
0
0
0
Regist
er
state
after
RST=
0 or
N/ N/ N/ N/ N/
VDD(F A A A A A
AIL) or
VSUPP
0
0
0
0
0
0
0
X
0
0
0
0
LY(POR
)
conditi
on
s = Output selection with the bit A as defined in Table 11
5.4.4.1
Previous Address SOA4 : SOA0 = 1A000 (STATR_s)
The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (VSUPPLY(POR)). This bit is only reset by
a read operation.
Bits OD7: OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits
SOA3 = A (Table 22).
• OC_s: overcurrent fault detection for a selected output,
• SC_s: severe short-circuit fault detection for a selected output,
• OS_s: output shorted to VPWR fault detection for a selected output,
• OLOFF_s: OpenLoad in OFF state fault detection for a selected output,
07XSC200
42
Analog Integrated Circuit Device Data
Freescale Semiconductor
• OLON_s: OpenLoad in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output,
• OV: overvoltage fault detection,
• UV: undervoltage fault detection
• POR: power on reset detection.
The FSB pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal).
5.4.4.2
Previous Address SOA4 : SOA0 = 1A001 (Pwmr_s)
The returned data contains the programmed values in the PWMR register for the output selected with A.
5.4.4.3
Previous Address SOA4 : SOA0 = 1A010 (confr0_s)
The returned data contains the programmed values in the CONFR0 register for the output selected with A.
5.4.4.4
Previous Address SOA4 : SOA0 = 1A011 (confr1_s)
The returned data contains the programmed values in the CONFR1 register for the output selected with A.
5.4.4.5
Previous Address SOA4 : SOA0 = 1A100 (ocr_s)
The returned data contains the programmed values in the OCR register for the output selected with A.
5.4.4.6
Previous Address SOA4 : SOA0 = 00101 (gcr)
The returned data contains the programmed values in the GCR register.
5.4.4.7
Previous Address SOA4 : SOA0 = 00111 (diagr0)
The returned data OD2 reports logic [1] in case of PWM clock on CLOCK pin is out of specified frequency range.
The returned data OD1 reports logic [1] in case of calibration failure.
The returned data OD0 reports logic [1] in case of overtemperature prewarning (temperature of GND flag is above TOTWAR).
5.4.4.8
Previous Address SOA4 : SOA0 = 01111 (diagr1)
The returned data OD4: OD3 report in real time the state of the direct input IN[1:0].
The OD0 indicates if the watchdog is enabled (set to logic [1]) or not (set to logic [0]). OD4:OD1 report the output state in case
of Fail-safe state due to watchdog time-out as explained in the following Table 23.
Table 23. Watchdog activation report
5.4.4.9
WD_en (OD0)
SPI Watchdog
0
disabled
1
enabled
Previous Address SOA4 : SOA0 = 10111 (diagr2)
The returned data is the product ID. Bits OD2:OD0 are set to 010 for Protected Dual 7.0 m high side Switches.
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
5.4.4.10
Default Device Configuration
The default device configuration is explained by the following:
• HS output is commanded by the corresponding IN input or On bit through the SPI. The medium slew-rate is used,
• HS output is fully protected by the Xenon overcurrent profile by default, the severe short-circuit protection, the undervoltage
and the overtemperature protection. The auto-retry feature is enabled,
• OpenLoad in ON and OFF state and HS shorted to VPWR detections are available,
• No current recopy and no analog temperature feedback active,
• Overvoltage protection is enabled,
• SO reporting fault status must be ignored,
• VDD failure detection is disabled.
07XSC200
44
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
Typical Applications
The following figure shows a typical lighting application (only one vehicle corner) using an external PWM clock from the main
MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe
condition.
It is recommended to locate a 22 nF decoupling capacitor to the module connector.
VPWR
VDD
Voltage regulator
100 nF
10 µF
100 nF
VDD
10 µF
VPWR
ignition
switch
VDD
10 k
VPWR
VDD
VPWR
VDD
10 k
100 nF
100 nF
100 nF
VDD
WAKE
I/O
FSB
CLOCK
IN0
IN1
10 k
I/O
MCU
SCLK
CSB
I/O
SO
SI
22 nF
LOAD 0
SPDL07 SOIC
10 k
10 k
10 k
10 k
A/D
HS0
SCLK
CSB
RSTB
SI
SO
CSNS
FSI
10 k
22 nF
HS1
22 nF
LOAD 1
GND
2.5 k
VPWR
Watchdog
direct light commands (pedal, comodo,...)
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
7
Packaging
7.1
Soldering Information
The 07XSC200 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board.
The 07XSC200 was qualified in accordance with JEDEC standards J-STD-020C Pb-Free reflow profile. The maximum peak
temperature during the soldering process should not exceed 260 °C for 40 seconds maximum duration.
07XSC200
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
7.2
Package Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to
www.freescale.com and perform a keyword search for the drawing’s document number.
Package
Suffix
32-Pin SOICW
EK
Package Outline Drawing Number
98ASA00368D
EK SUFFIX
32-PIN SOICW
98ASA00368D
REV. 0
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
EK SUFFIX
32-PIN SOICW
98ASA00368D
REV. 0
07XSC200
48
Analog Integrated Circuit Device Data
Freescale Semiconductor
EK SUFFIX
32-PIN SOICW
98ASA00368D
REV. 0
07XSC200
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
8
Revision History
Revision
Date
Description of Changes
1.0
8/2013
•
Initial release based on MC07XS3200 data sheet.
2.0
9/2013
•
Added the note “To achieve high reliability over 10 years of continuous operation, the device's
continuous operating junction temperature should not exceed 125C.” to Operating Temperature
07XSC200
50
Analog Integrated Circuit Device Data
Freescale Semiconductor
How to Reach Us:
Information in this document is provided solely to enable system and software implementers to use Freescale products.
Home Page:
freescale.com
There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based
Web Support:
freescale.com/support
Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no
on the information in this document.
warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by
customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.
Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:
freescale.com/SalesTermsandConditions.
Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2013 Freescale Semiconductor, Inc.
Document Number: MC07XSC200
Rev. 2.0
9/2013