V6211619 VID

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
RICK OFFICER
Original date of drawing
YY-MM-DD
CHECKED BY
RAJESH PITHADIA
11-12-01
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DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
TITLE
MICROCIRCUIT, LINEAR, NEGATIVE VOLTAGE
REGULATOR, MONOLITHIC SILICON
APPROVED BY
CHARLES F. SAFFLE
SIZE
AMSC N/A
3
CODE IDENT. NO.
DWG NO.
V62/11619
16236
PAGE
1
OF
11
5962-V089-11
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance negative voltage regulator microcircuit, with an
operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/11619
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
Circuit function
01
TPS7A3001-EP
Negative voltage regulator
1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter
Number of pins
X
8
JEDEC PUB 95
Package style
MO-187-AA-T
Plastic small outline with thermal pad
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
2
1.3 Absolute maximum ratings.
1/
Voltage :
IN pin to GND pin ...................................................................................................
OUT pin to GND pin ...............................................................................................
OUT pin to IN pin ...................................................................................................
FB pin to GND pin ..................................................................................................
FB pin to IN pin ......................................................................................................
EN pin to IN pin ......................................................................................................
EN pin to GND pin ..................................................................................................
NR/SS pin to IN pin ................................................................................................
NR/SS pin to GND pin ............................................................................................
Peak output current ....................................................................................................
Operating virtual junction temperature (TJ) ................................................................
-36 V to +0.3 V
-33 V to +0.3 V
-0.3 V to +36 V
-2 V to +0.3 V
-0.3 V to +36 V
-0.3 V to +36 V
-36 V to +36 V
-0.3 V to +36 V
-2 V to +0.3 V
Internally limited
-55C to +135C
Storage temperature range (TSTG) ............................................................................ -65C to +150C
Electrostatic discharge (ESD) rating:
Human body model (HBM) ..................................................................................... 1500 V
Charged device model (CDM) ................................................................................ 500 V
1.4 Recommended operating conditions. 2/
Operating junction temperature range (TJ) ................................................................ -55C to +125C
1.5 Thermal characteristics.
Thermal metric
Symbol
Case X
Unit
JA
69.3
C/W
Thermal resistance, junction-to-case (top)
JC(TOP)
40.3
C/W
Characterization parameter, junction-to-top
JT
2.4
C/W
Characterization parameter, junction-to-board
JB
38.7
C/W
Thermal resistance, junction-to-ambient
1/
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2/
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
3
2. APPLICABLE DOCUMENTS
JEDEC PUB 95
–
Registered and Standard Outlines for Semiconductor Devices
(Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107
or online at http://www.jedec.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Conditions 2/ 3/
Device
type
Limits
Unit
Min
Max
-55C to +125C
01
-36.0
-3.0
V
+25 C
01
-1.22
-1.142
V
|VIN|  | VOUT(NOM) | + 1.0 V
-55C to +125C
01
-33.0
VREF
V
VOUT
|VIN| = | VOUT(NOM) | + 0.5 V
+25 C
01
-1.5
+1.5
%VOUT
VOUT
| VOUT(NOM) | + 1.0 V  |VIN|  35 V,
-55C to +125C
01
-2.85
+2.85
%VOUT
Input voltage range
VIN
Internal reference
VREF
VNR/SS = VREF
Output voltage
range
VOUT
Nominal accuracy
Overall accuracy
4/
Temperature,
TJ
1 mA  IOUT  200 mA
Line regulation
VRLINE
| VOUT(NOM) | + 1.0 V  |VIN|  35 V,
+25 C
01
0.14 typical
%VOUT
Load regulation
VRLOAD
1 mA  IOUT  200 mA
+25 C
01
0.04 typical
%VOUT
Dropout voltage
|VDO|
VIN = 95% VOUT(NOM),
-55C to +125C
01
216 typical
mV
IOUT = 100 mA
600
VIN = 95% VOUT(NOM),
IOUT = 200 mA
Current limit
ILIM
VOUT = 90% VOUT(NOM)
-55C to +125C
01
Ground current
IGND
IOUT = 0 mA
-55C to +125C
01
220
|ISHDN|
-55C to +125C
VEN = +0.4 V
01
5/
Enable current
IFB
|IEN|
100
A
A
3.0
3.0
VEN = -0.4 V
Feedback
current
mA
950 typical
IOUT = 100 mA
Shutdown supply
current
500
VEN = |VIN| = | VOUT(NOM) | + 1.0 V
-55C to +125C
01
100
nA
-55C to +125C
01
1.0
A
VIN = VEN = -35 V
1.0
VIN = -35 V, VEN = +15 V
1.2
See footnotes at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
5
TABLE I. Electrical performance characteristics – Continued. 1/
Test
Positive enable high
level voltage
Symbol
Conditions 2/ 3/
Temperature,
TA
-55C to +125C
V+EN_HI
Device
type
01
-55C to +85C
Limits
Unit
Min
Max
+2.0
+15
+1.8
+15
V
Positive enable low
level voltage
V+EN_LO
-55C to +125C
01
0
+0.4
V
Negative enable high
level voltage
V-EN_HI
-55C to +125C
01
VIN
-2.0
V
Negative enable low
level voltage
V-EN_LO
-55C to +125C
01
-0.4
0
V
Output noise voltage
VNOISE
-55C to +125C
01
VIN = -3 V, VOUT(NOM) = VREF,
15.1 typical
VRMS
COUT = 10 F, CNR/SS = 10 nF,
BW = 10 Hz to 100 kHz
17.5 typical
VIN = -6.2 V, VOUT(NOM) = -5 V,
COUT = 10 F,
CNR/SS = CBYP = 10 nF, 6/
BW = 10 Hz to 100 kHz
Power supply
rejection ratio
PSRR
VIN = -6.2 V, VOUT(NOM) = -5 V,
-55C to +125C
01
72 typical
dB
-55C to +125C
01
+170 typical
C
COUT = 10 F,
CNR/SS = CBYP = 10 nF, 6/
f = 120 Hz
Thermal shutdown
temperature
TSD
Shutdown,
temperature increasing
Reset, temperature decreasing
1/
2/
+150 typical
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over
the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
At operating conditions, VIN  0 V, VOUT(NOM)  VREF  0 V. At regulation, VIN  VOUT(NOM) - |VDO|.
IOUT  0 flows from OUT to IN.
3/
Unless otherwise specified, at TJ = -55C to +125C, |VIN| = | VOUT(NOM) | + 1.0 V or |VIN| = 3.0 V (whichever is greater),
4/
5/
VEN = VIN, IOUT = 1 mA, CIN = 2.2 F, COUT = 2.2 F, CNR/SS = 0 nF, and the FB pin tied to OUT.
To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5 A is required.
IFB  0 flows into the device.
6/
CBYP refers to a bypass capacitor connected to the FB and OUT pins.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
6
Case X
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
7
Case X
Dimensions
Inches
Symbol
Millimeters
Min
Max
Min
Max
A
---
0.043
---
1.10
A1
0.001
0.005
0.05
0.15
b
0.009
0.014
0.25
0.38
c
0.005
0.009
0.13
0.23
D
0.114
0.122
2.90
3.10
e
0.025 BSC
0.65 BSC
E
0.114
0.122
2.90
3.10
E1
0.187
0.198
4.75
5.05
L
0.015
0.027
0.40
0.70
L1
0.009 BSC
0.25 BSC
NOTES:
1. Controlling dimensions are millimeters, inch dimensions are given for reference only.
2. Body dimensions do not include mold and flash or protrusion.
3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief
power pad thermally enhanced package, manufacturer’s literature number SLMA002 for information regarding
recommended board layout.
4. See additional figure in the manufacturer’s datasheet for details regarding the exposed thermal pad features and
dimension.
5. Falls within reference to JEDEC MO-187-AA-T.
FIGURE 1. Case outline - Continued.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
8
Device type
01
Case outline
X
Terminal number
Terminal
symbol
1
OUT
2
FB
This pin is the input to the control loop error
amplifier. It is used to set the output voltage of the
device.
3
NC
Not internally connected. This pin must either be
left open or tied to GND.
4
GND
5
EN
6
NR/SS
7
DNC
8
IN
Thermal pad
Description
Regulator output. A capacitor  2.2 F must be
tied from this pin to ground to assure stability.
Ground.
This pin turns the regulator on or off.
If VEN  V+EN_HI or VEN  V-EN_HI, the regulator
is enabled.
If V+EN_LO  VEN  V-EN_LO, the regulator is
disabled.
The EN pin can be connected to IN, if not used.
|VEN|  |VIN|.
Noise reduction pin. Connecting an external
capacitor to this pin bypass noise generated by the
internal bandgap. This capacitor allows RMS
noise to be reduced to very low levels and also
controls the soft start function.
Do not connect. Do not route this pin to any
electrical net, not even ground or IN.
Input supply.
Must either be left open or tied to GND. Solder to
printed circuit board (PCB) plane to enhanced
thermal performance.
FIGURE 2. Terminal connections.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
9
FIGURE 3. Logic diagram.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
10
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Top side
marking
Vendor part number 2/ 3/
V62/11619-01XE
01295
PXCM
TPS7A3001MDGNTEP
1/ The vendor item drawing establishes an administrative control number for identifying the
item on the engineering documentation.
2/ For the most current package and ordering information, see the package option addendum at the
end of the manufacturer’s data sheet.
3/ Package drawings, thermal data, and symbolization are available from the manufacturer.
CAGE code
01295
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/11619
PAGE
11