DEMO MANUAL DC981A/DC981B LTC4263 Main Board, Single Port Autonomous PSE/Daughter Card PSE Description Demonstration circuits 981A and 981B feature the LTC®4263 in single port Power over Ethernet (PoE) power sourcing equipment (PSE) midspan and endpoint solutions. The LTC4263 is an autonomous single-channel PSE controller for use in IEEE802.3af compliant PoE systems. It includes an onboard planar power MOSFET, internal inrush, current limit, and short-circuit control, powered device (PD) detection and classification circuitry, and selectable AC or DC disconnect sensing. Onboard control algorithms provide complete PSE control operation without the need of a microcontroller. The LTC4263 simplifies PSE implementation, needing only a single 48V supply and a small number of passive support components. Other options shown on the DC981A include legacy PD detection enable, midspan backoff timer enable, power class enforce mode, and power management enable. An LED for each port is driven by the respective LTC4263 to indicate the state of the port. Design files for this circuit board are available at http://www.linear.com/demo/DC981A L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Performance Summary Table 1. Typical DC981, Specifications are at TA = 25°C PARAMETER CONDITION VALUE Supply Voltage Voltage for IEEE802.3af Compliance at Port Output 46V to 57V Midspan Mode Detection Backoff Midspan Enabled, Failed Detection 3.2s Detection Range Valid IEEE802.3af PD Detection 17kΩ to 29.7kΩ Set Maximum Allocated Power Power Management Enabled, RPM = 12.4kΩ 17W Ethernet Powered Pairs Pinout Endpoint PSE, Alternative A (MDI) Midspan PSE, Alternative B 1/2(+), 3/6(–) 4/5(+), 7/8 (–) Quick Start Procedure Demonstration circuits 981A and 981B are easy to set up to evaluate the performance of the LTC4263. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below. 1.Place jumpers in the following positions: JP1 JP2 JP3 JP4 JP5 JP6 EN EN DIS AC AC EN 2.Insert daughter card (DC981B) to main board (DC981A) at polarized connector J3. 3.Apply 48V across VDD48 and VSS. 4.Connect a scope probe at VOUT_MD and VOUT_EP both referenced to positive rail VDD48. 5.Connect a valid PD to either midspan PSE or endpoint PSE. 6.Connect a second PD to the open port. dc981abf 1 DEMO MANUAL DC981A/DC981B Operating Principles Figure 1. Basic DC981A/DC981B Equipment Setup dc981abf 2 DEMO MANUAL DC981A/DC981B Operating Principles The DC981 provides two implementations of a PSE controlled by the LTC4263, a midspan PSE and an endpoint PSE. A single 48V supply is all that is required to power the board. This in turn provides power to the midspan PSE and endpoint PSE outputs. On each solution, an LTC4263 provides detection, classification, power management, safe power on, port current limit, and disconnect detection. Midspan PSE In the midspan solution, a legacy device (router, switch, etc.) that does not have PoE is connected to MIDSPAN IN. Data is passed through to MIDSPAN OUT along with PoE which goes out to a PD. Power is applied directly to Ethernet pairs 4/5 and 7/8. The LTC4263 circuitry is located in a small layout area behind the RJ45 connector and switches power on the negative rail. To show the different functions of the LTC4263, jumpers allow for the user to select the options of AC or DC disconnect, legacy detection, midspan backoff timing, and class enforcement. An LED that shows the status of the port is driven by a switcher in the LTC4263 to improve efficiency when VDD5 is provided internally. Push button switch SW1 ties the shutdown pin to ground to disable the LTC4263 in the midspan solution. A PSE implementing alternative B pin out must back off from detection for at least two seconds after a failed attempt. This is to avoid conflict of detection, for example, should a potential endpoint PSE and midspan PSE be connected to the same PD. To enable this feature, set JP2 to DIS. JP2 ties the MIDSPAN pin to VDD5 to enable the LTC4263 backoff timer or to VSS to disable. A 3.2s delay occurs after every failed detect cycle unless the result is open circuit. If held at VSS, no delay occurs after failed detect cycles. Endpoint PSE The endpoint solution is primarily shown on a small daughter card (DC981B). This card is the same height and width as the integrated RJ45 connector that it slides behind on the main board (DC981A). The RJ45 includes Ethernet magnetics and common mode termination. A layout option shows the same components can be placed under the same RJ45 connector. The minimum connections to the daughter card are VSS, VDD48 and VOUT. Power is switched over from the daughter card out to the Ethernet data pairs (1/2 and 3/6). A PHY can be connected to the TO PHY connector to pass data through to the data pairs along with PoE. LED drive and power management pins are also brought out for additional board functions. The board is set up for AC disconnect, but can be reworked for DC disconnect by removing components and replacing with shorts in certain locations. Two solder jumpers also provide selectable options for legacy detection and class enforce. Power Management The midspan and endpoint PSEs, although separate solutions on the DC981, are tied together at the PWRMGT pin for demonstration of the LTC4263 power management capability. Programmable onboard power management circuitry allows multiple LTC4263s to allocate and share power in multiport systems, allowing maximum utilization of the 48V power supply – all without the intervention of a host processor. The LTC4263 sources current (IPM) at the PWRMGT pin proportional to the class of the PD that it is powering. The voltage of this pin (VPM) is checked before powering the port (Table 2). The port will not turn on if this pin is more than 1V above VSS. The PWRMGT pins of the LTC4263s are tied together and connect to a resistor (RPM) and capacitor (CPM) in parallel to VSS to implement power management. This resistor is selected with the following equation: RPM = 213kΩ • W/PFULL_LOAD On the DC981A, the default RPM is 12.4kΩ for a full load power of 17W. Table 2. Power Management Voltage PD CLASS POWER REQUEST IPM (TYP) VPM* Class 1 4W 19μA 236mV Class 2 7W 33μA 409mV Class 0, 3, or 4 15.4W 73μA 905mV *RPM = 12.4kΩ dc981abf 3 DEMO MANUAL DC981A/DC981B Operating Principles VDD5 Option Table 3. Powered Device Combinations PD COMBINATION 1ST PD 2ND PD Class 1 / Class 1 Powered Powered Class 1 / Class 2 Powered Powered Class 1 / Class 3** Powered Power Denied Class 2 / Class 2 Powered Powered Class 2 / Class 3** Powered Power Denied Class 3 **/ Class 3** Powered Power Denied **Class 3 substitutable with Class 0 or 4. If power management is not used, move JP6 to DIS to tie the PWRMGT pins to VSS and disable this feature. Class Enforce Mode ENFORCE CLASS jumper JP1 ties the ENFCLS pin of the LTC4263 to either VDD5 or VSS to respectively enable or disable class enforce current limits. If held at VDD5, the LTC4263 will reduce the ICUT threshold for Class 1 or Class 2 PDs. If ENFCLS is held at VSS, ICUT remains at 375mA (typical) for all classes. Table 4. Port Current Limit According to Class PD CLASS CURRENT THRESHOLD (TYPICAL) Class 1 100mA Class 2 175mA Class 0, 3, 4, or Class Enforce Disabled 375mA LED Drive An LED pin indicates the state of the port controlled by the LTC4263. When the port is powered, the LED is on; when disconnected or detecting, the LED is off. If an invalid signature is detected or a fault occurs, the LED will flash a pattern that the user or host system can read to indicate the nature of the problem. When run from a single 48V supply, the LED pin can operate as a simple switching current source to reduce power dissipation in the LED drive circuitry. The logic 5V power supply can be supplied from the internal LTC4263 5V supply or an external 5V supply when above the internal supply. If the internal regulator is used, this pin should only be connected to the bypass capacitor and to logic pins of the LTC4263 held at VDD5. AC and DC Disconnect AC and DC disconnect are two different methods of detecting whether a valid PD is present and requires power. AC disconnect is the default method for the DC981 but can be converted to DC disconnect in the midspan solution through two jumpers. Moving DISCON (JP4) to DC will short the ACCOUT pin to VSS and configure the LTC4263 to DC disconnect. Moving jumper setting for ACCOMP (JP5) to DC bypasses the AC blocking diode and removes the RC used for AC disconnect from the main circuit. Legacy Detection LEGACY jumper JP3 controls whether legacy detect is enabled. If the LEGACY pin is held at VDD5 (EN selected), legacy detect is enabled and testing for a large capacitor is performed to detect the presence of a legacy PD on the port. If held at VSS (DIS selected), only IEEE 802.3af compliant PDs are detected. If left floating (no jumper), the LTC4263 enters force-power-on mode and any PD that generates between 1V and 10V when biased with 270μA of detection current will be powered as a legacy device. This mode is useful if the system uses a differential detection scheme to detect legacy devices. Warning: Legacy modes are not IEEE 802.3af compliant. dc981abf 4 DEMO MANUAL DC981A/DC981B Operating Principles Figure 2. DC981 Options dc981abf 5 DEMO MANUAL DC981A/DC981B DC981A Layout Top Silkscreen Layer 1 dc981abf 6 DEMO MANUAL DC981A/DC981B DC981A Layout Layer 2 Layer 3 dc981abf 7 DEMO MANUAL DC981A/DC981B DC981A Layout Layer 4 Silkscreen Bottom dc981abf 8 DEMO MANUAL DC981A/DC981B DC981B Layout Top Silkscreen Top Layer dc981abf 9 DEMO MANUAL DC981A/DC981B DC981B Layout Bottom Layer Bottom Silkscreen dc981abf 10 DEMO MANUAL DC981A/DC981B Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER DC981A-3 Required Circuit Components 1 1 CPM CAP, X5R, 1µF 16V, 10%, 0603 MURATA, GRM185R61C105KE44D 2 2 C1 CAP, X7R, 0.1µF 16V, 10%, 0603 MURATA, GRM188R71C104KA01D 3 2 C3, C4 CAP, X7R 0.1µF 100V, 10%, 0603 MURATA, GRM188R72A104KA35D 4 1 D1 DIODE, SWITCHING, SOT23 DIODES INC, BAS19-7-F 5 1 D2 DIODE, 58V TVS, SMA-DIODE DIODES INC, SMAJ58A-13 6 1 J4 JACK, POWER, RJ45-JK0-0144BNL PULSE, JK0-0144BNL 7 2 LED3, LED2 LED, GREEN, LED-ROHM, SML-010 ROHM, SML-010FTT86 8 1 L1 IND, PWR, 10000µH, L-COIL-DS1608C COILCRAFT, DS1608C-106MLC 9 1 RPM RES, CHIP 12.4k 1/16W 1%, 0805 VISHAY, CRCW080512K4FKEA 10 1 R1 RES, CHIP 2k 1/10W 5%, 0805 VISHAY, CRCW08052K00FKEA 11 1 R2 RES, CHIP 1k 1/16W 5%, 0603 YAGEO, RC0603FR-071KL 12 1 R3 RES, CHIP 10k 1/16W 5%, 0603 YAGEO, RC0603FR-0710KL 13 1 U1 IC, LTC4263CS, SO14 LINEAR TECHNOLOGY, LTC4263CS Optional Circuit Components 1 1 C2 CAP, X7R 1000PF 2kV, 1206 MURATA, GR431BR7LA102KW01L 2 4 C5, C8, C11, C13 CAP, X7R, 0.1µF 16V, 10%, 0603 MURATA, GRM188R71C104KA01D 3 1 C6 CAP, ELECT, 4.7µF 63V, C-PANA-EEVFK-C PANASONIC, EEE-FK1J4R7R 4 2 C7, C12 CAP, X7R, 0.47µF 100V, 10%, 0805 MURATA, GRM21BR72A474KA73L 5 2 C9, C10 CAP, X7R 0.1µF 100V, 10%, 0603 MURATA, GRM188R72A104KA35D 6 2 D3, D5 DIODE, SHOTTKY, PICO MINI, SOT563 CENTRAL SEMI, CMLSH05-4 7 1 D4 DIODE, 58V TVS, SMA-DIODE DIODES INC, SMAJ58A-13 8 1 D6 DIODE, RECTIFIER 3A, SMB-DIDOE DIODES INC, S3BB-13-F 9 2 D8, D7 DIODE, 15V, ZENER, SOD323 CENTRAL SEMI, CMDZ15L 10 2 J6, J5 CONN, RJ-45 RIGHT ANGLE, RJ45 STEWART CONN SYS, SS-6488-NF-K1 11 1 LED1 LED, YELLOW, LED-ROHM, SML-010 ROHM, SML-010YTT86 12 2 R6, R8 RES, CHIP 1k 1/16W 5%, 0603 YAGEO, RC0603FR-071KL 13 1 R4 RES, CHIP 5.1k 1/16W 5%, 0603 AAC, CR16-512JM 14 2 R5, R7 RES, CHIP 510k 1/16W 5%, 0603 VISHAY, CRCW0603510KJNEA 15 1 SW1 SWITCH, PUSH BUTTON WÜRTH, 434 123 050 816 16 1 J3 SOCKET, 1X6, 0.079", VERTICAL SAMTEC, SQT-106-01-LM-S-004 17 1 U2 IC, LTC4263CDE, DFN14DE LINEAR TECHNOLOGY, LTC4263CS Hardware for Demo Board Only 1 5 E1, E2, E9, E10, E11 TP, TURRET, 0.094" MILL-MAX, 2501-2-00-80-00-00-07-0 2 6 E3, E4, E5, E6, E7, E8 TP, TURRET, 0.064" MILL-MAX, 2308-2-00-80-00-00-07-0 3 6 JP1, JP2, JP3, JP4, JP5, JP6 JMP, 1X3, 0.079" SAMTEC, TMM-103-02-L-S 4 0 JP7 JMP, 2X3, 0.079" OPT 5 6 FOR JP1 TO JP6 (1 and 2) SHUNT, 0.079" CENTER SAMTEC, 2SN-BK-G 6 2 J1, J2 JACK, BANANA, KEY-575 KEYSTONE, 575-4 7 4 MH1 TO MH4 STANDOFF, SNAP ON, 1/2" KEYSTONE, 8833 dc981abf 11 DEMO MANUAL DC981A/DC981B Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER DC981B Required Circuit Components 1 2 C2, C1 CAP, X7R, 0.1µF 16V, 10%, 0603 MURATA, GRM188R71C104KA01D 2 2 C3, C4 CAP, X7R 0.1µF 100V, 10%, 0603 MURATA, GRM188R72A104KA35D 3 1 C5 CAP, X7R, 0.47µF 100V, 10%, 0805 MURATA, GRM21BR72A474KA73L 4 1 D1 DIODE, 58V TVS, SMA-DIODE DIODES INC, SMAJ58A 5 1 D2 DIODE, SCHOTTKY, PICO MINI, SOT563 CENTRAL SEMI, CMLSH05-4 6 1 J1 HEADER, 1X6, 0.079", SMT, HORIZONTAL SAMTEC, MMT-106-02-S-SH-004 7 1 R1 RES, CHIP 510kΩ 1/16W 5%, 0603 AAC, CR16-514JM 8 1 R2 RES, CHIP 1kΩ 1/16W 5%, 0603 AAC, CR16-102JM 9 1 U1 I.C., LTC4263CDE, DFN14DE LINEAR TECHNOLOGY, LTC4263CDE dc981abf 12 A B C D VDD48 + PANASONIC EEVFK1J4R7R JP1 E3 C6 4.7UF 63V SW1 SD D6 S3BB R3 10K 5 2. INSTALL SHUNTS ON JP1-JP6 PINS 1 AND 2. 1. ALL RESISTORS ARE IN OHMS, 0603. ALL CAPACITORS ARE 0603. 6 5 13 3 2 12 14 9 10 R2 1K E5 E4 1K D3 CMLSH05-4 1 3 2 5 4 6 R5 510K R6 VDD48 VSS VDD5 CUSTOMER NOTICE OUT OUT 8 7 4 1 VDD5 4 3 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. C5 0.1UF DS1608C-106 COILCRAFT L1 10000UH MIDPSE LED2 GRN SCALE = NONE DILIAN R. KIM T. APPROVALS 3 __ J5 DIS JP6 PWRMGT EN 4 5 7 8 1 2 3 6 DATE 4 5 7 8 1 2 3 6 J6 PWRMGT PM LED VDD48 09-26-14 SS-6468-NF-K1 E6 E7 DILIAN R. E9 VOUT_MID MIDSPAN IN RJ45 N/A DATE: SIZE 2 Friday, September 26, 2014 1 SHEET 1 OF 3 2 MAIN BOARD, SINGLE PORT AUTONOMOUS PSE IC NO. REV. LTC4263CS / LTC4263CDE DEMO CIRCUIT 981A 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only MIDSPAN OUT RJ45 1 APPROVED MIDSPAN PSE SS-6468-NF-K1 CPM 1UF D2 SMAJ58A RPM 12.4K 1% 0805 DESCRIPTION PRODUCTION REVISION HISTORY TECHNOLOGY C4 0.1UF 100V REV ECO TITLE: SCHEMATIC JP4 JP5 ACCOMP DISCON AC DC C7 0.47UF 100V 0805 D1 BAS19 C13 0.1UF (EXTERNAL 5V SUPPLY OPTIONAL) LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. VSS VSS ACCOUT OSC ENFCLS PWRMGT MIDSPAN LED VDD48 11 C3 0.1UF 100V VDD48 LED1 YELLOW LEGACY SD VDD5 U1 LTC4263CS C1 0.1UF 15V 15V VDD5 D8 CMDZ15L 2 1 D7 CMDZ15L 2 1 R4 5.1K NOTES: UNLESS OTHERWISE SPECIFIED VSS EN DIS ENFCLS VDD5 ENFORCE CLASS DIS JP2 VDD5 MIDSPAN EN MIDSPAN DIS E8 E2 E11 E1 _ VDD48 JP3 VDD5 LEGACY EN LEGACY SD VSS + J2 VDD48 VSS 46V-57V J1 1 2 1 2 1 2 VDD48 3 1 1 2 1 2 2 1 2 3 CHS CHS 4 CHS CHS 5 A B C D DEMO MANUAL DC981A/DC981B Schematic Diagram dc981abf 13 A B C PM VDD48 5 C8 0.1UF 6 5 13 3 2 12 14 OUT OUT ACCOUT OSC PWRMGT LED 3 4 R7 510K D5 CMLSH05-4 R8 1K CUSTOMER NOTICE 1 2 5 6 C11 0.1UF C9 0.1UF 100V 0603 C12 0.47UF 100V 0805 R1 2K 0805 4 3 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. KIM T. SCALE = NONE DILIAN R. VO- 2 5 10 6 11 1 7 8 2 9 VC1+ VC1VC2+ VC2- TD+ CT TDRD+ RD- J4 2 4 6 DATE: N/A SIZE DEMO CIRCUIT 981A 2 1 SHEET LTC4263CS / LTC4263CDE Friday, September 26, 2014 IC NO. 2 OF 2 3 REV. MAIN BOARD, SINGLE PORT AUTONOMOUS PSE 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only 1206 JP7 OPT HD2X3-079 TO PHY 1 3 5 E10 VOUT_EP 1 OUT TO PD ENDPOINT PSE JK0-0044 1 2 3 4 5 6 7 8 C2 1000PF,2KV TECHNOLOGY TITLE: SCHEMATIC D4 SMAJ58A APPROVALS C10 0.1UF 100V 0603 ENDPSE LED3 GRN VDD48 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. 9 10 8 7 4 1 11 PM OPTIONAL ENDPOINT PSE LAYOUT VSS VSS ENFCLS MIDSPAN LEGACY SD VDD5 6 5 4 3 2 1 VDD48 HD1X6-079 LED PM X VDD48 VOGND U2 LTC4263CDE TO DAUGHTER CARD J3 3 ENDPOINT PSE OPTIONS 1 2 D GND 15 1 2 4 CHS 12 CHS 14 13 5 A B C D DEMO MANUAL DC981A/DC981B Schematic Diagram dc981abf DEMO MANUAL DC981A/DC981B Schematic Diagram dc981abf Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 DEMO MANUAL DC981A/DC981B DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright © 2004, Linear Technology Corporation dc981abf 16 Linear Technology Corporation LT 1214 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2014