ANALOG IP BLOCK PECL_TX - CMOS PECL Transmitter PROCESS C35B3 (0.35um) DATA SHEET DESCRIPTION The PECL_TX is a differential 3.3 V PECL transmitter featuring a transmission speed of 622 Mb/s with standard F100K levels (referred to the positive supply). Unlike other low-voltage CMOS designs, this PECL transmitter supports FEATURES standard 50 Ω termination towards a supply of VDDPECL – ! PECL_TX area: 0.25 mm2, ! size: x = 723 µm y = 340 µm PETXREF ! size: x = 440 µm y = 340 µm PETXBIAS 2 V. The cell can be set in power down mode (high output impedance). It requires the PETXBIAS and PETXREF cells for biasing. An external voltage reference must be used. ! 3.3 V ±10% supply voltage ! 622 Mb/s transmission speed size: x = 446 µm y = 378 µm ! 900 ps max. propagation delay ! Power dissipation 191 mW at 3.3 V static (without PETXBIAS and PETXREF ) ! ! Junction temperature –40 - 125°C Output levels fully compatible with F100K PECL Family ! High capacitive loads driving capability: 10 pF ! @622 Mb/s Power down mode Revision B, 10.09.02 Page 1 of 8 Datasheet: PECL_TX – C35 TECHNICAL DATA FOR PECL_TX (Tjunction = −40 to 125 °C, VDDPECL = VDDCMOS = VDDA = +3.0 V to +3.6 V, XPD = High, SIM = Low, receiver input termination resistance: 50 Ω to VT, where VT = VDDPECL – 2 V ± 25 mV, unless otherwise specified) DC CHARACTERISTICS Symbol VOD Parameter Differential Output Swing Conditions Min 600 Typ 750 Max 900 Units mV Referred to VDDPECL −1.43 −1.3 −1.17 V VOD = VOUTP − VOUTN VOCM Common Mode Output Voltg. VOCM = (VOUTP + VOUTN)/2 VOH Output Voltage High Referred to VDDPECL –1025 –870 mV VOL Output Voltage Low Referred to VDDPECL –1830 –1620 mV VIH Input Voltage High VIL Input Voltage Low V CMOS levels V AC CHARACTERISTICS CL = 10 pF at each output, unless otherwise specified Symbol tPD Parameter 1) Propagation Delay tSKD1 Differential Pulse Skew 1) tSKD2 Differential Channel to Channel Skew 1) tTLH Rise Time 2) tTHL Fall Time 2) 3) Conditions Min 450 Typ 600 Max 900 Unit ps 150 ps 25 100 ps 150 200 350 ps 150 200 350 ps Cload Load Capacitance 10 12 pF fMAX Operating Frequency 3) 311 311 MHz TXS Transmission Rate 622 622 Mb/s @622 Mb/s 1) 2) Including the package: SOIC28, pins 5–10 or 19–24 for VOUTP and VOUTN Specified at 20% and 80% of the output voltage 3) fMAX generator input conditions: tr = tf < 250 ps, 50% duty cycle Revision B, 10.09.02 Page 2 of 8 Datasheet: PECL_TX – C35 POWER REQUIREMENTS Symbol ICCDC Parameter DC Current Consumption Conditions Without PETXBIAS and PETXREF ICCAC AC Current Consumption Cload = 10 pF @622 Mb/s, without PETXBIAS and PETXREF ICCPD Power Down Current Consumption XPD = Low, without PETXBIAS and PETXREF Pdiss_DC DC Power Consumption Without PETXBIAS and PETXREF Pdiss_AC AC Power Consumption Cload = 10 pF @622 Mb/s, without PETXBIAS and PETXREF Pdiss_PD Power Consumption in Power Down Mode XPD = Low, without PETXBIAS and PETXREF Revision B, 10.09.02 Min Typ 58 Max 82 Unit mA 65 92 mA 300 µA 191 296 mW 215 331 mW 1.08 mW Page 3 of 8 Datasheet: PECL_TX – C35 TECHNICAL DATA FOR PETXBIAS (Tjunction = −40 to 125 °C, VDDA = +3.0 V to +3.6 V, XSIM = High, unless otherwise specified) POWER REQUIREMENTS Symbol ICC Parameter DC Current Consumption Pdiss Power Consumption Conditions Min Typ 2 Max 3 Unit mA 6.6 10.8 mW Typ 1.22 Max 1.24 Unit V Typ 6 Max 9.2 Unit mA 25 µA 33.1 mW 90 µW REFERENCE CHARACTERISTICS Symbol VREF Parameter Reference Voltage Conditions Min 1.20 TECHNICAL DATA FOR PETXREF (Tjunction = −40 to 125 °C, VDDA = +3.0 V to +3.6 V, XPD = High, unless otherwise specified) POWER REQUIREMENTS Symbol ICC Parameter DC Current Consumption Conditions ICCPD Power Down Current Consumption XPD = Low Pdiss Power Consumption Pdiss_PD Power Consumption in Power Down Mode Revision B, 10.09.02 Min 19.8 XPD = Low Page 4 of 8 Datasheet: PECL_TX – C35 SYMBOL OF PECL_TX PIN LIST OF PECL_TX Pin VDDPECL Description Positive Supply for PECL Transmitter Type Supply VDDA Positive Supply Supply VDDCMOS Positive Supply for CMOS Input Buffer Supply VSSPECL Negative Supply Supply VSSCMOS Negative Supply Supply IREFP Bias Current Analog IREFN Bias Current Analog VMID Voltage Reference Analog VCL Voltage Reference Analog VCH Voltage Reference Analog XPD Power Down Digital SIM Test Pin Digital VINP Positive Input Digital XPD High VINP High VINN Low VOUTP High VOUTN Low VINN Negative Input Digital VOUTP Pos. PECL Output Analog High Low High Low High VOUTN Neg. PECL Output Analog Low X X High-Z High-Z SYMBOL OF PETXBIAS Revision B, 10.09.02 PIN LIST OF PETXBIAS Pin VDDA Description Positive Supply Type Supply VSSA Negative Supply Supply IREFP1 Bias Current Analog IREFP2 Bias Current Analog IREFP3 Bias Current Analog IREFPR Bias Current Analog IREFN1 Bias Current Analog IREFN2 Bias Current Analog IREFN3 Bias Current Analog IREFNR Bias Current Analog VMID Voltage Reference Analog VOH Voltage Reference Analog VOL Voltage Reference Analog VTT Voltage Reference Analog XSIM Test Pin Digital VREF External Reference Voltage Analog Page 5 of 8 Datasheet: PECL_TX – C35 SYMBOL OF PETXREF PIN LIST OF PETXREF Pin VDDA Description Positive Supply VSSPECL Negative Supply VSSCMOS Negative Supply IREFPR Bias Current IREFNR Bias Current VOH Voltage Reference VOL Voltage Reference VTT Voltage Reference VCL Voltage Reference VCH Voltage Reference XPD Power Down Type Supply Supply Supply Analog Analog Analog Analog Analog Analog Analog Digital THEORY OF OPERATION The PECL_TX is a fully differential line driver with a low voltage output swing (standard F100K levels). The signal lines must be 50 Ω transmission lines. At the receiver end each signal has to be terminated to the voltage level VT The cell PECL_TX requires the PETXBIAS and PETXREF cells for biasing. PETXREF is designed as a pad cell. It should be placed near PECL_TX cells for maximum matching. Up to 3 PECL_TX cells can be driven by PETXREF and PETXBIAS . (where VT = VDDPECL – 2 V) with an external termination resistor of 50 Ω, but also other termination schemes are possible. APPLICATION ! ! ! ! ! High Speed Backplane Driver Complementary Clock Drivers Level Translator System Interconnects ATM Applications Revision B, 10.09.02 ! ! ! ! SDH Applications High-Resolution Imaging Applications Laser Printers Digital Copiers Page 6 of 8 Datasheet: PECL_TX – C35 TYPICAL APPLICATION 1) chip internal VDDA external SNAP BACK 6) VDDA 1) 4) VDDA 1) 1 µF 100pF 22pF VSSA 3) VDD 7) 4) VDD 1 µF 7) 7) 100pF VSS 22pF 3) VT 50Ω DATA complementary CMOS signals 50Ω transmission lines (from digital core) DATAN 50Ω (receiver) VT 5) VDDA + 2V 1 µF - 100pF 22pF VT VREF VSS 1nF 3) 4) 180pF VSSA 3) VSSA 3) 4) VREF (external reference) SNAP BACK 1) 2) 3) 4) 5) 6) 7) 2) 6) Each power pin must have its own set of blocking capacitors. An external reference must be used. VSSA and VSS must be connected on the PCB level. The two power pads can be bonded to one package pin (double bonding). Two more PECLTX cells can be driven with IREFxx of the PETXBIAS cell. If an output IREFxx is not used it must be left unconnected. The PECL part of the chip has to be separated from the rest of the chip by use of snap backs (cell PWRCUT_DIG_P_SNAP_SNAP). The cells VDD3R1P and VDD3R2P are not in the standard library, they are part of the IP-block. Revision B, 10.09.02 Page 7 of 8 Datasheet: PECL_TX – C35 Contact Copyright austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 [email protected] Copyright © 2002 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Revision B, 10.09.02 Page 8 of 8