ANALOG IP BLOCK CDAC12 - CMOS 12-Bit D/A CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 (0.35um) The CDAC12 is a 12-bit high-resolution high-speed CMOS digital-toanalog converter (DAC). The CDAC12 uses a segmented current steering architecture combined with a simple and fast decoding logic to achieve a very high update rate, 12-bit of intrinsic static accuracy, and good dynamic characteristics. The CDAC12 is a differential current output DAC with a typical fullscale current of 10mA or 20mA. The output currents can be used to directly drive two external resistors to obtain two complementary output voltages, or they can be used to drive an external transformer (or amplifier) to obtain a single-ended output voltage. FEATURES ! Small Area: 2mm2 ! ! Size: x = 995µm y = 2021µm Supply Voltage: 3.0 to 3.6V ! ! ! ! ! Junction Temp. Range: −40 to +125°C Resolution: 12-Bit Maximum Update Rate: 200MS/s Diff. Current Outputs: 10 to 20mA Power of 150mW @ 3.3V Supply Voltage and 10mA output current VDDA VDDS VDDD B11 B10 B2 B1 B0 6 MSB SWITCHES B4 B3 6 2 CLK 4 IOUTN Revision B, 09.09.02 4 ISB SWITCHES B5 FOUR EQUAL CURRENT SOURCES 4 LSB SWITCHES B7 B6 ROW DECODER B8 VSSD CURRENT SOURCE ARRAY COLUMN DECODER INPUT REGENERATION B9 VSSA VSSS FOUR BINARY CURRENT SOURCES IOUTP BIAS GENERATION IBIAS Page 1 of 12 Datasheet : CDAC12 – C35 TECHNICAL DATA FOR OUTPUT CURRENT=10mA (Tjunction=–40 to 125°C, VDDA=VDDD=+3.0V to +3.6V, fclk=200MHz, RL=50Ω, unless otherwise specified) DC SPECIFICATIONS Symbol Parameter Resolution DNL INL Conditions Min 12 Typ Max Units bit Differential Linearity Error –1 ±0.7 +1 LSB Integral Linearity Error –2 ±0.7 +2 LSB Conditions Min IFS/16 Typ IFS/16 Max IFS/16 Units mA Conditions Min –5 Typ 0 Max +5 Units % FS REFERENCE INPUT Symbol IBIAS Parameter Reference Current ANALOG OUTPUT Symbol OFFSETB Parameter Offset Error FSERR Full-Scale Error –5 1 +5 % FS IFS Full-Scale Output Current 8 10 12 mA VFS Output Compliance Range 0.5 0.6 Rout Output Resistance Cout Output Capacitance foutmax Max. Output Signal Frequency V 100 kΩ 12 pF 30 MHz Max Units dBc AC ACCURACY (fclk=200MHz) Symbol THD Parameter Total Harmonic Distortion Conditions fout=1MHz Min Typ –80 THD Total Harmonic Distortion fout=10MHz –54 dBc THD Total Harmonic Distortion fout=30MHz –42 dBc SFDR Spurious Free Dynamic Range fout=1MHz 71 dBc SFDR Spurious Free Dynamic Range fout=10MHz 59 dBc SFDR Spurious Free Dynamic Range fout=30MHz 42 dBc AC ACCURACY (fclk=100MHz) Symbol THD Parameter Total Harmonic Distortion Conditions fout=0.5MHz Min THD Total Harmonic Distortion fout=5MHz –63 dBc THD Total Harmonic Distortion fout=15MHz –54 dBc SFDR Spurious Free Dynamic Range fout=0.5MHz 71 dBc SFDR Spurious Free Dynamic Range fout=5MHz 70 dBc 55 dBc –60 dBc 60 dBc SFDR Spurious Free Dynamic Range fout=15MHz TT-IMD Two-Tone Third Order Intermodulation Distortion fout1=10MHz fout2=11MHz TT-SFDR Two-Tone Spurious Free Dynamic Range fout1=10MHz 1) fout2=11MHz 1) 1) Typ –81 Max Both signals, fout1 and fout2, have an amplitude of –6dB full scale. Revision B, 09.09.02 Page 2 of 12 Units dBc Datasheet : CDAC12 – C35 DYNAMIC PERFORMANCE Symbol Ts Parameter Settling Time (0.1%) Conditions Min Typ 300 Max Units ns Tr Output Rise Time (10% - 90%) 2.2 ns Tf Output Fall Time (90% - 10%) 1.8 ns Tpd Output Propagation Delay 2.0 ns GA Glitch Area 10 pVs DIGITAL INPUTS Symbol Parameter Digital Input Level Conditions Digital Input Codes Min Typ CMOS levels Max Units Unsigned binary: 000h - FFFh POWER REQUIREMENTS Symbol VDDA VDDD Parameter Pos. Analog Supply Voltage Conditions ref. VSSA Min 3.0 Pos. Digital Supply Voltage ref. VSSD 3.0 Typ 3.3 Max 3.6 Units V 3.3 3.6 V Static Supply Current Digital 0 0 mA IDDAstat 1) Static Supply Current Analog 20 25 mA Pdissstat 1) 2) Static Total Power Consumption 68 93 mW IDDDdyn 3) Dynamic Supply Current Digital 25 36 mA IDDAdyn Dynamic Supply Current Analog 20 25 mA Pdissdyn 2) 3) Dynamic Total Power Consumption 150 222 mW IDDDstat 1) TIMING CHARACTERISTICS Symbol Tclk Parameter Clock Period fclk Master Clock Frequency Conditions Min 5 Typ 5 Max Units ns 200 200 MHz 200 200 Ur Update Rate Tsu Setup Time Data to Clock 0.5 0.5 ns Th Hold Time Clock to Data 1 1 ns 1) 2) 3) All digital input signals and the clock are set to a static level (Low or High). Including the bias current IBIAS. The measurement includes 13 digital input pads (ICP). Revision B, 09.09.02 Page 3 of 12 MS/s Datasheet : CDAC12 – C35 TYPICAL PERFORMANCE CHARACTERISTICS FOR OUTPUT CURRENT=10mA INL [LSB] DNL [LSB] (Tjunction =25°C, VDDA=VDDD=+3.3V, IBIAS=625µA, unless otherwise specified) Digital Code Output Signal Frequency [Hz] Output Signal Frequency [Hz] Output Signal Frequency [Hz] Spectrum @5MHz 2) 3) SFDR vs. Output Signal Frequency 1) FFT [dBc] FFT [dBc] SFDR vs. Output Signal Frequency 2) 1) 1) SFDR [dBc] INL SFDR [dBc] DNL Digital Code 1) 2) Output Signal Frequency [Hz] Two-Tone IMD @10MHz and 11MHz 2) 3) fclk=200MHz fclk=100MHz Both signals, fout1 and fout2, have an amplitude of –6dB full scale. Revision B, 09.09.02 Page 4 of 12 Datasheet : CDAC12 – C35 TECHNICAL DATA FOR OUTPUT CURRENT=20mA (Tjunction=–40 to 125°C, VDDA=VDDD=+3.0V to +3.6V, fclk=200MHz, RL=25Ω, unless otherwise specified) DC SPECIFICATIONS Symbol Parameter Resolution DNL INL Conditions Min 12 Typ Max Units bit Differential Linearity Error –1 ±0.7 +1 LSB Integral Linearity Error –2 ±0.6 +2 LSB Conditions Min IFS/16 Typ IFS/16 Max IFS/16 Units mA Conditions Min –5 Typ 0 Max +5 Units % FS REFERENCE INPUT Symbol IBIAS Parameter Reference Current ANALOG OUTPUT Symbol OFFSETB Parameter Offset Error FSERR Full-Scale Error –5 1 +5 % FS IFS Full-Scale Output Current 16 20 24 mA VFS Output Compliance Range 0.5 0.6 Rout Output Resistance Cout Output Capacitance foutmax Max. Output Signal Frequency V 100 kΩ 12 pF 30 MHz Max Units dBc AC ACCURACY (fclk=200MHz) Symbol THD Parameter Total Harmonic Distortion Conditions fout=1MHz Min Typ –81 THD Total Harmonic Distortion fout=10MHz –60 dBc THD Total Harmonic Distortion fout=30MHz –45 dBc SFDR Spurious Free Dynamic Range fout=1MHz 74 dBc SFDR Spurious Free Dynamic Range fout=10MHz 66 dBc SFDR Spurious Free Dynamic Range fout=30MHz 46 dBc AC ACCURACY (fclk=100MHz) Symbol THD Parameter Total Harmonic Distortion Conditions fout=0.5MHz Min THD Total Harmonic Distortion fout=5MHz –66 dBc THD Total Harmonic Distortion fout=15MHz –58 dBc SFDR Spurious Free Dynamic Range fout=0.5MHz 74 dBc SFDR Spurious Free Dynamic Range fout=5MHz 72 dBc 58 dBc –65 dBc 65 dBc SFDR Spurious Free Dynamic Range fout=15MHz TT-IMD Two-Tone Third Order Intermodulation Distortion fout1=10MHz fout2=11MHz TT-SFDR Two-Tone Spurious Free Dynamic Range fout1=10MHz 1) fout2=11MHz 1) 1) Typ –81 Max Both signals, fout1 and fout2, have an amplitude of –6dB full scale. Revision B, 09.09.02 Page 5 of 12 Units dBc Datasheet : CDAC12 – C35 DYNAMIC PERFORMANCE Symbol Ts Parameter Settling Time (0.1%) Conditions Min Typ 70 Max Units ns Tr Output Rise Time (10% - 90%) 1.0 ns Tf Output Fall Time (90% - 10%) 1.0 ns Tpd Output Propagation Delay 2.0 ns GA Glitch Area 10 pVs DIGITAL INPUTS Symbol Parameter Digital Input Level Conditions Digital Input Codes Min Typ CMOS levels Max Units Unsigned binary: 000h - FFFh POWER REQUIREMENTS Symbol VDDA VDDD Parameter Pos. Analog Supply Voltage Conditions ref. VSSA Min 3.0 Pos. Digital Supply Voltage ref. VSSD 3.0 Typ 3.3 Max 3.6 Units V 3.3 3.6 V Static Supply Current Digital 0 0 mA IDDAstat 1) Static Supply Current Analog 35 44 mA Pdissstat 1) 2) Static Total Power Consumption 120 163 mW IDDDdyn 3) Dynamic Supply Current Digital 25 36 mA IDDAdyn Dynamic Supply Current Analog 35 44 mA Pdissdyn 2) 3) Dynamic Total Power Consumption 202 293 mW IDDDstat 1) TIMING CHARACTERISTICS Symbol Tclk Parameter Clock Period fclk Master Clock Frequency Conditions Min 5 Typ 5 Max Units ns 200 200 MHz 200 200 Ur Update Rate Tsu Setup Time Data to Clock 0.5 0.5 ns Th Hold Time Clock to Data 1 1 ns 1) 2) 3) All digital input signals and the clock are set to a static level (Low or High). Including the bias current IBIAS. The measurement includes 13 digital input pads (ICP). Revision B, 09.09.02 Page 6 of 12 MS/s Datasheet : CDAC12 – C35 TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT CURRENT=20mA INL [LSB] DNL [LSB] (Tjunction =25°C, VDDA=VDDD=+3.3V, IBIAS=1250µA, unless otherwise specified) Digital Code Digital Code SFDR [dBc] INL 1) SFDR [dBc] DNL 1) Output Signal Frequency [Hz] Output Signal Frequency [Hz] Spectrum @5MHz 2) 1) 2) 3) SFDR vs. Output Signal Frequency 1) FFT [dBc] FFT [dBc] SFDR vs. Output Signal Frequency Output Signal Frequency [Hz] 2) Output Signal Frequency [Hz] Two-Tone IMD @10MHz and 11MHz 2) 3) fclk=200MHz fclk=100MHz Both signals, fout1 and fout2, have an amplitude of –6dB full scale. Revision B, 09.09.02 Page 7 of 12 Datasheet : CDAC12 – C35 SYMBOL PINLIST Pin CLK Description Clock Input Type DIN Cap 140fF B[11:0] Digital Input Data DIN 400fF IBIAS Reference Current AIN IOUTP IOUTN Differential Current Outputs AOUT VDDD Pos. Digital Supply S VSSD Neg. Digital Supply S VDDA1 Pos. Analog Supply S VDDA2 Pos. Analog Supply S VSSA Neg. Analog Supply S VDDS Analog Power Supply for N-Well Shielding S VSSS Substrate Supply S THEORY OF OPERATION POWER SUPPLIES The macro cell CDAC12 is a 12-bit digital to analog converter based on a current steering architecture. CDAC12 features a 6+2+4 bit double-segmented architecture, where the 6 most significant bits are implemented with 256 unity decoded cells. The two intermediate bits are also unity decoded but independently from the most significant bits, and the 4 least significant bits are implemented with 4 binary weighted cells. External loads are to be connected outside the CDAC12 and are recommended as terminations for high-speed operation. The full-scale output range is defined by the bias current applied to the BIAS pin. The converter requires a single +3.3V power supply. The supplies for analog and digital are separated. They may be connected together. There are also two special pins: VDDS must be connected to the analog supply and VSSS must be connected to the star point of the ground. However, for maximum noise immunity it is recommended to wire all supplies on chip to separated pins, especially when the block is embedded in a large digital circuit. The supplies may then be connected on PC-board level. The proper use of blocking capacitors in the application is important! REFERENCE CURRENT OPERATING MODES There are two operating modes possible with CDAC12 depending on the bias current applied at IBIAS (625µA or 1250µA). A 25Ω or 50Ω resistance must be used to achieve an output swing of 0.5V. Revision B, 09.09.02 The reference current is equal to 1/16 of the desired full-scale current. For best performance a value of 20mA is recommended. It is important to note that the external current reference circuit must be able to source the reference current. The proper use of blocking capacitors in the application is important! Page 8 of 12 Datasheet : CDAC12 – C35 CODE TABLE The digital representation of the data bus is described in the following table. VFS = IFS * RL , VLSB = 2 * VFS 4095 VOUT = (−2047.5 + Code ) * VLSB , Input Code 1111 1111 1111 Output Voltage: VOUTP–VOUTN 2047.5*VLSB 1111 1111 1110 2046.5*VLSB … … 1000 0000 0001 1.5*VLSB 1000 0000 0000 0.5*VLSB 0111 1111 1111 –0.5*VLSB 0111 1111 1110 –1.5*VLSB … … 0000 0000 0001 –2046.5*VLSB 0000 0000 0000 –2047.5*VLSB FUNCTIONAL BLOCK DIAGRAM VDDA VDDS VDDD B11 B10 B2 B1 B0 6 MSB SWITCHES B4 B3 2 CLK 4 IOUTN Revision B, 09.09.02 4 ISB SWITCHES B5 6 FOUR EQUAL CURRENT SOURCES 4 LSB SWITCHES B7 B6 ROW DECODER B8 VSSD CURRENT SOURCE ARRAY COLUMN DECODER INPUT REGENERATION B9 VSSA VSSS FOUR BINARY CURRENT SOURCES IOUTP BIAS GENERATION IBIAS Page 9 of 12 Datasheet : CDAC12 – C35 TIMING DIAGRAM The latch of each input bit line is transparent during the time the clock is high. In order to avoid wrong data at the output of the DAC the specified setup time (Tsu) and hold time (Th) must be met. At the rising edge of the CLK signal, the pre-selected current cells are connected in parallel. After the specified propagation delay (Tpd), the converter output lines start changing towards their final value. From this point on, the converter achieves the final value within the specified settling time. The CDAC12 operates according to the following timing diagram. Tsu Th CLK B[11:0] Data Valid 90% IOUTP 10% Tpd Tr Ts Tclk IOUTN 90% 10% Tpd Revision B, 09.09.02 Tf Ts Page 10 of 12 Datasheet : CDAC12 – C35 TYPICAL APPLICATION APPLICATION The CDAC12 is suitable for applications requiring very high update rates and high resolutions, such as direct digital synthesis, high-speed communications, and instrumentation. ! ! ! ! ! ! ! WLL, Cellular Base Station Digital Microwave Links Direct Digital Synthesis (DDS) Arbitrary Waveform Generation (AWG) Medical/Ultrasound High-Speed Instrumentation and Control Video, Digital TV VDDA VDDD VDDA 625uA +3.3V VDDA 100uF 3.3uF 4.7nF 200pF 10pF Digital Pattern Vout Generation Block VSSA 50Ω 50Ω 100MHz +3.3V VDDD 22uF 3.3uF 4.7nF 200pF 10pF 6.6uF 680pF 330pF 10pF VSSD GROUND Configuration: IFS = 10mA @ fclk=100MHz VDDA VDDD VDDA 1250uA +3.3V VDDA 100uF 3.3uF 4.7nF 200pF 10pF Digital Pattern Vout Generation Block VSSA 25Ω 200MHz +3.3V VDDD 22uF 3.3uF 4.7nF 200pF 10pF 6.6uF 680pF 330pF 10pF VSSD GROUND Configuration: IFS = 20mA @ fclk=200MHz Revision B, 09.09.02 Page 11 of 12 25Ω Datasheet : CDAC12 – C35 Contact Copyright austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 [email protected] Copyright © 2002 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Revision B, 09.09.02 Page 12 of 12