app note

Application Report
SBAA094 – June 2003
Combining the ADS1202 with an FPGA Digital Filter for
Current Measurement in Motor Control Applications
Miroslav Oljaca, Tom Hendrick
Data Acquisition Products
ABSTRACT
The ADS1202 is a precision, 80dB dynamic range, delta-sigma (∆Σ) modulator operating
from a single +5V supply. The differential inputs are ideal for direct connections to
transducers or low-level signals, such as shunt resistors. With the appropriate digital filter
and modulator rate, the device can be used to achieve 15-bit analog-to-digital (A/D)
conversion with no missing codes. This application report describes how to combine the
ADS1202 with appropriate filtering techniques for current measurement in motor control.
Contents
1
Introduction .....................................................................................................................................2
1.2 ADS1202 Description ................................................................................................................2
2
∆Σ Modulator Characteristics ........................................................................................................4
3
Digital Filter Design ........................................................................................................................7
4
SincK Filter .......................................................................................................................................9
5
Sinc3 Filter Implementation ..........................................................................................................11
6
Conclusion.....................................................................................................................................16
Appendix A. ...........................................................................................................................................17
Appendix B. ...........................................................................................................................................18
Appendix C. ...........................................................................................................................................19
Figures
Figure 1. ADS1202 Block Diagram ........................................................................................................2
Figure 2. ADS1202 Output Read Operation ..........................................................................................3
Figure 3. Analog Input versus Modulator Output of the ADS1202 .....................................................3
Figure 4. Block Diagram of the 2nd-Order Modulator .........................................................................4
Figure 5. 1st and 2nd Order ∆Σ Modulator Modulation Noise ............................................................5
Figure 6. Basic Block Diagram of Decimation for ∆Σ Converter ........................................................7
Figure 7. Simple Example of a Two-Stage Network for Decimation by a Factor of N1N2 .................7
Figure 8. Multistage Decimator Incorporating Programmable DSP with FIFO Between Stages .....8
Figure 9. Sinc3 Digital Filter Topology ..................................................................................................9
Figure 10. Frequency Response of the Sinc3 Filter with M = 16 .......................................................10
Figure 11. Xilinx Integrator Implementation .......................................................................................13
Figure 12. Xilinx Differentiator Implementation .................................................................................13
Figure 13. Xilinx Sinc3 Filter Implementation .....................................................................................14
Figure 14. Clock Divider Inputs ...........................................................................................................15
1
SBAA094
Introduction
This document provides information on the operation and use of the ADS1202 ∆Σ (delta-sigma)
modulator and a detailed description of the digital filter design implemented in the Xilinx field
programmable gate array (FPGA). The latest information, along with the FPGA files and
software, can be found on the Texas Instruments web site at www.ti.com.
For this specific application, the ADS1202 and FPGA communicate with a DSP board via two
SPI™ ports. The user-interface software controls graphical display and analysis. The filter
configuration and data retrieval are set up by switches directly on the board. A complete
description of the hardware and software features of the digital filter implemented in the FPGA
for the ADS1202 is given in this application report.
1.2
ADS1202 Description
The ADS1202 is a single-channel, second-order, delta-sigma modulator operating from a single
+5V supply, as shown in Figure 1.
VIN +
VIN -
MDAT
Second-Order
LS-Modulator
MCLK
RC Oscillator
200MHz
VDD
GND
Buffer
Interface
Circuit
Reference
Voltage
2.5V
M0
M1
Figure 1. ADS1202 Block Diagram
The delta-sigma modulator converts an analog signal into a digital data stream of 1s and 0s. The
1s density of the output data stream is proportional to the input analog signal. Oversampling and
noise shaping are used to reduce the quantization noise in the frequency band of interest. This
delta-sigma modulator, with 16-bit performance, can be used with a digital filter for wide dynamic
range A/D conversion of up to its full resolution.
The primary purpose of the digital filter is to filter the noise in the signal. The secondary purpose
is to convert the 1-bit data stream at high sampling rates into a higher resolution data stream at
a lower rate (decimation).
2
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
For evaluation purposes, the ASD1202 operates in mode 3. In this mode, input control signals
M0 and M1 are HIGH; this disables the internal RC oscillator. Input signal MCLK provides a
conversion clock to the modulator. The source for output signal MDAT is the signal arriving
directly from the delta-sigma modulator. The MCLK input can have a frequency from 500kHz to
20MHz with a fixed duty cycle around 50%. In this mode, output MDAT is read on every second
falling edge of the MCLK input, as shown in Figure 2.
tC4
MCLK
tw4
tD4
MDAT
Figure 2. ADS1202 Output Read Operation
The collected output of the modulator is then passed through a digital low-pass filter. The
resulting output word is decimated and truncated to the desired data rate and effective
resolution, respectively. The combination of the delta-sigma modulator and the digital decimation
filter forms a delta-sigma A/D converter. For more detailed information and specifications
concerning the ADS1202 modulator, refer to the ADS1202 data sheet (located at www.ti.com).
The MDAT signal is a digitized representation of the analog input. Unlike the MCLK signal, it
does not have a fixed frequency or duty cycle. The duty cycle is a function of the input analog
signal, as shown in Figure 3.
Modulator Output
+FS (Analog Input)
ÐFS (Analog Input)
Analog Input
Figure 3. Analog Input versus Modulator Output of the ADS1202
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 3
SBAA094
2 ∆Σ Modulator Characteristics
The modulator sampling frequency fS can operate over a range of a few MHz to 12MHz, when
the ADS1202 is in mode 3. The input frequency of MCLK can be adjusted with the clock
requirements of the application. The MCLK input must have the double modulator frequency,
2fS. When ADS1202 operates in other modes, the modulator sampling frequency fS has a
nominal value of 10MHz and is determined by the internal oscillator.
The modulator topology is a second-order, charge-balancing A/D converter, such as the one
conceptualized in Figure 4. The analog input voltage and the output of the 1-bit Digital-to-Analog
Converter (DAC) are subtracted, providing an analog voltage at X2 and X3. The voltages at X2
and X3 are then presented to their individual integrators. The output of these integrators
progresses in either a negative or a positive direction. When the value of the signal at X4 equals
the comparator reference voltage, the output of the comparator switches from negative to
positive or positive to negative, depending on its original state. When the output value of the
comparator switches from HIGH to LOW or vice-versa, the 1-bit DAC responds on the next clock
pulse by changing its analog output voltage at X6, causing the integrators to progress in the
opposite direction. The feedback of the modulator to the front end of the integrators forces the
value of the integrator output to track the average of the input.
fCLK
X(t)
fS
X2
+
X4
X3
Integrator 1
+
-
Integrator 2
-
DATA
VREF
X6
D/A Converter
Figure 4. Block Diagram of the 2nd-Order Modulator
The process of converting an analog signal, which has infinite resolution, into a finite range
number system introduces an error signal that depends on how the signal is being
approximated. The noise transfer function of the delta-sigma modulator can be described by
following equation:
K

f 
Q( f ) =
⋅  2 ⋅ sin π 
fS 
12 ⋅ fS 
VLSB
(1)
K represents the implemented order of the delta-sigma modulator. fS is the sampling frequency,
and VLSB is the value of the least significant bit of the converter. Figure 5 presents quantization
noise for first- and second-order delta-sigma modulators up to the Nyquist frequency of the
modulator.
4
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
0
0
−20
−20
−40
−40
−60
−60
Magnitude [dB]
Magnitude [dB]
Digital low-pass filters can remove the high-frequency quantization noise without affecting the
input signal characteristics residing in base-band. For both types of modulators, the noise
increases with frequency. The greater the order of the modulator, the closer that quantization
approaches the Nyquist frequency.
−80
−100
−120
−80
−100
−120
−140
−140
−160
−160
780
3125
780
5000
Frequency [kHz]
(a) First-Order ∆Σ Modulator
3125
Frequency [kHz]
5000
(b) Second-Order ∆Σ Modulator
Figure 5. 1st and 2nd Order ∆Σ Modulator Modulation Noise
If we introduce the over-sampling ratio M, or a decimation ratio that will be implemented on the
output signal from the delta-sigma modulator, the maximum bandwidth of the input signal can be
specified as:
B=
fS
2⋅M
(2)
The RMS quantization noise present in a bandwidth of interest B can now be calculated
combining equation 1 and 2:
B
VQe,RMS = 2 ⋅
∫
0
2
VLSB
12 ⋅ fS

f 
⋅ 2 ⋅ sin π 
fS 

2K
(3)
Solving equation 3, the RMS noise in bandwidth B can be written as:
VQe,RMS =
VLSB
12
⋅
πK
⋅
1
K +1 2
2 ⋅K +1 M
(4)
The ADS1202 has implemented a second-order modulator; thus, replacing K with 2 in equation
4, we can calculate the RMS noise in bandwidth B as:
VQe,RMS =
VLSB π 2
1
⋅
⋅ 52
12
5 M
(5)
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 5
SBAA094
Finally, we can calculate the theoretical, or ideal, delta-sigma modulator signal to noise ratio
using Equation 6.
SNRideal = 20 ⋅ log


VP 2
πK
= 6.02 ⋅ N + 1.76 − 20 ⋅ log
 + (20 ⋅ K + 10 ) ⋅ log M
VQe,RMS
 2 ⋅ K + 1 
(6)
Applying Equation 6 for a different order of modulator and a different decimation ratio (oversampling), it is possible to show that the theoretically achievable SNR is within the function of
this parameter. (See Table 1.) Now it is relatively easy to determine the effective number of bits
(ENOB) for the same conditions.
Table 1. Ideal SNR and ENOB of 2nd Order ∆Σ Modulator
for Different Decimation Ratios
Decimation Ratio
(M)
Ideal SNR
(dB)
Ideal ENOB
(bits)
4
24.99
3.9
8
40.04
6.4
16
55.09
8.9
32
70.14
11.4
64
85.19
13.9
128
100.24
16.4
256
115.30
18.9
As previously mentioned, ADS1202 has a second-order modulator. Ideally, for 64-bit oversamples, the SNR is -85dB, and the effective number of bits is 13.9.
6
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
3
Digital Filter Design
The total quantization energy is very high for the delta-sigma modulator, because the number of
bits per sample is extremely low. It is left to the decimator to filter unwanted noise in the
spectrum above the Nyquist band, so that the noise is not aliased into the base-band by the
decimation process.
Decimation by the integer factor M, in principle, will reduce the sampling frequency by the same
number. Figure 6 presents the basic block diagram of the filter.
Sampling Rate
Decimator
LPF
Analog
∆Σ
Modulator
Analog
Input
x(n)
fS
1
w(n)
h(n)
p
fS
y(m)
M
p
F = fS/M
Figure 6. Basic Block Diagram of Decimation for ∆Σ Converter
The signal coming from the delta-sigma modulator x(n) is a bit stream with the frequency fS. The
signal x(n) is first digitally filtered by a low-pass filter h(n) with digital cut off frequency of π/M,
where π is the normalized (radian) frequency corresponding to the Nyquist frequency, or half of
the sampling frequency fS. The filter h(n) removes all energy from signal x(n) above the
frequency π/M, and avoids aliasing in the decimation process when the signal w(n) is resampled by the sampling rate decimator. This process is typically performed by using only one
out of every M outputs of the digital filter, as shown by Equation 7.
∞
y(m) =
∑ h(k ) ⋅ x(Mm − k )
(7)
k = −∞
This equation shows that the input signal x(n) is shifted by M samples for each new computed
output.
To keep costs low, the most important design criteria is the efficiency with which the decimator
operation can be implemented. This is directly related to the type, order and architecture of the
digital filter used in the implementation. The order of the low-pass filter, in turn, is directly related
to a function of the required characteristics of ripple in the pass-band and stop-band as the ratio
of the cut-off frequency to the stop band frequency.
Sampling Rate
Decimator
LPF1
Analog
Input
Analog
∆Σ
modulator
x(n)
1
fS
h1(n)
w(n)
p
fS
x1(n)
N1
p
Sampling Rate
Decimator
LPF2
fS/N 1
h2(n)
w1(n)
p1
fS /N1
y(m)
N2
p1
F=
Figure 7. Simple Example of a Two-Stage Network for Decimation by a Factor of N1N2
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 7
SBAA094
The combined filter order of the two-stage decimation network from Figure 7 is several times
smaller than the one-stage decimation network from Figure 6. Practical considerations of
implementing more than two stages, however, may lead to the conclusion that a two-stage
design is best.
The most popular filter architecture for delta-sigma conversion entails the combination of a SincK
filter at the high sampling rate and a finite-impulse response (FIR) or infinite-impulse response
(IIR) filter operating at intermediate and low sampling rates (see Figure 8). The suggested
design will break the decimation process into a SincK filter stage that decimates by a large factor
N1 (typically 64), followed by an FIR (or IIR) narrow-band filtering stage that decimates by a
small factor N2 (for example, 2-8).
FPGA
Programmable Digital Signal Processor (DSP)
SincK Decimation Filter
Sampling Rate
Decimator
LPF1
Analog
Input
Analog
∆Σ
Modulator
x(n)
1
fhS 1
(n)
w(n)
p
fS
Sampling Rate
Decimator
LPF2
x1(n)
N1
p
fS/N1
FIFO
x1(n)
p
fS/N1
h2(n)
w1(n)
p1
fS/N1
y(m)
N2
p1
F = fS/N1N2
Figure 8. Multistage Decimator Incorporating Programmable DSP with FIFO Between Stages
The hardware structure that implements a SincK filter can be a very simple architecture
composed of adders and registers. Such structures consume relatively little chip area. This
design will be discussed in Section 4.
8
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
4 SincK Filter
One of the most effective illustrations of matching design simplicity with the previously specified
criteria is given by the use of a SincK filter for high rate stage of decimation. These filters are very
attractive for hardware implementation because they do not require the use of digital multipliers.
They are more efficiently implemented by cascading K stages of accumulators operating at the
high sample rate (sampling frequency fS), followed by K stages of cascaded differentiators
operating at the lower sample rate, fS/N1. This architecture utilizes wrap-around arithmetic and is
inherently stable. The block diagram of the third-order Sinc filter (a Sinc3) is presented in Figure 9.
M
x(n)
1
fS
Integrator
-1
1/(1- z )
Integrator
-1
1/(1- z )
Integrator
-1
1/(1-z )
Differentiator
-1
1- z
Differentiator
-1
1- z
Differentiator
-1
1- z
y(m)
p
F = fS/M
Figure 9. Sinc3 Digital Filter Topology
Equation 8 describes the transfer function of a SincK filter, where M is the decimation ratio of the
sampling rate compressor.
K
 1 1 − z −M 

H( z ) =  ⋅
 M 1 − z −1 


(8)
Substituting Z by e-j, the frequency response obtained is:
K
 1 sin(ωM / 2 

H(e jω ) =  ⋅
 M sin(ω / 2 
(9)
where:
ω = 2π
f
fS
(10)
Figure 10 illustrates an example of the frequency response of a Sinc3 filter, from Figure 9, having
a decimation factor of M = 16. The spectral zeroes are at frequencies that are multiples of the
decimated sampling frequency.
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 9
SBAA094
0
-40
H [dB]
-80
-120
0
1
2
3
4
5
f [MHz]
Figure 10. Frequency Response of the Sinc3 Filter with M = 16
The relationship between the modulator clock (or sampling frequency fS), output data rate (or
first notch frequency), and the decimation ratio M is given by:
DataRate =
fS
M
(11)
Therefore, data rate can be used to place a specific notch frequency in the digital filter response.
In the choice of the order of the Sinc filter, it is necessary to know the order of the delta-sigma
modulator that will provide data. The order K of the SincK filter should be at least 1 plus the order
of the delta-sigma modulator in order to prevent excessive aliasing of out-of-band noise from the
modulator from entering the base-band.
K ≥ 1 + (order _ ∆Σ )
(12)
The output word size from the SincK filter is larger than the input by a factor p, which is a function
of decimation factor M and filter order K.
p = K ⋅ log2 M
(13)
Using Equation 9, it is possible to find the –3dB SincK filter response point. This point is more
dependent upon the filter order K and less dependent on the decimation ratio M. A Sinc3 filter
response point is 0.262 times the data rate.
10
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
For a sampling frequency of the delta-sigma modulator fS = 10MHz, applying Equations 7
through 13, it is possible to summarize the results for a Sinc3 filter and decimation ratio from 4 to
256, as shown in Table 2.
Table 2. Summary of the Sinc3 Filter Applied to the ADS1202
Decimation
4
Data Rate
(kHz)
2,500.0
Output Word
Size (bits)
6
Filter Response
f-3dB
(kHz)
655
8
1,250.0
9
327.5
16
625.0
12
163.7
32
312.5
15
81.8
64
156.2
18
40.9
128
78.1
21
20.4
256
39.1
24
10.2
5 Sinc3 Filter Implementation
The digital filter structure chosen to decode the output of the ADS1202 second-order deltasigma modulator is a Sinc3 digital filter. The function of the Sinc3 digital filter is to output M word
samples after each input, which represents a weighted average of the last 3(M-1)+1 input
samples. This filter can also be implemented in software using a straight linear convolution from
Equation 14:
3⋅M−1
y(k ) =
∑ h(n) ⋅ x(k − n)
(14)
n =0
where x(i) denotes the input data stream made up of ones and zeros, h(n) are the filter
coefficients, y(k) represents the decimated output data words and M is the decimation ratio. The
coefficients of the digital filter, h(n), are calculated based on the desired decimation ratio as
follows:
h(n) =
n ⋅ (n + 1)
2
0 ≤ n ≤ M −1
(15)
h(n) =
M ⋅ (M + 1)
+ (n + M) ⋅ (2 ⋅ M − 1 − n)
2
M ≤ n ≤ 2⋅M −1
(16)
h(n) =
(3 ⋅ M − n − 1) ⋅ (3 ⋅ M − n)
2
2 ⋅M ≤ n ≤ 3 ⋅M −1
(17)
The filter transfer function in Equation 8 can be implemented using a cascading series of three
integrators and three differentiators, as shown in Figure 10. The three integrators operate at the
high modulator clock frequency fS. The output from the third integrator is decimated down by M
and fed to the input of the first differentiator. The three differentiators operate at the low clock
frequency of fS /M, where M is the decimation ratio. Figure 11 and Figure 12 show the detailed
schematic of the Sinc3 digital filter, as implemented in the Xilinx FPGA.
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 11
SBAA094
The gain of the Sinc3 filter at dc is described by Equation 18. This means, for example, that for
third order filter and decimation 64, the input will be multiplied by 262,144. In this case, the result
from the filter, prior to scaling, is 18 bit.
GainDC = MK
(18)
In each added filter order, the output word size is increased by log2M. If the input is 1 bit, the
output from the first-order filter (for decimation 64) will be a 6-bit word. A second-order filter will
add another 6 bits; its output will be 13-bit, and so on. The internal bus of the Sinc filter,
integrators and differentiators, needs to have a bus width that is one bit wider than the filter’s dc
gain (see Equation 19). The results for a Sinc3 filter and a decimation ratio from 4 up to 256 are
presented in Table 3.
Bus _ Width = 1 + K ⋅ log2 M
(19)
Table 3. Output Word Size from Different Integrators
in Sinc3 Filter for 1-Bit Input Word
Sinc3
Decimation Ratio (M)
GainDC
GainDC
Bus Width
(bits)
6
(bits)
7
4
64
8
512
9
10
16
4,096
12
13
32
32,768
15
16
64
262,144
18
19
128
2,097,152
21
22
256
16,777,216
24
25
The evaluation board has the capacity to implement up to 256 decimations on the output signal
coming from ADS1202. The 25-bit word on the filter output is latched into the output data
register and transferred to a FIFO buffer. Eight words at a time will be later transferred to the
DSP via the SPI port.
12
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
Figure 11 shows the implementation of a single integrator in the Xilinx FPGA. The 25-bit wide
incoming data is continuously added to the previously accumulated result.
25
D
Q
Data Out
Data In
CLK
MCLK
Figure 11. Xilinx Integrator Implementation
Figure 12 shows the implementation of a single differentiator. The 25-bit wide incoming data is
latched onto the D flip-flop array while being subtracted from the previously latched result.
25
Data Out
Data In
MCLK/M
D
Q
CLK
Figure 12. Xilinx Differentiator Implementation
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 13
SBAA094
Integrating Figure 11 and Figure 12 into Figure 9, we can present the implemented block
diagram of the sinc3 filter into the Xilinx FPGA.
Figure 13 presents the final implementation of the filter as described by VHDL code shown in
Appendix A.
MOUT
CN1
Q
D
Q
D
CN2
Q
DELTA1
CLK
CLK
CLK
MCLK
CN3
DN0
CN4
CN5
D
Q
CLK
D
Q
CLK
DN1
D
Q
DN3
CLK
D
Q
DN5
CLK
CNR
Figure 13. Xilinx Sinc3 Filter Implementation
The Sinc3 filter circuit from Figure 13 was simulated in an Excel spreadsheet. Appendix B
presents results for a decimation ratio of 4. Appendix C presents results for a decimation ratio of
16.
14
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
The decimation ratio of the implemented Sinc3 is set up by a switch on the evaluation board. The
3-bit input data is passed to a configuration register inside the FPGA and used to program the
modulator clock frequency divider (MCLK), as shown in Figure 14. The divided clock, CNR, will
be use to update differentiators in the Sinc3 filter as well as moving this result into the FIFO
buffer. After this, the output data rate is calculated and the appropriate values are programmed
into the configuration and decimation registers inside the FPGA. For the third-order Sinc filter,
the step function response will require three clock periods. Table 4 presents the input code of
the clock divider, decimation ratio, data rate and filter response.
+5V
+5V
+5V
M2
MCLK
M1
M0
Decimation Ratio or Clock Divider
CNR = MCLK
M
Figure 14. Clock Divider Inputs
Table 4. Decimation Ratio and Filter Response
for Different Clock Divider Inputs
M2
0
M1
0
M0
0
Decimation
Ratio
(M)
4
0
0
1
8
1,250.0
2.4
0
1
0
16
625.0
4.8
0
1
1
32
312.5
9.6
1
0
0
64
156.2
19.2
1
0
1
128
78.1
38.4
1
1
0
256
39.1
76.7
Clock Divider Inputs
Data
Rate
(kHz)
2,500.0
Filter
Response
(µs)
1.2
Appendix D presents the filter response on the input step function for decimation ratios of 4, 8,
16, and 32.
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 15
SBAA094
6 Conclusion
The ADS1202 is designed for current measurement in motor control applications. The current
loop regulator typically works between 1 and 4 kHz. The signal used for this control loop must
contain information from 10 up to 40kHz, with a required resolution from 12- to 16-bits. This
application note provides designers of motor control systems with a solution for the easy
implementation of the third-order Sinc filter. Table 5 presents an overview of the different
parameters in the function of over-sampling or decimation ratio.
Table 5. Third-Order Sinc Filter Characteristics
16
Decimation
Ratio (M)
4
Ideal SNR
(dB)
24.99
Ideal ENOB
(Bits)
3.9
Data Rate
(kHz)
2,500.0
Filter Response
f-3dB
(kHz)
655
Filter
Response
(µs)
1.2
gainDC
(Bits)
6
8
40.04
6.4
1,250.0
327.5
2.4
9
16
55.09
8.9
625.0
163.7
4.8
12
32
70.14
11.4
312.5
81.8
9.6
15
64
85.19
13.9
156.2
40.9
19.2
18
128
100.24
16.4
78.1
20.4
38.4
21
256
115.30
18.9
39.1
10.2
76.7
24
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
Appendix A.
VHDL code of implemented Sinc3 filter from Figure 13.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FLT is
port(RESN, MOUT, MCLK, CNR : in std_logic;
CN5
: out std_logic_vector(24 downto 0));
end FLT;
architecture RTL of FLT is
signal DN0, DN1, DN3, DN5 : std_logic_vector(24 downto 0);
signal CN1, CN2, CN3, CN4 : std_logic_vector(24 downto 0);
signal DELTA1
: std_logic_vector(24 downto 0);
begin
process(MCLK, RESn)
begin
if RESn = '0' then
DELTA1 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
if MOUT = '1' then
DELTA1 <= DELTA1 + 1;
end if;
end if;
end process;
process(RESN, MCLK)
begin
if RESN = '0' then
CN1 <= (others => '0');
CN2 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
CN1 <= CN1 + DELTA1;
CN2 <= CN2 + CN1;
end if;
end process;
process(RESN, CNR)
begin
if RESN = '0' then
DN0 <= (others => '0');
DN1 <= (others => '0');
DN3 <= (others => '0');
DN5 <= (others => '0');
elsif CNR'event and CNR = '1' then
DN0 <= CN2;
DN1 <= DN0;
DN3 <= CN3;
DN5 <= CN4;
end if;
end process;
CN3 <= DN0 - DN1;
CN4 <= CN3 - DN3;
CN5 <= CN4 - DN5;
end RTL;
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 17
SBAA094
Appendix B.
The responses of the Sinc3 filter circuit from Figure 13 for decimation ratio 4.
Data In
K
MOUT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
18
MCLK/M
Delta1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CN1
0
0
0
0
0
0
1
3
6
10
15
21
28
36
45
55
66
78
91
105
120
8
25
43
62
82
103
125
20
44
69
95
122
22
51
81
112
16
49
83
118
CN2
0
0
0
0
0
0
0
1
4
10
20
35
56
84
120
37
92
30
108
71
48
40
48
73
116
50
4
107
104
124
40
109
76
70
92
15
96
80
96
17
100
CNR
Data Out
DN0
0
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
0
0
0
0
0
0
0
0
0
4
4
4
4
56
56
56
56
92
92
92
92
48
48
48
48
116
116
116
116
104
104
104
104
76
76
76
76
96
96
96
96
DN1
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
56
56
56
56
92
92
92
92
48
48
48
48
116
116
116
116
104
104
104
104
76
76
76
76
CN3
0
0
0
0
0
0
0
0
0
4
4
4
4
52
52
52
52
36
36
36
36
84
84
84
84
68
68
68
68
116
116
116
116
100
100
100
100
20
20
20
20
DN3
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
52
52
52
52
36
36
36
36
84
84
84
84
68
68
68
68
116
116
116
116
100
100
100
100
CN4
0
0
0
0
0
0
0
0
0
4
4
4
4
48
48
48
48
112
112
112
112
48
48
48
48
112
112
112
112
48
48
48
48
112
112
112
112
48
48
48
48
DN5
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
48
48
48
48
112
112
112
112
48
48
48
48
112
112
112
112
48
48
48
48
112
112
112
112
CN5
0
0
0
0
0
0
0
0
0
4
4
4
4
44
44
44
44
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
SBAA094
Appendix C.
The responses of the Sinc3 filter circuit from Figure 13 for decimation ratio 8.
Data In
K
MOUT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
MCLK/M
Delta1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CN1
0
0
0
0
0
0
1
3
6
10
15
21
28
36
45
55
66
78
91
105
120
136
153
171
190
210
231
253
276
300
325
351
378
406
435
465
496
528
561
595
630
CN2
0
0
0
0
0
0
0
1
4
10
20
35
56
84
120
165
220
286
364
455
560
680
816
969
116
306
516
747
1000
252
552
877
204
582
988
399
864
336
864
401
996
CNR
Data Out
DN0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
220
220
220
220
220
220
220
220
116
116
116
116
116
116
116
116
204
204
204
204
204
204
204
204
DN1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
220
220
220
220
220
220
220
220
116
116
116
116
116
116
116
116
CN3
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
216
216
216
216
216
216
216
216
920
920
920
920
920
920
920
920
88
88
88
88
88
88
88
88
DN3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
216
216
216
216
216
216
216
216
920
920
920
920
920
920
920
920
CN4
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
212
212
212
212
212
212
212
212
704
704
704
704
704
704
704
704
192
192
192
192
192
192
192
192
DN5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
212
212
212
212
212
212
212
212
704
704
704
704
704
704
704
704
CN5
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
208
208
208
208
208
208
208
208
492
492
492
492
492
492
492
492
512
512
512
512
512
512
512
512
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications 19
Application Report
SBAA094 – June 2003
Appendix D.
Third-order Sinc filter response on the step function for different decimation ratios.
Output of the third order Sinc filter with decimation ratio 16
120%
120%
100%
100%
Filter Output
Filter Output
Output of the third order Sinc filter with decimation ratio 4
80%
80%
60%
60%
40%
40%
20%
20%
0%
0%
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
0
128
8
16
24
32
40
48
56
Output of the third order Sinc filter with decimation ratio 8
72
80
88
96
104
112
120
128
112
120
128
Output of the third order Sinc filter with decimation ratio 32
120%
120%
100%
100%
80%
Filter Output
Filter Output
64
Sample
Sample
60%
40%
80%
60%
40%
20%
20%
0%
0%
0
8
16
24
32
40
48
56
64
Sample
72
80
88
96
104
112
120
128
0
8
16
24
32
40
48
56
64
72
80
88
96
104
Sample
20
Application Report
SBAA094 – June 2003
References
ADS1202 Product Data Sheet (SBAS275A)
21
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