8 6 7 2 3 4 5 1 REVISIONS POWER SUPPLY INPUT J101 3 1 2 1.6A C101 10UF APPROVED DATE INITIAL DESIGN C.R. 07/23/2010 VIN CR102 A C CR101 SH1 SIG SH2 S2A-TP RAPC722X DESCRIPTION A S2A-TP FL101 F101 REV A J103 - J106 JUMPER SETTINGS LTST-C190GKT C CR103 BNX016-01 PGND GND D R101 300 2 -> 3 1 -> 2 GND D REGULATOR CONNECTION DC POWER SUPPLY J103 1 2 3 DC POWER SUPPLY INPUT E109 1 C125 10UF GND ADP2108AUJZ-3.3-R7 GND C103 10UF GND C104 1UF R102 100K VIN 3 GND U101 SW EN FB L102 2.2UH 100NH 5 4 C105 10UF C 1 C108 10UF GND C107 1UF 39OHM GND E102 GND 2 3.3V_CLK_REG 1 C1 10UF C3 10UF C109 1UF 39OHM GND GND J102 1 1 2 3 4 5 6 GND C116 10UF GND C117 1UF GND 1 R103 100K VIN 3 SW EN FB 5 4 2.2UH 100NH C110 10UF GND GND C127 10UF GND GND GND C112 1UF ALIAS DRVDD GND AVDD_BENCH 2 R104 0 AVDD_REG REF_AVDD 39OHM C129 10UF 2 AVDD_REG GND C113 10UF C128 0.1UF E112 GND E105 C111 10UF DRVDD_REG SPI_DVDD 39OHM ADP2108AUJZ-1.8-R7 C115 10UF DRVDD_BENCH 2 1 1 C E111 3.3V GND DVDD (1.8V) GND AVDD (1.8V) GND Z5.530.3625.0 GND U102 3.3V_AMPVDD 39OHM 2 L104 3.3V_AMPVDD_REG 2 2 3.3V_AMPVDD_REG 1 GND L103 E110 E101 C106 10UF GND GND GND J106 1 2 3 C102 10UF 1 L101 3.3V_CLK 39OHM J105 1 2 3 VIN C126 0.1UF J104 1 2 3 SUPPLY REGULATORS 3.3V_CLK_REG 2 C130 0.1UF ALIAS AVDD R105 0 GND 39OHM GND 2 E107 GND 1 C2 10UF B C4 10UF C114 1UF 2 DRVDD_REG 39OHM B GND GND GND TP102 BLK TP101 BLK GND POWER SUPPLY A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, A SCHEMATIC AD9286 CUSTOMER EVALUATION BOARD AD9286 DESIGN VIEW REV DRAWING NO. - A 9286CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 1 OF 7 8 6 7 2 3 4 5 1 REVISIONS REV AVDD PIN 1 AVDD DESCRIPTION DATE APPROVED AVDD C201 .1UF C202 .1UF DNI DNI D D R1 0 GND J201 DRVDD PIN 20 DRVDD AVDD PIN 4 AVDD DRVDD C219 .1UF C204 .1UF SCLK_DUT SCLK_DUT_CMOS_LVDS DRVDD C220 .1UF 1-2 SPI MODE (SCLK) 1 2-3 LVDS MODE 2 NO CONNECT CMOS MODE (DEFAULT) 3 SAMTECTSW10608GS3PIN DNI GND GND J202 DNI GND B AVDD PINS 16 AVDD C214 .1UF GND AVDD PINS 45 AVDD C215 .1UF C216 .1UF DNI GND AVDD PINS 48 AVDD C218 .1UF GND AVDD GND 1 DNI V_P DNI U202 ADR512ARTZ-REEL7 DNI R206 0 0 V_N DNI 2 GND DRVDD D6A(D7A-/D7B-) D7A(D7A+/D7B+) DRVDD DRGND OUTPUT_ENABLE D7B/(D3A+/D3B+) AIN B+ D6B/(D3A-/D3B-) AIN B- D5B/(D2A+/D2B+) AVDD D5A_D6P D4A_D6M D3A_D5P D2A_D5M D1A_D4P D0A_D4M DCO_A DCO_B D7B_D3P D6B_D3M D5B_D2P D4B_D2M D3B/(D1A+/D1B+) D2B/(D1A-/D1B-) D4B/(D2A-/D2B-) D3B_D1P D2B_D1M D1B_D0P D0B_D0M R204 5K DRVDD B J204 CONNECT -> CLKB ENABLED 1 DEFAULT LOW -> CLKB DISABLED 2 TSW-102-08-G-S 3 DNI GND SPI_SDIO/PWRDN DCOB/(DCO-) AVDD 24 23 22 21 20 19 18 17 16 15 14 13 R202 0 R203 3 TRIM DCOA/(DCO+) D1B/(D0A+/D0B+) R201 2.7K D0A/(D4A-/D4B-) 65/135/250 MSPS DNI C224 0.1UF SPI_SCLK/CMOS_LVDS ENC A- SPI_CSB ENC A+ AVDD 36 35 34 33 32 31 30 29 28 27 26 25 AVDD REF IN D0B/(D0A-/D0B-) DNI AVDD GND D1A/(D4A+/D4B+) AD9286 AVDD DRVDD DNI C223 0.1UF GND REF_AVDD D2A/(D5A-/D5B-) CMV OUT DRGND C212 .1UF REF IN CKT DNI D3A/(D5A+/D5B+) AVDD CLOCK B ENABLE C211 .1UF GND C227 0.1UF AVDD D7A_D7P D6A_D7M D4A/(D6A-/D6B-) GND DRVDD AVDD PINS 13 AVDD C226 0.1UF C D5A/(D6A+/D6B+) AIN A+ RBIAS GND AVDD GND AIN A- ENC B- DNI AVDD CMV_OUT AVDD ENC B+ C210 .1UF AINAIN+ 37 38 39 40 41 42 43 44 45 46 47 48 PAD AVDD C209 .1UF AVDD AVDD AVDD PINS 12 AVDD DEFAULT HIGH -> OUTPUT DISABLED 1 CONNECT -> OUTPUT ENABLED 2 TSW-102-08-G-S 1 2 3 4 5 6 7 8 9 10 11 12 GND U201 SG-MLF-7006 AVDD AVDD ENC_B+ ENC_B- C208 .1UF GND 2 RBIAS CW C DNI SHARE PADS AVDD PINS 8 & 9 AVDD J203 1 DECOUPLING CAPACITORS, ONE ON THE TOP AND ONE ON THE BOTTOM CLOSE TO THE PINS GND C222 .1UF 1-2 SPI MODE (SDIO) 1 2-3 PWRDN MODE 2 NO CONNECT (DEFAULT) 3 SAMTECTSW10608GS3PIN AVDD AVDD ENC_A+ ENC_ACSB_DUT SDIO_DUT_PWRDN SCLK_DUT_CMOS_LVDS C221 .1UF C206 .1UF A SDIO_DUT SDIO_DUT_PWRDN DRVDD DRVDD PIN 39 DRVDD AVDD PIN 6 AVDD C225 0.1UF DNI 10K GND DNI R205 10K TP201 1 BLK GND DUT AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC AD9286 CUSTOMER EVALUATION BOARD AD9286 DESIGN VIEW REV DRAWING NO. - A 9286CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 A JON HARRIS 2 SCALE NONE SHEET 1 2 OF 7 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED D D SPI CIRCUITRY SPI_DVDD C301 0.1UF R302 1.1K 3.3V_CLK GND C C R303 1.1K SDIO_DUT VCC Y1 3 A2 Y2 4 2 GND 6 1 A1 GND 100K R304 10K R301 USB_SDI R305 1.1K 5 USB_SDO U301 NC7WZ07P6X GND SPI_DVDD GND 5 100K GND R308 R310 0 C302 0.1UF 10K R306 DNI VCC 1 A1 Y1 6 USB_SCLK 3 A2 Y2 4 B 2 10K R307 GND CSB_DUT SCLK_DUT U302 NC7WZ16P6X 100K USB_CSB R309 SDIO_DUT_1P8 B GND GND GND DNI DNI R311 0 R312 0 CSB_DUT_1P8 SCLK_DUT_1P8 SPI A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC AD9286 CUSTOMER EVALUATION BOARD AD9286 DESIGN VIEW REV DRAWING NO. - A 9286CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 A JON HARRIS 2 SCALE NONE SHEET 1 3 OF 7 8 6 7 2 3 4 5 1 REVISIONS REV D DESCRIPTION DATE APPROVED D PASSIVE PATH LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER C403 0 0.1UF AIN_A - 2 3 4 5 R402 49.9 3 ETC1-1-13 SEC PASSIVE_OUT- 3 ETC1-1-13 4 GND 0.1UF DNI DNI PASSIVE_OUT+ 0.1UF R405 0 DNI GND SEC 0.1UF C404 0 DNI 1 4 ADT1-1WT+ PRI 4 R404 1 J402 DNI 2 C402 1 DNI GND T402 5 PRI 3 T401 6 DNI GND T403 1 R401 49.9 2 3 4 5 5 AIN_A + C401 R403 1 J401 GND GND C C COMMON PATH AMP_OUT- DNI R406 0 0 R412 R414 R416 33 0 0 AIN- 2 3 4 5 B R448 DNI R411 33 J405 1 AIN_AMP 2.7PF 0 C407 R449 C406 CMV_OUT 4.7PF R410 33 DNI R407 PASSIVE_OUT- TBD0402 SHARE PADS R436 61.9 ACTIVE PATH DNI GND GND R438 R440 200 200 PASSIVE_OUT+ R408 R413 R415 R417 0 33 0 0 SHARE PADS AIN+ B R409 0 DNI 3.3V_AMPVDD C417 R442 GND CMV_OUT 10UF 0 R450 FB-OUT -OUT +OUT FB+OUT 1 11 10 4 -VS R443 GND ADA4937-1YCPZ-R7 R439 R441 200 200 AMP_OUT- 24 1 2 3 4 5 A VOCM +IN -IN PD_N PAD 16 15 14 13 0.1UF GND DNI 24 +VS 9 2 3 12 PAD C416 J406 5 6 7 8 U401 AMP_OUT+ AMP_OUT+ R437 27.4 ANALOG INPUT GND GND AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, A SCHEMATIC AD9286 CUSTOMER EVALUATION BOARD AD9286 DESIGN VIEW REV DRAWING NO. - A 9286CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 4 OF 7 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED XFMR / BALUN CLK CIRCUITRY DNI DNI C501 R503 SHARE PADS? R501 49.9 C503 0.1UF DNI ADT1-1WT+ T501 DNI DNI GND GND C505 C502 R504 1 SILKSCREEN ON BOARD = CLK+ 2 3 4 5 R502 49.9 GND 0.1UF 4 0 0.1UF DNI 1 0.1UF 0.1UF R506 24.9 GND R508 R510 0 0 C508 ENC_A+ 0.1UF GND LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER OPTIONAL TERMINATION NEAR DUT HMPS-2822-BLK T502 PRI ENC_A- CR501 TP501 BLK DNI 0 C506 2 J502 0 C507 SHARE PADS CLK_A + R509 R505 24.9 6 3 R507 D R511 0 DNI DNI 2 3 4 5 SILKSCREEN ON BOARD = CLK- 0 0.1UF 100 D CLK_A - XSTAL_INSHARE PADS 1 R512 J501 SEC R513 0 DNI XSTAL_IN+ -(NC)- C504 1000PF MABA-007159-000000 GND C C OPTIONAL CRYSTAL OSCIALLATOR CLOCK SOURCE C517 3.3V_CLK 0.1UF DNI GND Y505 6 VDD DNI 1 TRISTATE 2 NC Q Q_N 3 DNI DNI XSTAL_IN+ XSTAL_IN- 500MEGHZ DNI GND R527 130 4 5 GND R525 1K R526 130 GND R528 75 R529 75 DNI DNI GND OPTIONAL CLOCK B INPUT 1 2 3 4 5 R515 49.9 TP502 BLK DNI T503 ADT1-1WT+ 1 DNI 4 DNI GND 2 R520 R522 0 0 R518 24.9 C513 C515 ENC_B- 0.1UF CR503 C514 J503 SHARE PADS? 1 CLK_B 2 3 4 5 R514 49.9 0.1UF C509 DNI DNI R516 GND 0.1UF 3 0 6 0.1UF R519 24.9 C511 0.1UF DNI CLK_B + B R517 0 100 J504 R524 B C510 0.1UF OPTIONAL TERMINATION NEAR DUT HMPS-2822-BLK GND R521 R523 0 0 MABA-007159-000000 C516 ENC_B+ 0.1UF GND GND 6 LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER DNI C512 1000PF A 1 PRI SEC 4 5 3 2 -(NC)- CLOCK T504 A GND AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC AD9286 CUSTOMER EVALUATION BOARD AD9286 DESIGN VIEW REV DRAWING NO. - A 9286CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 5 OF 7 8 7 6 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED D D 0 OHM RESISTOR NETWORK FOR LVDS MODE 22 OHM RESISTOR NETWORK FOR CMOS MODE D7A_D7P 1 RN601 16 D7B_D3P 1 O_D7A C D6B_D3M O_D6A CHANNEL B CHANNEL A D6A_D7M 0 D5A_D6P 3 RN601 14 O_D5A 0 D4A_D6M 4 RN601 13 O_D4A 0 D3A_D5P RN601 5 12 O_D7B 0 0 RN601 2 15 RN602 16 2 RN602 15 O_D6B 0 D5B_D2P 3 RN602 14 O_D5B 0 D4B_D2M 4 RN602 13 O_D4B 0 D3B_D1P 5 O_D3A RN602 12 C O_D3B 0 0 D2A_D5M RN601 6 11 D2B_D1M 6 O_D2A RN602 11 O_D2B 0 0 D1A_D4P 7 RN601 10 D1B_D0P 7 O_D1A RN602 10 O_D1B 0 0 D0A_D4M RN601 8 9 D0B_D0M O_D0A 8 RN602 9 O_D0B 0 0 B B DCO DCO_A R601 O_DCO_A 0 DCO_B R602 O_DCO_B 0 OUTPUT NETWORK A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, A SCHEMATIC AD9286 CUSTOMER EVALUATION BOARD AD9286 DESIGN VIEW REV DRAWING NO. - A 9286CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 6 OF 7 8 7 6 5 2 3 4 1 REVISIONS REV DESCRIPTION DATE APPROVED D D 6469169-1 B GND 6469169-1 PLUG HEADER PLUG HEADER C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 CSB_DUT_1P8 O_D0B O_D4B O_D0A O_D4A P1 6469169-1 P1 P2 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 GND GND 6469169-1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 PLUG HEADER P1 6469169-1 USB_SDO USB_SDI USB_SCLK C 6469169-1 PLUG HEADER BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 PLUG HEADER P2 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 6469169-1 6469169-1 P2 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 P1 6469169-1 P1 PLUG HEADER O_D1B O_D5B O_D1A O_D5A C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 USB_CSB O_D2B O_D6B O_D2A O_D6A 6469169-1 PLUG HEADER SDIO_DUT_1P8 SCLK_DUT_1P8 PLUG HEADER P2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 O_DCO_B PLUG HEADER 6469169-1 C B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 PLUG HEADER O_D3B O_D7B O_D3A O_D7A P1 P2 PLUG HEADER A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 O_DCO_A PLUG HEADER P2 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 6469169-1 B GND FIFO5 CONNECTIONS A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, A SCHEMATIC AD9286 CUSTOMER EVALUATION BOARD AD9286 DESIGN VIEW REV DRAWING NO. - A 9286CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 7 OF 7