REVISIONS LTR DESCRIPTION DATE APPROVED A Correct lead finish on last page. Update boilerplate. - CFS 05-11-01 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-06-04 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 REV B B B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 REV STATUS OF PAGES PMIC N/A PREPARED BY RICK OFFICER Original date of drawing CHECKED BY TOM HESS 02-12-12 APPROVED BY RAYMOND MONNIN SIZE A REV AMSC N/A CODE IDENT. NO. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 TITLE MICROCIRCUIT, DIGITAL-LINEAR, CMOS, 12BIT, ANALOG-TO-DIGITAL CONVERTER, MONOLITHIC SILICON DWG NO. V62/03609 16236 B PAGE 1 OF 28 5962-V060-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance linear-digital microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03609 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function THS1206-EP CMOS, 12-bit, 6 MSPS, analog-to-digital converter 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins X 32 JEDEC PUB 95 Package style MO-153 Plastic thin shrink small outline package with gull wing leads 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage range: DGND to DVDD ..................................................................................... -0.3 V to 6.5 V BGND to BVDD ..................................................................................... -0.3 V to 6.5 V AGND to AVDD ..................................................................................... -0.3 V to 6.5 V Analog input voltage range ...................................................................... AGND – 0.3 V to AVDD + 1.5 V Reference input voltage ........................................................................... -0.3 V + AGND to AVDD + 0.3 V Digital input voltage range ........................................................................ -0.3 V to BVDD / DVDD + 0.3 V Power dissipation (PD) (TA ≤ 25°C) ........................................................ 1453 mW 2/ Operating virtual junction temperature range (TJ) .................................... -55°C to +150°C Storage temperature range ...................................................................... -65°C to +150°C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ............. 260°C 1.4 Recommended operating conditions. 3/ Power supply section Supply voltage: AVDD ..................................................................................................... 4.75 V to 5.25 V DVDD ..................................................................................................... 3 V to 5.25 V BVDD ..................................................................................................... 3 V to 5.25 V Analog and reference inputs section Analog input voltage in single-ended configuration .................................. VREFM to VREFP Common-mode input voltage VCM in differential configuration ................ 1 V to 4 V External reference voltage, VREFP ........................................................... AVDD – 1.2 V maximum External reference voltage, VREFM ........................................................... 1.4 V minimum Digital inputs section High-level input voltage (VIH): With BVDD = 3.3 V ................................................................................ 2 V minimum With BVDD = 5.25 V .............................................................................. 2.6 V minimum Low-level input voltage (VIL) With BVDD = 3.3 V ................................................................................ 0.6 V maximum With BVDD = 5.25 V .............................................................................. 0.6 V maximum Input CONV_CLK frequency, (with DVDD = 3 V to 5.25 V) ...................... 0.1 MHz to 6 MHz CONV_CLK pulse duration, clock high, tW (CONV_CLKH): With DVDD = 3 V to 5.25 V ................................................................... 80 ns to 5000 ns CONV_CLK pulse duration, clock low, tW (CONV_CLKL): With DVDD = 3 V to 5.25 V ................................................................... 80 ns to 5000 ns Ambient operating temperature (TA) ........................................................... -55°C to +125°C 1/ 2/ 3/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The derating factor above TA = +25°C is 11.62 mW/°C. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 – Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http://www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 4 TABLE I. Electrical performance characteristics. Test Symbol Digital input section High-level input current IIH Low-level input current IIL Input capacitance CIN High-level output voltage VOH Low-level output voltage VOL High-impedance-state output current IOZ Output capacitance COUT Load capacitance at databus D0 – D11 CL Resolution Integral nonlinearity RES INL Differential nonlinearity DNL Offset error OE 2/ 1/ Conditions -55°C ≤ TA ≤ +125°C Limits Unit Min Max DVDD = digital inputs -50 50 µA Digital input = 0 V -50 50 µA 5 TYP IOH = -50 µA, BVDD = 3.3 V BVDD – 0.5 IOH = -50 µA, BVDD = 5 V BVDD – 0.5 pF V IOL = 50 µA, BVDD = 3.3 V 0.4 IOL = 50 µA, BVDD = 5 V 0.4 -10 CS1 = DGND, CS0 = DVDD 10 5 TYP -20 µA pF 30 pF ±1.8 Bits LSB 12 After calibration in differential mode After calibration in single-ended mode V ±1 20 LSB 20 LSB ±10 µA LSB 20 TYP Gain error 2/ Analog input section Input capacitance GE -20 Input leakage current IINL Internal voltage reference section Accuracy VREFP 3.3 3.7 V VREFM 1.3 1.7 V REFOUT TC 2.3 Temperature coefficient Reference noise RN Power supply section Analog supply current IDDA Digital supply current 15 TYP CIN VAIN = VREFM to VREFP 2.7 V 50 TYP PPM/°C 10 TYP µV 40 mA IDDD 1 mA Buffer supply current IDDB 4 mA Supply current in power-down mode IDD P 10 mA Power dissipation PD 216 mW Power dissipation In power down PD AVDD = 5 V, BVDD = DVDD = 3.3 V 30 TYP mW See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 5 TABLE I. Electrical performance characteristics – Continued. Test Symbol 1/ Conditions -55°C ≤ TA ≤ +125°C Limits Min Unit Max AC section Signal-to-noise ratio + distortion 3/ SINAD Differential mode 63 Single-ended mode 4/ Signal-to-noise ratio 3/ SNR Differential mode 64 Single-ended mode 4/ Total harmonic distortion 3/ THD 68 TYP Differential mode -67 Single-ended mode Effective number of bits Spurious free dynamic range ENOB (SNR) 3/ SFDR Analog input section Full power bandwidth with a source impedance of 150 Ω in differential configuration Full power bandwidth with a source impedance of 150 Ω in single ended configuration Small signal bandwidth with a source impedance of 150 Ω in differential configuration Small signal bandwidth with a source impedance of 150 Ω in single ended configuration Timing specification section Delay time Delay time Latency Timing section Clock cycle of the internal clock oscillator dB 64 TYP -68 TYP Differential mode 10.17 Single-ended mode 4/ Bits 10.4 TYP Differential mode 67 dB Single-ended mode 69 TYP FS sinewave, -3 dB 96 TYP FS sinewave, -3 dB 54 TYP 100 mVpp sinewave, -3 dB 96 TYP 100 mVpp sinewave, -3 dB 54 TYP MHz td(DATA_AV) td(o) tpipe 5/ Pulse width, CONVST 5/ Aperture time ns CONV CLK 159 tC t1 1 analog input 1.5 x tC 2 analog input 2.5 x tC 3 analog input 3.5 x tC 4 analog input 4.5 x tC 1 TYP tdA Time between consecutive start of single conversion t2 5/ 1 analog input 2 x tC 2 analog input 3 x tC 3 analog input 4 x tC 4 analog input 5 x tC 175 ns See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 6 TABLE I. Electrical performance characteristics – Continued. Test Symbol 1/ Conditions -55°C ≤ TA ≤ +125°C Limits Min Unit Max Timing section - continued Delay time, DATA-AV becomes active for the trigger level condition: TRIG0 = 0, TRG1 = 0 td(DATA_AV) 5/ Delay time, DATA-AV becomes active for the trigger level condition: TRIG0 = 1, TRG1 = 0 td(DATA-AV) 5/ Delay time, DATA-AV becomes active for the trigger level condition:TRIG0 = 0, TRG1 = 1 1/ 2/ 3/ 4/ 5/ 6 x tC 2 analog inputs, TL = 2 7 x tC 3 analog inputs, TL = 3 8 x tC 4 analog inputs, TL = 4 9 x tC 1 analog input, TL = 4 3 x t2 + 6 x tC 2 analog inputs, TL = 4 t2 +7 x tC 3 analog inputs, TL = 6 t2 + 8 x tC 4 analog inputs, TL = 8 t2 + 9 x tC 1 analog input, TL = 8 7 x t2 + 6 x tC 2 analog inputs, TL = 8 3 x t2 + 7 x tC 3 analog inputs, TL = 9 2 x t2 + 8 x tC 4 analog inputs, TL = 12 2 x t2 + 9 x tC 1 analog input, TL = 14 13 x t2 + 6 x tC 2 analog inputs, TL = 12 5 x t2 + 7 x tC 3 analog inputs, TL = 12 3 x t2 + 8 x tC td(DATA-AV) 5/ Delay time, DATA-AV becomes active for the trigger level condition: TRIG0 = 1, TRG1 = 1 1 analog input, TL = 1 td(DATA-AV) 5/ ns Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. This test is not production tested. fS = 6 MHz, f1 = 2 MHz at –1 dBFS, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF. The SNR (ENOB) and SINAD is degraded typically be 2 dB in single-ended mode when the reading of data is asynchronous to the sampling clock. This timing parameter is ensured by design but is not tested. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 7 Case outline X Terminal symbol A A1 b C D e E E1 L Q N Millimeters Min ----0.19 0.15 10.90 --6.20 7.80 0.50 0.05 Max 1.20 0.25 0.30 --11.10 0.65 --8.40 0.75 0.15 32 NOTE: All dimensions are in millimeters. FIGURE 1. Case outlines. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 8 Device type Case outline Terminal number Terminal symbol 01 X Terminal number Terminal symbol 1 2 D0 D1 17 18 DGND 3 D2 19 RD 4 D3 20 5 6 D4 D5 21 22 WR (R / W ) CS1 7 BVDD 23 AVDD 8 9 10 11 12 13 14 15 BGND D6 D7 D8 D9 D10 / RA0 D11 / RA1 CONV_CLK ( CONVST ) 24 25 26 27 28 29 30 31 AGND REFM REFP REFOUT REFIN BINM BINP AINM 16 DATA_AV 32 AINP DVDD CS0 FIGURE 2. Terminal connection. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 9 Terminal symbol I/O AINP AINM BINP BINM I I I I I Analog input, single-ended or positive input of differential channel A Analog input, single-ended or negative input of differential channel A Analog input, single-ended or positive input of differential channel B Analog input, single-ended or negative input of differential channel B Analog supply voltage I I Analog ground Digital supply voltage for buffer I I Digital ground for buffer Digital input. This input is used to apply an external conversion clock in continuous conversion mode. In single conversion mode, this input functions as the conversion start ( AVDD AGND BVDD BGND CONV_CLK ( CONVST ) CS0 I CS1 DATA_AV I O DGND Description CONVST ) input. A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs. Chip select input (active low) Chip select input (active high) Data available signal, which can be used to generate an interrupt for processors and as level information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. Digital ground. Ground reference for digital circuitry. Digital supply voltage. DVDD I I D0-D9 D10/RA0 I/O/Z I/O/Z D11/RA1 I/O/Z REFIN I REFP I REFM I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. REFOUT O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output requires a capacitor of 10 µF to AGND for filtering and stability. RD (See note) I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active low as a data read select from the processor. WR (R / W ) (See note) I This input is programmable. It functions as a read-write input R / W and can also be Digital input, output; D0 = LSB Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is required for writing to the control register 0 and control register 1. Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REFOUT. Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. configured as write-only input WR , which is active low and used as data write selection from the processor. In this case, the RD input is used as a read input from the processor. NOTE: The start-conditions of RD and WR (R / W ) are unknown. The first access to the ADC has to be a write access to initialize the ADC. FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 10 Reference voltage This device has a built in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins. REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full scale and zero scale reading respectively. Analog inputs This device consists of 4 analog input, which are sampled simultaneously. These inputs can be selected individually and configured as single ended or differential inputs. The desired analog input channel can be programmed. Converter This device uses a 12-bit pipelined multi-staged architecture with 4 1-bit stages followed by 4 2-bit stages, which achieves a high sample rate with low power consumption. This device distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample and hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples. Conversion modes The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is initiated by an external signal ( CONVST ). An internal oscillator controls the conversion time. In the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal. Sampling rate The maximum possible conversion rate per channel is dependent on the selected analog input channels. The table below shows the maximum conversion rate in the continuous conversion mode for different combinations. Maximum conversion ratio in continuous conversion mode Channel configuration Number of channels 1 single ended channel 2 single ended channels 3 single ended channels 4 single ended channels 1 differential channel 2 differential channels 1 single ended and 1 differential channel 2 single ended and 1 differential channels 1 2 3 4 1 2 2 3 Maximum conversion rate per channel 6 MSPS 3 MSPS 2 MSPS 1.5 MSPS 6 MSPS 3 MSPS 3 MSPS 2 MSPS The maximum conversion rate in the continuous conversion mode per channel, fC is given by: fC = 6 MSPS / (number of channels) FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 11 Sampling rate – continued. Maximum conversion rate in single conversion mode Channel configuration Number of channels 1 single ended channel 2 single ended channels 3 single ended channels 4 single ended channels 1 differential channel 2 differential channels 1 single ended and 1 differential channel 2 single ended and 1 differential channels 1 2 3 4 1 2 2 3 Maximum conversion rate per channel 3 MSPS 2 MSPS 1.5 MSPS 1.2 MSPS 3 MSPS 2 MSPS 1.5 MSPS 1.2 MSPS Digital output data format The digital output data format of this device can either be in binary format or in two’s complement format. The following tables list the digital outputs for the analog input voltages. Binary output format for single ended configuration Analog input voltage AIN = VREFP Digital output code FFFh AIN = (VREFP + VREFM) / 2 800h AIN = VREFM 000h Two’s complement output format for single ended configuration Analog input voltage AIN = VREFP Digital output code 7FFh AIN = (VREFP + VREFM) / 2 000h AIN = VREFM 800h Binary output format for differential configuration Analog input voltage Vin = AINP – AINM VREF = VREFP - VREFM Digital output code Vin = VREF FFFh Vin = 0 800h Vin = -VREF 000h FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 12 Digital output data format – continued. Two’s complement output format for differential configuration Analog input voltage Vin = AINP – AINM VREF = VREFP - VREFM Digital output code Vin = VREF 7FFh Vin = 0 000h Vin = -VREF 800h ADC control register This device contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in the table below. Bit definitions of control register CR0 and CR1 BIT CR0 BIT 9 TEST1 BIT 8 TEST0 BIT 7 SCAN BIT 6 DIFF1 BIT 5 DIFF0 BIT 4 CHSEL1 BIT 3 CHSEL0 BIT 2 PD BIT 1 MODE BIT 0 CR1 RBACK OFFSET BIN/2’s R/W DATA_P DATA_T TRIG1 TRIG0 OVFL/FRST VREF RESET Writing to control register 0 and control register 1 The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC. The addressing is performed with the upper data bits D10 and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0 to D9 contain the desired control register value. The table below shows the addressing of each control register. Control register addressing D0-D9 Desired register value Desired register value Desired register value Desires register value D10/RA0 D11/RA1 0 1 0 1 0 0 1 1 Addressed control register Control register 0 Control register 1 Reserved for future Reserved for future FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 13 ADC control registers Control register 0 BIT 9 TEST1 BIT 8 TEST0 BIT 7 SCAN BIT 6 DIFF1 BIT 5 DIFF0 BIT 4 CHSEL1 BIT 3 CHSEL0 BIT 2 PD BIT 1 MODE BIT 0 VREF Control register 0 bit functions Bits 0 Reset value 0 Name 1 0 MODE VREF Function VREF select: Bit 0 = 0 → The internal reference is selected Bit 0 = 1 →The external reference voltage to selected. Continuous conversion mode/single conversion mode Bit 1 = 0 → Continuous conversion mode is selected. An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the CONV_CLK signal a new converted value is written into the FIFO. Bit 1 = 1 → Single conversion mode is selected. In this mode, the CONV_CLK input function as a CONVST input. A single conversion is initiated on the device by pulsing the CONVST 2 0 PD 3,4 0,0 CHSEL0, CHSEL1 5,6 1,0 DIFF0, DIFF1 7 0 SCAN 8,9 0,0 TEST0, TEST1 input. On the falling edge of CONVST , the sample and hold stages of the selected analog inputs are placed into hold simultaneously and the conversion sequence for the selected channels is started. The signal DATA_AV (data available) becomes active when the trigger condition is satisfied. Power down Bit 2 = 0 → The ADC is active Bit 2 = 1 → Power down The reading and writing to and from the digital outputs is possible during power down. It is also possible to read out the FIFO. Channel select. Bit 3 and bit 4 select the analog input channel of the ADC. Refer to the analog input channel configuration table. Number of differential channels. Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to the analog input channel configuration table. Autoscan enable. Bit 7 enables or disables the autoscan function of the ADC. Refer to the analog input channel configuration table. Test input enable. Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This feedback allows the check of all hardware connections and the ADC operation. Refer to the test mode table for selection of the three different test voltages. FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 14 Analog input channel selection The analog input channels of the device can be selected via bits 3 to 7 of control register 0. One single channel (single ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. The table below shows the possible selections. Analog input channel configuration Bit 7 SCAN 0 0 0 0 0 0 1 Bit 6 DIFF1 0 0 0 0 0 0 0 Bit 5 DIFF0 0 0 0 0 1 1 0 Bit 4 CHSEL1 0 0 1 1 0 0 0 Bit 3 CHSEL0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 1 Description of the selected inputs Analog input AINP (single ended) Analog input AINM (single ended) Analog input BINP (single ended) Analog input BINM (single ended) Differential channel (AINP - AINM) Differential channel (BINP - BINM) Autoscan two single ended channels: AINP, AINM, AINP,… Autoscan three single ended channels: AINP, AINM, BINP, AINP,… Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP,... Autoscan one differential channel and one single ended channel AINP, (BINP - BINM), AINP, (BINP - BINM),… Autoscan one differential channel and two single ended channel AINP, AINM, (BINP - BINM), AINP,… Autoscan two differential channels (AINP - AINM), (BINP - BINM), (AINP - AINM),… Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 15 Analog input channel selection – continued. Test mode The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The differential sections are shown in the table below. Three different options can be selected. This feature allows support testing of hardware connections between the ADC and the processor. Bit 9 Test1 0 0 Bit 8 Test0 0 1 Output result 1 0 ((VREFM) + (VREFP)) / 2 1 1 VREFM Normal mode VREFP Control register 1 BIT 9 RBACK BIT 8 OFFSET BIT 7 BIN/2’s BIT 6 R/ W BIT 5 DATA_P BIT 4 DATA_T BIT 3 TRIG1 BIT 2 TRIG0 BIT 1 OVFL/FRST BIT 0 RESET Control register 1 bit functions Bits 0 Reset value 0 1 0 Name Function RESET Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values. In addition, the FIFO pointer and offset register is reset. After reset, it takes 5 clock cycles until the first value is converted and written into the FIFO. Overflow flag (read only) Bit 1 of control register 1 indicates an overflow in the FIFO. Bit 1 = 0 → no overflow occurred. Bit 1 = 1 → an overflow occurred. This bit is reset to 0, after this control register is read from the processor. FRST: FIFO reset (write only) By writing a 1 into this bit, the FIFO is reset. FIFO trigger level Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached, the signal DATA_AV (data available) becomes active according to the settings of DATA_T and DATA_P. This indicates to the processor that the ADC values can be read. Refer to the FIFO trigger level table. DATA_AV type. Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static ( for edge or level sensitive interrupt inputs ). If it is set to 0, the DATA_AV signal is static. If it is set to 1, the DATA_AV signal is a pulse. Refer to DATA_AV type table. OVFL (read only) 2,3 0,0 FRST (write only) TRIG 0, TRIG 1 4 1 DATA_T FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 16 Control register 1 bit functions - continued Bits Name Function 5 Reset value 1 DATA_P DATA_AV polarity. Bit 5 of control register 1 control the polarity of DATA_AV. If it is set to 1, DATA_AV is active high. If it is set to 0, DATA_AV is active low. Refer to the DATA_AV type table. 6 0 R/ W R/ W , RD/ WR selection. Bit 6 of control register 1 controls the function of the inputs RD and WR . When bit 6 in control register 1 is set to 1, WR becomes a R/ W input and RD is disabled. From now on, a read is signalled with R/W high and write with R/W as low signal. If bit 6 in control register 7 0 BIN/2’s 8 0 OFFSET 9 0 RBACK 1 is set to 0, the input RD becomes a read input and the input WR becomes a write input. Complement select. If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of control register 1 is set to 1, the output value of the ADC is in binary format. Refer to digital output data format tables.. Offset cancellation mode. Bit 8 = 0 → normal conversion mode Bit 8 = 1 → offset calibration mode If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion results is stored in an offset register and subtracted from all conversions in order to reduce the offset error. Debug mode. Bit 9 = 0 → normal conversion mode Bit 9 = 1 → enable debug mode. When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of control register 0. The second read after bit 9 is set to 1 contains the value of control register 1. FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 17 FIFO trigger level Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO. If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to indicate to the processor that the ADC values can be read. The table below shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be selected, is dependent on the number of input channels. Both, a differential or single ended input is considered as one channel. The processor therefore always reads the data from the FIFO in the same order and is able to distinguish between the channels. Bit 3 TRIG1 Bit 2 TRIG0 0 0 1 1 0 1 0 1 Trigger level for 1 channel (ADC values) 01 04 08 14 Trigger level for 2 channels (ADC values) 02 04 08 12 Trigger level for 3 channel (ADC values) 03 06 09 12 Trigger level for 4 channels (ADC values) 04 08 12 Reversed DATA_AV type Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of DATA_AV. This is shown in the table below. Bit 5 DATA_P 0 0 1 1 Bit 4 DATA_T 0 1 0 1 DATA_AV type Active low level Active low pulse Active high level Active high pulse FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 18 FIGURE 3. Block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 19 In this mode, up to four analog input channels can be selected to be sampled simultaneously. The maximum throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case of a trigger level set to 1 or 4. FIGURE 4. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 20 The maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 2 or 4. The maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 3. FIGURE 4. Timing waveforms – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 21 CONTINUOUS CONVERSION MODE (4-CHANNEL OPERATION) The maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DATA_AV signal here is for a trigger level of 4. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse. FIGURE 4. Timing waveforms – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 22 The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse. FIGURE 4. Timing waveforms. – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 23 The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse. FIGURE 4. Timing waveforms. – continued. This diagram shows the read timing behavior when the WR (R/ W ) input is programmed as a combined read-write input R/ W . The RD input has to be tied to high-level in this configuration. This timing is called CS0 controlled because CS0 is the last external signal of CS0 , CS1, and R/ W which becomes valid. Design Parameters Symbol Min 0 Max Unit ns ta 0 10 ns th 0 5 ns th(R/ W ) 5 ns tw(CS) 10 ns Setup time, R/ W high to last CS valid Access time, last CS valid to data valid tSU(R/ W ) Hold time, first CS invalid to data invalid Hold time, first external CS invalid to R/ W change Pulse duration, CS active FIGURE 4. Timing waveforms. – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 24 This diagram shows the write timing behavior when the WR (R/ W ) input is programmed as a combined read-write input R/ W . The RD input has to be tied to high-level in this configuration. This timing is called CS0 controlled because CS0 is the last external signal of CS0 , CS1, and R/ W which becomes valid. Design Parameters Symbol Min 0 Max Unit ns Setup time, R/ W high to last CS valid Setup time, data valid to first CS invalid tSU(R/ W ) tSU 5 ns Hold time, first CS invalid to data invalid th 5 ns th(R/ W ) 5 ns tw(CS) 10 ns Hold time, first CS invalid to R/ W change Pulse duration, CS active FIGURE 4. Timing waveforms. – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 25 This diagram shows the read timing behavior when the WR (R/ W ) input is programmed as a write-input only. The RD input acts as the read-input in this configuration. This timing is called RD controlled because RD is the last external signal of CS0 , CS1, and RD which becomes valid. tSU(CS) Min 0 Max Setup time, RD low to last CS valid Access time, last CS valid to data valid Design Parameters Unit ns ta 0 10 ns Hold time, first CS invalid to data invalid th 0 5 ns th(CS) 5 ns tw( RD ) 10 ns Hold time, RD change to first CS invalid Pulse duration, RD active Symbol FIGURE 4. Timing waveforms. – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 26 This diagram shows the write timing behavior when the WR (R/ W ) input is programmed as a write-input WR only. The input RD acts as the read-input in this configuration. This timing is called WR controlled because WR is the last external signal of CS0 , CS1, and WR which becomes valid. Design Parameters Symbol tSU(CS) Min 0 Setup time, data valid to first WR invalid tsu 5 ns Hold time, WR invalid to data invalid th 5 ns th(CS) 5 ns tw( WR ) 10 ns Setup time, CS stable to last WR valid Hold time, WR invalid to CS change Pulse duration, WR active Max Unit ns FIGURE 4. Timing waveforms. – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 27 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/03609-01XE 01295 THS1206MDAREP THS1206MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV B DWG NO. V62/03609 PAGE 28