CYUSB306X EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller Features ■ ■ ■ Applications Universal Serial Bus (USB) integration ❐ USB 3.0 and USB 2.0 peripherals, compliant with USB 3.0 specification 1.0 ❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0 ❐ Thirty-two physical endpoints MIPI CSI-2 RX interface nd ❐ MIPI CSI-2 compliant (Version 1.01, Revision 0.04 – 2 April 2009) ❐ Supports up to four data lanes (CYUSB3065 supports up to four lanes; CYUSB3064 supports up to two lanes) ❐ Each lane supports up to 1 Gbps (CYUSB3065 supports up to four lanes; CYUSB3064 supports up to two lanes) ❐ CCI interface for image sensor configuration Supports the following video data formats: ❐ User-defined 8-bit ❐ RAW8/10/12/14 ❐ YUV422 (CCIR/ITU 8/10bit), YUV444 ❐ RGB888/666/565 ■ Fully accessible 32-bit CPU ❐ ARM926EJ-S core with 200-MHz operation ❐ 512-KB or 256-KB embedded SRAM ■ Additional connectivity to the following peripherals: 2 ❐ I C master controller at 1 MHz 2 ❐ I S master (transmitter only) at sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz ❐ UART support of up to 4 Mbps ❐ SPI master at 33 MHz ■ Twelve GPIOs ■ Ultra-low-power in core power-down mode ■ Independent power domains for core and I/O ❐ Core operation at 1.2 V 2 ❐ I S, UART, and SPI operation at 1.8 to 3.3 V 2 ❐ I C, I/O operation at 1.8 to 3.3 V ■ 10 × 10 mm, 0.8-mm pitch Pb-free ball grid array (BGA) package ■ ■ Digital video cameras ■ Digital still cameras ■ Webcams ■ Scanners ■ Video conference systems ■ Gesture-based control ■ Surveillance cameras ■ Medical imaging devices ■ Video IP phones ■ USB microscopes ■ Industrial cameras EZ-USB® software development kit (SDK) for easy code development Cypress Semiconductor Corporation Document Number: 001-87516 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 24, 2016 CYUSB306X TMS TCK TRST TDI TD0 Logic Block Diagram JTAG CPU ARM926EJ-S SSRXCP / CM SSRX+ SS D0P / D0M 32 EPs MIPI CSI-2 RX interface D1P / D1M Peripheral HS/FS D2P / D2M Peripheral D3P / D3M USB Port SSTXSSTX+ D+ D- MCLK XRST XSHUTDOWN Program RAM RESET# CLKIN CLKIN_32 Document Number: 001-87516 Rev. *K SPI UART TX RX CTS RTS I2S MISO MOSI SSN SCK I2C_SDA I2C_SCL I2C I2S_CLK I2S_SD I2S_WS I2S_MCLK REFCLK Page 2 of 32 CYUSB306X More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources refer to the cypress web page for CX3 at www.cypress.com/CX3. ■ Overview: USB Portfolio, USB Roadmap ■ USB 3.0 Product Selectors: FX3, FX3S, CX3, GX3, HX3, West Bridge Benicia ■ Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with CX3 are: ❐ AN75705 - Getting Started with EZ-USB FX3 ❐ AN90369 - How to Interface a MIPI CSI-2 Image Sensor With EZ-USB® CX3 ❐ AN75779 - How to Implement an Image Sensor Interface with EZ-USB® FX3™ in a USB Video Class (UVC) Framework ❐ AN76405 - EZ-USB FX3 Boot Options ❐ AN70707 - EZ-USB FX3/FX3S Hardware Design Guidelines and Schematic Checklist ❐ AN86947 - Optimizing USB 3.0 Throughput with EZ-USB FX3 ■ Code Examples: ❐ USB SuperSpeed ■ Technical Reference Manual (TRM): ❐ EZ-USB® CX3 Technical Reference Manual Document Number: 001-87516 Rev. *K ■ Knowledge Base Articles: ❐ CX3 Firmware: Frequently Asked Questions - KBA91297 ❐ CX3 Hardware: Frequently Asked Questions - KBA91295 ❐ CX3 Application Software / USB Driver: Frequently Asked Questions - KBA91298 ❐ Knowledge Base - Cypress Semiconductor Cage Code KBA89258 ■ Development Kits: ❐ Ascella - Cypress® CX3™ THine® ISP 13MP reference design kit (RDK) ❐ Denebola - USB 3.0 UVC Reference Design Kit (RDK) ■ Models: ❐ CX3 Device OrCad Schematic Symbol ❐ CYUSB306x - IBIS EZ-USB Software Development Kit Cypress delivers the complete firmware stack for CX3, in order to easily integrate SuperSpeed USB into any embedded MIPI image sensor application. The Software Development Kit (FX3 SDK) comes with tools, drivers and application examples, which help accelerate application development. The FX3 SDK Setup includes CX3 APIs and example firmware for OmniVision OV5640 and Aptina AS0260 image sensor interface. The eclipse plugin for the FX3 SDK accelerates CX3 firmware development for any other image sensor. Page 3 of 32 CYUSB306X Contents Functional Overview ........................................................ 5 Application Examples .................................................. 5 USB Interface .................................................................... 6 ReNumeration ............................................................. 6 VBUS Overvoltage Protection ..................................... 6 MIPI CSI-2 RX Interface .................................................... 7 Additional Outputs ....................................................... 7 CPU .................................................................................... 7 JTAG Interface .................................................................. 7 Other Interfaces ................................................................ 7 UART Interface ............................................................ 7 I2C Interface ................................................................ 7 I2S Interface ................................................................ 8 SPI Interface ................................................................ 8 Boot Options ..................................................................... 8 Reset .................................................................................. 8 Hard Reset .................................................................. 8 Soft Reset .................................................................... 8 Clocking ............................................................................ 9 32-kHz Watchdog Timer Clock Input ........................... 9 Power ............................................................................... 10 Power Modes ............................................................ 10 Configuration Options ................................................... 13 Digital I/Os ....................................................................... 13 GPIOs ............................................................................... 13 EMI ................................................................................... 13 System-level ESD ........................................................... 13 Document Number: 001-87516 Rev. *K Pin Configuration ........................................................... 14 Pin Description ............................................................... 15 Absolute Maximum Ratings .......................................... 17 Operating Conditions ..................................................... 17 DC Specifications ........................................................... 17 MIPI D-PHY Electrical Characteristics .......................... 18 AC Timing Parameters ................................................... 19 MIPI Data to Clock Timing Reference ....................... 19 Reference Clock Specifications ................................. 19 MIPI CSI Signal Low Power AC Characteristics ....... 20 AC Specifications ...................................................... 20 Serial Peripherals Timing .......................................... 21 Reset Sequence .............................................................. 26 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagram ............................................................ 28 Acronyms ........................................................................ 29 Document Conventions ................................................. 29 Units of Measure ....................................................... 29 Document History Page ................................................. 30 Sales, Solutions, and Legal Information ...................... 32 Worldwide Sales and Design Support ....................... 32 Products .................................................................... 32 PSoC®Solutions ....................................................... 32 Cypress Developer Community ................................. 32 Technical Support ..................................................... 32 Page 4 of 32 CYUSB306X Functional Overview CX3 comes with application development tools. The software development kit comes with application examples for accelerating time-to-market. Cypress’s EZ-USB CX3 is the next-generation bridge controller that can connect devices with the Mobile Industry Processor Interface – Camera Serial Interface 2 (MIPI CSI-2) interface to any USB 3.0 Host. CX3 complies with the USB 3.0 v1.0 specification and is also backward compatible with USB 2.0. It also complies with the MIPI CSI-2 v1.01, revision 0.04 specification dated 2nd April 2009. CX3 has a 4-lane CSI-2 receiver with up to 1 Gbps on each lane. It supports video data formats such as RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-bit), RGB888/666/565, and user-defined 8-bit. Application Examples In a typical application (see Figure 1), CX3 acts as the main processor and connects to an image sensor, an audio device, or camera control devices amongst others. CX3 has integrated the USB 3.0 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. CX3 contains 512 KB of on-chip SRAM (see Ordering Information on page 27) for code and data. EZ-USB CX3 also provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S. Figure 1. EZ-USB CX3 Example Application Clock 6-40 MHz Clock 19.2 MHz REFCLK CLKIN Power subsystem VDD MIPI CSI-2 RX EZ-USB CX3 Image sensor I2C Autofocus, Pan, Tilt, Zoom, Shutter control, Lighting, etc. Document Number: 001-87516 Rev. *K U S B I2S Audio output USB Host SPI Audio input Page 5 of 32 CYUSB306X USB Interface VBUS Overvoltage Protection ■ Supports USB peripheral functionality compliant with USB 3.0 Specification, Revision 1.0, and is also backward compatible with the USB 2.0 Specification. The maximum input voltage on CX3's VUSB pin is 6 V. A charger can supply up to 9 V on VUSB. In this case, an external overvoltage protection (OVP) device is required to protect CX3 from damage on VUSB. Figure 3 shows the system application diagram with an OVP device connected on VUSB. Refer to DC Specifications on page 17 for the operating range of VUSB. ■ As a peripheral, CX3 is capable of SuperSpeed, High-Speed, and Full-Speed. Note: The VBUS pin of the USB connector should be connected to the VUSB pin of CX3. ■ Supports up to 16 IN and 16 OUT endpoints Figure 3. System Diagram with OVP Device For VUSB ■ Supports the USB 3.0 Streams feature ■ As a USB peripheral, CX3 supports USB-attached storage (UAS), USB Video Class (UVC), and Media Transfer Protocol (MTP) USB peripheral classes. As a USB peripheral, all other device classes are supported only in pass-through mode when handled entirely by a host processor external to the device. Figure 2. USB Interface Signals 1 OVP device USB Connector USB Interface 2 SSRXSSRX+ SSTXSSTX+ DD+ AVDD VDD CVDDQ VDDIO3 VDDIO2 VDDIO1 EZ-USB CX3 EZ-USB CX3 VUSB U3TXVDDQ U3RXVDDQ POWER SUBSYSTEM SSRXSSRX+ SSTXSSTX+ DD+ 3 4 5 6 7 8 9 VUSB USB-Port CX3 complies with the following specifications and supports the following features: GND ReNumeration Because of CX3’s soft configuration, one chip can take on the identities of multiple distinct USB devices. When first plugged into USB, CX3 enumerates automatically with the Cypress Vendor ID (0x04B4) and downloads the firmware and USB descriptors over the USB interface. The downloaded firmware executes an electrical disconnect and connect. CX3 enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumeration, happens instantly when the device is plugged in. Document Number: 001-87516 Rev. *K Page 6 of 32 CYUSB306X MIPI CSI-2 RX Interface The Mobile Industry Processor Interface (MIPI) association defined the Camera Serial Interface 2 (CSI-2) standard to enable image data to be sent on high-bandwidth serial lines. CX3 implements a MIPI CSI-2 Receiver with the following features: 1. It can receive clock and data in 1, 2, 3, or 4 lanes. (CYUSB3065 part supports up to four lanes; CYUSB3064 part supports up to two lanes) 2. Up to 1 Gbps of data on each CSI lane is supported (total maximum bandwidth should not exceed 2.4 Gbps). 3. Video formats such as RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-bit), RGB888/666/565, and User-Defined 8-bit are supported 4. A CCI interface (compatible with 100-kHz or 400-kHz I2C interface with 7-bit addressing) is provided to configure the sensor. 5. GPIOs are available for synchronization of external flash or lighting system with image sensors to illuminate the scene that improves the image quality by improving Signal to noise ratio. 6. GPIOs can also be used to synchronize the image sensor with external events, so that image can be captured based on external event. 7. Serial interfaces (such as I2C, I2S, SPI, UART) are available to implement camera functions such as Auto focus and Pan, Tilt, Zoom (PTZ) Additional Outputs In addition to the standard MIPI CSI-2 signals, the following three additional outputs are provided: 1. XRST: this can be used to reset the image sensor 2. XSHUTDOWN: this pin can be used to put the sensor to a standby/shutdown mode 3. MCLK: this pin can provide the clock output. It can be used only for testing the image sensor. For production, use an external clock generator as clock input for image sensors. CPU CX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU. The core has direct access to 16 kB of Instruction Tightly Coupled Memory (TCM) and 8 kB of data TCM. The ARM926EJ-S core provides a JTAG interface for firmware debugging. CX3 offers the following advantages: ■ Integrates 512 KB of embedded SRAM for code and data and 8 kB of instruction cache and data cache. ■ Implements efficient and flexible DMA connectivity between the various peripherals (such as, USB, CSI-2 Rx, I2S, SPI, and UART), requiring firmware only to configure data accesses between peripherals, which are then managed by the DMA fabric. ■ Allows easy application development on industry-standard development tools for ARM926EJ-S. Document Number: 001-87516 Rev. *K Examples of the CX3 firmware are available with the Cypress EZ-USB CX3 Development Kit. Software APIs that can be ported to an external processor are available with the Cypress EZ-USB CX3 Software Development Kit. JTAG Interface CX3’s JTAG interface has a standard five-pin interface to connect to a JTAG debugger in order to debug firmware through the CPU-core's on-chip-debug circuitry. Industry-standard debugging tools for the ARM926EJ-S core can be used for the CX3 application development. Other Interfaces CX3 supports the following serial peripherals: ■ UART ■ I2C ■ I2S ■ SPI The CYUSB306X Pin List on page 15 shows the details of how these interfaces are mapped. UART Interface The UART interface of CX3 supports full-duplex communication. It includes the signals noted in Table 1. Table 1. UART Interface Signals Signal TX RX CTS RTS Description Output signal Input signal Flow control Flow control The UART is capable of generating a range of baud rates, from 300 bps to 4608 Kbps, selectable by the firmware. If flow control is enabled, then CX3's UART only transmits data when the CTS input is asserted. In addition to this, CX3's UART asserts the RTS output signal, when it is ready to receive data. I2C Interface CX3’s I2C interface is compatible with the I2C Bus Specification Revision 3. This I2C interface is capable of operating only as I2C master; therefore, it may be used to communicate with other I2C slave devices. For example, CX3 may boot from an EEPROM connected to the I2C interface, as a selectable boot option. CX3’s I2C Master Controller also supports multi-master mode functionality. The power supply for the I2C interface is VDDIO1, which is a separate power domain from the other serial peripherals. This gives the I2C interface the flexibility to operate at a different voltage than the other serial interfaces. Page 7 of 32 CYUSB306X The I2C controller supports bus frequencies of 400 kHz, and 1 MHz. When VDDIO1 is 1.8 V, 2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz and 1 MHz. The I2C controller supports the clock-stretching feature to enable slower devices to exercise flow control. Boot Options CX3 can load boot images from various sources, selected by the configuration of the PMODE pins. Following are the CX3 boot options: The I2C interface’s SCL and SDA signals require external pull-up resistors. The pull-up resistors must be connected to VDDIO1. ■ Boot from USB Note: I2C addresses with the pattern 0x0000111x are used internally and no slave devices with those addresses should be connected to the bus. ■ Boot from I2C ■ I2S Interface Table 2. CX3 Booting Options CX3 has an I2S port to support external audio codec devices. CX3 functions as I2S Master as transmitter only. The I2S interface consists of four signals: clock line (I2S_CLK), serial data line (I2S_SD), word select line (I2S_WS), and master system clock (I2S_MCLK). CX3 can generate the system clock as an output on I2S_MCLK or accept an external system clock input on I2S_MCLK. The sampling frequencies supported by the I2S interface are 32 kHz, 44.1 kHz, and 48 kHz. SPI Interface CX3 supports an SPI Master interface on the Serial Peripherals port. The maximum operation frequency is 33 MHz. The SPI controller supports four modes of SPI communication (see SPI Timing Specification on page 24 for details on the modes) with the Start-Stop clock. This controller is a single-master controller with a single automated SSN control. It supports transaction sizes ranging from 4 bits to 32 bits. Boot from SPI (SPI devices supported are M25P16 (16 Mbit), M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents PMODE[2:0][1] Boot From F11 USB boot F1F I2C, On failure, USB boot is enabled 1FF I2C only 0F1 SPI, On failure, USB boot is enabled Reset Hard Reset A hard reset is initiated by asserting the RESET# pin on CX3. The specific reset sequence and timing requirements are detailed in Figure 11 on page 26 and Table 14 on page 26. All I/Os are tristated during a hard reset. An additional reset pin called MIPI_RESET is provided that resets the MIPI CSI-2 core. It should be pulled down with a resistor for normal operation. Soft Reset There are two types of Soft Reset: ■ CPU Reset – The CPU Program Counter is reset. Firmware does not need to be reloaded following a CPU Reset. ■ Whole Device Reset – This reset is identical to Hard Reset. The firmware must be reloaded following a Whole Device Reset. Note 1. F indicates Floating. Document Number: 001-87516 Rev. *K Page 8 of 32 CYUSB306X Clocking CX3 requires two clocks for normal operation: 1. A 19.2-MHz clock to be connected at the CLKIN pin 2. A 6-MHz to 40-MHz clock to be connected at the REFCLK pin Clock inputs to CX3 must meet the phase noise and jitter requirements specified in Table 3 on page 9. The input clock frequency is independent of the clock and data rate of the CX3 core or any of the device interfaces (including the CSI-2 Rx Port). The internal PLL applies the appropriate clock-multiply option depending on the input frequency. Note: REFCLK and CLKIN must have either separate clock inputs or if the same source is used, the clock must be passed through a buffer with two outputs and then connected to the clock pins. Table 3. CX3 Input Clock Specifications Parameter Phase noise Specification Description Min Units Max 100-Hz offset – –75 dB 1-kHz offset – –104 dB 10-kHz offset – –120 dB 100-kHz offset – –128 dB – –130 dB Maximum frequency deviation 1-MHz offset – – 150 ppm Duty cycle – 30 70 % Overshoot – – 3 % Undershoot – – –3 % Rise time/fall time – – 3 ns 32-kHz Watchdog Timer Clock Input CX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically wake up the CX3 in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock, which may be optionally supplied from an external source on a dedicated CX3 pin. The firmware can disable the watchdog timer. Document Number: 001-87516 Rev. *K Table 4 provides the requirements for the optional 32-kHz clock input Table 4. 32-kHz Clock Input Requirements Parameter Min Max Units Duty cycle 40 60 % Frequency deviation – ±200 ppm Rise time/fall time – 200 ns Page 9 of 32 CYUSB306X Power Power Modes CX3 supports the following power modes: CX3 has the following power supply domains: ■ IO_VDDQ: This is a group of independent supply domains for digital I/Os. 2 ❐ VDDIO1: GPIO, I C, JTAG, XRST, XSHUTDOWN and REFCLK 2 ❐ VDDIO2: UART and I S (except MCLK) 2 ❐ VDDIO3: I S_MCLK and SPI ❐ CVDDQ: CLKIN ❐ VDD_MIPI: MIPI CSI-2 clock and data lanes ■ VDD: This is the supply voltage for the logic core. The nominal supply-voltage level is 1.2 V. This supplies the core logic circuits. The same supply must also be used for the following: ❐ AVDD: This is the 1.2-V supply for the PLL, crystal oscillator, and other core analog circuits. ❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply voltages for the USB 3.0 interface. ■ VUSB: This is the 3.2-V to 6-V battery power supply for the USB I/O and analog circuits. This supply powers the USB transceiver through CX3’s internal voltage regulator. VUSB is internally regulated to 3.3 V. ■ Normal mode: This is the full-functional operating mode. The internal CPU clock and the internal PLLs are enabled in this mode. ❐ Normal operating power consumption does not exceed the sum of ICC Core max and ICC USB max (see DC Specifications on page 17 for current consumption specifications). ❐ The I/O power supplies VDDIO2 and VDDIO3 can be turned off when the corresponding interface is not in use. VDDIO1 should never be turned off for normal operation. ■ Low-power modes (see Table 5 on page 11): ❐ Suspend mode with USB 3.0 PHY enabled ❐ Standby mode ❐ Core power-down mode Note: The different power supplies have to be powered on or off in a specific sequence as illustrated in Figure 4. Figure 4. Power-up Sequence VUSB (VBUS) VDD (VDD, AVDD, VDD_MIPI) VDDIO1 <= 10 ms <= 10 ms CVDDQ, VDDIO2, VDDIO3 CLK_IN, REFCLK RESET# MIPI_RESET >= 1 ms XRST (Image Sensor RESET) User programmable in firmware Document Number: 001-87516 Rev. *K Page 10 of 32 CYUSB306X Table 5. Entry and Exit Methods for Low-Power Modes Low-Power Mode Suspend Mode with USB 3.0 PHY Enabled Standby Mode Characteristics ■ Power consumption in this mode does not exceed ISB1 ■ USB 3.0 PHY is enabled and is in U3 mode (one of the suspend modes defined by the USB 3.0 specification). This one block alone is operational with its internal clock, while all other clocks are shut down ■ All I/Os maintain their previous state ■ Power supply for the wakeup source and core power must be retained. All other power domains can be turned on or off individually ■ The states of the configuration registers, buffer memory, and all internal RAM are maintained ■ All transactions must be completed before CX3 enters suspend mode (state of outstanding transactions are not preserved) ■ The firmware resumes operation from where it was suspended (except when woken up by RESET# assertion) because the program counter does not reset ■ The power consumption in this mode does not exceed ISB3 ■ All configuration register settings and program/data RAM contents are preserved. However, data in the buffers or other parts of the data path, if any, is not guaranteed. Therefore, the external processor should take care that the data needed is read before putting CX3 into the standby mode ■ The program counter is reset after waking up from the standby mode ■ GPIO pins maintain their configuration ■ Internal PLL is turned off ■ USB transceiver is turned off ■ ARM926EJ-S core is powered down. Upon wakeup, the core re-starts and runs the program stored in the program/data RAM ■ Power supply for the wakeup source and core power must be retained. All other power domains can be turned on or off individually Document Number: 001-87516 Rev. *K Methods of Entry ■ ■ Firmware executing on ARM926EJ-S core can put CX3 into the suspend mode. For example, on USB suspend condition, the firmware may decide to put CX3 into suspend mode The firmware executing on ARM926EJ-S core or external processor configures the appropriate register Methods of Exit ■ D+ transitioning to low or high ■ D- transitioning to low or high ■ Resume condition on SSRX± ■ Detection of VBUS ■ Level detect on UART_CTS (programmable polarity) ■ Assertion of RESET# ■ Detection of VBUS ■ Level detect on UART_CTS (programmable polarity) ■ Assertion of RESET# Page 11 of 32 CYUSB306X Table 5. Entry and Exit Methods for Low-Power Modes (continued) Low-Power Mode Core Power-down Mode Characteristics ■ The power consumption in this mode does not exceed ISB4 ■ Core power is turned off ■ All buffer memory, configuration registers, and the program RAM do not maintain state. After exiting this mode, reload the firmware ■ Methods of Entry ■ Turn off VDD Methods of Exit ■ Reapply VDD ■ Assertion of RESET# In this mode, all other power domains can be turned on or off individually Document Number: 001-87516 Rev. *K Page 12 of 32 CYUSB306X Configuration Options EMI Configuration options are available for specific usage models. Contact Cypress Marketing ([email protected]) for details. CX3 can meet EMI requirements outlined by FCC 15B (USA) and EN55022 (Europe) for consumer electronics at system level. CX3 can tolerate reasonable EMI, conducted by the aggressor, outlined by these specifications and continue to function as expected. Digital I/Os CX3 has internal firmware-controlled pull-up or pull-down resistors on all digital I/O pins. An internal 50-k resistor pulls the pins high, while an internal 10-k resistor pulls the pins low to prevent them from floating. The I/O pins may have the following states: ■ Tristated (High-Z) ■ Weak pull-up (via internal 50 k) ■ Pull-down (via internal 10 k) ■ Hold (I/O hold its value) when in low-power modes ■ The JTAG TDI, TMC, and TRST# signals have fixed 50-k internal pull-ups, and the TCK signal has a fixed 10-k pull-down resistor. All unused I/Os should be pulled high by using the internal pull-up resistors. All unused outputs should be left floating. All I/Os can be driven at full-strength, three-quarter strength, half-strength, or quarter-strength. These drive strengths are configured separately for each interface. System-level ESD CX3 has built-in ESD protection on the D+, D–, and GND pins on the USB interface. The ESD protection levels provided on these ports are: ■ ±2.2-kV human body model (HBM) based on JESD22-A114 specification ■ ±6-kV contact discharge and ±8-kV air gap discharge based on IEC61000-4-2 level 3A using external system-level protection devices ■ ± 8-kV contact discharge and ±15-kV air gap discharge based on IEC61000-4-2 level 4C using external system-level protection devices This protection ensures that the device continues to function after ESD events up to the levels stated in this section. The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to ±2.2-kV HBM internal ESD protection. GPIOs CX3 provides 12 pins for general purpose I/O (for example, can be used for lighting, sync-in, sync-out and so on). See Pin Configuration on page 14 for pinout details. All GPIO pins support an external load of up to 16 pF for every pin. Document Number: 001-87516 Rev. *K Page 13 of 32 CYUSB306X Pin Configuration Figure 5. CX3 Ball Map (Top View) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 U3VSSQ U3RXVDDQ SSRXM SSRXP SSTXP SSTXM AVDD VSS DP DM GPIO[24] B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 VDDIO3 VSS GPIO[23] GPIO[21] U3TXVDDQ CVDDQ AVSS VSS VSS VDD TRST# C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 SPI_SSN / GPIO[54] SPI_MISO / GPIO[55] VDD GPIO[26] RESET# GPIO[18] GPIO[19] GPIO[22] GPIO[45] TDO I2S_MCLK / GPIO[57] D10 D11 D1 D2 D3 D4 D5 D6 D7 D8 D9 I2S_CLK / GPIO[50] I2S_SD / GPIO[51] I2S_WS / GPIO[52] SPI_SCK / GPIO[53] SPI_MOSI / GPIO[56] CLKIN_32 CLKIN VSS I2C_SCL E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 UART_CTS / GPIO[47] VSS VDDIO2 UART_RX / GPIO[49] UART_TX / GPIO[48] GPIO[20] TDI TMS VDD VUSB VSS F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 TCK DNU DNU DNU DNU VDD I2C_SDA GPIO[17] DNU REFCLK GPIO[44] XRST UART_RTS / GPIO[46] G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 VSS XSHUTDOW N MCLK PMODE[0] / GPIO[30] GPIO[25] HSYNC_test DNU DNU DNU DNU VSS H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 VDD DNU DNU DNU PCLK_test DNU DNU VDDIO1 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 DNU DNU DNU DNU MIPI_D0P MIPI_D1P1 DNU VDD K1 K2 K3 K4 K5 K6 K9 K10 K11 DNU DNU VSS VSS MIPI_D0N MIPI_D1N1 DNU DNU DNU L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 VSS VSS VSS PMODE[2] / GPIO[32] VDD_MIPI VSS VDD MIPI_D3P1, 2 VDDIO1 DNU VSS PMODE[1] / VSYNC_test MIPI RESET GPIO[31] MIPI_CP MIPI_D2P1, 2 MIPI_D2N1, 2 K7 K8 MIPI_CN MIPI_D3N1, 2 1. Unused MIPI input data lanes to be connected to GND. 2. The signals MIPI_D2N, MIPI_D2P, MIPI_D3N, and MIPI_D3P are not available in the CYUSB3064 part. These pins should be left "open" in the customer board. Legend Ground USB PHY power supply; Clock power supply Power supply Document Number: 001-87516 Rev. *K Page 14 of 32 CYUSB306X Pin Description Table 6. CYUSB306X Pin List (continued) CX3 Table 6. CYUSB306X Pin List CX3 Pin# Pin name I/O F10 DNU I/O F9 DNU I/O F7 DNU I/O G10 DNU I/O G9 DNU I/O F8 DNU I/O H10 DNU I/O H9 DNU I/O J10 DNU I/O H7 DNU I/O K11 DNU I/O L10 DNU I/O K10 DNU I/O K9 DNU I/O G7 DNU I/O G8 DNU I/O K2 DNU I/O J4 DNU I/O K1 DNU I/O J2 DNU I/O J3 DNU I/O J1 DNU I/O H2 DNU I/O H3 DNU I/O G6 HSYNC_test I/O H5 VSYNC_test I/O H8 PCLK_test I/O VDDIO1 Power Domain Pin# Pin name I/O C4 GPIO[26] I/O F3 GPIO[44] I/O C9 GPIO[45] I/O G4 PMODE[0] / GPIO[30] I/O H4 PMODE[1] / GPIO[31] I/O L4 PMODE[2] / GPIO[32] I/O F1 DNU I/O H6 MIPI RESET I/O C5 RESET# I F4 XRST O G2 XSHUTDOWN O G3 MCLK O VDDIO2 Power Domain F5 UART_RTS / GPIO[46] I/O E1 UART_CTS / GPIO[47] I/O E5 UART_TX / GPIO[48] I/O E4 UART_RX / GPIO[49] I/O D1 I2S_CLK / GPIO[50] I/O D2 I2S_SD / GPIO[51] I/O D3 I2S_WS / GPIO[52] I/O VDDIO3 Power Domain D4 SPI_SCK / GPIO[53] I/O C1 SPI_SSN / GPIO[54] I/O C2 SPI_MISO / GPIO[55] I/O D5 SPI_MOSI / GPIO[56] I/O I2S_MCLK / GPIO[57] I/O C11 USB Port (U3TXVDDQ/U3RXVDDQ Power Domain) A3 SSRXM I A4 SSRXP I D11 GPIO[17] I/O A6 SSTXM O C6 GPIO[18] I/O A5 SSTXP O C7 GPIO[19] I/O E6 GPIO[20] I/O A9 B4 GPIO[21] I/O A10 C8 GPIO[22] I/O B3 GPIO[23] I/O A11 GPIO[24] I/O G5 GPIO[25] I/O Document Number: 001-87516 Rev. *K USB Port (VUSB Power Domain) DP I/O DM I/O VDDIO1 Power Domain F2 REFCLK I VDD_MIPI Power Domain J7 MIPI_CP I Page 15 of 32 CYUSB306X Table 6. CYUSB306X Pin List (continued) Table 6. CYUSB306X Pin List (continued) CX3 CX3 Pin# Pin name I/O Pin# Pin name I/O K7 MIPI_CN I L7 VDD PWR J5 MIPI_D0P I D8 VSS PWR K5 MIPI_D0N I E2 VSS PWR J6 MIPI_D1P1 I E11 VSS PWR K6 MIPI_D1N1 I G1 VSS PWR J9 MIPI_D2N1, 2 I A8 VSS PWR J8 MIPI_D2P1, 2 I G11 VSS PWR L8 MIPI_D3P1, 2 I L1 VSS PWR K8 MIPI_D3N1, 2 I B8 VSS PWR L6 VSS PWR D7 CLKIN I B2 VSS PWR D6 CLKIN_32 I L11 VSS PWR B9 VSS PWR CVDDQ Power Domain VDDIO1 Power Domain D9 I2C_SCL I/O K4 VSS PWR D10 I2C_SDA I/O L3 VSS PWR E7 TDI I K3 VSS PWR C10 TDO O L2 VSS PWR B11 TRST# I E8 TMS I F6 TCK I 1. Unused MIPI input data lanes to be connected to GND. 2. The signals MIPI_D2N, MIPI_D2P, MIPI_D3N, and MIPI_D3P are not available in the CYUSB3064 part. These pins should be left "open" in the customer board. Power Domains E10 VUSB PWR A1 U3VSSQ PWR H11 VDDIO1 PWR L9 VDDIO1 PWR E3 VDDIO2 PWR B1 VDDIO3 PWR B6 CVDDQ PWR B5 U3TXVDDQ PWR A2 U3RXVDDQ PWR A7 AVDD PWR B7 AVSS PWR L5 VDD_MIPI PWR B10 VDD PWR J11 VDD PWR C3 VDD PWR E9 VDD PWR F11 VDD PWR H1 VDD PWR Document Number: 001-87516 Rev. *K Page 16 of 32 CYUSB306X Absolute Maximum Ratings Operating Conditions Exceeding maximum ratings may shorten the useful life of the device. TA (ambient temperature under bias) Industrial ................................................... –40 °C to +85 °C Storage temperature ......................... ...... –65 °C to +150 °C VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ Supply voltage .............................................1.15 V to 1.25 V Supply voltage to ground potential VDD, AVDDQ ................................................................. 1.25 V VDDIO1, VDDIO2, VDDIO3 ............................................. ...3.6 V U3TXVDDQ, U3RXVDDQ ......................................... .....1.25 V VUSB supply voltage ...........................................3.2 V to 6 V VDDIO1, VDDIO2, VDDIO3, CVDDQ Supply voltage .................................................1.7 V to 3.6 V DC input voltage to any input pin ...........................VCC + 0.3 DC voltage applied to outputs in high Z state (VCC is the corresponding I/O voltage) ..................VCC + 0.3 Maximum latch-up current ........................................ 140 mA Maximum output short-circuit current for all I/O configurations. (VOUT = 0 V) .................. –100 mA DC Specifications Min Max Units VDD Parameter Core voltage supply Description 1.15 1.25 V 1.2-V typical Notes AVDD Analog voltage supply 1.15 1.25 V 1.2-V typical VDD_MIPI MIPI bridge D-PHY supply voltage 1.15 1.25 V 1.2-V typical VDDIO1 I2C, JTAG and GPIO power domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical VDDIO2 UART/I2S power supply domain 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical VDDIO3 SPI/I2S 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical VUSB USB voltage supply 3.2 6 V 5-V typical U3TXVDDQ USB 3.0 1.2-V supply 1.15 1.25 V 1.2-V typical. A 22-µF bypass capacitor is required on this power supply. U3RXVDDQ USB 3.0 1.2-V supply 1.15 1.25 V 1.2-V typical. A 22-µF bypass capacitor is required on this power supply. CVDDQ Clock voltage supply 1.7 3.6 V 1.8-, 3.3-V typical power supply domain VIH1 Input HIGH voltage 1 0.625 × VCC VCC + 0.3 V For 2.0 V VCC 3.6 V (except USB and MIPI CSI-2 pins).VCC is the corresponding I/O voltage supply. VIH2 Input HIGH voltage 2 VCC – 0.4 VCC + 0.3 V For 1.7 V VCC 2.0 V (except USB USB and MIPI CSI-2 pins).VCC is the corresponding I/O voltage supply. VIL Input LOW voltage –0.3 0.25 × VCC V VCC is the corresponding I/O voltage supply. VOH Output HIGH voltage 0.9 × VCC – V IOH (max) = –100 µA tested at quarter drive strength. VCC is the corresponding I/O voltage supply. VOL Output LOW voltage – 0.1 × VCC V IOL (min) = +100 µA tested at quarter drive strength. VCC is the corresponding I/O voltage supply. Document Number: 001-87516 Rev. *K Page 17 of 32 CYUSB306X DC Specifications (continued) Parameter Description Min Max Units Notes IIX Input leakage current for all pins except SSTXP/SSXM/SSRXP/SSRXM –1 1 µA All I/O signals held at VDDQ (For I/Os with a pull-up or pull-down resistor connected, the leakage current increases by VDDQ/RPU or VDDQ/RPD) IOZ Output High-Z leakage current for all pins except SSTXP/ SSXM/ SSRXP/SSRXM and MIPI CSI-2 signals –1 1 µA All I/O signals held at VDDQ ICC Core Core and analog voltage operating current – 192 mA Total current through AVDD, VDD ICC USB USB voltage supply operating current – 60 mA – Core: 558.35 µA Total suspend current during suspend mode with USB 3.0 PHY I/O: 4.58 µA enabled USB: 4672 µA – µA ISB1 – µA Core Current is measured through VDD, AVDD and VDD_MIPI. – µA Core: 148.31 µA – µA ISB3 Total standby current during core power-down mode I/O: 3.16 µA – µA USB: 15.8 µA – µA I/O Current is measured through VDDIO1 to VDDIO3. USB Current is measured through VUSB, U3TXVDDQ and U3RXVDDQ. VRAMP Voltage ramp rate on core and I/O supplies 0.2 12 VN Noise level permitted on VDD and I/O supplies – 100 mV Max p-p noise level permitted on all supplies except AVDD VN_AVDD Noise level permitted on AVDD supply – 20 mV Max p-p noise level permitted on AVDD V/ms Voltage ramp must be monotonic MIPI D-PHY Electrical Characteristics Parameter Description Spec Min Nom Max Unit MIPI D-PHY RX DC Characteristics VPIN Pin signal voltage range –50 – 1350 mV VIH Logic 1 input voltage 880 – – mV VIL Logic 0 input voltage – – 550 mV VCMRX (DC) Common-mode voltage HS receiver mode 70 – 330 mV VIDTH Differential input high threshold – 70 mV VIDTL Differential input low threshold –70 – – mV VIHHS Single-ended input high voltage – 460 mV VILHS Single-ended input low voltage – – mV Document Number: 001-87516 Rev. *K –40 Page 18 of 32 CYUSB306X AC Timing Parameters MIPI Data to Clock Timing Reference Figure 6. MIPI CSI Signal Data to Clock Timing Reference Reference Time TSETUP THOLD 0.5UIINST + TSKEW CLKp CLKn 1 UIINST TCLKp Table 7. MIPI Data to Clock Timing Reference Parameter Description Min Max Units TSKEW Data to clock skew measured at the transmitter –0.15 0.15 UIINST TSETUP Data to clock setup time at receiver 0.15 – UIINST THOLD Clock to data hold time at receiver 0.15 – UIINST UIINST One data bit time (instantaneous) 1 12.5 ns TCLKp Period of dual data rate clock 2 25 ns Reference Clock Specifications Table 8. Reference Clock Specifications Parameter Min Max Units Notes 6 40 MHz – RefclkDutyCyl Duty cycle 40% 60% – – RefClkPJ -100 100 ps – RefClk Description Reference clock frequency Reference clock input period jitter Document Number: 001-87516 Rev. *K Page 19 of 32 CYUSB306X MIPI CSI Signal Low Power AC Characteristics Figure 7. MIPI CSI bus Input Glitch Rejection 2*TLPX eSPIKE 2*TLPX VIH Input VIL TMIN-RX TMIN-RX eSPIKE Output Table 9. MIPI CSI Signal Low Power AC Characteristics Parameter Description Min Max Units Notes Time-voltage integration of a spike above VIL when being in LP-0 or below VIH when being in V.ps LP-1 state. An impulse less than this will not change the receiver state. eSPIKE Input noise rejection – 300 TMIN-RX Minimum pulse width response 20 – ns An input pulse greater than this shall toggle the output. VINT peak interference amplitude – 200 mV – FINT Interference frequency 450 – MHz – TLPX Length of any low power state period 50 – ns – Min Max Units Details / Conditions AC Specifications Table 10. AC Specifications Parameter Description ∆VCMRX(HF) Common-mode interference beyond 450 MHz – 100 mV ∆VCMRX(HF) is the peak amp. Of a sine wave superimposed on the receiver inputs. ∆VCMRX(LF) Common-mode interference beyond 50 - 450 MHz -50 50 mV Excluding static ground shift of 50 mV. Voltage difference compared to the DC average common-mode potential Document Number: 001-87516 Rev. *K Page 20 of 32 CYUSB306X Serial Peripherals Timing I2C Timing Figure 8. I2C Timing Definition Table 11. I2C Timing Parameters[2] Parameter Description I2C Min Max Units Standard Mode Parameters fSCL SCL clock frequency 0 100 kHz tHD:STA Hold time START condition 4 – µs tLOW LOW period of the SCL 4.7 – µs tHIGH HIGH period of the SCL 4 – µs tSU:STA Setup time for a repeated START condition 4.7 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 250 – ns tr Rise time of both SDA and SCL signals – 1000 ns tf Fall time of both SDA and SCL signals – 300 ns tSU:STO Setup time for STOP condition 4 – µs tBUF Bus free time between a STOP and START condition 4.7 – µs tVD:DAT Data valid time – 3.45 µs tVD:ACK Data valid ACK – 3.45 µs tSP Pulse width of spikes that must be suppressed by input filter n/a n/a Note 2. All parameters guaranteed by design and validated through characterization. Document Number: 001-87516 Rev. *K Page 21 of 32 CYUSB306X Table 11. I2C Timing Parameters[2] (continued) Parameter Description Min Max Units 0 400 kHz I2C Fast Mode Parameters fSCL SCL clock frequency tHD:STA Hold time START condition 0.6 – µs tLOW LOW period of the SCL 1.3 – µs tHIGH HIGH period of the SCL 0.6 – µs tSU:STA Setup time for a repeated START condition 0.6 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 100 – ns tr Rise time of both SDA and SCL signals – 300 ns tf Fall time of both SDA and SCL signals – 300 ns tSU:STO Setup time for STOP condition 0.6 – µs tBUF Bus free time between a STOP and START condition 1.3 – µs tVD:DAT Data valid time – 0.9 µs tVD:ACK Data valid ACK – 0.9 µs tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns 0 1000 kHz I2C Fast Mode Plus Parameters fSCL SCL clock frequency tHD:STA Hold time START condition 0.26 – µs tLOW LOW period of the SCL 0.5 – µs tHIGH HIGH period of the SCL 0.26 – µs tSU:STA Setup time for a repeated START condition 0.26 – µs tHD:DAT Data hold time 0 – µs tSU:DAT Data setup time 50 – ns tr Rise time of both SDA and SCL signals – 120 ns tf Fall time of both SDA and SCL signals – 120 ns tSU:STO Setup time for STOP condition 0.26 – µs tBUF Bus-free time between a STOP and START condition 0.5 – µs tVD:DAT Data valid time – 0.45 µs tVD:ACK Data valid ACK – 0.55 µs tSP Pulse width of spikes that must be suppressed by input filter 0 50 ns Document Number: 001-87516 Rev. *K Page 22 of 32 CYUSB306X I2S Timing Diagram Figure 9. I2S Transmit Cycle tT tTR tTF tTL tTH SCK tThd SA, WS (output) tTd Table 12. I2S Timing Parameters[3] Parameter Description Min Max Units tTR – ns transmitter cycle LOW period 0.35 tTR – ns I2S transmitter cycle HIGH period 0.35 tTR – ns transmitter rise time – 0.15 tTR ns transmitter fall time – 0.15 tTR ns transmitter data hold time 0 – ns – 0.8 tT ns tT I2S transmitter clock cycle tTL I2S tTH tTR I2S tTF I2S tThd I2S tTd I2S transmitter delay time Note tT is selectable through clock gears. Max tTR is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz). Note 3. All parameters guaranteed by design and validated through characterization. Document Number: 001-87516 Rev. *K Page 23 of 32 CYUSB306X SPI Timing Specification Figure 10. SPI Timing SSN (output) tlead SCK (CPOL=0, Output) tsdi MISO (input) twsck thoi MSB LSB td tsdd tdis tdi v MOSI (output) tlag trf twsck SCK (CPOL=1, Output) tssnh tsck LSB MSB SPI Master Timing for CPHA = 0 SSN (output) SCK (CPOL=0, Output) tssnh tsck tlead twsck trf tlag twsck SCK (CPOL=1, Output) tsdi MISO (input) thoi LSB tdis tdi tdv MOSI (output) MSB LSB MSB SPI Master Timing for CPHA = 1 Document Number: 001-87516 Rev. *K Page 24 of 32 CYUSB306X Table 13. SPI Timing Parameters[4] Parameter Description Min Max Units fop Operating frequency 0 33 MHz tsck Cycle time 30 – ns twsck Clock HIGH/LOW time 13.5 – ns tlead SSN-SCK lead time tsck[5] tlag Enable lag time tsck[5] tsck[5] trf Rise/fall time – 8 ns tsdd Output SSN to valid data delay time – 5 ns tdv Output data valid time – 5 ns tdi Output data invalid 0 – ns tssnh Minimum SSN HIGH time 10 – ns tsdi Data setup time input 8 – ns thoi Data hold time input 0 – ns tdis Disable data output on SSN HIGH 0 – ns 1/2 0.5 –5 1.5 1.5 +5 ns +5 ns Notes 4. All parameters guaranteed by design and validated through characterization. 5. Depends on LAG and LEAD setting in the SPI_CONFIG register. Document Number: 001-87516 Rev. *K Page 25 of 32 CYUSB306X Reset Sequence CX3’s hard reset sequence requirements are specified in this section. Table 14. Reset and Standby Timing Parameters Parameter Definition tRPW Minimum RESET# pulse width tRH Minimum HIGH on RESET# tRR Reset recovery time (after which the boot loader begins firmware download) tSBY Time to enter standby/suspend mode (from the time MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set) tWU Time to wakeup from standby tWH Minimum time before standby/suspend source may be reasserted Conditions Min (ms) Max (ms) Clock Input 1 – – 5 – Clock Input 1 – – – 1 Clock Input 1 – – 5 – Figure 11. Reset Sequence VDD ( core ) xVDDQ CLKIN CLKIN must be stable before exiting Standby/Suspend Mandatory Reset Pulse tRR Hard Reset tRh RESET# tWH tRPW Standby/ Suspend Source tSBY Standby/Suspend source Is asserted (MAIN_POWER_EN/ MAIN_CLK_EN bit is set) Document Number: 001-87516 Rev. *K tWU Standby/Suspend source Is deasserted Page 26 of 32 CYUSB306X Ordering Information Table 15. Ordering Information Ordering Code MIPI CSI-2 Lanes Package Type Temperature Grade CYUSB3065-BZXI 4 121-ball BGA Industrial CYUSB3065-BZXC 4 121-ball BGA Commercial CYUSB3064-BZXI 2 121-ball BGA Industrial CYUSB3064-BZXC 2 121-ball BGA Commercial Ordering Code Definitions CY USB 3 06X - BZ X I Temperature Grade: I = Industrial C = Commercial Pb-free Package Type: BZ = 121-ball BGA X = 4 for up to 2 MIPI CSI-2 lanes X = 5 for up to 4 MIPI CSI-2 lanes Density: Base part number for USB 3.0 Marketing Code: USB = USB Controller Company ID: CY = Cypress Document Number: 001-87516 Rev. *K Page 27 of 32 CYUSB306X Package Diagram Figure 12. 121-ball BGA (10 × 10 × 1.7 mm) Package Outline, 001-87293 001-87293 ** Document Number: 001-87516 Rev. *K Page 28 of 32 CYUSB306X Acronyms Document Conventions Table 16. Acronyms Used in this Document Units of Measure Acronym Description Table 17. Units of Measure CSI - 2 Camera Serial Interface - 2 DMA Direct Memory Access °C degree Celsius DNU Do Not Use Mbps Megabits per second HNP Host Negotiation Protocol MBps Megabytes per second MIPI Mobile Industry Processor Interface MHz megahertz MMC Multimedia Card µA microampere MTP Media Transfer Protocol µs microsecond PLL Phase Locked Loop mA milliampere PMIC Power Management IC ms millisecond SD Secure Digital ns nanosecond SDIO Secure Digital Input / Output ohm SLC Single-Level Cell pF picofarad SPI Serial Peripheral Interface V volt SRP Session Request Protocol USB Universal Serial Bus WLCSP Wafer Level Chip Scale Package Document Number: 001-87516 Rev. *K Symbol Unit of Measure Page 29 of 32 CYUSB306X Document History Page Document Title: CYUSB306X, EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller Document Number: 001-87516 Revision ECN Orig. of Change Submission Date ** 3994736 KUMR 05/09/2013 New datasheet 07/17/2013 Updated Logic Block Diagram. Updated Pin Description. Updated DC Specifications. Replaced “VBUS” and “VBATT” by “VUSB” in all instances across the document. Updated in new template. *A 4065766 KUMR Description of Change *B 4080302 KUMR 07/29/2013 Updated status as “Preliminary”. *C 4088328 KUMR 08/06/2013 Updated Pin Configuration (Updated Figure ). 09/04/2013 Updated Clocking: Added a Note at the bottom of section. Updated Pin Description. Updated Table 6. Updated DC Specifications: Updated description of VDDIO2 parameter. Updated description of VDDIO3 parameter. Changed maximum value of ICC Core parameter from 200 mA to 380 mA. 11/14/2013 Changed status from Preliminary to Final. Updated Features: Updated description. Updated Applications: Updated description. Updated Logic Block Diagram. Updated Functional Overview. Updated MIPI CSI-2 RX Interface. Updated Additional Outputs: Updated description. Updated Reset. Updated Soft Reset: Updated description. Updated Power. Updated Power Modes. Updated Table 5. Updated “Methods of Entry” corresponding to “Suspend Mode with USB 3.0 PHY Enabled”. Updated “Characteristics” corresponding to “Standby Mode”. Updated EMI: Updated description. Updated System-level ESD: Updated description. Updated Pin Configuration: Updated details of G4, H4, L4, F1, F5, E1, E5, E4, D1, D2, D3, D4, C1, C2, D5, C11 pins in Figure . Updated Pin Description. Updated details in “Pin name” column for G4, H4, L4, F1, F5, E1, E5, E4, D1, D2, D3, D4, C1, C2, D5, C11 pins. Updated Absolute Maximum Ratings: Removed “Ambient temperature with power applied”. Removed “Static discharge voltage ESD protection levels”. Renamed “Latch-up current” as “Maximum latch-up current” and updated the values. Updated DC Specifications: Updated details in “Notes” column corresponding to VIH1 and VIH2 parameters. Updated description of IOZ parameter. Updated minimum value of ISB1 and ISB3 parameters. Updated details in “Notes” column corresponding to ISB1 and ISB3 parameters. Added MIPI D-PHY Electrical Characteristics. Updated AC Timing Parameters. Updated MIPI Data to Clock Timing Reference. *D *E 4113754 4188453 KUMR KUMR Document Number: 001-87516 Rev. *K Page 30 of 32 CYUSB306X Document History Page (continued) Document Title: CYUSB306X, EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller Document Number: 001-87516 Revision *E (cont.) ECN 4188453 Orig. of Change Submission Date KUMR Description of Change 11/14/2013 Updated Figure 6. Updated Table 7. Updated minimum value of UIINST parameter. Updated maximum value of TCLKp parameter. Updated MIPI CSI Signal Low Power AC Characteristics: Updated Figure 7. Updated Serial Peripherals Timing. Updated I2C Timing. Updated Table 11: Removed “(Not supported at I2C_VDDQ = 1.2 V)” in “I2C Fast Mode Plus Parameters” sub-heading. Updated Reset Sequence. Updated Table 14. Removed “Crystal Input” condition for tRPW, tRR, tWU parameters. Updated Figure 11. Updated Ordering Information: Updated part numbers. *F 4214952 RAJA 03/12/2014 Updated Features. Updated Functional Overview. Updated Application Examples. Updated Figure 1. Updated Configuration Options: Added email. Updated Pin Description. Updated caption of Table 6. Updated DC Specifications: Updated maximum value of VIL parameter. Updated maximum value of VRAMP parameter. Updated AC Timing Parameters. Updated MIPI CSI Signal Low Power AC Characteristics. Updated Table 9. Updated details in “Notes” column. Updated to new template. *G 4417040 KUMR 06/23/2014 Updated Power: Updated details of IO_VDDQ power supply domain. Updated DC Specifications: Updated maximum value of ICC Core parameter. Added new part numbers: 2 and 4 MIPI CSI-2 lane parts with Industrial and Commercial temperature grades. *H 4467092 RAJA 08/06/2014 HSYNC, VSYNC, PCLK test points mentioned in the pin configuration table MCLK - Signal description updated. Updated information for CYUSB3064 part number: MIPI_D2P, MIPI_D2N, MIPI_D3P, MIPI_D3N signals not available. *I 4862446 RAGO 08/13/2015 Added footnote 1, and updated Pin Configuration (Figure 5) and Pin Description (Table 6) to indicate grounding of unused MIPI lanes. *J 4974015 RAGO 10/19/2015 Added More Information. *K 5283275 RAGO 05/24/2016 Updated to new template. Completing Sunset Review. Document Number: 001-87516 Rev. *K Page 31 of 32 CYUSB306X Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/clocks cypress.com/interface cypress.com/powerpsoc cypress.com/memory PSoC Cypress Developer Community Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2013-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-87516 Rev. *K ® EZ-USB is a registered trademark of Cypress Semiconductor Corporation. Revised May 24, 2016 Page 32 of 32