5 4 3 2 1 D D BLOCK DIAGRAM USB LINES C C Type-C Connector Type-C Connector CC VCONN VCONN U2 CCG2 U1 CCG2 B B A A CYPRESS SEMICONDUCTOR © 2015 Title PCA: PCB: FAB DRW: ASSY DRW: 121-60200-01 600-60233-01 610-60223-01 620-60231-01 CY4502 Size Document Number B 630-60230-01 Date: 5 4 3 2 Thursday, March 26, 2015 Rev 08 Sheet 1 1 of 3 5 4 3 2 VCONN_2 J7 TP2 CONN PCB 3 TEST POINT I2C pullups VDDIO_2 C6 R5 R6 4.7 K 4.7 K 4.7 K 4.7 K CYPD2103-20FNXIT 0.1uF U1 I2C_SDA_1 I2C_SDA_2 C1 I2C_SDA_1 A2 1uF I2C_SCL_1 A3 CC2_1 A4 RESET_1 B1 GPIO_1_1 B2 RD B3 LED1 GREEN All resisitances are NO LOAD R1 1 KOhms CC B4 VCCD VSS1 I2C_0_SDA P[1.3] I2C_0_SCL P[2.1] CC2 VCONN2 XRES SWD_CLK P[1.5] P[1.0] RD1 P[1.7] CC1 VSS2 VCONN2_1 D1 SWD_CLK_1 D2 GPIO_4_1 D3 GPIO_5_1 2 E1 VDDIO_1 E2 SWD_IO_1 Enable RD on CC VCONN1_1 GPIO_1_2 GPIO_2_2 GPIO_3_2 I2C_SDA_2 I2C_SCL_2 RD VCONN2_2 VCONN2_1 VCONN1_2 6 VSS P[1.7] CC1 XRES VCONN2 P[1.5] VCONN1 P[1.3] VCCD 7 VDDD SWD_IO C2 0.1uF 1uF C5 C4 1uF 1uF 10 GPIO_1_2 9 SWD_CLK_2 8 SWD_IO_2 D+ D- B6 B7 VDDIO_1 TX1+ TX1NC1 NC2 RX2+ RX2- R8 RESET_1 50MIL KEYED SMD_NL C7 VDDD_2 0.1uF J4 SWD_IO_2 SWD_CLK_2 VDDIO_2 R9 4.7 K RESET_2 50MIL KEYED SMD_NL C8 0.1uF NO LOAD 2 4 6 8 10 TX2+ TX2- 4.7 K NO LOAD 2 4 6 8 10 SWD_IO_1 SWD_CLK_1 A1 A12 B1 B12 CC VCONN GND_1 GND_2 GND_3 GND_4 SBU1 SBU2 A6 A7 D+ D- A6 A7 B11 B10 RX1+ RX1- A2 A3 A2 A3 TX1+ TX1- B11 B10 A11 A10 RX2+ RX2- B2 B3 B2 B3 A5 B5 A8 B8 TX2+ TX2VCONN_1 VCONN_2 A11 A10 A5 B5 CC SBU1 SBU2 USB-PD_TYPE-C B8 A8 D+ D- VBUS_1 VBUS_2 VBUS_3 VBUS_4 VBUS A4 A9 B4 B9 B TX1+ TX1- J10 CON2 RX1+ RX1TX2+ TX2- VDDD_2 NC1 NC2 B6 B7 J11 CON2 VDDD_1 VCONN2_2 VCONN2_1 NO LOAD NO LOAD RX2+ RX2CC VCONN SBU2 SBU1 GND_1 GND_2 GND_3 GND_4 A1 A12 B1 B12 PCA: PCB: FAB DRW: ASSY DRW: USB-PD_TYPE-C 121-60200-01 600-60233-01 610-60223-01 620-60231-01 A CYPRESS SEMICONDUCTOR © 2015 RX+/RX- and TX+/TX- are USB3.0 Super Speed Differential signals Title CY4502 Size Document Number B 630-60230-01 Date: 4 VDDD_2 2 1 VBUS_1 VBUS_2 VBUS_3 VBUS_4 J3 TVS1 5V/350W GPIO_2_2 1 2 J2 RX1+ RX1- TVS2 5V/350W 11 VDDD_1 J1 A4 A9 B4 B9 5 RESET_2 J5 CON2 USB Type-C Plugs NO LOAD 1 3 5 7 9 12 GREEN Dual Chip Configuration Both Powered RD CON20 A GPIO_3_2 C D+/D- are USB2.0 High Speed Differential signals 1 3 5 7 9 13 R2 1 KOhms SWD_CLK NO LOAD SWD Connectors LED2 VDDD_2 VCONN1_1 E4 D I2C_SDA_2 14 I2C_0_SDA 1 CC VBUS VDDD_1 I2C_0_SCL 1 2 VCONN_1 VCONN2_2 4 3 VDDIO_2 J6 CON2 TP1 TEST POINT J12 CON2 CC VDDD_1 C3 CC GPIO_2_1 GPIO_3_1 GPIO_4_1 GPIO_1_1 I2C_SDA_1 I2C_SCL_1 CC2_1 J8 CON2 E3 VDDD VCONN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 B GPIO_3_1 C4 D4 SWD_IO J9 C3 1 1 2 C GPIO_2_1 VCONN1_2 5 VDDIO Header to bring out various signals VDDD_2 I2C_SCL_2 C2 2 1 VDDD_1 15 I2C_SCL_2 C1 2 1 A1 I2C_SCL_1 J13 CON2 CYPD2103-14LHXIT U2 D 1 2 R4 EPAD R3 3 2 1 1 VDDIO_1 1 3 2 Thursday, March 26, 2015 Rev 08 Sheet 1 2 of 3 5 4 Revision D 3 2 1 Description of the change 02 Updating for the sanity no changes in the schematic 03 Changing the revision number to match with Layout 04 Changing the revision number to match with Layout 05 Adding a pull-up on the XRES line of each chip D Added Jumper J8 06 C C Increases R1 and R2 from 150 Ohms to 1K Ohms Replaced U2 with CYPD2103-14LHXIT Updated jumpers, changes jumper numbers 07 08 Added additional TVS diode for J4 and seperated VDDD rails for both the chips U1 and U2 Changed LED from P2[1] to P1[5] Changed the MPN to CY4502 B B A A CYPRESS SEMICONDUCTOR © 2015 Title PCA: PCB: FAB DRW: ASSY DRW: 121-60200-01 600-60233-01 610-60223-01 620-60231-01 CY4502 Size Document Number A 630-60230-01 Date: 5 4 3 Thursday, March 26, 2015 2 Rev 08 Sheet 3 1 of 3