PHILIPS PDI1394P23BD

INTEGRATED CIRCUITS
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
Preliminary data
Supersedes data of 2001 Jul 18
2001 Sep 06
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
1.0 FEATURES
• Fully supports provisions of IEEE 1394–1995 Standard for high
PDI1394P23
• Interoperable with link-layer controllers using 3.3 V and 5 V
performance serial bus and the P1394a–2000 Standard.1
supplies
• Fully interoperable with Firewire and i.LINK implementations of
• Interoperable with other Physical Layers (PHYs) using 3.3 V and
the IEEE 1394 Standard.2
5 V supplies
• Full P1394a support includes:
• Node power class information signaling for system power
management
– Connection debounce
• Cable power presence monitoring
• Power down features to conserve energy in battery-powered
– Arbitrated short reset
– Multispeed concatenation
– Arbitration acceleration
applications include:
– Fly-by concatenation
– Automatic device power down during suspend
– Port disable/suspend/resume
– Device power down terminal
• Provides two 1394a fully-compliant cable ports at
– Link interface disable via LPS
100/200/400 Mbps.
– Inactive ports powered-down
• Fully compliant with Open HCI requirements
• Interface to link-layer controller supports both low-cost bus-holder
• While unpowered and connected to the bus, will not drive TPBIAS
on a connected port, even if receiving incoming bias voltage on
that port
isolation and optional Annex J electrical isolation
• Can be used as a one port PHY without the use of any extra
• Supports extended bias-handshake time for enhanced
external components
interoperability with camcorders
• Low-cost 24.576 MHz crystal provides transmit, receive data at
• Data interface to link-layer controller through 2/4/8 parallel lines at
100/200/400 Mbps, and link-layer controller clock at 49.152 MHz
49.152 MHz
• Does not require external filter capacitors for PLL
• LQFP package is function and pin compatible with the Texas
• Register bits give software control of contender bit, power class
bits, link active bit, and 1394a features
• Cable ports monitor line conditions for active connection to remote
Instruments TSB41LV02AE and TSB41AB2E 400 Mbps
PHYs.
node.
• Separate cable bias (TPBIAS) for each port
• Logic performs system initialization and arbitration functions
• Encode and decode functions included for data-strobe bit level
2.0 DESCRIPTION
The PDI1394P23 provides the digital and analog transceiver functions
needed to implement a two/one port node in a cable-based IEEE
1394–1995 and/or 1394a–2000 network. Each cable port incorporates
two differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and
transmission. The PDI1394P23 is designed to interface with a Link
Layer Controller (LLC), such as the PDI1394L40, or PDI1394L41.
encoding
• Incoming data resynchronized to local clock
• Single 3.3 volt supply operation
• Minimum VDD of 2.7 V for end-of-wire power-consuming devices
3.0 ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
PKG. DWG. #
64-pin plastic LQFP
PACKAGE
0 to +70 °C
PDI1394P23BD
SOT314-2
64-ball plastic LFBGA
0 to +70 °C
PDI1394P23EC
SOT534-1
1.
2.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
Firewire is a trademark of Apple Computer Inc. i.LINK is a trademark of Sony.
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
DGND
DGND
DVDD
DVDD
XO
XI
PLLGND
PLLGND
PLLV DD
NC
NC
RESET
AV DD
AV DD
AGND
AGND
4.0 PIN AND BALL CONFIGURATION
4.1 LQFP CONFIGURATION
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LREQ 1
48 AGND
SYSCLK 2
47 TPBIAS1
CNA 3
46 TPA1+
CTL0 4
45 TPA1–
CTL1 5
44 TPB1+
D0 6
43 TPB1–
D1 7
42 AVDD
D2 8
41 R1
PDI1394P23
22
23
24
25
26
27
28
29
30
31
32
AGND
21
AV DD
20
AV DD
19
TEST0
18
BRIDGE
17
TWOPORT
33 AGND
DV DD
34 TPB0–
NC 16
CPS
LPS 15
DV DD
35 TPB0+
ISO
36 TPA0–
PD 14
PC2
37 TPA0+
D7 13
PC1
D6 12
PC0
38 TPBIAS0
C/LKON
D5 11
DGND
40 R0
39 AGND
DGND
D3 9
D4 10
SV001871
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
4.2 LFBGA CONFIGURATION
A
B
C
D
E
F
G
H
BOTTOM (BALL) VIEW
1
2
3
4
5
6
7
8
SV01909
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
AGND
C1
RESET
E1
PLLGND
G1
DGND
A2
TPBIAS1
C2
AVDD
E2
XI
G2
DGND
A3
TPA1–
C3
AVDD
E3
XO
G3
CTL0
A4
R1
C4
TPB1+
E4
D2
G4
CTL1
A5
AGND
C5
AVDD
E5
CPS
G5
D5
A6
TPBIAS0
C6
TPB0+
E6
DVDD
G6
PD
A7
TPB0–
C7
AVDD
E7
PC1
G7
DGND
A8
AGND
C8
TEST0
E8
ISO
G8
DGND
B1
AGND
D1
PLLVDD
F1
DVDD
H1
LREQ
B2
AGND
D2
AVDD
F2
DVDD
H2
SYSCLK
B3
TPA1+
D3
PLLGND
F3
CNA
H3
D0
B4
TPB1–
D4
PLLVDD
F4
D4
H4
D1
B5
TPA0+
D5
R0
F5
D6
H5
D3
B6
TPA0–
D6
BRIDGE
F6
C/LKON
H6
D7
B7
AGND
D7
TWOPORT
F7
PC0
H7
LPS
B8
AVDD
D8
DVDD
F8
PC2
H8
DGND
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
5.0 PIN DESCRIPTION
Name
Pin Type
LQFP
Pin
Numbers
LFBGA
Ball
Numbers
I/O
Description
AGND
Supply
32, 33,
39, 48,
49, 50
A1, A5,
A8, B1,
B2, B7
—
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
AVDD
Supply
30, 31,
42, 51,
52
B8, C2,
C3, C5,
C7, D2
—
Analog circuit power terminals. A combination of high frequency
decoupling capacitors on each side are suggested, such as paralleled
0.1 µF and 0.001 µF. These supply terminals are separated from
PLLVDD and DVDD internal to the device to provide noise isolation. They
should be tied at a low impedance point on the circuit board.
BRIDGE
CMOS
28
D6
I
BRIDGE input. This input is used to set the Bridge_Aware bits located in
the Vendor-Dependent register Page 7, base address 1001b, bit
positions 6 and 7. This pin is sampled during a hardware reset (RESET
low). When the BRIDGE pin is tied low (or through a 1 kΩ resistor to
accommodate other vendor’s pin-compatible chips), the Bridge_Aware
bits are set to “00” indicating a “non-bridge device.” When the BRIDGE
pin is tied high, the Bridge_Aware bits are set to “11” indicating a “1394.1
bridge compliant” device. The default setting of the Bridge_Aware bits
can be overridden by writing to the register. The Bridge_Aware bits are
reported in the self-ID packet at bit positions 18 and 19.
C/LKON
CMOS 5V tol
19
F6
I/O
Bus Manager/Isochronous Resource Manager (IRM) Contender
programming input and link-on output. On hardware reset, this terminal
is used to set the default value of the contender status indicated during
self-ID. Programming is done by tying the terminal through a 10-kΩ
resistor to a high (contender) or low (not contender). The resistor allows
the link-on output to override the input.
If this pin is connected to a LLC driver pin for setting Bus Manager/IRM
contender status, then a 10-kΩ series resistor should be placed on this
line between the PHY and the LLC to prevent possible contention. In this
case. the pull-high or pull-low resistors mentioned in the previous
paragraph should not be used. Refer to Figure 9.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is otherwise driven low,
except during hardware reset when it is high impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the
LCtrl bit cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node,
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-timeout interrupt), CPSI
(cable-power-status interrupt), or STOI (state-timeout interrupt)
register bits are 1 and the RPIE (resuming-port interrupt enable)
register bit is also 1.
Once activated, the link-on output will continue active until the LLC
becomes active (both LPS active and the LCtrl bit set). The PHY also
deasserts the link-on output when a bus-reset occurs unless the link-on
output would otherwise be active because one of the interrupt bits is set
(i.e., the link-on output is active due solely to the reception of a link-on
PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the
link-on output to be activated if the LLC were inactive, the link-on output
will be activated when the LLC subsequently becomes inactive.
CNA
CMOS
3
F3
O
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
CPS
CMOS
24
E5
I
Cable Power Status input. This terminal is normally connected to cable
power through a 390 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
Name
Pin Type
LQFP
Pin
Numbers
LFBGA
Ball
Numbers
I/O
PDI1394P23
Description
CTL0,
CTL1
CMOS 5V tol
4
5
G3
G4
I/O
Control I/Os. These bi-directional signals control communication
between the PDI1394P23 and the LLC. Bus holders are built into
these terminals.
D0–D7
CMOS 5V tol
6, 7, 8,
9, 10,
11, 12,
13
H3, H4,
E4, H5,
F4, G5,
F5, H6
I/O
Data I/Os. These are bi-directional data signals between the
PDI1394P23 and the LLC. Bus holders are built into these terminals.
Unused Dn pins should be pulled to ground through 10 kΩ resistors.
DGND
Supply
17, 18,
63, 64
G7, H8,
G8, G1,
G2
—
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
DVDD
Supply
25, 26,
61, 62
D8, E6,
F1, F2
—
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each side of the IC package are suggested,
such as paralleled 0.1 µF and 0.001 µF. These supply terminals are
separated from PLLVDD and AVDD internal to the device to provide noise
isolation. They should be tied at a low impedance point on the circuit
board.
ISO
CMOS
23
E8
I
Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1995
is implemented between the PDI1394P23 and LLC, the ISO terminal
should be tied low to enable the differentiation logic. If no isolation barrier
is implemented (direct connection), or bus holder isolation is
implemented, the ISO terminal should be tied high to disable the
differentiation logic.
LPS
CMOS 5V tol
15
H7
I
Link Power Status input. This terminal is used to monitor the
active/power status of the link layer controller and to control the state of
the PHY-LLC interface. This terminal should be either connected to the
LPS output of the LLC, or if no LPS terminal is available on the LLC the
LPS terminal can be connected to the VDD supplying the LLC through a
10 kΩ resistor. A pulsed signal should be used when an isolation barrier
exists between the LLC and PHY. (See Figure 8)
The LPS input is considered inactive if it is sampled low by the PHY for
more than 2.6 µs (128 SYSCLK cycles), and is considered active
otherwise (i.e., asserted steady high or an oscillating signal with a low
time less than 2.6 µs). The LPS input must be high for at least 21 ns in
order to be guaranteed to be observed as high by the PHY.
When the PDI1394P23 detects that LPS is inactive, it will place the
PHY-LLC interface into a low-power reset state. In the reset state, the
CTL and D outputs are held in the logic zero state and the LREQ input is
ignored; however, the SYSCLK output remains active. If the LPS input
remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC
interface is put into a low-power disabled state in which the SYSCLK
output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the
LCtrl register bit is set to 1, and is considered inactive if either the LPS
input is inactive or the LCtrl register bit is cleared to 0.
LREQ
CMOS 5V tol
1
H1
—
—
LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P23. Bus holder is built into this terminal.
NC
No connect
PC0
PC1
PC2
CMOS 5V tol
20
21
22
F7
E7
F8
I
Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 21 for encoding.
PD
CMOS 5V tol
14
G6
I
Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. For more information, refer to Section 17.2
2001 Sep 06
16, 54,
55
I
These pins are not internally connected and consequently are “don’t
cares”. Other vendors’ pin compatible chips may require
connections and external circuitry on these pins.
6
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
Name
Pin Type
PLLGND
Supply
PLLVDD
PDI1394P23
LFBGA
Ball
Numbers
I/O
Description
57, 58
E1, D3
—
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
Supply
56
D1, D4
—
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1 µF
and 0.001 µF. This supply terminals is separated from DVDD and AVDD
internal to the device to provide noise isolation. They should be tied at a
low impedance point on the circuit board.
Bias
40
41
D5
A4
—
Current setting resistor pins. These pins are connected to an external
resistor to set the internal operating currents and cable driver output
currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE
1394–1995 Std. output voltage limits.
CMOS 5V tol
53
C1
I
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to VDD is provided so only an external
delay capacitor is required for proper power-up operation. For more
information, refer to Section 17.2. This input is otherwise a standard
Schmitt logic input, and can also be driven by an open-drain type driver.
SYSCLK
CMOS
2
H2
O
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
TEST0
CMOS
29
C8
I
Test control input. This input is used in manufacturing tests of the
PDI1394P23. For normal use, this terminal should be tied to GND.
TPA0+,
TPA1+
Cable
37
46
B5
B3
I/O
TPA0–,
TPA1–
Cable
36
45
B6
A3
I/O
TPB0+,
TPB1+
Cable
35
44
C6
C4
I/O
TPB0–,
TPB1–
Cable
34
43
A7
B4
I/O
TPBIAS0,
TPBIAS1
Cable
38
47
A6
A2
I/O
27
D7
59
60
E2
E3
R0
R1
RESET
TWOPORT
XI
XO
2001 Sep 06
Crystal
LQFP
Pin
Numbers
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector. TPA1+ and TPA1– can be left unconnected if the
TWOPORT pin is tied to DGND.
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector. TPB1+ and TPB1– can be left unconnected if the
TWOPORT pin is tied to DGND.
Twisted-pair bias output. This provides the 1.86V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. These terminals must be decoupled with a
0.3 µF–1 µF capacitor to ground. TPBIAS1 can be left unconnected if
the TWOPORT pin is tied to DGND.
One/two port selector pin. This pin should be tied to DVDD for two port
operation and tied to DGND for one port operation. When tied to DVDD,
both ports 0 and 1 are operational. When tied to DGND, port 0 is
operational and port 1 is disabled.
—
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case and start supplying the external clock
before resetting the PDI1394P23). For more information, refer to
Section 17.5
7
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
6.0 BLOCK DIAGRAM
LPS
RECEIVED DATA
DECODER/
RETIMER
/ISO
CABLE POWER
DETECTOR
CPS
C/LKON
SYSCLK
LREQ
CTL0
CTL1
D0
CABLE PORT 0
LINK
INTERFACE
I/O
TPA0+
TPA0–
D1
D2
D3
D4
D5
D6
D7
ARBITRATION
AND CONTROL
STATE MACHINE
LOGIC
TPB0+
TPB0–
PC0
PC1
TPA1+
TPA1–
PC2
CNA
R0
R1
TPBIAS0
TPBIAS1
TWOPORT
PD
/RESET
CABLE PORT 1
TPB1+
TPB1–
BIAS VOLTAGE
AND
CURRENT
GENERATOR
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND CLOCK
GENERATOR
XI
XO
TRANSMIT
DATA
ENCODER
SV01785
7.0 FUNCTIONAL SPECIFICATION
the ISO on the PHY terminal must be tied high. For more details on
using single capacitor isolation, please refer to the Philips Isolation
Application Note AN2452.
The PDI1394P23 requires only an external 24.576 MHz crystal as a
reference. An external clock can be connected to XI instead of a
crystal. An internal oscillator drives an internal phase-locked loop
(PLL), which generates the required 393.216 MHz reference signal.
This reference signal is internally divided to provide the clock signals
used to control transmission of the outbound encoded Strobe and
Data information. A 49.152 MHz clock signal, supplied to the
associated LLC for synchronization of the two chips, is used for
resynchronization of the received data. The Power Down (PD)
function, when enabled by asserting the PD terminal high, stops
operation of the PLL and disables all circuits except the cable bias
detectors at the TPB terminals. The port transmitter circuitry and the
receiver circuitry are also disabled when the port is disabled,
suspended, or disconnected.
Data bits to be transmitted through the cable ports are received from
the LLC on two, four or eight parallel paths (depending on the
requested transmission speed). They are latched internally in the
PDI1394P23 in synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and transmitted at
98.304/196.608/393.216 Mbps (referred to as S100, S200, and
S400 speed, respectively) as the outbound data-strobe information
stream. During transmission, the encoded data information is
transmitted differentially on the TPB cable pair(s), and the encoded
strobe information is transmitted differentially on the TPA cable
pair(s).
The PDI1394P23 supports an optional isolation barrier between
itself and its LLC. When the ISO input terminal is tied high, the
LLC interface outputs behave normally. When the ISO terminal is
tied low, internal differentiating logic is enabled, and the outputs are
driven such that they can be coupled through a capacitive or
transformer galvanic isolation barrier as described in IEEE 1394a
section 5.9.4. To operate with single capacitor (bus holder) isolation,
2001 Sep 06
During packet reception the TPA and TPB transmitters of the
receiving cable port are disabled, and the receivers for that port are
enabled. The encoded data information is received on the TPA cable
pair, and the encoded strobe information is received on the TPB
cable pair. The received data-strobe information is decoded to
recover the receive clock signal and the serial data bits. The serial
8
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
The TWOPORT terminal is used to select between one port and two
port operation. This pin should be tied high for two port operation
and tied to ground to use the PDI1394P23 as a one port PHY.
data bits are split into two-, four- or eight-bit parallel streams
(depending upon the indicated receive speed), resynchronized to
the local 49.152 MHz system clock and sent to the associated LLC.
The received data is also transmitted (repeated) on the other active
(connected) cable ports.
Four package terminals, used as inputs to set the default value for
four configuration status bits in the self-ID packet, should be
hard-wired high or low as a function of the equipment design. The
PC0–PC2 terminals are used to indicate the default power-class
status for the node (the need for power from the cable or the ability
to supply power to the cable). See Table 21 for power class
encoding. The C/LKON terminal is used as an input to indicate that
the node is a contender for bus manager.
Both the TPA and TPB cable interfaces incorporate differential
comparators to monitor the line states during initialization and
arbitration. The outputs of these comparators are used by the
internal logic to determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to set the
speed of the next packet transmission (speed signaling). In addition,
the TPB channel monitors the incoming cable common-mode
voltage on the TPB pair for the presence of the remotely supplied
twisted-pair bias voltage (cable bias detection).
The PHY supports suspend/resume as defined in the IEEE 1394a
specification. The suspend mechanism allows pairs of directly
connected ports to be placed into a low power state while
maintaining a port-to-port connection between 1394 bus segments.
While in a low power state, a port is unable to transmit or receive
data transaction packets. However, a port in a low power state is
capable of detecting connection status changes and detecting
incoming TPBIAS. When all used ports of the PDI1394P23 are
suspended, all circuits except the bias-detection circuits are
powered down, resulting in significant power savings. The TPBIAS
circuit monitors the value of incoming TPA pair common-mode
voltage when local TPBIAS is inactive. Because this circuit has an
internal current source and the connected node has a current sink,
the monitored value indicates the cable connection status. This
monitor is called connect-detect.
The PDI1394P23 provides a 1.86 V nominal bias voltage at the
TPBIAS terminal for port termination. The PHY contains two
independent TPBIAS circuits. This bias voltage, when seen through
a cable by a remote receiver, indicates the presence of an active
connection. This bias voltage source must be stabilized by an
external filter capacitor of 0.3 µF–1 µF.
The line drivers in the PDI1394P23 operate in a high-impedance
current mode, and are designed to work with external 112 Ω
line-termination resistor networks in order to match the 110 Ω cable
impedance. One network is provided at each end of all twisted-pair
cable connections. Each network is composed of a pair of
series-connected 56 Ω resistors. The midpoint of the pair of resistors
that is directly connected to the twisted-pair A terminals is connected
to its corresponding TPBIAS voltage terminal. The midpoint of the pair
of resistors that is directly connected to the twisted-pair B terminals is
coupled to ground through a parallel R-C network with recommended
values of 5 kΩ and 220 pF. The values of the external line termination
resistors are designed to meet the standard specifications when
connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver
output current, along with other internal operating currents. This
current setting resistor should be a low TCR part with a value of
6.34 kΩ ±1%.
Both the cable bias-detect monitor and TPBIAS connect-detect
monitor are used in suspend/resume signaling and cable connection
detection. For additional details of suspend/resume operation, refer
to the 1394a specification. The use of suspend/resume is
recommended for new designs.
The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the RESET input terminal is asserted low), when no active
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.
When the power supply of the PDI1394P23 is removed while the
twisted-pair cables are connected, the PDI1394P23 transmitter and
receiver circuitry presents a high impedance to the cable in order to
not load the TPBIAS voltage on the other end of the cable.
The CNA (cable-not-active) terminal provides a high when there are
no twisted-pair cable ports receiving incoming bias (i.e., they are
either disconnected or suspended), and can be used along with LPS
to determine when to power-down the PDI1394P23. The CNA
output is not debounced. When the PD terminal is asserted high, the
CNA detection circuitry is enabled (regardless of the previous state
of the ports) and a pull-down is activated on the RESET terminal so
as to force a reset of the PDI1394P23 internal logic.
When the PDI1394P23 is used with one or more of the ports not
brought out to a connector, the twisted-pair terminals of the unused
ports must be terminated for reliable operation. For each unused
port, the TPB+ and TPB– terminals can be tied together and then
pulled to ground, or the TPB+ and TPB– terminals can be connected
to the suggested termination network. The TPA+ and TPA– and
TPBIAS terminals of an unused port can be left unconnected.
The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC is used in conjunction with the LCtrl bit (see Table 1
and Table 2) to indicate the active/power status of the LLC. The LPS
signal is also used to reset, disable, and initialize the PHY-LLC
interface (the state of the PHY-LCC interface is controlled solely by
the LPS input regardless of the state of the LCtrl bit).
The TEST0 terminal is used to set up various manufacturing test
conditions. For normal operation, it should be connected to ground.
The BRIDGE terminal is used to set the default value of the
Bridge_Aware bits in the Page 7 (Vendor Dependent) register. Tying
BRIDGE low directly (or through a 1 kΩ resistor to accommodate
other vendors’ pin-compatible chips), defaults the Bridge_Aware
field to “00” indicating a “non-bridge device.” Tying BRIDGE high,
defaults the Bridge_Aware bit to “11” indicating a “1394.1 bridge
compliant” device. Writing to the Bridge_Aware field overrides the
default setting from the BRIDGE terminal. The Bridge_Aware field is
reported in the self-ID packet at bit positions 18 and 19.
2001 Sep 06
PDI1394P23
9
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
The PHY uses the C/LKON terminal to notify the LLC to power up
and become active. When activated, the C/LKON signal is a square
wave of approximately 163 ns period. The PHY activates the
C/LKON output when the LLC is inactive and a wake-up event
occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrI bit is cleared to 0. A
wake-up event occurs when a link-on PHY packet addressed to this
node is received, or conditionally when a PHY interrupt occurs. The
PHY deasserts the C/LKON output when the LLC becomes active
(both LPS active and the LCtrl bit set to 1). The PHY also deasserts
the C/LKON output when a bus-reset occurs unless a PHY interrupt
condition exists which would otherwise cause C/LKON to be active.
The LPS input is considered inactive if it remains low for more than
2.6 µs and is considered active otherwise. When the PDI1394P23
detects that LPS is inactive, it will place the PHY-LLC interface into a
low-power reset state in which the CTL and D outputs are held in the
logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for
more than 26 µs, the PHY–LLC interface is put into a low-power
disabled state in which the SYSCLK output is also held inactive. The
PHY-LLC interface is also held in the disabled state during hardware
reset. The PDI1394P23 will continue the necessary repeater
functions required for normal network operation regardless of the
state of the PHY-LLC interface. When the interface is in the reset or
disabled state and LPS is again observed active, the PHY will
initialize the interface and return it to normal operation.
8.0 ABSOLUTE MAXIMUM RATINGS 1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
VDD
VI
VI–5V
VO
PARAMETER
CONDITION
UNIT
MIN
MAX
DC supply voltage
–0.5
4.0
V
DC input voltage
–0.5
VDD+0.5
V
5 volt tolerant input voltage range
–0.5
5.5
V
DC output voltage range at any output
–0.5
VDD+0.5
V
Human Body Model
—
2
kV
Machine Model
—
200
V
0
+70
°C
–65
+150
°C
Electrostatic discharge
Tamb
Operating free-air temperature range
Tstg
Storage temperature range
NOTE:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2001 Sep 06
10
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
9.0 RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
PARAMETER
MIN
TYP
MAX
UNIT
3.0
3.3
3.6
V
Non-source power node
2.7 1
3.0
3.6
V
ISO = VDD, VDD >= 2.7 V
2.3
—
—
V
ISO = VDD, VDD >= 3.0 V
2.6
—
—
V
High-level input voltage, C/LKON2,
PC0–PC2, ISO, PD
0.7 VDD
—
—
V
High-level input voltage, RESET
0.6 VDD
—
—
—
—
—
0.7
V
—
—
0.2 VDD
V
—
—
0.3 VDD
—
2.5
mA
Supply
Su
ly voltage
High-level
g
input voltage,
g LREQ,
CTL0, CTL1, D0-D7
VIH
Low-level input voltage, LREQ,
CTL0, CTL1, D0–D7
VIL
CONDITION
Source power node
ISO = VDD
Low-level input voltage, C/LKON2,
PC0–PC2, ISO, PD,
Low-level input voltage, RESET
IO
Output current
VID
input
amplitude
Differential in
ut voltage am
litude
VIC-100
IC 100
VIC-200
IC 200
VIC-400
IC 400
tPU
TPB common-mode in
input
ut voltage
input
TPB common-mode in
ut voltage
–6
TPA, TPB cable inputs, during data reception
118
—
260
mV
TPA, TPB cable inputs, during data arbitration
168
—
265
mV
Source power node
1.165
—
2.515
V
Non-source power node
1.165
—
2.0151
V
Source power node
0.935
—
2.515
V
V
V
Speed signaling
g
g off
or S100 speed signal
S200 sspeed
eed signal
Non-source power node
0.935
—
2.0151
Source power node
0.523
—
2.515
Non-source power node
0.523
—
2.0151
V
TPB common-mode in
input
ut voltage
S400 sspeed
eed signal
Power-up reset time
Set by capacitor between RESET pin and GND
2
—
—
ms
TPA, TPB cable inputs, S100 operation
—
—
1.08
ns
TPA, TPB cable inputs, S200 operation
—
—
0.5
ns
TPA, TPB cable inputs, S400 operation
—
—
0.315
ns
Between TPA and TPB cable inputs, S100 operation
—
—
0.8
ns
Receive input skew
Between TPA and TPB cable inputs, S200 operation
—
—
0.55
ns
Between TPA and TPB cable inputs, S400 operation
—
—
0.5
ns
Crystal or external clock frequency
Crystal connected according to Figure 10 or external
clock input at pin XI
24.5735
24.576
24.5785
MHz
Receive input jitter
fXTAL
TPBIAS outputs
NOTES:
1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).
2. C/LKON is only an input when RESET = 0.
2001 Sep 06
11
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
10.0 CABLE DRIVER
SYMBOL
PARAMETER
TEST CONDITION
LIMITS
MIN
TYP
MAX
UNIT
Differential output voltage
56 Ω load
172
—
265
mV
IO(diff)
Driver Difference current, TPA+, TPA–, TPB+, TPB– 1
Drivers enabled,
speed signaling OFF
–0.88
—
0.88
mA
ISP
S
Common mode speed signaling
g
g output current,, TPB+,,
TPB– 2
200 Mbps speed signaling enabled
–4.84
—
–2.53
mA
400 Mbps speed signaling enabled
–12.4
—
–8.10
mA
OFF state differential voltage
Drivers disabled
—
—
20
mV
VOD
VOFF
NOTES:
1. Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.
2. Limits defined as one half of the algebraic sum of currents flowing out of TPB+ and TPB–.
11.0 CABLE RECEIVER
SYMBOL
ZID
PARAMETER
Differential input impedance
TEST CONDITION
Drivers disabled
ZIC
C
Common mode input impedance
Drivers disabled
LIMITS
MIN
TYP
MAX
10
14
—
UNIT
kΩ
—
—
4
pF
20
—
—
kΩ
—
—
24
pF
VTH-R
Receiver input threshold voltage
Drivers disabled
–30
—
30
mV
VTH-CB
Cable bias detect threshold, TPBn cable inputs
Drivers disabled
0.6
—
1.0
V
VTH+
Positive arbitration comparator input threshold
voltage
Drivers disabled
89
—
168
mV
VTH–
Negative arbitration comparator input threshold
voltage
Drivers disabled
–168
—
–89
mV
VTH–SP200
Speed signal input threshold
TPBIAS–TPA common mode voltage,
drivers disabled 200 Mbps
49
—
131
mV
VTH–SP400
Speed signal input threshold
TPBIAS–TPA common mode voltage,
drivers disabled 400 Mbps
314
—
396
mV
Connect detect output at TPBIAS pins
Drivers disabled
—
—
–76
µA
ICD
2001 Sep 06
12
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
12.0 OTHER DEVICE I/O
SYMBOL
MIN
TYP
MAX
UNIT
See Note 1
—
81
—
mA
See Note 2
—
56
—
mA
See Note 3
—
50
—
mA
Supply current in power down mode
PD = VDD in power down mode
—
150
—
µA
VTH
Cable power status threshold voltage
390 kΩ resistor between cable power
and CPS pin: Measured at cable power
side of resistor
4.7
—
7.5
V
VDD = 2.7 V, IOH = –4 mA, ISO = VDD
2.4
—
—
V
VOH
High-level
Hi
hl
l output
t t voltage,
lt
pins
i CTL0
CTL0,
CTL1, D0
D0–D7,
D7, SYSCLK, CNA
VDD >= 3.0 V, IOH = –4 mA, ISO = VDD
2.8
—
—
V
IDD
IDD–PD
PARAMETER
Supply current
TEST CONDITION
Annex J: IOH = –9 mA, ISO = 0
VDD–0.4
—
—
V
IOL = 4 mA, ISO = VDD
—
—
0.4
V
Annex J: IOL = 9 mA, ISO = 0
—
—
0.4
V
VDD = 2.7 V, IOH = –4 mA; See Note 4
2.4
—
—
V
VDD >= 3.0 V, IOH = –4 mA; See Note 4
2.7
—
—
V
—
—
0.3
V
VOL
O
Low-level output voltage,
g , pins CTL0,,
CTL1, D0–D7, CNA, SYSCLK
VOH
O
High level output voltage,
High-level
voltage pin C/LKON
VOL
Low-level output voltage, pin C/LKON
VDD = 2.7 V, IOL = 4 mA; See Note 4
IBH+
Positive peak bus holder current, pins
CTL0, CTL1, D0–D7, LREQ
ISO = VDD, VI = 0 V to VDD
0.05
—
1.0
mA
IBH–
Negative peak bus holder current, pins
CTL0, CTL1, D0–D7, LREQ
ISO = VDD, VI = 0 V to VDD
–1.0
—
–0.05
mA
II
Input current, pins LREQ, LPS, PD,
TEST0, BRIDGE, PC0–PC2
ISO = 0 V; VDD = 3.6 V
—
—
5
µA
IOZ
Off-state current, pins CTL0, CTL1,
D0–D7, C/LKON
VO = VDD or 0 V
–5
—
5
µA
IRST-UP
Pullup current, RESET input
VI = 1.5 V or 0 V
–90
—
–20
µA
IRST-DN
Pulldown current, RESET input
VI = VDD, PD = VDD
.4
1.6
2.8
mA
VIT+
Positive going threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
ISO = 0 V
VDD/2 + 0.3
—
VDD/2 + 0.9
V
VIT–
Negative going threshold voltage, LREQ,
ISO = 0 V
CTL0, CTL1, D0–D7 inputs
VDD/2 – 0.9
—
VDD/2 – 0.3
V
VLIT+
Positive going threshold voltage, LPS
inputs
VLREF = 0.42 x VDD
—
—
VLREF+1
V
VLIT–
Negative going threshold voltage, LPS
inputs
VLREF = 0.42 x VDD
VLREF+0.2
—
—
V
VO
TPBIAS output voltage
At rated IO current
1.665
—
2.015
V
NOTES:
1. Transmit Max Packet (2 ports transmitting max size isochronous packet (4096 bytes), sent on every isochronous interval, S400, data value
of 0xCCCCCCCCh), VDD = 3.3 V, TA = 25 °C
2. Repeat typical packet (1 port receiving DV packets on every isochronous interval, 1 port repeating the packet, S100), VDD = 3.3 V,
TA = 25 °C
3. Idle (receive cycle start on one port, transmit cycle start on other port) VDD = 3.3 V, TA = 25 °C
4. The C/LKON pin is able to drive an isolation circuit according to Figure 5A-20 of the IEEE-1394a-2000 standard.
2001 Sep 06
13
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
13.0 THERMAL CHARACTERISTICS
SYMBOL
RΘjA
PARAMETER
TEST CONDITION
Junction-to-free-air thermal resistance
Board mounted, no air flow
LIMITS
UNIT
MIN
TYP
MAX
—
68
—
°C/W
14.0 AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITION
Transmit jitter
TPA, TPB
MIN
TYP
MAX
UNIT
—
—
0.15
ns
Transmit skew
Between TPA and TPB
—
—
0.10
ns
tr
TPA, TPB differential output voltage rise time
10% to 90%; At 1394 connector
0.5
—
1.2
ns
tf
TPA, TPB differential output voltage fall time
90% to 10%; At 1394 connector
0.5
—
1.2
ns
tSU
Setup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK
50% to 50%; See Figure 2
5
—
—
ns
tH
Hold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK
50% to 50%; See Figure 2
0
—
—
ns
tD
Delay time SYSCLK to CTL0, CTL1, D0–D7
50% to 50%; See Figure 3
0.5
—
11
ns
CL
Capacitance load value CTL0, CTL1, D0–D7,
SYSCLK
—
10
—
pF
Ci
Input capacitance CTL0, CTL1, D0–D7, LREQ
—
3.3
—
pF
15.0 TIMING WAVEFORMS
TPAn+
TPBn+
SYSCLK
56 Ω
tD
TPAn–
TPBn–
Dn, CTLn
SV01098
SV01803
Figure 1. Test load diagram
Figure 3. Dn, CTLn, output delay relative to SYSCLK
SYSCLK
tSU
tH
Dn, CTLn, LREQ
SV01099
Figure 2. Dn, CTLn, LREQ input setup and hold times
2001 Sep 06
14
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
16.0 INTERNAL REGISTER CONFIGURATION
The configuration of the base registers is shown in Table 1, and
corresponding field descriptions are given in Table 2. The base
register field definitions are unaffected by the selected page number.
There are 16 accessible internal registers in the PDI1394P23. The
configuration of the registers at addresses 0 through 7 (the base
registers) is fixed, while the configuration of the registers at
addresses 8h through Fh (the paged registers) is dependent upon
which one of eight pages, numbered 0h through 7h, is currently
selected. The selected page is set in base register 7h.
A reserved register or register field (marked as Reserved or Rsvd in
the following register configuration tables) is read as 0, but is subject
to future usage. All registers in address pages 2 through 6 are
reserved.
Table 1. Base Register Configuration
BIT POSITION
ADDRESS
0
1
RHB
IBR
2
0000
0001
3
4
5
Physical ID
6
7
R
CPS
Gap_Count
0010
Extended (111b)
Rsvd
Num_Ports (0010b)
0011
PHY_Speed (010b)
Rsvd
Delay (0001b)
Jitter (000)
0100
LCtrl
C
0101
RPIE
ISBR
CTOI
Pwr_Class
CPSI
0110
STOI
PEI
EAA
EMC
Reserved
0111
Page_Select
Rsvd
Port Select
Table 2. Base Register Field Descriptions
SIZE
TYPE
Physical ID
FIELD
6
Rd
This field contains the physical address ID of this node determined during self-ID. The physical-ID is
invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status
transfer.
R
1
Rd
Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to
1 during tree-ID if this node becomes root.
CPS
1
Rd
Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally
tied to serial bus cable power through a 390 kΩ resistor. A 0 in this bit indicates that the cable power
voltage has dropped below its threshold for ensured reliable operation.
RHB
1
Rd/Wr
Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB
bit is reset to 0 by a hardware reset, and is unaffected by a bus reset.
IBR
1
Gap_Count
6
Rd/Wr
Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay
times. The gap count can be set either by a write to the register, or by reception or transmission of a
PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus
resets without an intervening write to the gap count register (either by a write to the PHY register or by
a PHY_CONFIG packet).
Extended
3
Rd
Extended register definition. For the PDI1394P23, this field is 111b, indicating that the extended register
set is implemented.
Num_Ports
4
Rd
Number of ports. This field indicates the number of ports implemented in the PHY. For the PDI1394P23
with the TWOPORT pin high this field is 2. With the TWOPORT pin low this field is 1.
PHY_Speed
3
Rd
PHY speed capability. For the PDI1394P23, this field is 010b, indicating S400 speed capability.
Delay
4
Rd
PHY repeater data delay. This field indicates the worst case repeater data delay for this PHY,
expressed as 144+(delay × 20) ns. For the PDI1394P23, this field is 1.
2001 Sep 06
Rd/Wr
DESCRIPTION
Initiate bus reset. This bit instructs the PHY to initiate a long (166 µs) bus reset at the next opportunity.
Any receive or transmit operation in progress when this bit is set will complete before the bus reset is
initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset.
15
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
FIELD
LCtrl
SIZE
TYPE
1
Rd/Wr
PDI1394P23
DESCRIPTION
Link-active status control. This bit is used to control the active status of the LLC as indicated during
self-ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the
self-ID packet. The LLC is considered active only if both the LPS input is active the and LCtrl bit is set.
The LCtrl bit provides a software controllable means to indicate the LLC active status in lieu of using the
LPS input.
The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state
of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active,
then received packets and status information will continue to be presented on the interface, and any
requests indicated on the LREQ input will be processed, even if the LCtrl bit is cleared to 0.
C
1
Jitter
3
Pwr_Class
3
RPIE
1
ISBR
1
Rd/Wr
Rd
Rd/Wr
Rd/Wr
Rd/Wr
Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the “c” field (bit 20) of the self-ID packet. This bit is set to the state
specified by the C/LKON input terminal by a hardware reset and is unaffected by a bus reset.
PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest
repeater data delay, expressed as (Jitter + 1) × 20 ns. For the PDI1394P23, this field is 0.
Node power class. This field indicates this node’s power consumption and source characteristics and is
replicated in the pwr field (bits 21–23) of the self-ID packet. This field is reset to the state specified by
the PC0–PC2 input terminals upon hardware reset, and is unaffected by a bus reset. See Table 21.
Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set
whenever resume operations begin on any port. This bit is reset to 0 by hardware reset and is
unaffected by bus reset.
Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 µs)
arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset.
NOTE: Legacy IEEE Std 1394–1995 compliant PHYs are not capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long
bus reset being performed.
CTOI
1
Rd/Wr
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times-out during
tree-ID start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware
reset, or by writing a 1 to this register bit.
NOTE: If the network is configured in a loop, only those nodes which are part of the loop should
generate a configuration time out interrupt. All other nodes should instead time out waiting for the
tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset.
CPSI
1
Rd/Wr
Cable-power-status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low
indicating that cable power may be too low for reliable operation. This bit is set to 1 by hardware reset,
and set to 0 by writing a 1 to this register bit.
STOI
1
Rd/Wr
State time-out interrupt. This bit indicates that a state time-out has occurred. This bit is reset to 0 by
hardware reset, or by writing a 1 to this register bit.
PEI
1
Rd/Wr
Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for
any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt
enable (RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is
reset to 0 by hardware reset, or by writing a 1 to this register bit.
EAA
1
Rd/Wr
Enable arbitration acceleration. This bit enables the PHY to perform the various arbitration acceleration
enhancements defined in P1394a (ACK-accelerated arbitration, asynchronous fly-by concatenation,
and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus
reset.
NOTE: The EAA bit should be set only if the attached LLC is P1394a compliant. If the LLC is not
P1394a compliant, use of the arbitration acceleration enhancements can interfere with isochronous
traffic by excessively delaying the transmission of cycle-start packets.
EMC
1
Rd/Wr
Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of
differing speeds in accordance with the protocols defined in P1394a. This bit is reset to 0 by hardware
reset and is unaffected by bus reset.
NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy
IEEE Std 1394–1995 PHYs. However, use of multispeed concatenation requires that the attached LLC
be P1394a compliant.
Page_Select
3
Rd/Wr
Page_Select. This field selects the register page to use when accessing register addresses 8 through
15. This field is reset to 0 by a hardware reset and is unaffected by bus-reset.
Port_Select
4
Rd/Wr
Port_Select. This field selects the port when accessing per-port status or control (e.g., when one of the
port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset
to 0 by hardware reset and is unaffected by bus reset.
2001 Sep 06
16
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
The Port Status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the
Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is
shown in Table 3 and corresponding field descriptions given in Table 4. If the selected port is unimplemented, all registers in the port status page
are read as 0.
Table 3. Page 0 (Port Status) Register Configuration
BIT POSITION
ADDRESS
0
1000
1
2
AStat
1001
3
BStat
Peer_Speed
PIE
4
5
6
7
Ch
Con
Bias
Dis
Fault
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Reserved
Table 4. Page 0 (Port Status) Register Field Descriptions
FIELD
AStat
SIZE
TYPE
2
Rd
DESCRIPTION
TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
Code
11
01
10
00
Arb Value
Z
1
0
invalid
BStat
2
Rd
TPB line state. This field indicates the TPB line state of the selected port. This field has the same
encoding as the ASTAT field.
Ch
1
Rd
Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected
port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch
bit is invalid after a bus-reset until tree-ID has completed.
Con
1
Rd
Debounced port connection status. This bit indicates that the selected port is connected. The
connection must be stable for the debounce time of 330ms–350ms for the Con bit to be set to 1. The
Con bit is reset to 0 by hardware reset and is unaffected by bus reset.
NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but the port is not
necessarily active.
Bias
1
Rd
Dis
1
Rd/Wr
Peer_Speed
3
Rd
Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable
bias. The incoming cable bias must be stable for the debounce time of 41.6µs–52µs for the Bias bit to
be set to 1.
Port disabled control. If 1, the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all
ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus
reset.
Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the
selected port, encoded as follows:
Code
000
001
010
011–111
Peer Speed
S100
S200
S400
invalid
The Peer_Speed field is invalid after a bus reset until self-ID has completed.
NOTE: Peer speed codes higher than 010b (S400) are defined in P1394a. However, the PDI1394P23
is only capable of detecting peer speeds up to S400.
PIE
1
Rd/Wr
Port event interrupt enable. When set to 1, a port event on the selected port will set the port event
interrupt (PEI) bit and notify the link. This bit is reset to 0 by a hardware reset, and is unaffected by
bus-reset.
Fault
1
Rd/Wr
Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that
the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming
cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect
incoming cable bias from its attached peer. Writing 1 to this bit clears the fault bit to 0. This bit is reset to
0 by hardware reset and is unaffected by bus reset.
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
The Vendor Identification page is used to identify the vendor/manufacturer and compliance level. The page is selected by writing 1 to the
Page_Select field in base register 7. The configuration of the Vendor Identification page is shown in Table 5, and corresponding field
descriptions are given in Table 6.
Table 5. Page 1 (Vendor ID) Register Configuration
BIT POSITION
ADDRESS
0
1
2
3
4
1000
Compliance
1001
Reserved
1010
Vendor_ID[0]
1011
Vendor_ID[1]
1100
Vendor_ID[2]
1101
Product_ID[0]
1110
Product_ID[1]
1111
Product_ID[2]
5
6
7
Table 6. Page 1 (Vendor ID) Register Field Descriptions
SIZE
TYPE
Compliance
FIELD
8
Rd
Compliance level. For the PDI1394P23, this field is 01h, indicating compliance with the P1394a
specification.
DESCRIPTION
Vendor_ID
24
Rd
Manufacturer’s organizationally unique identifier (OUI). For the PDI1394P23, this field is 00_60_37h
(Philips Semiconductors) (the MSB is at register address 1010b).
Product_ID
24
Rd
Product identifier. For the PDI1394P23, this field is 42_20_01 (the MSB is at register address 1101b).
The Vendor-Dependent page provides access to the special control features of the PDI1394P23, as well as configuration and status information
used in manufacturing test and debug. This page is selected by writing 7 to the Page Select field in base register 7. The configuration of the
Vendor-Dependent page is shown in Table 7 and corresponding field descriptions given in Table 8.
Table 7. Page 7 (Vendor-Dependent) Register Field Descriptions
ADDRESS
BIT POSITION
0
1
2
3
1000
Reserved
1001
Reserved for test
4
6
7
Link_Speed
1010
Reserved for test
1011
Reserved for test
1100
Reserved for test
1101
Reserved for test
1110
Reserved for test
1111
Reserved for test
2001 Sep 06
5
18
Bridge_Aware
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
Link_Speed
SIZE
TYPE
2
Rd/Wr
DESCRIPTION
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
00
01
10
11
Speed
S100
S200
S400
illegal
This field is replicated in the “sp” field of the self-ID packet to indicate the speed capability of the node
(PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to
peer PHYs during self-ID; the PDI1394P23 PHY identifies itself as S400 capable to its peers regardless
of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
An 11b can be written into this field, however, a 10b will be sent in the self-ID packet.
Bridge_Aware
2
Rd/Wr
Bridge_Aware. This field reports Bridge_Aware capability to all nodes via the self-ID packet. Encoding
is as follows:
Code
00
01
10
11
Meaning
Non-bridge device
Reserved (BRAN Bridge)
Bridge compliant with 1394.1 (unchanged state)
Bridge compliant with 1394.1 (changed state)
This field is replicated in bits 18 and 19 of the self-ID packet. The value of this field does not affect PHY
operation. It is a reporting mechanism. The default value for this field is set by the BRIDGE pin. The
BRIDGE pin is sampled during a hardware reset (RESET low). When the BRIDGE pin is low, this field
is set to “00” indicating a “non-bridge device.” When the BRIDGE pin is high, this field is set to “11”
indicating a “1394.1 bridge compliant” device. Writing to this field overrides the default setting by the
BRIDGE pin.
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
17.0 APPLICATION INFORMATION
390KΩ
CPS
PDI1394P23
0.3–1.0 µF
TPBIAS
56Ω
VP
CABLE
VG
POWER PAIR
56Ω
TPAn+
CABLE
PAIR A
TPAn–
CABLE PORT
TPBn+
CABLE
PAIR B
TPBn–
56Ω
56Ω
OUTER SHIELD
TERMINATION
220pF
5 kΩ
SV01821
The IEEE Std 1394–1995 calls for a 250 pF capacitor, which is a non-standard component value. A 220 pF capacitor is recommended.
Figure 4. Twisted pair cable interface connections
NON-ISOLATED
OUTER SHIELD TERMINATION
COMPLIANT DC-ISOLATED
OUTER SHIELD TERMINATION
OUTER CABLE SHIELD
1 MΩ
0.01 µF
0.1 µF
OUTER CABLE SHIELD
CHASSIS GROUND
CHASSIS GROUND
SV01748
Figure 5. Cable outer shield termination methods
10 kΩ
3
VDD
6
SQUARE WAVE INPUT
LPS
10 kΩ
DVDD (AVDD)
SV01805
SV01806
Use one of these networks per side for all digital power and ground
pins and one per side for all analog power and ground pins. Place
the network as close to the PHY as possible.
Figure 6. Power supply decoupling network
2001 Sep 06
LPS
DGND (AGND)
0.001 µF
0.1 µF
LINK POWER
Figure 7. Non-isolated connection variations for LPS
20
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
PHY VDD
13 kΩ
3.3 nF
PHY CHIP
LINK LAYER CHIP
10 K
LPS
SQUARE WAVE SIGNAL
CONTENDER/
LINKON
C/LKON
9.1 kΩ
10 K
SV01807
Figure 8. Isolated circuit connection for LPS
LINK LAYER CHIP
LINKON
TIE TO LLCVDD (CONTENDER)
OR GND (NOT CONTENDER)
PHY CHIP
C/LKON
SV01873
Figure 9. Three configurations for C/LKON signal in a
non-isolated system
2001 Sep 06
21
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
17.1 External Component Connections
REFER TO SECTION 17.5
VDD
12 pF
12 pF
0.1 µF
24.576 MHz
CONNECT RESET TO THE SAME SOURCE AS THE LINK IC
OR THROUGH OPTOCOUPLER FOR GALVANIC ISOLATION.
USE 0.1 µF CAPACITOR TO GND ONLY IN NON-LINK DESIGNS.
0.001 µF
CNA OUT
AGND
AGND
AV DD
AV DD
NC
RESET
NC
PLLVDD
PLLGND
XI
PLLGND
XO
DV DD
DGND
DV DD
DGND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
0.3–1.0 µF
1
LREQ
2
SYSCLK
3
CNA
4
CTL0
TPA1– 45
5
CTL1
TPB1+ 44
6
D0
TPB1– 43
7
D1
AVDD 42
8
D2
R1 41
9
D3
10
D4
AGND 39
TPBIAS0 38
11
D5
12
D6
13
AGND 48
TPBIAS1 47
TPBIAS
TPA1+ 46
PDI1394P23
R0 40
TPA0+
D7
TPA0– 36
14
PD
TPB0+ 35
LINK PULSE OR
LINK VDD OR VDD
(REFER TO
FIGURES 7 AND 8)
15
LPS
16
NC
TPB0– 34
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE CONNECTION
(REFER TO FIGURES 4 AND 5)
33
AGND
AVDD
TEST0
AVDD
BRIDGE
TWOPORT
DVDD
DVDD
CPS
ISO
PC2
PC1
C/LKON
PC0
DGND
DGND
6.34 kΩ ±1%
37
POWER DOWN
AGND
TP CABLES
INTERFACE CONNECTION
(REFER TO FIGURES 4 AND 5)
ISO
390 kΩ
CABLE POWER
POWER CLASS
PROGRAMMING
(SEE FIGURE 9)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SV001872
See Figure 6 for recommended power and ground connections.
Figure 10. External Component Connections
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
request, the arbitration enhancements should not be enabled (see
the EAA bit in PHY register 5).
17.2 RESET and Power Down
Forcing the RESET pin low resets the internal logic to the Reset
Start state and deactivates SYSCLK. Returning the RESET pin high
causes a Bus Reset condition on the active cable ports. For
power-up (and after Power Down is asserted) RESET must be
asserted low for a minimum of 2 ms from the time that the PHY
power reaches the minimum required supply voltage. This is
required to assure proper PLL operation before the PHY begins
using the clock.
• The capability to perform multispeed concatenation (the
concatenation of packets of differing speeds) was added in order
to improve bus efficiency (primarily during isochronous
transmission). If the LLC does not support multispeed
concatenation, multispeed concatenation should not be enabled
in the PHY (see the EMC bit in PHY register 5).
• In order to accommodate the higher transmission speeds expected
The PHY must come out of RESET simultaneously or just after the
Link comes out of RESET so that the LLC/PHY handshake occurs
properly. To assure that this happens, it is recommended that the
same signal source originate LLC and PHY reset signals. If galvanic
isolation is used, an optocoupler should be used to drive the RESET
pin of the PHY. (See Philips AN2452 “IEEE 1394 bus node galvanic
isolation and power supply design”.) If galvanic isolation is not used,
the LCC and PHY reset pins should be connected directly together.
A single capacitor on the RESET pin of the PHY as described below
is recommended only in designs without an LLC device (i.e. repeater
designs).
in future revisions of the standard, P1394a extended the speed
code in bus requests from 2 bits to 3 bits, increasing the length of
the bus request from 7 bits to 8 bits. The new speed codes were
carefully selected so that new P1394a PHY and LLC devices
would be compatible, for speeds from S100 to S400, with legacy
PHY and LLC devices that use the 2-bit speed codes. The
PDI1394P23 correctly interprets both 7-bit bus requests (with 2-bit
speed code) and 8-bit bus requests (with 3-bit speed codes).
Moreover, if a 7-bit bus request is immediately followed by another
request (e.g., a register read or write request), the PDI1394P23
correctly interprets both requests. Although the PDI1394P23
correctly interprets 8-bit bus requests, a request with a speed code
exceeding S400 results in the PDI1394P23 transmitting a null
packet (data-prefix followed by data-end, with no data in the
packet).
An internal pull-up resistor is connected to VDD, so only an external
delay capacitor is required. When using a passive capacitor on the
RESET terminal to generate a power-on reset signal, the minimum
reset time will be assured if the capacitor has a minimum value of
0.1 µF and also satisfies the following equation:
17.4 Using the PDI1394P23 with a lower-speed
link layer
Cmin = 0.0077 × T + 0.085
where Cmin is the minimum capacitance on the RESET terminal in
µF, and T is the VDD ramp time, 10%–90%, in ms.
Although the PDI1394P23 is an S400 capable PHY, it may be used
with lower speed LLCs. In such a case, the LLC has fewer data
terminals than the PHY, and some Dn terminals on the PDI1394P23
will be unused. Unused Dn terminals should be pulled to ground
through 10 kΩ resistors.
An alternative to the passive reset is to actively drive RESET low for
the minimum reset time following power on. This input is a standard
logic Schmitt buffer and may also be driven by an open drain logic
output buffer.
The PDI1394P23 transfers all received packet data to the LLC, even
if the speed of the packet exceeds the capability of the LLC to
accept it. Some lower speed LLC designs do not properly ignore
packet data in such cases. On the rare occasions that the first 16
bits of partial data accepted by such a LLC match a node’s bus and
node ID, spurious header CRC or tcode errors may result.
The RESET pin also has an internal n-channel pull-down transistor
activated by the Power Down pin. For a reset during normal
operation, a 10 µs low pulse on this pin will accomplish a full PHY
reset. This pulse, as well as the 2 ms power up reset pulse, could be
microprocessor controlled, in which case the external delay
capacitor would not be needed. For more details on using single
capacitor isolation with this pin, please refer to the Philips Isolation
Application Note AN2452.
In discussing this topic, the reader should be aware that the
IEEE1394a-2000 standard (paragraph 8.3.2.4.2) made the speed
maps defined in IEEE1394-1995 obsolete and defined a new field
(link_spd) in the Configuration ROM Bus_Info_Block where the
maximum speed of the node’s link layer is available. The
PDI1394P23 PHY’s default maximum speed is reported in the
self-ID packet. The IEEE1394a-2000 standard notes that bus
managers that implement the SPEED_MAP registers as specified
by IEEE Std 1394-1995 are compliant with the IEEE1394a-2000
standard but users are cautioned that the addresses utilized by
these registers may be redefined in future IEEE standards. Without
a bus manager-created and maintained speed map, in order to
transmit at the highest speed along a path, a transmitting node must
determine the node speed capability (lesser of link speed or PHY
speed) for a target node and each of the PHY speed capabilities
along the path between the source and target nodes. That is, each
node would have to create a network speed map. Some designers
may choose to implement a speed map in bus manager-capable
nodes to maximize transmission speed when a slower-than-PHY
link chip exists in a node along the transmission path. The following
paragraphs are presented for use with products that utilize speed
maps.
The Power Down input powers down all device functions with the
exception of the CNA circuit to conserve power in portable or
battery-powered applications. It must be held high for at least 2 ms
to assure a successful reset after power down.
17.3 Using the PDI1394P23 with a non-P1394a
link layer
The PDI1394P23 implements the PHY-LLC interface specified in the
P1394a Supplement. This interface is based upon the interface
described in informative Annex J of IEEE Std 1394-1995, which is the
interface used in older PHY devices. The PHY-LLC interface specified
in P1394a is completely compatible with the older Annex J interface.
The P1394a Supplement includes enhancements to the Annex J
interface that must be comprehended when using the PDI1394P23
with a non-P1394a LLC device.
• A new LLC service request was added which allows the LLC to
temporarily enable and disable asynchronous arbitration
accelerations. If the LLC does not implement this new service
2001 Sep 06
PDI1394P23
23
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
have a difference of up to 200 ppm from each other in their internal
clocks, and PHYs must be able to compensate for this difference
over the maximum packet length. Larger clock variations may cause
resynchronization overflows or underflows, resulting in corrupted
packet data.
During bus initialization following a bus-reset, each PHY transmits a
self-ID packet that indicates, among other information, the speed
capability of the PHY. The bus manager (if one exists) may build a
speed-map from the collected self-ID packets. This speed-map
gives the highest possible speed that can be used on the
node-to-node communication path between every pair of nodes in
the network. However, as explained below, the speed reported in the
self-ID packet of a PDI1394P23 PHY may be adjusted to account for
a slow link chip.
For the PDI1394P23, the SYSCLK output may be used to measure
the frequency accuracy and stability of the internal oscillator and
PLL from which it is derived. The frequency of the SYSCLK output
must be within ±100 ppm of the nominal frequency of 49.152 MHz.
In the case of a node consisting of a higher-speed PHY and a
lower-speed LLC, the speed capability of the node (lesser of the
PHY and LLC speed) is that of the lower-speed LLC. A
sophisticated bus manager can determine the LLC speed capability
by reading the configuration ROM Bus_Info_Block, or by sending
asynchronous request packets at different speeds to the node and
checking for an acknowledge; the speed-map may then be adjusted
accordingly. The speed-map should reflect that communication to
such a node must be done at the lower speed of the LLC, instead of
the higher speed of the PHY. However, speed-map entries for paths
that merely pass through the node’s PHY, but do not terminate at
that node, should not be restricted by the lower speed of the LLC.
The following are some typical specifications for crystals used with
the PDI1394P23 in order to achieve the required frequency
accuracy and stability:
• Crystal mode of operation: Fundamental
• Frequency tolerance at 25 °C: Total frequency variation for the
complete circuit is +100 ppm. A crystal with +30 ppm frequency
tolerance is recommended for adequate margin.
• Frequency stability (over temperature and age): A crystal with +30
ppm frequency stability is recommended for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm
from nominal with some allowance for error introduced by board and
device variations. Trade–offs between frequency tolerance and
stability may be made as long as the total frequency variation is less
than ±100 ppm. For example, the frequency tolerance of the crystal
may be specified at 50 ppm and the temperature tolerance may be
specified at 30 ppm to give a total of 80 ppm possible variation due
to the crystal alone. Crystal aging also contributes to the frequency
variation.
To assist in building an accurate speed-map, the PDI1394P23 has
the capability of indicating a speed other than S400 in its transmitted
self-ID packet. This is controlled by the Link_Speed field in
register 8 of the Vendor-Dependent page (page 7). Setting the
Link_Speed field affects only the speed indicated in the self-ID
packet; it has no effect on the speed signaled to peer (adjacent
directly connected) PHYs during self-ID. The PDI1394P23 identifies
itself as S400 capable to its peers regardless of the value in the
Link_Speed field.
• Load capacitance: For parallel resonant mode crystal circuits, the
Generally, the Link_Speed field in register 8 of the
Vendor-Dependent page should not be changed from its power-on
default value of S400 unless it is determined that the speed-map (if
one exists) is incorrect for path entries terminating in the local node
(i.e. the node has a slower link layer chip). If the speed-map is
incorrect, it can be assumed that the bus manager has used only
the self-ID packet information to build the speed-map. In this case,
the node may update the Link_Speed field in register 8 to reflect the
lower speed capability of the LLC and then initiate another bus-reset
to cause the speed-map to be rebuilt. Note that in this scenario any
speed-map entries for node-to-node communication paths that pass
through the local node’s PHY will be restricted by the lower speed.
frequency of oscillation is dependent upon the load capacitance
specified for the crystal. Total load capacitance (CL) is a function
of not only the discrete load capacitors, but also board layout and
circuit. It may be necessary to iteratively select discrete load
capacitors until the SYSCLK output is within specification. It is
recommended that load capacitors with a maximum of "5%
tolerance be used.
As an example, for a board which uses a crystal specified for 12 pF
loading, load capacitors (C9 and C10 in Figure 11) of 16 pF each
are appropriate for the layout of that particular board. The load
specified for the crystal includes the load capacitors (C9, C10), the
loading of the PHY terminals (CPHY), and the loading of the board
itself (CBD). The value of CPHY is typically about 1 pF, and CBD is
typically 0.8 pF per centimeter of board etch; a typical board can
have 3 pF to 6 pF or more. The load capacitors C9 and C10
combine as capacitors in series so that the total load capacitance is:
In the case of a leaf node (which has only one active port) the
Link_Speed field in register 8 may be set to indicate the speed of the
LLC without first checking the speed-map. Changing the
Link_Speed field in a leaf node can only affect those paths that
terminate at that node, since no other paths can pass through a leaf
node. It can have no effect on other paths in the speed-map. For
hardware configurations which can only be a leaf node (all ports but
one are unimplemented), it is recommended that the Link_Speed
field be updated immediately after power-on or hardware reset.
CL = [(C9 * C10) / (C9+C10)] + CPHY + CBD.
C9
XI
17.5 Crystal selection
24.576 MHz
ls
The PDI1394P23 is designed to use an external 24.576 MHz crystal
connected between the XI and XO terminals to provide the
reference for an internal oscillator circuit. This oscillator in turn
drives a PLL circuit that generates the various clocks required for
transmission and resynchronization of data at the S100 through
S400 media data rates.
X1
CPHY + CBD
XO
C10
SV01808
A variation of less than ±100 ppm from nominal for the media data
rates is required by IEEE Std 1394. Adjacent PHYs may therefore
2001 Sep 06
PDI1394P23
Figure 11. Load Capacitance for the PDI1394P23 PHY
24
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
It is strongly recommended that part of the verification process for
the design be to measure the frequency of the SYSCLK output of
the PHY. This should be done with a frequency counter with an
accuracy of 6 digits or better. If the SYSCLK frequency is more than
the crystal’s tolerance from 49.152 MHz, the load capacitance of the
crystal may be varied to improve frequency accuracy. If the
frequency is too high add more load capacitance; if the frequency is
too low decrease load capacitance. Typically, changes should be
done to both load capacitors (C9 and C10 above) at the same time,
and both should be of the same value. Additional design details and
requirements may be provided by the crystal vendor.
NOTE: The layout of the crystal portion of the PHY circuit is
important for obtaining the correct frequency, minimizing noise
introduced into the PHY’s Phase Lock Loop, and minimizing any
emissions from the circuit. The crystal and two load capacitors
should be considered as a unit during layout. The crystal and load
capacitors should be placed as close as possible to one another
while minimizing the loop area created by the combination of the
three components. Varying the size of the capacitors may help in
this. Minimizing the loop area minimizes the effect of the resonant
current (Is) that flows in this resonant circuit. This layout unit (crystal
and load capacitors) should then be placed as close as possible to
the PHY XI and XO terminals to minimize trace lengths.
C9
C10
X1
SV01809
Figure 12. Recommended Crystal and Capacitor Layout
2001 Sep 06
PDI1394P23
25
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
18.0 PRINCIPLES OF OPERATION
D0–D3 terminals are used; and in S400 operation all D0–D7
terminals are used for data transfer. When the PDI1394P23 is in
control of the D0–D7 bus, unused Dn terminals are driven low during
S100 and S200 operations. When the LLC is in control of the D0–D7
bus, unused Dn terminals are ignored by the PDI1394P23.
The PDI1394P23 is designed to operate with an LLC such as the
Philips Semiconductors PDI1394L21, PDI1394L40, or PDI1394L41.
The following paragraphs describe the operation of the PHY-LLC
interface.
The interface to the LLC consists of the SYSCLK, CTL0–CTL1,
D0–D7, LREQ, LPS, C/LKON, and ISO terminals on the
PDI1394P23 as shown in Figure 13.
The LREQ terminal is controlled by the LLC to send serial service
requests to the PHY in order to request access to the serial bus for
packet transmission, read or write PHY registers, or control
arbitration acceleration.
The LPS and C/LKON terminals are used for power management of
the PHY and LLC. The LPS terminal indicates the power status of
the LLC, and may be used to reset the PHY-LLC interface or to
disable SYSCLK. The C/LKON terminal is used to send a wake-up
notification to the LLC and to indicate an interrupt to the LLC when
either LPS is inactive or the PHY register L bit is zero.
PDI1394P23
SYSCLK
CTL0–CTL1
LINK LAYER
CONTROLLER
The ISO terminal is used to enable the output differentiation logic on
the CTL0–CTL1 and D0–D7 terminals. Output differentiation is
required when an isolation barrier of the type described in Annex J
of IEEE Std 1394-1995 is implemented between the PHY and LLC.
D0–D7
LREQ
LPS
The PDI1394P23 normally controls the CTL0–CTL1 and D0–D7
bidirectional buses. The LLC is allowed to drive these buses only
after the LLC has been granted permission to do so by the PHY.
C/LKON
/ISO
/ISO
/ISO
There are four operations that may occur on the PHY-LLC interface:
link service request, status transfer, data transmit, and data receive.
The LLC issues a service request to read or write a PHY register, to
request the PHY to gain control of the serial bus in order to transmit
a packet, or to control arbitration acceleration.
SV01822
Figure 13. PHY-LLC interface
The SYSCLK terminal provides a 49.152 MHz interface clock to
which all control and data signals are synchronized. These signals
are sampled on the rising edge of SYSCLK.
The PHY may initiate a status transfer either autonomously or in
response to a register read request from the LLC.
The PHY initiates a receive operation whenever a packet is received
from the serial bus.
The CTL0 and CTL1 terminals form a bidirectional control bus,
which controls the flow of information and data between the
PDI1394P23 and LLC.
The PHY initiates a transmit operation after winning control of the
serial-bus following a bus request by the LLC. The transmit
operation is initiated when the PHY grants control of the interface to
the LLC.
The D0–D7 terminals form a bidirectional data bus, which is used to
transfer status information, control information, or packet data
between the devices. The PDI1394P23 supports S100, S200, and
S400 data transfers over the D0–D7 data bus. In S100 operation
only the D0 and D1 terminals are used; in S200 operation only the
The encoding of the CTL0–CTL1 bus is shown in Table 9 and
Table 10.
Table 9. CTL encoding when PHY has control of the bus
CTL0
CTL1
0
0
Idle
NAME
No activity (this is the default mode)
DESCRIPTION
0
1
Status
Status information is being sent from the PHY to the LLC
1
0
Receive
An incoming packet is being sent from the PHY to the LLC
1
1
Grant
The LLC has been given control of the bus to send an outgoing packet
Table 10. CTL encoding when LLC has control of the bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
The LLC releases the bus (transmission has been completed)
0
1
Hold
The LLC is holding the bus while data is being prepared for transmission, or indicating
that another packet is to be transmitted (concatenated) without arbitrating
1
0
Transmit
An outgoing packet is being sent from the LLC to the PHY
1
1
Reserved
None
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
LR0
LR1
LR2
PDI1394P23
LR3
LR(n–2)
LR(n–1)
SV01758
Figure 14. LREQ Request Stream
For a bus request the length of the LREQ bit stream is 7 or 8 bits, as
shown in Table 13.
18.1 LLC service request
To request access to the bus, to read or write a PHY register, or to
control arbitration acceleration, the LLC sends a serial bit stream on
the LREQ terminal as shown in Figure 14.
Table 13. Bus Request
The length of the stream will vary depending on the type of request
as shown in Table 11.
BIT(S)
0
Table 11. Request Stream Bit Length
REQUEST TYPE
7 or 8
Read register request
9
Write register request
17
Acceleration control request
6
1–3
Request Type
Indicates the type of bus request. See
Table 12.
4–6
Request Speed
Indicates the speed at which the PHY
will send the data for this request. See
Table 14 for the encoding of this field.
Stop Bit
Indicates the end of the transfer
(always 0). If bit 6 is 0, this bit may be
omitted.
7
Regardless of the type of request, a start bit of 1 is required at the
beginning of the stream, and a stop bit of 0 is required at the end of
the stream. The second through fourth bits of the request stream
indicate the type of the request. In the descriptions below, bit 0 is the
most significant, and is transmitted first in the request bit stream.
The LREQ terminal is normally low.
The 3-bit request speed field used in bus requests is shown in
Table 14.
Table 14. Bus Request Speed Encoding
Encoding for the request type is shown in Table 12.
Table 12. Request Type Encoding
NAME
DESCRIPTION
000
ImmReq
Immediate bus request. Upon
detection of idle, the PHY takes
control of the bus immediately
without arbitration
001
IsoReq
Isochronous bus request. Upon
detection of idle, the PHY arbitrates
for the bus without waiting for a
subaction gap.
010
PriReq
Priority bus request. The PHY
arbitrates for the bus after a
subaction gap, ignores the fair
protocol.
011
FairReq
Fair bus request. The PHY
arbitrates for the bus after a
subaction gap, follows the fair
protocol
100
RdReg
The PHY returns the specified
register contents through a status
transfer.
101
WrReg
Write to the specified register.
110
AccelCtl
Enable or disable asynchronous
arbitration acceleration.
111
Reserved
Reserved.
2001 Sep 06
DESCRIPTION
Indicates the beginning of the transfer
(always 1).
NUMBER OF BITS
Bus request
LR1–LR3
NAME
Start Bit
LR4–LR6
DATA RATE
000
S100
010
S200
100
S400
All others
Invalid
NOTE:
The PDI1394P23 will accept a bus request with an invalid speed
code and process the bus request normally. However, during packet
transmission for such a request, the PDI1394P23 will ignore any
data presented by the LLC and will transmit a null packet.
For a read register request, the length of the LREQ bit stream is
9 bits as shown in Table 15.
Table 15. Read Register Request
BIT(S)
0
27
NAME
DESCRIPTION
Start Bit
Indicates the beginning of the transfer
(always 1).
1–3
Request Type
A 100 indicating this is a read register
request.
4–7
Address
Identifies the address of the PHY register
to be read.
8
Stop Bit
Indicates the end of the transfer
(always 0).
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
the bus request was “lost” (bus arbitration lost and another packet
received), or “won” (bus arbitration won and the LLC granted
control). The PHY ignores new bus requests while a previous bus
request is pending. All bus requests are cleared upon a bus reset.
For a write register request, the length of the LREQ bit stream is
17 bits as shown in Table 16.
Table 16. Write Register Request
BIT(S)
0
NAME
Indicates the beginning of the transfer
(always 1).
1–3
Request Type
A 101 indicating that this is a write
register request.
4–7
Address
Identifies the address of the PHY
register to be written to.
8–15
Data
Gives the data that is to be written to the
specified register address.
Stop Bit
Indicates the end of the transfer
(always 0).
16
For write register requests, the PHY loads the specified data into the
addressed register as soon as the request transfer is complete. For
read register requests, the PHY returns the contents of the
addressed register to the LLC at the next opportunity through a
status transfer. If a received packet interrupts the status transfer,
then the PHY continues to attempt the transfer of the requested
register until it is successful. A write or read register request may be
made at any time, including while a bus request is pending. Once a
read register request is made, the PHY ignores further read register
requests until the register contents are successfully transferred to
the LLC. A bus reset does not clear a pending read register request.
DESCRIPTION
Start Bit
The PDI1394P23 includes several arbitration acceleration
enhancements which allow the PHY to improve bus performance
and throughput by reducing the number and length of inter-packet
gaps. These enhancements include autonomous (fly-by)
isochronous packet concatenation, autonomous fair and priority
packet concatenation onto acknowledge packets, and accelerated
fair and priority request arbitration following acknowledge packets.
Then enhancements are enabled when the EAA bit in PHY
register 5 is set.
For an acceleration control request, the length of the LREQ data
stream is 6 bits as shown in Table 17.
Table 17. Acceleration Control Request
BIT(S)
0
1–3
NAME
Start Bit
DESCRIPTION
Indicates the beginning of the transfer
(always 1).
Request Type
A 110 indicating this is an acceleration
control request.
4
Control
Asynchronous period arbitration
acceleration is enabled if 1, and
disabled if 0.
5
Stop Bit
Indicates the end of the transfer
(always 0).
The arbitration acceleration enhancements may interfere with the
ability of the cycle master node to transmit the cycle start packet
under certain circumstances. The acceleration control request is
therefore provided to allow the LLC to temporarily enable or disable
the arbitration acceleration enhancements of the PDI1394P23
during the asynchronous period. The LLC typically disables the
enhancements when its internal cycle counter rolls over indicating
that a cycle start packet is imminent, and then re-enables the
enhancements when it receives a cycle start packet. The
acceleration control request may be made at any time, however, and
is immediately serviced by the PHY. Additionally, a bus reset or
isochronous bus request will cause the enhancements to be
re-enabled, if the EAA bit is set.
For fair or priority access, the LLC sends the bus request (FairReq or
PriReq) at least one clock after the PHY-LLC interface becomes idle. If
the CTL terminals are asserted to the receive state (10b) by the PHY,
then any pending fair or priority request is lost (cleared). Additionally,
the PHY ignores any fair or priority requests if the Receive state is
asserted while the LLC is sending the request. The LLC may then
reissue the request one clock after the next interface idle.
18.2 Status transfer
A status transfer is initiated by the PHY when there is status
information to be transferred to the LLC. The PHY waits until the
interface is idle before starting the transfer. The transfer is initiated
by the PHY asserting Status (01b) on the CTL terminals, along with
the first two bits of status information on the D[0:1] terminals. The
PHY maintains CTL = Status for the duration of the status transfer.
The PHY may prematurely end a status transfer by asserting
something other than Status on the CTL terminals. This occurs if a
packet is received before the status transfer completes. The PHY
continues to attempt to complete the transfer until all status
information has been successfully transmitted. There is at least one
idle cycle between consecutive status transfers.
The cycle master node uses priority bus request (PriReq) to send a
cycle start packet. After receiving or transmitting a cycle start
packet, the LLC can issue an isochronous bus request (IsoReq).
The PHY will clear an isochronous request only when the bus has
been won.
To send an acknowledge packet, the link must issue an immediate
bus request (ImmReq) during the reception of the packet addressed
to it. This is required in order to minimize the idle gap between the
end of the received packet and the start of the transmitted
acknowledge packet. As soon as the receive packet ends, the PHY
immediately grants control of the bus to the LLC. The LLC sends an
acknowledgment to the sender unless the header CRC of the
received packet is corrupted. In this case, the LLC does not transmit
an acknowledge, but instead cancels the transmit operation and
releases the interface immediately; the LLC must not use this grant
to send another type of packet. After the interface is released, the
LLC may proceed with another request.
The PHY normally sends just the first four bits of status to the LLC.
These bits are status flags that are needed by the LLC state
machines. The PHY sends an entire 16-bit status packet to the LLC
after a read register request, or when the PHY has pertinent
information to send to the LLC or transaction layers. The only
defined condition where the PHY automatically sends a register to
the LLC is after self-ID, where the PHY sends the physical-ID
register that contains the new node address. All status transfers are
either 4 or 16 bits unless interrupted by a received packet. The
status flags are considered to have been successfully transmitted to
the LLC immediately upon being sent, even if a received packet
The LLC may request only one bus request at a time. Once the LLC
issues any request for bus access (ImmReq, IsoReq, FairReq, or
PriReq), it cannot issue another request until the PHY indicates that
2001 Sep 06
PDI1394P23
28
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
D0 and D1 lines (only 2 bits of status are transferred per cycle).
Normally (unless interrupted by a receive operation), a status
transfer will be either 2 or 8 cycles long. A 2-cycle (4 bit) transfer
occurs when only status information is to be sent. An 8-cycle
(16 bit) transfer occurs when register data is to be sent in addition
to any status information.
subsequently interrupts the status transfer. Register contents are
considered to have been successfully transmitted only when all
8 bits of the register have been sent. A status transfer is retried after
being interrupted only if any status flags remain to be sent, or if a
register transfer has not yet completed.
The definition of the bits in the status transfer is shown in Table 18,
and the timing is shown in Figure 15.
• Status transfer terminated. The PHY normally terminates a status
transfer by asserting idle on the CTL lines. If a bus reset is
pending, the PHY may also assert Grant on the CTL line
immediately following a complete status transfer.
The sequence of events for a status transfer is as follows:
• Status transfer initiated. the PHY indicates a status transfer by
asserting status on the CTL lines along with the status data on the
Table 18. Status Bits
BIT(S)
NAME
DESCRIPTION
0
Arbitration Reset Gap
Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as
defined in the IEEE 1394–1995 standard). This bit is used by the LLC in the busy/retry state machine.
1
Subaction gap
Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the
IEEE 1394–1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.
2
Bus reset
Indicates that the PHY has entered the bus reset state.
3
Interrupt
Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a
cable-power voltage falling too low, a state time-out, or a port status change.
4–7
Address
This field holds the address of the PHY register whose contents are being transferred to the LLC.
8–15
Data
This field holds the register contents.
SYSCLK
(a)
(b)
00
CTL0, CTL1
D0, D1
00
01
00
S[0:1]
01
S[14:15]
00
SV01759
Figure 15. Status Transfer Timing
18.3 Receive
Whenever the PHY detects the data-prefix state on the serial bus, it
initiates a receive operation by asserting Receive on the CTL terminals
and a logic 1 on each of the D terminals (“data-on” indication). The
PHY indicates the start of a packet by placing the speed code
(encoded as shown in Table 19) on the D terminals, followed by
packet data. The PHY holds the CTL terminals in the Receive state
until the last symbol of the packet has been transferred. The PHY
indicates the end of packet data by asserting Idle on the CTL
terminals. All received packets are transferred to the LLC. Note that
the speed code is part of the PHY-LLC protocol and is not included in
the calculation of CRC or any other data protection mechanisms.
2001 Sep 06
Table 19. Speed Code for the Receiver
D0–D7
DATA RATE
0000 0000
S100
0100 0000
S200
0101 0000
S400
1111 1111
“data-on” indication
It is possible for the PHY to receive a null packet, which consists of
the data-prefix state on the serial bus followed by the data-end state,
29
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
progress so that the CTL lines may change from status to receive
without an intervening idle.
without any packet data. A null packet is transmitted whenever the
packet speed exceeds the capability of the receiving PHY, or
whenever the LLC immediately releases the bus without transmitting
any data. In this case, the PHY will assert Receive on the CTL
terminals with the “data-on” indication (all 1’s) on the D terminals,
followed by Idle on the CTL terminals, without any speed code or
data being transferred. In all cases, in normal operation, the
PDI1394P23 sends at least one “data-on” indication before sending
the speed code or terminating the receive operation.
• Data-on indication. The PHY may assert the data-on indication code
on the D lines for one or more cycles preceding the speed code.
• Speed code. the PHY indicates the speed of the received packet
by asserting a speed code on the D lines for one cycle
immediately preceding packet data. The link decodes the speed
code on the first Receive cycle for which the D lines are not the
data-on code. If the speed code is invalid, or indicates a speed
higher than that which the link is capable of handling, the link
should ignore the subsequent data.
The PDI1394P23 also transfers its own self-ID packet, transmitted
during the self-ID phase of bus initialization to the LLC. This packet
is transferred to the LLC just as any other received self-ID packet.
• Receive data. Following the data-on indication (if any) and the
The sequence of events for a normal packet reception is as follows:
• Receive operation initiated. The PHY indicates a receive
speed code, the PHY asserts packet data on the D lines with
receive on the CTL lines for the remainder of the receive operation.
operation by asserting Receive on the CTL lines. Normally, the
interface is idle when receive is asserted. However, the receive
operation may interrupt a status transfer operation that is in
• Receive operation terminated. The PHY terminates the receive
operation by asserting the idle on the CTL lines. The PHY asserts
at least one cycle of idle following a receive operation.
SYSCLK
(a)
00
CTL0, CTL1
10
01
00
(b)
D0–D7
XX
(e)
FF (“data-on”)
(c)
(d)
SPD
d0
dn
00
SV01760
NOTE: SPD = Speed code; see Table 19; d0–dn = Packet data.
Figure 16. Normal Packet Reception Timing
• Data-on indication. The PHY asserts the data-on indication code
The sequence of events for a null packet reception is as follows:
• Receive operation initiated. The PHY indicates a receive
on the D lines for one or more cycles.
• Receive operation terminated. The PHY terminates the receive
operation by asserting receive on the CTL lines. Normally, the
interface is idle when receive is asserted. However, the receive
operation may interrupt a status transfer operation that is in
progress so that the CTL lines may change from status to receive
without an intervening idle.
operation by asserting Idle on the CTL lines. The PHY shall
assert at least one cycle of Idle following a receive operation.
SYSCLK
(a)
00
CTL0, CTL1
01
D0–D7
XX
10
00
(b)
(c)
FF (“data-on”)
00
SV01761
Figure 17. Null Packet Reception Timing
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
18.4 Transmit
CTL terminals change direction between the PHY and the LLC,
there is an extra clock period allowed so that both sides of the
interface can operate on registered versions of the interface signals.
When the LLC issues a bus request through the LREQ terminal, the
PHY arbitrates to gain control of the bus. If the PHY wins arbitration
for the serial bus, the PHY-LLC interface bus is granted to the link by
asserting the Grant state (11b) on the CTL terminals for one
SYSCLK cycle, followed by Idle for one clock cycle. The LLC then
takes control of the bus by asserting either Idle (00b), Hold (01b), or
Transmit (10b) on the CTL terminals. Unless the LLC is immediately
releasing the interface, the link may assert the Idle state for at most
one clock before it must assert either Hold or Transmit on the CTL
terminals. The Hold state is used by the LLC to retain control of the
bus while it prepares data for transmission. The LLC may assert
Hold for zero or more clock cycles (i.e., the LLC need not assert
Hold before Transmit). The PHY asserts data-prefix on the serial
bus during this time.
The sequence of events for a normal packet transmission is as
follows:
• Transmit operation initiated. The PHY asserts grant on the CTL
lines followed by Idle to hand over control of the interface to the
link so that the link may transmit a packet. The PHY releases
control of the interface (i.e., it 3-States the CTL and D outputs)
following the idle cycle.
• Optional idle cycle. The link may assert at most one idle cycle
preceding assertion of either hold or transmit. This idle cycle is
optional; the link is not required to assert Idle preceding either
hold or transmit.
When the LLC is ready to send data, the LLC asserts Transmit on
the CTL terminals as well as sending the first bits of packet data on
the D lines. The Transmit state is held on the CTL terminals until the
last bits of data have been sent. The LLC then asserts either Hold or
Idle on the CTL terminals for one clock cycle and then asserts Idle
for one additional cycle before releasing the interface bus and
putting the CTL and D terminals in a high-impedance state. The
PHY then regains control of the interface bus.
• Optional hold cycles. The link may assert hold for up to 47 cycles
preceding assertion of transmit. These hold cycle(s) are optional;
the link is not required to assert hold preceding transmit.
• Transmit data. When data is ready to be transmitted, the link
asserts transmit on the CTL lines along with the data on the D
lines.
• Transmit operation terminated. The transmit operation is
The Hold state asserted at the end of packet transmission indicates
to the PHY that the LLC requests to send another packet
(concatenated packet) without releasing the serial bus. The PHY
responds to this concatenation request by waiting the required
minimum packet separation time and then asserting Grant as
before. This function may be used to send a unified response after
sending an acknowledge, or to send consecutive isochronous
packets during a single isochronous period. Unless multi-speed
concatenation is enabled, all packets transmitted during a single bus
ownership must be of the same speed (since the speed of the
packet is set before the first packet). If multi-speed concatenation is
enabled (when the EMSC bit of PHY register 5 is set), the LLC must
specify the speed code of the next concatenated packet on the D
terminals when it asserts Hold on the CTL terminals at the end of a
packet. The encoding for this speed code is the same as the speed
code that precedes received packet data as given in Table 19.
terminated by the link asserting hold or idle on the CTL lines the
link asserts hold to indicate that the PHY is to retain control of the
serial bus in order to transmit a concatenated packet. the link
asserts idle to indicate that packet transmission is complete and
the PHY may release the serial bus. The link then asserts Idle for
one more cycle following this cycle of hold or idle before releasing
the interface and returning control the the PHY.
• Concatenated packet speed-code. If multi-speed concatenation is
enabled in the PHY, the link shall assert a speed-code on the D
lines when it asserts Hold to terminate packet transmission. This
speed-code indicates the transmission speed for the
concatenated packet that is to follow. The encoding for this
concatenated packet speed-code is the same as the encoding for
the received packet speed-code (see Table 19). the link may not
concatenate an S100 packet onto any higher speed packet.
After sending the last packet for the current bus ownership, the LLC
releases the bus by asserting Idle on the CTL terminals for two clock
cycles. The PHY begins asserting Idle on the CTL terminals one
clock after sampling Idle from the link. Note that whenever the D and
• After regaining control of the interface, the PHY shall assert at
least one cycle of idle before any subsequent status transfer,
receive operation, or transmit operation.
SYSCLK
(a)
CTL0, CTL1
(b)
(c)
(d)
(e)
(g)
00
00
11
00
00
01
10
01
00
00
00
00
(f)
D0–D7
00
00
d0, d1, ...
00
dn
SPD
Link Controls Ctl and D
PHY High-impedance Ctl and D Outputs
SV01762
NOTE: SPD = Speed code; see Table 19; d0–dn = Packet data.
Figure 18. Normal Packet Transmission Timing
2001 Sep 06
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Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
• Null transmit termination. The null transmit operation is terminated
The sequence of events for a cancelled/null packet transmission is
as follows:
by the link asserting two cycles of idle on the CTL lines and then
releasing the interface and returning control to the PHY. Note that
the link may assert Idle for a total of 3 consecutive cycles if it
asserts the optional first idle cycle but does not assert hold. It is
recommended that the link assert 3 cycles of Idle to cancel a
packet transmission if no hold cycles are asserted. This ensures
that either the link or PHY controls the interface in all cycles.
• Transmit operation initiated. PHY asserts grant on the CTL lines
followed by idle to hand over control of the interface to the link.
• Optional Idle cycle. The link may assert at most one idle cycle
preceding assertion of hold. This idle cycle is optional; the link is
not required to assert idle preceding Hold.
• Optional Hold cycles. The link may assert Hold for up to 47 cycles
• After regaining control of the interface, the PHY shall assert at
preceding assertion of idle. These hold cycle(s) are optional; the
link is not required to assert hold preceding Idle.
least one cycle of Idle before any subsequent status transfer,
receive operation, or transmit operation.
SYSCLK
(a)
CTL0, CTL1
D0–D7
00
11
(b)
00
(c)
00
(d)
01
00
(e)
00
00
00
00
Link Controls Ctl and D
PHY High-impedance Ctl and D Outputs
SV01763
Figure 19. Cancelled/Null Packet Transmission
The LPS signal may be either a level signal or a pulsed signal,
depending upon whether the PHY–LLC interface is a direct
connection or is made across an isolation barrier. When an isolation
barrier exists between the PHY and LLC (whether of the Philips
bus-holder type or Annex J type) the LPS signal must be pulsed. In
a direct connection, the LPS signal may be either a pulsed or a level
signal. Timing parameters for the LPS signal are given in Table 20.
18.5 Interface reset and disable
The LLC controls the state of the PHY-LLC interface using the LPS
signal. The interface may be placed into a reset state, a disabled
state, or be made to initialize and then return to normal operation.
When the interface is not operational (whether reset, disabled, or in
the process of initialization) the PHY cancels any outstanding bus
request or register read request, and ignores any requests made via
the LREQ line. Additionally, any status information generated by the
PHY will not be queued and will not cause a status transfer upon
restoration of the interface to normal operation.
2001 Sep 06
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Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
Table 20. LPS Timing Parameters
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
TLPSL
LPS low time (when pulsed) (see Note 1)
0.09
2.60
µS
TLPSH
LPS high time (when pulsed) (see Note 1)
0.021
2.60
µS
LPS duty cycle (when pulsed) (see Note 2)
20
55
%
TLPS_RESET
Time for PHY to recognize LPS deasserted and reset the interface
2.60
2.68
µS
TLPS_DISABLE
Time for PHY to recognize LPS deasserted and disable the interface
26.03
26.11
µS
TRESTORE
Time to permit optional isolation circuits to restore during an interface reset
15
233
µS
TCLK_ACTIVATE
Time for SYSCLK to be activated from reassertion of LPS
60
nS
—
NOTES:
1. The specified TLPSL and TLPSH times are worst–case values appropriate for operation with the PDI1394P23. These values are broader than
those specified for the same parameters in the P1394a Supplement (i.e., an implementation of LPS that meets the requirements of P1394a
will operate correctly with the PDI1394P23).
2. A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when using an
isolation barrier on the LPS signal (e.g., as shown in Figure 8)
3. The maximum value for TRESTORE does not apply when the PHY–LLC interface is disabled, in which case an indefinite time may elapse
before LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is
deasserted for less than TLPS_DISABLE.
its CTL and D outputs in the logic 0 state and ignores any activity on
the LREQ signal. The timing for interface reset is shown in Figure 20
and Figure 21.
The LLC requests that the interface be reset by deasserting the LPS
signal and terminating all bus and request activity. When the PHY
observes that LPS has been deasserted for TLPS_RESET, it resets
the interface. When the interface is in the reset state, the PHY sets
(low)
ISO
(c)
(a)
SYSCLK
CTL0, CTL1
D0 – D7
(b)
LREQ
(d)
LPS
TLPS_RESET
TLPSL
TLPSH
SV01810
Figure 20. Interface Reset, ISO Low
2001 Sep 06
TRESTORE
33
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
3. Interface reset. After TLPS_RESET time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and places
its CTL and D outputs into a high-impedance state (the PHY will
terminate any output signal activity such that signals end in a
logic 0 state). The PHY-LLC interface is now in the reset state.
The sequence of events for resetting the PHY-LLC interface when it
is in the differentiated mode of operation (ISO terminal is low) is as
follows:
1. Normal operation. Interface is operating normally, with LPS
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line.
4. Interface restored. After the minimum TRESTORE time, the LLC
may again assert LPS active. (The minimum TRESTORE interval
provides sufficient time for the biasing networks used in Annex J
type isolation barrier circuits to stabilize and reach a quiescent
state if the isolation barrier has somehow become unbalanced.)
When LPS is asserted, the interface will be initialized as
described on the next page.
2. LPS deasserted. The LLC deasserts the LPS signal and, within
1.0 ms, terminates any request or interface bus activity, and
places its LREQ, CTL, and D outputs into a high-impedance
state (the LLC should terminate any output signal activity such
that signals end in a logic 0 state).
ISO
PDI1394P23
(high)
(c)
(a)
SYSCLK
CTL0, CTL1
D0 – D7
(b)
LREQ
(d)
LPS
TLPS_RESET
TRESTORE
SV01811
Figure 21. Interface Reset, ISO High
2001 Sep 06
34
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
4. Interface restored. After the minimum TRESTORE time, the LLC
may again assert LPS active. (The minimum TRESTORE interval
provides sufficient time for the biasing networks used in Annex J
type isolation barrier circuits to stabilize and reach a quiescent
state if the isolation barrier has somehow become unbalanced.)
When LPS is asserted, the interface will be initialized as
described below.
The sequence of events for resetting the PHY-LLC interface when it
is in the nondifferentiated mode of operation (ISO terminal is high) is
as follows:
1. Normal operation. Interface is operating normally, with LPS
asserted, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line. In the above diagram, the LPS signal is shown
as a non-pulsed level signal. However, it is permissible to use a
pulsed signal for LPS in a direct connection between the PHY
and LLC; a pulsed signal is required when using an isolation
barrier (whether of the Philips Bus Holder type or Annex J type).
If the LLC continues to keep the LPS signal deasserted, it requests
that the interface be disabled. The PHY disables the interface when
it observes that LPS has been deasserted for TLPS_DISABLE. When
the interface is disabled, the PHY sets its CTL and D outputs as
stated above for interface reset, but also stops SYSCLK activity. The
interface is also placed into the disabled condition upon a hardware
reset of the PHY. The timing for interface disable is shown in
Figure 22 and Figure 23.
2. LPS deasserted. The LLC deasserts the LPS signal and, within
1.0 ms, terminates any request or interface bus activity, places
its CTL and D outputs into a high-impedance state, and drives
its LREQ output low.
3. Interface reset. After TLPS_RESET time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and drives
its CTL and D outputs low. The PHY-LLC interface is now in the
reset state.
When the interface is disabled, the PHY will enter a low-power state
if none of its ports is active.
(low)
ISO
(a)
(c)
(d)
SYSCLK
CTL0, CTL1
D0 – D7
(b)
LREQ
LPS
TLPS_RESET
TLPS_DISABLE
TLPSL
TLPSH
SV01812
Figure 22. Interface Disable, ISO Low
2001 Sep 06
35
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
3. Interface reset. After TLPS_RESET time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and places
its CTL and D outputs into a high-impedance state (the PHY will
terminate any output signal activity such that signals end in a
logic 0 state). The PHY-LLC interface is now in the reset state.
The sequence of events for disabling the PHY-LLC interface when it
is in the differentiated mode of operation (ISO terminal is low) is as
follows:
1. Normal operation. Interface is operating normally, with LPS
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line.
4. Interface disabled. If the LPS signal remain inactive for
TLPS_DISABLE time, the PHY terminates SYSCLK activity by
placing the SYSCLK output into a high-impedance state. The
PHY-LLC interface is now in the disabled state.
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1
ms, terminates any request or interface bus activity, and places
its LREQ, CTL, and D outputs into a high-impedance state (the
LLC should terminate any output signal activity such that signals
end in a logic 0 state).
ISO
PDI1394P23
(high)
(c)
(a)
(d)
SYSCLK
CTL0, CTL1
D0 – D7
(b)
LREQ
LPS
TLPS_RESET
TLPS_DISABLE
Figure 23. Interface Disable, ISO High
2001 Sep 06
36
SV01813
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
its CTL and D outputs low. The PHY-LLC interface is now in the
reset state.
The sequence of events for disabling the PHY-LLC interface when it
is in the non-differentiated mode of operation (ISO terminal is high)
is as follows:
1. Normal operation. Interface is operating normally, with LPS
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line.
4. Interface disabled. If the LPS signal remain inactive for
TLPS_DISABLE time, the PHY terminates SYSCLK activity by
driving the SYSCLK output low. The PHY-LLC interface is now in
the disabled state.
After the interface has been reset, or reset and then disabled, the
interface is initialized and restored to normal operation when LPS is
reasserted by the LLC. The timing for interface initialization is shown
in Figure 24 and Figure 25.
2. LPS deasserted. The LLC deasserts the LPS signal and, within
1.0 ms, terminates any request or interface bus activity, places
its CTL and D outputs into a high-impedance state, and drives
its LREQ output low.
3. Interface reset. After TLPS_RESET time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and drives
(low)
ISO
7 cycles
SYSCLK
5 ns. min
10 ns. max
(c)
CTL0
(b)
(d)
CTL1
D0 – D7
LREQ
(a)
LPS
TCLK_ACTIVATE
SV01814
Figure 24. Interface Initialization, ISO Low
2001 Sep 06
37
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
+100 ppm (period of 20.345 ns). Upon the first full cycle of
SYSCLK, the PHY drives the CTL and D terminals low for one
cycle. The LLC is also required to drive its CTL, D, and LREQ
outputs low during one of the first six cycles of SYSCLK (in the
above diagram, this is shown as occurring in the first SYSCLK
cycle).
The sequence of events for initialization of the PHY-LLC interface
when the interface is in the differentiated mode of operation (ISO
terminal is low) is as follows:
1. LPS reasserted. After the interface has been in the reset or
disabled state for at least the minimum TRESTORE time, the LLC
causes the interface to be initialized and restored to normal
operation by re-activating the LPS signal. (In the above diagram,
the interface is shown in the disabled state with SYSCLK
high-impedance inactive. However, the interface initialization
sequence described here is also executed if the interface is
merely reset but not yet disabled.)
3. Receive indicated. Upon the eighth SYSCLK cycle following
reassertion of LPS, the PHY asserts the Receive state on the
CTL lines and the data-on indication (all ones) on the D lines for
one or more cycles (because the interface is in the differentiated
mode of operation, the CTL and D lines will be in the
high-impedance state after the first cycle).
2. SYSCLK activated. If the interface is disabled, the PHY
re-activates its SYSCLK output when it detects that LPS has
been reasserted. SYSCLK will be restored within 60 ns. The
PHY commences SYSCLK activity by driving the SYSCLK
output low for half a cycle. Thereafter, the SYSCLK output is a
50% duty cycle square wave with a frequency of 49.152 MHz
ISO
(high)
PDI1394P23
4. Initialization complete. The PHY asserts the Idle state on the
CTL lines and logic 0 on the D lines. This indicates that the
PHY-LLC interface initialization is complete and normal
operation may commence. The PHY will now accept requests
from the LLC via the LREQ line.
7 cycles
SYSCLK
(b)
(c)
CTL0
CTL1
D0 – D7
LREQ
(a)
LPS
TCLK_ACTIVATE
SV01815
Figure 25. Interface Initialization, ISO High
During the first seven cycles of SYSCLK, the PHY continues to
drive the CTL and D terminals low. The LLC is also required to
drive its CTL and D outputs low for one of the first six cycles of
SYSCLK but to otherwise place its CTL and D outputs in a
high-impedance state. The LLC continues to drive its LREQ
output low during this time.
The sequence of events for initialization of the PHY-LLC interface
when the interface is in the non-differentiated mode of operation
(ISO terminal is high) is as follows:
1. LPS reasserted. After the interface has been in the reset or
disabled state for at least the minimum TRESTORE time, the LLC
causes the interface to be initialized and restored to normal
operation by reasserting the LPS signal. (In the above diagram,
the interface is shown in the disabled state with SYSCLK low
inactive. However, the interface initialization sequence described
here is also executed if the interface is merely reset but not yet
disabled.)
3. Receive indicated. Upon the eighth SYSCLK cycle following
reassertion of LPS, the PHY asserts the Receive state on the
CTL lines and the data-on indication (all ones) on the D lines for
one or more cycles.
4. Initialization complete. The PHY asserts the Idle state on the
CTL lines and logic 0 on the D lines. This indicates that the
PHY-LLC interface initialization is complete and normal
operation may commence. The PHY will now accept requests
from the LLC via the LREQ line.
2. SYSCLK activated. If the interface is disabled, the PHY
re-activates its SYSCLK output when it detects that LPS has
been reasserted. SYSCLK will be restored within 60 ns. The
SYSCLK output is a 50% duty cycle square wave with a
frequency of 49.152 MHz +100 ppm (period of 20.345 ns).
2001 Sep 06
38
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
19.0 POWER-CLASS PROGRAMMING
The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted
self-ID packet. Descriptions of the various power-classes are given in Table 21. The default power-class value is loaded following a hardware
reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4.
Table 21. Power Class Descriptions
PC0–PC2
DESCRIPTION
000
Node does not need power and does not repeat power.
001
Node is self powered, and provides a minimum of 15 W to the bus.
010
Node is self powered, and provides a minimum of 30 W to the bus.
011
Node is self powered, and provides a minimum of 45 W to the bus.
100
Node may be powered from the bus and is using up to 3 W.
101
Node is powered from the bus and uses up to 3 W. No additional power is needed to enable the link.
110
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
2001 Sep 06
39
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
2001 Sep 06
40
PDI1394P23
SOT314-2
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls;
body 8 x 8 x 1.05 mm
2001 Sep 06
41
PDI1394P23
SOT534-1
Philips Semiconductors
Preliminary data
2-port/1-port 400 Mbps physical layer interface
PDI1394P23
Data sheet status
Data sheet status [1]
Product
status [2]
Definitions
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Koninklijke Philips Electronics N.V. 2001
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 09-01
For sales offices addresses send e-mail to:
[email protected]
Document order number:
2001 Sep 06
42
9397 750 08748