INTEGRATED CIRCUITS DATA SHEET TDA8762 10-bit high-speed low-power analog-to-digital converter Product specification Supersedes data of 1995 Feb 15 File under Integrated Circuits, IC02 1996 Mar 28 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 FEATURES APPLICATIONS • 10-bit resolution High-speed analog-to-digital conversion for: • Sampling rate up to 40 MHz • Video data digitizing • DC sampling allowed • Radar pulse analysis • One clock cycle conversion only • Transient signal analysis • High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) • High energy physics research • Σ∆ modulators • Medical imaging. • No missing codes guaranteed • In range (IR) TTL output GENERAL DESCRIPTION • TTL compatible digital inputs and outputs The TDA8762 is a 10-bit high-speed analog-to-digital converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed. • Low-level AC clock input signal allowed • External reference voltage regulator • Power dissipation only 380 mW (typical) • Low analog input capacitance, no buffer amplifier required • No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.4 5.0 5.25 V ICCA analog supply current − 29 36 mA ICCD digital supply current − 24 30 mA ICCO output stages supply current − 23 30 mA INL integral non-linearity fclk = 40 MHz; ramp input − ±0.75 ±1.5 LSB DNL differential non-linearity fclk = 40 MHz; ramp input − ±0.3 ±0.7 LSB fclk(max) maximum clock frequency 40 − − MHz Ptot total power dissipation − 380 500 mW ORDERING INFORMATION TYPE NUMBER TDA8762M/4 1996 Mar 28 PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm 2 VERSION SAMPLING FREQUENCY (MHz) SOT341-1 40 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 BLOCK DIAGRAM handbook, full pagewidth V CCA CLK VCCD OE 3 1 11 10 2 CLOCK DRIVER VRT TC TDA8762 9 25 D9 24 D8 MSB 23 D7 22 D6 RLAD analog voltage input VI VRM 21 D5 8 ANALOG -TO - DIGITAL CONVERTER LATCHES TTL OUTPUTS data outputs 20 D4 19 D3 7 18 D2 17 D1 16 D0 13 VRB 6 LSB VCCO1 28 VCCO2 IN RANGE LATCH 4 AGND1 5 AGND2 analog grounds 12 14 OGND1 digital ground output grounds 3 26 27 DGND Fig.1 Block diagram. 1996 Mar 28 TTL OUTPUT OGND2 MGC035 IR output Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 PINNING SYMBOL PIN DESCRIPTION CLK 1 clock input TC 2 two’s complement input (active LOW) VCCA 3 analog supply voltage (+5 V) AGND1 4 analog ground 1 AGND2 5 analog ground 2 VRB 6 reference voltage BOTTOM input VRM 7 reference voltage MIDDLE VI 8 analog input voltage VRT 9 reference voltage TOP input OE 10 output enable input (TTL level input, active LOW) VCCD 11 digital supply voltage (+5 V) DGND 12 digital ground VCCO1 13 supply voltage for output stages 1 (+5 V) handbook, halfpage CLK 1 28 VCCO2 TC 2 27 OGND2 VCCA 3 26 IR AGND1 4 25 D9 AGND2 5 24 D8 VRB 6 23 D7 VRM 7 VI 8 21 D5 VRT 9 20 D4 OE 10 19 D3 VCCD 11 18 D2 DGND 12 17 D1 22 D6 TDA8762 OGND1 14 output ground 1 n.c. 15 not connected D0 16 data output; bit 0 (LSB) D1 17 data output; bit 1 D2 18 data output; bit 2 D3 19 data output; bit 3 V CCO1 13 16 D0 D4 20 data output; bit 4 OGND1 14 15 n.c. D5 21 data output; bit 5 D6 22 data output; bit 6 D7 23 data output; bit 7 D8 24 data output; bit 8 D9 25 data output; bit 9 (MSB) IR 26 in range data output OGND2 27 output ground 2 VCCO2 28 supply voltage for output stages 2 (+5 V) 1996 Mar 28 MGC036 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output stages supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage difference VCCA − VCCD −1.0 +1.0 V VCCA − VCCO −1.0 +1.0 V VCCD − VCCO −1.0 +1.0 V VI input voltage referenced to AGND −0.3 +7.0 V Vclk(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCD V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +70 °C Tj junction temperature − +150 °C Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Mar 28 PARAMETER thermal resistance from junction to ambient in free air 5 VALUE UNIT 110 K/W Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 CHARACTERISTICS VCCA = V3 to V4 and V5 = 4.75 to 5.25 V; VCCD = V11 to V12 = 4.75 to 5.25 V; VCCO = V13 and V28 to V14 and V27 = 4.4 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V; VI(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCCA analog supply voltage 4.75 VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.4 5.0 5.25 V ∆VCC voltage difference VCCA − VCCD −0.25 − +0.25 V VCCA − VCCO −0.4 − +0.4 V VCCD − VCCO −0.4 − +0.4 V − 29 36 mA − 24 30 mA − 23 30 mA 0 − 0.8 V ICCA analog supply current ICCD digital supply current ICCO output stages supply current CL = 15 pF; ramp input 5.0 5.25 V Inputs CLOCK INPUT CLK (REFERENCED TO DGND); note 1 VIL LOW level input voltage VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current Vclk = 0.4 V −1 0 +1 µA IIH HIGH level input current Vclk = 2.7 V − − 20 µA ZI input impedance fclk = 40 MHz − 2 − kΩ CI input capacitance fclk = 40 MHz − 2 − pF INPUTS OE AND TC (REFERENCED TO DGND); see Table 2 VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current VIL = 0.4 V −400 − − µA IIH HIGH level input current VIH = 2.7 V − − 20 µA VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) IIL LOW level input current VI = 1.3 V − 0 − µA IIH HIGH level input current VI = 3.8 V − 70 − µA ZI input impedance fi = 4.43 MHz − 5 − kΩ CI input capacitance fi = 4.43 MHz − 8 − pF 1996 Mar 28 6 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter SYMBOL PARAMETER TDA8762 CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder; see Table 1 VRB reference voltage BOTTOM 1.2 1.3 − VRT reference voltage TOP − 3.8 VCCA − 0.8 V V Vdiff differential reference voltage VRT − VRB 1.8 2.5 3.0 V V Iref reference current − 28 − mA RLAD resistor ladder − 90 − Ω TCRLAD temperature coefficient of the resistor ladder − 1860 − ppm − 167 − mΩ/K VosB offset voltage BOTTOM note 2 − 220 − mV VosT offset voltage TOP note 2 − 220 − mV VI(p-p) analog input voltage (peak-to-peak value) note 3 1.5 2.06 2.5 V Outputs DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND) VOL LOW level output voltage IO = 1 mA 0 − 0.4 V VOH HIGH level output voltage IO = 0 mA 2.7 − VCCO − 0.5 V IO = −0.4 mA 2.7 − VCCO − 1.3 V IO = −1 mA 2.4 − VCCO − 1.4 V 0.4 V < VO < VCCO −20 − +20 µA IOZ output current in 3-state mode Switching characteristics CLOCK INPUT CLK; see Fig.4; note 1 fclk(max) maximum clock frequency 40 − − MHz tCPH clock pulse width HIGH 8 − − ns tCPL clock pulse width LOW 8 − − ns Analog signal processing LINEARITY INL integral non-linearity fclk = 40 MHz; ramp input − ±0.75 ±1.5 LSB DNL differential non-linearity fclk = 40 MHz; ramp input − ±0.3 ±0.7 LSB OFER offset error − middle code; VRB = 1.3 V; VRT = 3.8 V ±1 − LSB GER gain error (from device to device) VRB = 1.3 V; VRT = 3.8 V; note 4 ±0.1 − % 1996 Mar 28 7 − Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter SYMBOL PARAMETER TDA8762 CONDITIONS MIN. TYP. MAX. UNIT BANDWIDTH (fclk = 40 MHz) B analog bandwidth full-scale sine wave; note 5 − 40 − MHz 75% full-scale sine wave; note 5 − 55 − MHz small signal at mid-scale; VI = ±10 LSB at code 512; note 5 − 700 − MHz tSTLH analog input settling time LOW-to-HIGH full-scale square wave; Fig.6; note 6 − 2.0 3 ns tSTHL analog input settling time HIGH-to-LOW full-scale square wave; Fig.6; note 6 − 2.5 3.5 ns fi = 4.43 MHz − − 0 dB second harmonics − −70 −62 dB third harmonics − −75 −67 dB fi = 4.43 MHz − −70 − dB without harmonics; fclk = 40 MHz; fi = 4.43 MHz 57 59 − dB fi = 4.43 MHz − 9.4 − bits fi = 7.5 MHz − 9.3 − bits fi = 10 MHz − 9.0 − bits fi = 15 MHz − 8.7 − bits fclk = 40 MHz − −70 − dB fclk = 40 MHz; fi = 4.43 MHz; VI = ±16 LSB at code 512 − 10−13 − times/ sample HARMONICS (fclk = 40 MHZ) h1 fundamental harmonics (full scale) hall harmonics (full scale); all components fi = 4.43 MHz THD total harmonic distortion SIGNAL-TO-NOISE RATIO; see Fig.8; note 7 S/N signal-to-noise ratio (full scale) EFFECTIVE BITS; see Figs 7, 8 and 9; note 7 EB effective bits fclk = 40 MHz TWO-TONE; note 8 TTIR two-tone intermodulation rejection BIT ERROR RATE BER bit error rate 1996 Mar 28 8 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter SYMBOL TDA8762 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DIFFERENTIAL GAIN; note 9 Gdiff differential gain fclk = 40 MHz; PAL modulated ramp − 0.5 − % fclk = 40 MHz; PAL modulated ramp − 0.5 − deg DIFFERENTIAL PHASE; note 9 ϕdiff differential phase Timing (fclk = 40 MHz; CL = 15 pF); see Fig.4; note 10 tds sampling delay time − − 2 ns th output hold time 5 − − ns td output delay time − 10 14 ns CL digital output load − 15 40 pF 3-state output delay times; see Fig.5 tdZH enable HIGH − 45 50 ns tdZL enable LOW − 25 35 ns tdHZ disable HIGH − 12 15 ns tdLZ disable LOW − 12 15 ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. Analog input voltages producing code 0 up to and including code 1023: a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 °C. b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 °C. 3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3. V RT – V RB a) The current flowing into the resistor ladder is IL = ------------------------------------------ and the full-scale input range at the converter, R OB + R L + R OT RL to cover code 0 to code 1023, is . V I = R L × I L = ------------------------------------------ × ( V RT – V RB ) = 0.824 × ( V RT – V RB ) . R OB + R L + R OT b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio RL ----------------------------------------- will be kept reasonably constant from part to part. Consequently variation of the output codes R OB + R L + R OT at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 4. ( V 1023 – V 0 ) – 2 V GER = ------------------------------------------------ × 100 . 2V 1996 Mar 28 9 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal. 6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter. 9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. 10. Output data acquisition: the output data is available after the maximum delay time of td. handbook, halfpage VRT ROT code 1023 RL VRM RLAD IL code 0 ROB VRB MGD281 Fig.3 Explanation of note 3. 1996 Mar 28 10 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter Table 1 TDA8762 Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.8 V) BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS STEP VI(p-p) IR U/F <1.52 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1.52 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 . 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1022 . 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1023 3.58 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 O/F >3.58 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 Table 2 Mode selection TC OE D9 TO D0 IR X 1 high impedance 0 0 active; two’s complement active 1 0 active; binary active high impedance t CPL handbook, full pagewidth t CPH 1.4 V CLK sample N sample N + 1 sample N + 2 Vl t ds th 2.4 V DATA D0 to D9 DATA N-2 DATA N-1 DATA N DATA N+1 1.4 V 0.4 V td Fig.4 Timing diagram. 1996 Mar 28 11 MGC037 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter handbook, full pagewidth TDA8762 V CCD 50 % OE t dHZ t dZH HIGH 90 % output data 50 % t dLZ LOW t dZL HIGH output data 50 % LOW 10 % V CCD 3.3 kΩ S1 TDA8762 15 pF TEST S1 t dLZ t dZL VCCD VCCD t dHZ GND t dZH GND OE MGC038 fOE = 100 kHz. Fig.5 Timing diagram and test conditions of 3-state output delay time. 1996 Mar 28 12 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 t STHL t STLH handbook, full pagewidth code 1023 VI 50 % 50 % code 0 2 ns 2 ns CLK 50 % 50 % 0.5 ns MGD345 0.5 ns Fig.6 Analog input settling-time diagram. MLC947 0 handbook, full pagewidth A (dB) 20 40 60 80 100 120 0 2.5 5 7.5 10 12.5 15 17.5 20 f (MHz) Effective bits: 9.46; THD = −71.19 dB; Harmonic levels (dB): 2nd = −79.70; 3rd = −72.84; 4th = −81.54; 5th = −83.93; 6th = −86.47. Fig.7 Fast Fourier Transform (fclk = 40 MHz; fi = 4.43 MHz). 1996 Mar 28 13 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 MLC948 0 handbook, full pagewidth A (dB) 20 40 60 80 100 120 0 2.5 5 7.5 10 12.5 15 17.5 20 f (MHz) Effective bits: 9.11; THD = −63.18 dB; Harmonic levels (dB): 2nd = −66.49; 3rd = −66.52; 4th = −85.15; 5th = −75.95; 6th = −83.47. Fig.8 Fast Fourier Transform (fclk = 40 MHz; fi = 10 MHz). MLC949 0 handbook, full pagewidth A (dB) 20 40 60 80 100 120 0 2.5 5 7.5 10 12.5 15 17.5 20 f (MHz) Effective bits: 8.70; THD = −60.18 dB; Harmonic levels (dB): 2nd = −62.24; 3rd = −70.44; 4th = −77.29; 5th = −65.99; 6th = −89.67. Fig.9 Fast Fourier Transform (fclk = 40 MHz; fi = 15 MHz). 1996 Mar 28 14 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 INTERNAL PIN CONFIGURATIONS handbook, halfpage VCCO2 handbook, halfpage VCCO1 V CCA D9 to D0 IR VI OGND1 AGND MGC039 MGC040 - 1 Fig.10 TTL data and in-range outputs. Fig.11 Analog inputs. handbook, halfpage VCCO1 VCCA VRT OE (TC) VRM R LAD VRB AGND MBE565 OGND2 MGD344 Fig.12 OE (TC) input. 1996 Mar 28 Fig.13 VRB, VRM and VRT. 15 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 handbook, halfpage VCCD V ref (1.3 V) CLK DGND MGC042 - 1 Fig.14 CLK input. 1996 Mar 28 16 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 APPLICATION INFORMATION Additional application information will be supplied upon request (please quote number “AN96025”). CLK handbook, halfpage TC VCCA AGND1 AGND2 (1) 100 nF (3)(1) V RB V RM 28 2 27 3 26 4 25 5 24 6 23 D7 7 22 AGND (4) VI 100 nF (1) AGND V RT V CCO2 1 OGND2 IR D9 D8 D6 TDA8762 8 21 9 20 10 19 11 18 12 17 13 16 14 15 D5 D4 100 nF OE D3 AGND V CCD DGND V CCO1 OGND1 D2 D1 D0 n.c.(2) MGC043 The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VCCA supply through a resistor bridge and a decoupled capacitor. (1) VRB, VRM and VRT are decoupled to AGND. (2) Pin 15 should be connected to DGND in order to prevent noise influence. (3) When VRM is not used, pin 7 can be left open, avoiding the decoupling capacitor. In any case, this pin must not be grounded. (4) When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 8). Fig.15 Application diagram. 1996 Mar 28 17 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1996 Mar 28 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 18 o Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Mar 28 19 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Mar 28 20 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 NOTES 1996 Mar 28 21 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 NOTES 1996 Mar 28 22 Philips Semiconductors Product specification 10-bit high-speed low-power analog-to-digital converter TDA8762 NOTES 1996 Mar 28 23 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02) 805 4455, Fax. (02) 805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. (01) 60 101-1256, Fax. (01) 60 101-1250 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. (172) 200 733, Fax. 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VB, Tel. (040) 2783749, Fax. (040) 2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09) 849-4160, Fax. (09) 849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022) 74 8000, Fax. (022) 74 8341 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. (022) 612 2831, Fax. (022) 612 2327 Portugal: see Spain Romania: see Italy Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65) 350 2000, Fax. (65) 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011) 470-5911, Fax. (011) 470-5494 South America: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011) 821-2333, Fax. (011) 829-1849 Spain: Balmes 22, 08007 BARCELONA, Tel. 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(708) 296-8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. (381) 11 825 344, Fax. (359) 211 635 777 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31-40-2724825 SCDS48 © Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1100/02/pp24 Document order number: Date of release: 1996 Mar 28 9397 750 00767