PHILIPS 74AHCT1G125GV

INTEGRATED CIRCUITS
DATA SHEET
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Product specification
Supersedes data of 2002 Mar 22
2002 Jun 06
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
FEATURES
DESCRIPTION
• Symmetrical output impedance
The 74AHC1G/AHCT1G125 is a high-speed Si-gate
CMOS device.
• High noise immunity
• ESD protection:
The 74AHC1G/AHCT1G125 provides one non-inverting
buffer/line driver with 3-state output. The 3-state output is
controlled by the output enable input (OE). A HIGH at OE
causes the output to assume a high-impedance
OFF-state.
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
• Low power dissipation
• Balanced propagation delays
• Very small 5-pin package
• Output capability: standard
• Specified from −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
AHC1G
tPHL/tPLH
propagation delay A to Y
CI
input capacitance
CPD
power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 9
CL = 15 pF; VCC = 5 V
AHCT1G
3.4
3.4
ns
1.5
1.5
pF
11
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo ) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
FUNCTION TABLE
See note 1.
INPUTS
OE
OUTPUT
A
L
L
L
L
H
H
H
X
Z
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
2002 Jun 06
Y
2
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
ORDERING INFORMATION
TYPE NUMBER
PACKAGES
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
MARKING
−40 to +125 °C
5
SC-88A
plastic
SOT353
AM
74AHC1G125GW
74AHCT1G125GW
−40 to +125 °C
5
SC-88A
plastic
SOT353
CM
74AHC1G125GV
−40 to +125 °C
5
SC-74A
plastic
SOT753
A25
74AHCT1G125GV
−40 to +125 °C
5
SC-74A
plastic
SOT753
C25
PINNING
PIN
SYMBOL
DESCRIPTION
1
OE
output enable input
2
A
data input A
3
GND
ground (0 V)
4
Y
data output Y
5
VCC
supply voltage
handbook, halfpage
OE 1
A 2
GND
handbook, halfpage
5 VCC
A
1
OE
Y
4
125
3
4
Y
MNA118
MNA117
Fig.1 Pin configuration.
handbook, halfpage
2
Fig.2 Logic symbol.
handbook, halfpage
Y
A
2
4
1
OE
OE
MNA119
MNA120
Fig.3 IEC logic symbol.
2002 Jun 06
Fig.4 Logic diagram.
3
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
RECOMMENDED OPERATING CONDITIONS
74AHC1G
SYMBOL
PARAMETER
74AHCT1G
CONDITIONS
UNIT
MIN.
TYP. MAX. MIN.
TYP. MAX.
4.5
5.0
5.5
V
VCC
supply voltage
2.0
5.0
5.5
VI
input voltage
0
−
5.5
0
−
5.5
V
VO
output voltage
0
−
VCC
0
−
VCC
V
Tamb
operating ambient
temperature
−40
+25
+125 −40
+25
+125 °C
tr, tf
input rise and fall times
see DC and AC
characteristics per device
VCC = 3.3 ±0.3 V
−
−
100
−
−
−
ns/V
VCC = 5 ±0.5 V
−
−
20
−
−
20
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
VCC
supply voltage
−0.5
+7.0
V
VI
input voltage
−0.5
+7.0
V
IIK
input diode current
−
−20
mA
VI < −0.5 V
IOK
output diode current
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−
±20
mA
IO
output source or sink current
−0.5 V < VO < VCC + 0.5 V
−
±25
mA
ICC
VCC or GND current
−
±75
mA
Tstg
storage temperature
−65
+150 °C
PD
power dissipation per package for temperature range from −40 to +125 °C
−
250
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Jun 06
4
mW
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
DC CHARACTERISTICS
Family 74AHC1G
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
OTHER
VIH
VIL
VOH
VOL
VCC
(V)
−40 to +85
25
MIN.
TYP.
−40 to +125
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
2.0
1.5
−
−
1.5
−
1.5
−
V
3.0
2.1
−
−
2.1
−
2.1
−
V
5.5
3.85
−
−
3.85
−
3.85
−
V
2.0
−
−
0.5
−
0.5
−
0.5
V
3.0
−
−
0.9
−
0.9
−
0.9
V
5.5
−
−
1.65
−
1.65
−
1.65
V
HIGH-level output VI = VIH or VIL;
voltage
IO = −50 µA
2.0
1.9
2.0
−
1.9
−
1.9
−
V
VI = VIH or VIL;
IO = −50 µA
3.0
2.9
3.0
−
2.9
−
2.9
−
V
VI = VIH or VIL;
IO = −50 µA
4.5
4.4
4.5
−
4.4
−
4.4
−
V
VI = VIH or VIL;
IO = −4.0 mA
3.0
2.58
−
−
2.48
−
2.40
−
V
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94
−
−
3.8
−
3.70
−
V
VI = VIH or VIL;
IO = 50 µA
2.0
−
0
0.1
−
0.1
−
0.1
V
VI = VIH or VIL;
IO = 50 µA
3.0
−
0
0.1
−
0.1
−
0.1
V
VI = VIH or VIL;
IO = 50 µA
4.5
−
0
0.1
−
0.1
−
0.1
V
VI = VIH or VIL;
IO = 4.0 mA
3.0
−
−
0.36
−
0.44
−
0.55
V
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
0.36
−
0.44
−
0.55
V
HIGH-level input
voltage
LOW-level input
voltage
LOW-level output
voltage
IOZ
3-state OFF-state VI = VCC or GND
current
5.5
−
−
0.25
−
2.5
−
10
µA
ILI
input leakage
current
VI = VCC or GND
5.5
−
−
0.1
−
1.0
−
2.0
µA
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
1.0
−
10
−
40
µA
CI
input capacitance
−
1.5
10
−
10
−
10
pF
2002 Jun 06
5
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
Family 74AHCT1G
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
Tamb (°C)
PARAMETER
−40 to +85
25
OTHER
VCC (V)
MIN.
−40 to +125 UNIT
TYP. MAX. MIN. MAX. MIN. MAX.
VIH
HIGH-level input
voltage
4.5 to 5.5 2.0
−
−
2.0
−
2.0
−
V
VIL
LOW-level input
voltage
4.5 to 5.5 −
−
0.8
−
0.8
−
0.8
V
VOH
HIGH-level output VI = VIH or VIL;
voltage
IO = −50 µA
4.5
4.4
4.5
−
4.4
−
4.4
−
V
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94
−
−
3.8
−
3.70
−
V
VI = VIH or VIL;
IO = 50 µA
4.5
−
0
0.1
−
0.1
−
0.1
V
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
0.36
−
0.44
−
0.55
V
VOL
LOW-level output
voltage
IOZ
3-state OFF-state VI = VCC or GND
current
5.5
−
−
0.25
−
2.5
−
10
µA
ILI
input leakage
current
VI = VIH or VIL
5.5
−
−
0.1
−
1.0
−
2.0
µA
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
1.0
−
10
−
40
µA
∆ICC
additional
quiescent supply
current per input
pin
VI = 3.4 V;
other inputs at
VCC or GND;
IO = 0
−
−
1.35
−
1.5
−
1.5
mA
CI
input capacitance
−
1.5
10
−
10
−
10
pF
2002 Jun 06
5.5
6
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
AC CHARACTERISTICS
Type 74AHC1G125
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
SYMBOL
PARAMETER
WAVEFORMS
Tamb (°C)
−40 to +85
25
CL
(pF)
−40 to +125 UNIT
MIN.
TYP.
MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH
propagation delay
A to Y
see Figs 5 and 7 15
−
4.7
8.0
1.0
9.5
1.0
11.5
ns
tPZH/tPZL
propagation delay
OE to Y
see Figs 6 and 7 15
−
5.0
8.0
1.0
9.5
1.0
11.5
ns
tPHZ/tPLZ
propagation delay
OE to Y
see Figs 6 and 7 15
−
6.0
9.7
1.0
11.5
1.0
12.5
ns
tPHL/tPLH
propagation delay
A to Y
see Figs 5 and 7 50
−
6.6
11.5
1.0
13.0
1.0
14.5
ns
tPZH/tPZL
propagation delay
OE to Y
see Figs 6 and 7 50
−
6.9
11.5
1.0
13.0
1.0
14.5
ns
tPHZ/tPLZ
propagation delay
OE to Y
see Figs 6 and 7 50
−
8.3
13.2
1.0
15.0
1.0
16.5
ns
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH
propagation delay
A to Y
see Figs 5 and 7 15
−
3.4
5.5
1.0
6.5
1.0
7.0
ns
tPZH/tPZL
propagation delay
OE to Y
see Figs 6 and 7 15
−
3.6
5.1
1.0
6.0
1.0
6.5
ns
tPHZ/tPLZ
propagation delay
OE to Y
see Figs 6 and 7 15
−
4.1
6.8
1.0
8.0
1.0
8.5
ns
tPHL/tPLH
propagation delay
A to Y
see Figs 5 and 7 50
−
4.8
7.5
1.0
8.5
1.0
9.5
ns
tPZH/tPZL
propagation delay
OE to Y
see Figs 6 and 7 50
−
4.9
7.5
1.0
8.5
1.0
9.5
ns
tPHZ/tPLZ
propagation delay
OE to Y
see Figs 6 and 7 50
−
5.7
8.8
1.0
10.0
1.0
11.0
ns
Notes
1. All typical values are measured at VCC = 3.3 V.
2. All typical values are measured at VCC = 5.0 V.
2002 Jun 06
7
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
Type 74AHCT1G125
GND = 0 V; tr = tf ≤ 3.0 ns.
Tamb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
WAVEFORMS
−40 to +85
25
CL
(pF)
−40 to +125 UNIT
MIN.
TYP.
MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH
propagation delay
A to Y
see Figs 5 and 7 15
−
3.4
5.5
1.0
6.5
1.0
7.0
ns
tPZH/tPZL
propagation delay
OE to Y
see Figs 6 and 7 15
−
3.9
5.1
1.0
6.0
1.0
6.5
ns
tPHZ/tPLZ
propagation delay
OE to Y
see Figs 6 and 7 15
−
4.5
6.8
1.0
8.0
1.0
8.5
ns
tPHL/tPLH
propagation delay
A to Y
see Figs 5 and 7 50
−
4.8
7.5
1.0
8.5
1.0
9.5
ns
tPZH/tPZL
propagation delay
OE to Y
see Figs 6 and 7 50
−
5.1
7.5
1.0
8.5
1.0
9.5
ns
tPHZ/tPLZ
propagation delay
OE to Y
see Figs 6 and 7 50
−
6.1
8.8
1.0
10.0
1.0
11.0
ns
Note
1. All typical values are measured at VCC = 5.0 V.
AC WAVEFORMS
handbook, halfpage
VI
VM
A input
GND
tPHL
tPLH
VM
Y output
MNA121
FAMILY
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
AHC1G
GND to VCC
50% VCC 50% VCC
AHCT1G
GND to 3.0 V
1.5 V
50% VCC
Fig.5 The input (A) to output (Y) propagation delays.
2002 Jun 06
8
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
VI
handbook, full pagewidth
VM
OE input
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VOL +0.3 V
tPHZ
tPZH
VOH −0.3 V
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
output
enabled
output
enabled
output
disabled
MNA122
FAMILY
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
AHC1G
GND to VCC
50% VCC 50% VCC
AHCT1G
GND to 3.0 V
1.5 V
50% VCC
Fig.6 The 3-state enable and disable times.
S1
handbook, full pagewidth
VCC
PULSE
GENERATOR
VI
RL =
1000 Ω
VO
VCC
open
GND
D.U.T.
CL
RT
MNA232
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance (see Chapter “AC characteristics”).
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
2002 Jun 06
9
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
PACKAGE OUTLINES
Plastic surface mounted package; 5 leads
SOT353
D
E
B
y
X
A
HE
5
v M A
4
Q
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E (2)
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT353
2002 Jun 06
REFERENCES
IEC
JEDEC
EIAJ
SC-88A
10
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
Plastic surface mounted package; 5 leads
SOT753
D
E
B
y
A
X
HE
5
v M A
4
Q
A
A1
c
1
2
3
Lp
detail X
bp
e
w M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
HE
Lp
Q
v
w
y
mm
1.1
0.9
0.100
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
SOT753
2002 Jun 06
REFERENCES
IEC
JEDEC
JEITA
SC-74A
11
EUROPEAN
PROJECTION
ISSUE DATE
02-04-16
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Jun 06
12
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Jun 06
13
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Jun 06
14
Philips Semiconductors
Product specification
Bus buffer/line driver; 3-state
74AHC1G125; 74AHCT1G125
NOTES
2002 Jun 06
15
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA74
© Koninklijke Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/06/pp16
Date of release: 2002
Jun 06
Document order number:
9397 750 09706