PHILIPS PHP3055E

Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
FEATURES
PHP3055E, PHD3055E
SYMBOL
QUICK REFERENCE DATA
• ’Trench’ technology
• Low on-state resistance
• Fast switching
d
VDSS = 55 V
ID = 10.3 A
g
RDS(ON) ≤ 150 mΩ (VGS = 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode, field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:• d.c. to d.c. converters
• switched mode power supplies
The PHP3055E is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHD3055E is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT78 (TO220AB)
PIN
SOT428 (DPAK)
DESCRIPTION
tab
tab
1
gate
2
drain1
3
source
2
tab
drain
1
1 23
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
- 55
55
55
± 20
10.3
7.3
41
33
175
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
1 It is not possible to make connection to pin:2 of the SOT428 package
August 1999
1
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHP3055E PHD3055E
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS
Non-repetitive avalanche
energy
IAS
Peak non-repetitive
avalanche current
CONDITIONS
MIN.
MAX.
UNIT
-
25
mJ
-
10.3
A
TYP.
MAX.
UNIT
-
4.5
K/W
60
50
-
K/W
K/W
Unclamped inductive load, IAS = 3.3 A;
tp = 220 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:15
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
SOT78 package, in free air
SOT428 package, pcb mounted, minimum
footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
MIN.
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
RDS(ON)
gfs
IGSS
IDSS
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current
Zero gate voltage drain
current
VGS = 10 V; ID = 5.5 A
Tj = 175˚C
VDS = 25 V; ID = 5.5 A
VGS = ±10 V; VDS = 0 V
VDS = 55 V; VGS = 0 V;
Tj = 175˚C
TYP. MAX. UNIT
55
50
2.0
1.0
1.5
-
3.0
120
250
3.2
10
0.05
-
4.0
6
150
315
100
10
500
V
V
V
V
V
mΩ
mΩ
S
nA
µA
µA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 10 A; VDD = 44 V; VGS = 10 V
-
5.8
1.5
3.2
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; RD = 2.7 Ω;
RG = 5.6 Ω; VGS = 10 V
Resistive load
-
3
26
8
10
10
35
15
20
ns
ns
ns
ns
Ld
Ld
Internal drain inductance
Internal drain inductance
-
3.5
4.5
-
nH
nH
Ls
Internal source inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
190
55
40
250
80
50
pF
pF
pF
August 1999
2
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHP3055E PHD3055E
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
IS
ISM
August 1999
CONDITIONS
MIN.
TYP. MAX. UNIT
-
-
10.3
A
-
-
41
A
IF = 10 A; VGS = 0 V
-
1.1
1.5
V
IF = 10 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
32
50
-
ns
nC
3
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHP3055E PHD3055E
Normalised Power Derating, PD (%)
Transient thermal impedance, Zth j-mb (K/W)
10
100
90
D = 0.5
80
70
0.2
60
1
50
0.1
40
P
D
0.05
D = tp/T
tp
30
0.02
20
single pulse
10
0.1
1E-06
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
90
80
70
60
50
40
30
20
10
0
150
175
Tj = 25 C
1E-01
1E+00
VGS = 10V
8V
7V
6.5 V
6V
5.5 V
5V
4.5 V
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Peak Pulsed Drain Current, IDM (A)
100
1E-02
Drain Current, ID (A)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Normalised Current Derating, ID (%)
50
75
100
125
Mounting Base temperature, Tmb (C)
1E-03
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
100
25
1E-04
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
0
1E-05
T
0.5
Drain-Source On Resistance, RDS(on) (Ohms)
5.5V
5V
0.45
RDS(on) = VDS/ ID
0.4
tp = 10 us
10
Tj = 25 C
6V
0.35
6.5 V
0.3
100 us
D.C.
1
0.25
1 ms
0.2
10 ms
0.15
100 ms
7V
8V
0.1
VGS = 10V
0.05
0.1
0
1
10
Drain-Source Voltage, VDS (V)
100
0
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
August 1999
1
2
3
4
5
6
Drain Current, ID (A)
7
8
9
10
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
4
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHP3055E PHD3055E
Drain current, ID (A)
4.5
10
VDS > ID X RDS(ON)
9
Threshold Voltage, VGS(TO) (V)
4
8
3.5
7
3
6
2.5
5
maximum
typical
minimum
2
4
1.5
3
175 C
1
2
0.5
Tj = 25 C
1
0
0
0
1
2
3
4
5
6
7
8
9
10
-60
-40
-20
Gate-source voltage, VGS (V)
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
4
0
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
Drain current, ID (A)
1.0E-01
VDS > ID X RDS(ON)
3.5
Tj = 25 C
1.0E-02
3
2.5
minimum
1.0E-03
175 C
2
typical
1.0E-04
1.5
maximum
1
1.0E-05
0.5
1.0E-06
0
0
1
2
3
4
5
6
Drain current, ID (A)
7
8
9
0
10
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
0.5
1
1.5
2
2.5
3
3.5
Gate-source voltage, VGS (V)
4
4.5
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1000
Capacitances, Ciss, Coss, Crss (pF)
Ciss
100
Coss
Crss
10
-60
-40
-20
0
20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
0.1
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
August 1999
1
10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
5
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PHP3055E PHD3055E
Gate-source voltage, VGS (V)
Maximum Avalanche Current, IAS (A)
100
ID = 10A
Tj = 25 C
VDD = 11 V
10
VDD = 44 V
25 C
1
Tj prior to avalanche = 150 C
0
1
2
3
4
5
Gate charge, QG (nC)
6
7
0.1
0.001
8
0.01
0.1
1
10
Avalanche time, tAV (ms)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Source-Drain Diode Current, IF (A)
10
VGS = 0 V
9
8
7
6
5
175 C
4
3
Tj = 25 C
2
1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
6
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHP3055E PHD3055E
MECHANICAL DATA
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
E
SOT78
A
A1
P
q
D1
D
L1
L2(1)
Q
b1
L
1
2
e
e
3
c
b
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
UNIT
A
A1
b
b1
c
D
D1
E
mm
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
e
L
L1
2.54
15.0
13.5
3.30
2.79
L2
max.
P
q
Q
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT78
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-06-11
TO-220
Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
7
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHP3055E PHD3055E
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
E
A2
A
A1
b2
D1
mounting
base
E1
D
HE
L2
2
L1
L
1
3
b1
w M A
b
c
e
e1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max.
mm
2.38
2.22
A1(1)
A2
b
b1
max.
b2
c
0.65
0.45
0.89
0.71
0.89
0.71
1.1
0.9
5.36
5.26
0.4
0.2
D1
E
D
max. max. max.
6.22
5.98
4.81
4.45
6.73
6.47
E1
min.
4.0
e
e1
2.285 4.57
HE
max.
L
10.4
9.6
2.95
2.55
L1
min.
L2
w
y
max.
0.5
0.7
0.5
0.2
0.2
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
SOT428
EUROPEAN
PROJECTION
ISSUE DATE
98-04-07
Fig.17. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
8
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHP3055E PHD3055E
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
1.5
2.5
4.57
Fig.18. SOT428 : soldering pattern for surface mounting.
August 1999
9
Rev 1.200
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHP3055E PHD3055E
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
10
Rev 1.200