PHILIPS SAA5250P

INTEGRATED CIRCUITS
DATA SHEET
SAA5250
Interface for data acquisition and
control
(for multi-standard teletext
systems)
Product specification
File under Integrated Circuits, IC02
January 1987
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
GENERAL DESCRIPTION
The SAA5250 is a CMOS Interface for Data Acquisition and Control (CIDAC) designed for use in conjunction with the
Video Input Processor (SAA5230) in a multi-standard teletext decoder. The device retrieves data from a user selected
channel (channel demultiplexer), as well as providing control signals and consecutive addressing space necessary to
drive a 2 K bytes buffer memory.
The system operates in accordance with the following transmission standards:
• French Didon Antiope specification D2 A4-2 (DIDON)
• North American Broadcast Teletext specification (NABTS)
• U.K. teletext (CEEFAX)
Features
• 7,5 MHz maximum conversion rate
• Three prefixes; DIDON, NABTS and U.K. teletext (CEEFAX)
• Mode without prefix
• Internal calculation of the validation (VAL) and colour burst blanking (CBB) signals, if programmed
• Programmable framing code and channel numbers
• Error parity calculation or not (odd parity)
• Hamming processing of the prefix byte
• Full channel or VBI reception
• Slow/fast mode (detection of page flags or not)
• Maximum/default format up to 63 bytes
• Addressing space of 2 K bytes of the static memory
• Multiplexed address/data information is compatible with Motorola or Intel microcontrollers
• CIDAC is ‘MOTEL’ compatible
PACKAGE OUTLINES
SAA5250P: 40-lead DIL; plastic (SOT129); SOT129-1; 1996 December 02.
SAA5250T: 40-lead mini-pack; plastic (VSO40); SOT158-1; 1996 December 02.
January 1987
2
January 1987
3
CBB
VAL OUT
4
2
3
5
VALIDATION
SIGNAL
PROCESSING
CLOCK
GENERATION
SERIAL/PARALLEL
CONVERTER
PARALLEL
REGISTER
SERIAL
REGISTER
8
WE
7
MS
FORMAT
COUNTER
FORMAT
TRANSCODER
FORMAT
PROCESSOR
HAMMING
CORRECTOR
1, 39-30
29-22
D7 to D0
8
VDD
40
VSS
20
SAA5250
CHANNEL
COMPARATOR
PROGRAM
REGISTER
INTERFACE
MGH075
19
21
18
17
9-16
8
WR
RD
CS
ALE
DB7
to
DB0
Interface for data acquisition and control
(for multi-standard teletext systems)
Fig.1 Block diagram.
A10 to A0
11
SEQUENCE
CONTROLLER
2 K BYTE
FIFO MEMORY
CONTROLLER
MEMORY INTERFACE
REGISTER
PAGE DETECTION
k, full pagewidth
VAL IN/
SYNC
DCK
SD
6
FRAMING
CODE
DETECTION
Philips Semiconductors
Product specification
SAA5250
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
handbook, halfpage
A10
1
40 V
VAL OUT
2
39 A9
VAL IN/
3
SYNC
38 A8
CBB
4
37 A7
DCK
5
36 A6
SD
6
35 A5
MS
7
34 A4
WE
8
33 A3
DB7
9
32 A2
DB6 10
31 A1
DB5 11
SAA5250
DD
30 A0
DB4 12
29 D7
DB3 13
28 D6
DB2 14
27 D5
DB1 15
26 D4
DB0 16
25 D3
ALE 17
24 D2
CS 18
23 D1
WR 19
22 D0
20
21 RD
V
SS
MGH074
Fig.2 Pinning diagram.
January 1987
4
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
PINNING FUNCTION
MNEMONIC
PIN NO.
FUNCTION
A10 and
A0 to A9
1 and
30 to 39
Memory address outputs used by CIDAC to address a 2 K byte buffer memory
VAL OUT
2
Validation output signal used to control the location of the window for the framing code.
VAL IN/SYNC
3
Validation input signal (line signal) used to give or calculate a window for the framing
code detection
CBB
4
Colour burst blanking output signal used by the SAA5230 as a data slicer reset pulse
DCK
5
Data clock input, in synchronization with the serial data signal
SD
6
Serial data input, arriving from the demodulator
MS
7
Chip enable output signal for buffer memory selection
WE
8
Write command output for the buffer memory
DB7 to DB0
9 to 16
8-bit three state input/output data/address bus used to transfer commands, data and
status between the CIDAC registers and the CPU
ALE
17
Demultiplexing input signal for the CPU data bus
CE
18
Chip enable input for the SAA5250
WR
19
Write command input (when LOW)
VSS
20
ground
RD
21
Read command input (when LOW)
D0 to D7
22 to 29
8-bit three state input/output data bus used to transfer data between CIDAC and the
buffer memory
VDD
40
+5 V power supply
January 1987
5
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
FUNCTIONAL DESCRIPTION
Microcontroller interface
The microcontroller interface communicates with the CPU via the handshake signals DB7 − DB0, ALE, CS, RD, WR. The
microcontroller interface produces control commands as well as programming the registers to write their contents or read
incoming status/data information from the buffer memory. The details of the codes used to address the registers are
given in Table 2.
The CIDAC is ‘MOTEL’ compatible (MOTEL compatible means it is compatible with standard Motorola or Intel
microcontrollers). It automatically recognizes the microcontroller type (such as the 6801 or 8501) by using the ALE signal
to latch the state of the RD input. No external logic is required.
Table 1
Recognition signals
8049/8051
TIMING 1
CIDAC
6801/6805
TIMING 2
ALE
ALE
AS
RD
RD
DS, E, Φ 2
WR
WR
R/W
Table 2
CIDAC register addressing
CODES
R
W
CS
DB2
DB1
DB0
FUNCTION
1
0
0
0
0
0
write register R0
1
0
0
0
0
1
write register R1
1
0
0
0
1
0
write register R2
1
0
0
0
1
1
write register R3
1
0
0
1
0
0
write register R4
1
0
0
1
0
1
write register R5
1
0
0
1
1
0
write command register R6 (initialization command)
1
0
0
1
1
1
write register R7
0
1
0
0
0
0
read status
0
1
0
0
0
1
read data register
0
1
0
0
1
0
test (not used)
0
1
0
0
1
1
test (not used)
January 1987
6
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Register organization
R0 register
Table 3
R0 Register contents
R04
SLOW/FAST MODE
R03
PARITY
R02 TO R00
USED PREFIXES
0 = slow mode
0 = no parity control
000 = DIDON long
1 = fast mode
1 = odd parity
001 = DIDON medium
010 = DIDON short
011 = not used
100 = U.K. teletext
101 = NABTS
110 = without prefix
111 = without prefix
handbook, full pagewidth
CEEFAX
magazine and row address group
FC
MRAG
DIDON
short
DIDON
medium
A
format
A1
A2
A1
A2
A3
CI
format
A1
A2
A3
CI
PS
FC
FC
DIDON
long
FC
NABTS
FC
MGH077
Fig.3 Five prefixes.
All of the bytes (see Fig.3) are Hamming protected. The hatched bytes are always stored in the memory in order to be
processed by the CPU (see section ‘Prefix processing’). In the mode without prefix all of the bytes which follow the
framing code are stored in the memory until the end of the data packet, the format is then determined by the contents of
the R3 register.
If R03 = 0; no parity control is carried out and the 8-bits of the incoming data bytes are stored in the fifo memory.
If R03 = 1; the 8th bit of the bytes following the prefix (data bytes) represents the result of the odd parity control.
If R04 = 0; the device operates in the slow mode. The CIDAC retrieves data from the user selected magazine (see
section ‘R1 and R2’) and without searching for a start to a page stores the data into the FIFO memory.
January 1987
7
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
If R04 = 1; the device operates in the fast mode. Prior to writing into the FIFO memory, the CIDAC searches for a start
to a page which is variable due to the different prefixes:
• DIDON (long, medium and short): using the redundant bytes, SOH RS, X RS and SOH X (where X is a bit affected by
a parity error)
• NABTS, the least significant bit of the PS byte is set to 1
• U.K. teletext, ROW = 0
R1 register
Table 4
R1 Register contents
R17
VAL IN/SYNC
R16 TO R14
FORMAT TABLE (1)
R13 TO R10
CHANNEL NUMBERS (FIRST DIGIT)
1 = VAL
000 = list 1
first digit hexadecimal value
0 = SYNC
001 = list 2
010 = list 3
011 = list 4
1XX = maximum/default value used (R3)
Note
1. X = don’t care
If VAL IN/SYNC = 1; the line signal immediately produces a validation signal for the framing code detection.
If VAL OUT = 0; the line signal is used as a starting signal for an internally processed validation signal (see Fig.15). The
framing code window width is fixed at 13 clock periods and the delay is determined by the contents of the R5 register
(R56 to R50).
At any moment the user is able to ensure that the framing code window is correctly located. This is accomplished by the
VAL OUT pin reflecting the internal validation signal. A CBB signal with programmable width (see section ‘R7 register’)
can also be generated, this is used as a data slicer reset pulse by the SAA5230. The line signal is used as the starting
point of the internal CBB signal width fixed by the contents of the R7 register.
If R16 = 0; then bits R15 and R14 provide the format table number using DIDON long and short prefixes (see Table 6).
If R16 = 1; then the format is determined by the contents of the R3 register.
The bits R13 to R10 represent the first channel number to be checked in the prefix. In U.K. teletext mode only 3 bits are
required, so R13 = X.
January 1987
8
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
Table 5
SAA5250
Format table
FORMAT BYTE
B8, B6, B4 AND B2 (1)
LIST 1
LIST 2
LIST 3
LIST 4
0000
0
0
0
0
0001
1
1
1
1
0010
2
2
2
2
0011
3
3
3
3
0100
4
5
6
7
0101
8
9
10
11
0110
12
13
14
15
0111
16
17
18
19
1000
20
21
22
23
1001
24
25
26
27
1010
28
29
30
31
1011
32
33
34
35
1100
36
37
38
39
1101
40
41
42
43
1110
44
45
46
47
1111
48
49
50
51
Note
1. B8 = MSB and B2 = LSB.
R2 register
Table 6
R2 Register contents
R27 TO R24
R23 TO R20
channel number, third digit
channel number, second digit
(hexadecimal value, third digit)
(hexadecimal value, second digit
Note
1. R27 and R23 = MSB and R24 and R20 = LSB
The R2 register provides the other two parts of the channel number (depending on the prefix) that require checking.
January 1987
9
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
R3 register
Table 7
R3 register contents
R35 TO R30
6-BIT FORMAT MAXIMUM/DEFAULT VALUE
000000 = 0
000001 = 1
−
−
−
111111 = 63
This 6-bit byte gives:
• In the DIDON long and short mode, a maximum format in case of corrupted transmission (multiple errors on the
Hamming corrector)
• A possible 63-bit format for all types of prefix
R4 register
Table 8
R4 register contents
R47 TO R40
8-bit register used for storing the framing code value which will be compared with the third byte of each data
line
R5 register
Table 9
R5 register contents
R57
NEGATIVE/POSITIVE
R56 TO R50
SYNCHRONIZATION DELAY
0 = negative edge for sync signal
7-bit sync delay, giving a maximum
1 = positive edge for sync signal
delay of (27 − 1) × 106 µs/F (Hz)
Note
1. F = data clock acquisition frequency (DCK).
Using R57 it is possible to start the internal synchronization delay (tDVAL) on the positive or negative edge.
R6 write command register
This is a fictitious register. Only the address code (see Table 2) is required to reset the CIDAC. See Table 11 for the
status of the FIFO memory on receipt of this command.
R7 register
Table 10 R7 register contents
R75 TO R70
6-bit register used to give a maximum colour burst blanking signal of: (26 − 1) × 106 µs/F (Hz)
Note
1. F = data clock acquisition frequency.
January 1987
10
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Fifo status register (read R0 register)
Table 11 Fifo register contents
DB2 TO DB0
DB2 = 1
memory empty
DB1 = 1, data not present in the
read data register
DB0 = 0
memory not full
Once the relevant prefix and the right working modes have been given by the corresponding registers, a write command
to the R6 register enables the CIDAC to accept and process serial data.
Channel comparator
This is a four bit comparator which compares the three user hexadecimal defined values in R1 and R2 to corresponding
bytes of the prefix coming from the Hamming corrector. If the three bytes match, the internal process of the prefix
continues. If they do not match the CIDAC returns to a wait state until the next broadcast data package is received.
FIFO memory controller
The FIFO memory contains all the necessary functions required for the control of the 11-bit address memory (2 K byte).
The functions contained in the FIFO memory are as follows:
• write address register (11-bits)
• read address register (11-bits)
• memory pointer (11-bits)
• address multiplexer (11-bits)
• write data register (8-bits)
• read data register (8-bits)
• data multiplexer
• control logic
The FIFO memory provides the memory interface with the following:
• 11-bit address bus (A10 to A0)
• 8-bit data bus (D7 to D0)
• two control signals, memory select (MS) and write enable (WE)
January 1987
11
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Operation
The CIDAC uses the same clock signal for data acquisition and internal processing, this allows the CIDAC to have a write
and a read cycle during each character period (see Fig.13). The first half of the character period is a write cycle and the
second half is a read cycle. Consequently, for an 8 MHz bit rate the maximum memory cycle time is 500 ns.
When the first data byte is written into the FIFO memory, thus transferred into the read register, the FIFO memory enters
the status shown in Table 12.
Table 12 FIFO status
DB2 TO DB0
DB2 = 1
memory empty
DB1 = 0
data available
DB0 = 0
memory not full
When the FIFO memory is full two events occur:
• the write address register points to the next address after the last written address
• when new data is to be written, the memory select signal output ceases
Memory interface
The memory interface contains all the buffers for the memory signals mentioned in the section ‘FIFO memory controller’.
Page detection
This part of the CIDAC contains a parallel register with logic which detects (only in fast mode) a start of a page or data
group (see section ‘R0 register’).
Hamming correction (see Tables 13 and 14)
The Hamming correction provides (see section ‘Prefix processing’):
• hexadecimal value of the Hamming code
• accept/reject code signal
• parity information
January 1987
12
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Table 13 Hamming correction (coding)
HEXADECIMAL
NOTATION
B8
B7
B6
B5
B4
B3
B2
B1
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
1
0
2
0
1
0
0
1
0
0
1
3
0
1
0
1
1
1
1
0
4
0
1
1
0
0
1
0
0
5
0
1
1
1
0
0
1
1
6
0
0
1
1
1
0
0
0
7
0
0
1
0
1
1
1
1
8
1
1
0
1
0
0
0
0
9
1
1
0
0
0
1
1
1
A
1
0
0
0
1
1
0
0
B
1
0
0
1
1
0
1
1
C
1
0
1
0
0
0
0
1
D
1
0
1
1
0
1
1
0
E
1
1
1
1
1
1
0
1
F
1
1
1
0
1
0
1
0
Note
1. B7 = B8 ⊕ B6 ⊕ B4
B5 = B6 ⊕ B4 ⊕ B2
B3 = B4 ⊕ B2 ⊕ B8
B1 = B2 ⊕ B8 ⊕ B6
⊕ = exclusive OR gate function
B8, B6, B4 and B2 = data bits
B7, B5, B3 and B1 = redundancy bits
January 1987
13
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Table 14 Hamming correction (decoding)
A
B
C
D
INTERPRETATION
INFORMATION
1
1
1
1
no error
accepted
0
0
1
0
error on B8
corrected
1
1
1
0
error on B7
accepted
0
1
0
0
error on B6
corrected
1
1
0
0
error on B5
accepted
1
0
0
0
error on B4
corrected
1
0
1
0
error on B3
accepted
0
0
0
0
error on B2
corrected
0
1
1
0
error on B1
accepted
1
multiple errors
rejected
A.B.C = 0
Note
1. A = B8 ⊕ B6 ⊕ B2 ⊕ B1
B = B8 ⊕ B4 ⊕ B3 ⊕ B2
C = B6 ⊕ B5 ⊕ B4 ⊕ B2
D = B8 ⊕ B7 ⊕ B6 ⊕ B5 ⊕ B4 ⊕ B3 ⊕ B2 ⊕ B1
⊕ = exclusive OR gate function
Format processing
The format processing consist of two parts:
part 1
A format transcoder produces a 6-bit code (up to 63) and uses the following as inputs:
• DIDON long and short prefixes;
hamming corrected code (4-bits)
accept/reject code condition
table number (see section ‘R1 register’, bits R15 and R14)
• Other prefixes (R16 = 1)
• 6-bit maximum/default format (see section ‘R3 register’)
part 2
A format counter operating at the character clock frequency which receives the 6-bit code from the format transcoder and
is used to check the data packet length following the prefix.
Serial/parallel converter
The serial/parallel converter consists of three parts:
• An 8-bit shift register which receives the SD input and operates at the bit frequency (DCK).
• An 8-bit parallel register used for storage.
• A framing code detection circuit. This logic circuit compares the 8-bits of the R4 register with that of the serial register.
If seven bits out of eight match (in coincidence with a validation window), it produces a start signal for a new teletext
data line to the sequence controller.
January 1987
14
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Clock generation
The clock generator does the following:
• acts as a buffer for the DCK clock
• generates the character clock
As soon as a framing code has been detected, a divide by 8 counter is initialized and the character clock is started. The
clock drives the following:
• sequence controller
• parallel registers
• format counter
Processing of VAL and CBB signals
The circuit has one input (VAL IN/SYNC) and two outputs (VAL OUT and CBB). The circuit consists of:
• 7-bit counter operating at DCK frequency which produces the framing code validation pulse delay
• 7-bit comparator which compares the contents of the R5 register (bits R56 to R50) to the bit counter
• a 6-bit counter operating at DCK frequency which produces the CBB pulse width
• 6-bit comparator which compares the contents of the R7 register (bits R75 to R70) to the bit counter
• control logic required to provide the start condition for the VAL signal and the CBB pulse width (on the negative or
positive edge of the sync signal)
The CBB signal useful occurs when the associated video processor:
• has no sandcastle pulse to send back to the demodulator
• carries out the synchronization of the time base clock. In this event the CBB acts as a data slicer reset pulse
The VAL OUT is a control signal which reflects the internal framing code window.
Prefix processing (see Table 21)
Figs 4 to 9 show the acquisition flow charts for each prefix type coded in the R0 register (bits R02 to R00).
As soon as an initialization command is received by the CIDAC, a write command to the R6 register (only the address is
significant), is ready to receive data from a dedicated channel number and store the data in the FIFO memory (explained
in the following paragraphs, each paragraph being dedicated to an individual type of prefix).
DIDON long (see Fig.4)
In this mode, the continuity index, format and data bytes are written into the FIFO memory. (In fast mode, information
can be written into the FIFO memory only after a page detection.)
January 1987
15
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Table 15 Continuity index processing result
D7
D6
D5
D4
D3
D2
D1
D0
A/R
X
X
X
CI3
CI2
CI1
CI0
Table 16 Format processing result
D7
D6
D5
D4
D3
D2
D1
D0
A/R
X
F5
F4
F3
F2
F1
F0
Note
1. A/R = 0, if rejected
2. A/R = 1, if accepted
3. X = don’t care
DIDON mediun (see Fig.5)
Only data bytes are written into the FIFO memory. (In fast mode, information can be written into the FIFO memory only
after a page detection.)
DIDON short (see Fig.6)
In this mode, format and data bytes are written into the FIFO memory. (In fast mode, information can be written into the
FIFIFO memory only after a page detection.)
Table 17 Format processing result
D7
D6
D5
D4
D3
D2
D1
D0
A/R
X
F5
F4
F3
F2
F1
F0
NABTS (see Fig.7)
In this mode, the continuity index, packet structure and data bytes are written into the FIFO memory. (In fast mode,
information can be written into the FIFO memory only after a page detection.)
Table 18 Continuity index processing result
D7
D6
D5
D4
D3
D2
D1
D0
A/R
X
X
X
CI3
CI2
CI1
CI0
Table 19 Packet structure processing result
D7
D6
D5
D4
D3
D2
D1
D0
A/R
X
X
X
PS3
PS2
PS1
PS0
U.K. teletext (see Fig.8)
In this mode, the magazine and row address group (two bytes) and data bytes are written into the FIFO memory. (In fast
mode, information can be written into the FIFO memory only after a flag detection.)
January 1987
16
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Table 20 Magazine and row address group processing results
D7
D6
D5
D4
D3
D2
D1
D0
A/R
X
X
RW4
RW3
RW2
RW1
RW0
Without prefix
All the data following the framing code are stored in the FIFO memory.
Table 21 Prefix processing
PREFIXES
CONSTRUCTION
OF PREFIXES
BYTES STORED IN FIFO
MEMORY DURING SLOW MODE
BYTES STORED IN FIFO
MEMORY DURING FAST MODE
DIDON
long
A1, A2, A3,
CI, F and D
CI, F and D
CI(1) , F(1) and D(1)
DIDON
medium
A1, A2 and D
D
D(1)
DIDON
short
A1, F and D
F and D
F(1) and D(1)
A1, A2, A3
CI, PS and D
CI, PS and D
CI(1), PS(1) and D(1)
MRAG and D
MRAG and D
MRAG(1) and D(1)
NABTS
U.K.
teletext
without
prefix
all bytes of the data packet following the framing code are written into the
FIFO memory
Note
1. after page/flag detection
2. A1, A2, A3 are channel numbers
CI = continuity index
F = format
PS = packet structure
D = data
MRAG = magazine and row address group
January 1987
17
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
Fig.4 DIDON (long) acquisition flow chart.
January 1987
18
SAA5250
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
handbook, full pagewidth
INITIALIZE CIDAC
FRAMING
CODE DETECT
0
1
A1 O.K.
0
1
A2 O.K.
0
1
LOAD FORMAT COUNTER
WITH EXPLICIT VALUE
FORMAT
COUNTER = 0
1
0
FAST
PAGE IN
PROGRESS
1
SLOW/FAST
MODE
SLOW
0
DECREMENT FORMAT COUNTER
1
0
START OF
PAGE DETECT
SET PAGE IN PROGRESS FLAG
DECREMENT FORMAT COUNTER.
WRITE DATA BYTES INTO FIFO
MGH084
Fig.5 DIDON (medium) acquisition flow chart.
January 1987
19
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
handbook, full pagewidth
INITIALIZE CIDAC
FRAMING
CODE DETECT
0
1
A O.K.
0
1
LOAD FORMAT COUNTER
WITH INCOMING VALUE
FAST
PAGE IN
PROGRESS
1
SLOW/FAST
MODE
SLOW
0
1
FORMAT
COUNTER = 0
0
DECREMENT FORMAT COUNTER
START OF
PAGE DETECT
0
1
SET PAGE IN PROGRESS FLAG
WRITE FORMAT INTO FIFO
FORMAT
COUNTER = 0
1
0
DECREMENT FORMAT COUNTER.
WRITE DATA BYTES INTO FIFO
MGH083
Fig.6 DIDON (short) acquisition flow chart.
January 1987
20
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
handbook, full pagewidth
INITIALIZE CIDAC
FRAMING
CODE DETECT
0
1
A1 O.K.
0
1
A2 O.K.
0
1
A3 O.K.
0
1
SAVE CI BYTES
LOAD FORMAT COUNTER
WITH IMPLICIT FORMAT
FAST
DATA GROUP IN
PROGRESS
1
SLOW/FAST
MODE
SLOW
0
0
SYNCHRONIZING
PACKET
1
SET DATA GROUP IN
PROGRESS FLAG
WRITE CI BYTE INTO FIFO
WRITE PS BYTE INTO FIFO
FORMAT
COUNTER = 0
1
0
DECREMENT FORMAT COUNTER.
WRITE DATA BYTES INTO FIFO
MGH082
Fig.7 NABTS acquisition flow chart.
January 1987
21
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
handbook, full pagewidth
SAA5250
INITIALIZE CIDAC
FRAMING
CODE DETECT
0
1
MAG O.K.
0
1
SLOW/FAST
MODE
PAGE IN
PROGRESS
1
SLOW
0
0
ROW 0
SET PAGE IN PROGRESS FLAG
WRITE ROW NUMBER INTO FIFO
LOAD FORMAT COUNTER
WITH IMPLICIT FORMAT
FORMAT
COUNTER = 0
DECREMENT FORMAT COUNTER.
WRITE DATA BYTES INTO FIFO
MGH081
Fig.8 U.K. teletext acquisition flow chart.
January 1987
22
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
handbook, halfpage
SAA5250
INITIALIZE CIDAC
FRAMING
CODE DETECT
0
1
LOAD FORMAT COUNTER
WITH EXPLICIT FORMAT
FORMAT
COUNTER = 0
1
0
DECREMENT FORMAT COUNTER.
WRITE DATA BYTES INTO FIFO
MGH080
Fig.9 Without prefix acquisition chart.
handbook, full pagewidth
DCK
clock input to
data acquisition
circuit
5
D
SD
data input to
data acquisition
circuit
6
D
CBI
D = clamping diodes
CBI = clamping pulse, the pulse width
is given by the R7 register
Fig.10 SD and DCK input circuitry.
January 1987
23
MGH076
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
Supply voltage range
VDD
−0,3
6,5
V
Input voltage range
VI
−0,3
VDD+0,3
V
Total power dissipation
Ptot
−
400
mW
Operating ambient temperature range
Tamb
0
70
°C
Storage temperature range
Tstg
−20
+125
°C
D.C. CHARACTERISTICS (except SD and DCK)
VDD = 5 V±10%; VSS = 0 V; Tamb = 0 to 70 °C, unless otherwise specified
PARAMETER
CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage range
VDD
4,5
5,0
5,5
V
Input voltage HIGH
VIH
2
−
VDD
V
Input voltage LOW
VIL
−
−
0,8
V
II
−
−
1,0
µA
Output voltage HIGH
Iload = 1 mA
VOH
VDD−0,4
−
−
V
Output voltage LOW
Iload = 4 mA,
at pins 9 to 16
and 22 to 29
VOL
−
−
0,4
V
Iload = 1 mA all
other outputs
VOL
−
−
0,4
V
Power dissipation
P
−
5
−
mW
Input capacitance
CI
−
−
7,5
pF
Input leakage current
January 1987
24
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
SD and DCK D.C. CHARACTERISTICS (see Fig.10)
VDD = 5 V; VSS = 0 V; Tamb = 0 to 70 °C, unless otherwise specified
PARAMETER
CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
DCK
VI(p-p)
2,0
−
−
V
II
5
−
200
µA
Input capacitance
CI
−
−
30
pF
External coupling capacitor
Ctext
10
−
−
nF
VIH
2,0
−
−
V
D.C. input voltage range LOW note 2
VIL
−
−
0,8
V
A.C. input voltage
(peak-to-peak value)
VI(p-p)
2,0
−
−
V
II
−
−
10
µA
Input capacitance
CI
−
−
30
pF
External coupling capacitor
Cext
10
−
−
nF
Input voltage range
(peak-to-peak value)
Input current
VI = 0 to VDD
SD
D.C. input voltage range HIGH note 1
Input leakage current
January 1987
VI = 0 to VDD
25
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
A.C. CHARACTERISTICS
VDD = 5 V ± 10%; Reference levels for all inputs and outputs, VIH = 2 V; VIL = 0,8 V; VOH = 2,4 V; VOL = 0,4 V;
CL = 50 pF on DB7 to DB0; Tamb = 0 to 70 = C, unless otherwise specified
PARAMETER
Microcontroller
interface
CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Figs 11 and 12
tCY
400
−
−
ns
Address pulse width
tLHLL
50
−
−
ns
RD HIGH or WR to ALE HIGH Fig.11
tAHRD
0
−
−
ns
DS LOW to AS HIGH
Fig.12
tAHRD
0
−
−
ns
ALE LOW to RD
LOW or WR LOW
Fig.11
tALRD
30
−
−
ns
AS LOW to DS HIGH
Fig.12
tALRD
30
−
−
ns
Write pulse width
tWL
120
−
−
ns
Address and chip select
set-up time
tASL
10
−
−
ns
Address and chip select hold
time
tAHL
20
−
−
ns
Read to data out period
tRD
−
−
130
ns
Cycle time
tDR
10
−
100
ns
R/W to DS set-up time
Fig.12
tRWS
40
−
−
ns
R/W to DS hold time
Fig.12
tRWH
10
−
−
ns
Data set-up time
write cycle
tDW
50
−
−
ns
Data hold time
write cycle
tWD
10
−
−
ns
Read pulse width
note 3
tRL
150 or
DCK + 50
−
−
ns
Memory interface
Fig.13
WE LOW to DCK falling edge
tWEL
10
−
80
ns
WE HIGH to DCK falling edge
tWEH
10
−
80
ns
MS LOW to DCK rising edge
tMSL
10
−
80
ns
MS HIGH to DCK rising edge
tMSH
10
−
85
ns
Address output from DCK
rising edge
tAV
10
−
120
ns
Data output from WE falling
edge
tDWL
0
−
10
ns
Data hold from WE rising edge
tDWH
0
−
−
ns
Data hold after RD
Address set-up time to data
note 4
tAD
−
−
3 × DCK
−110
ns
WE pulse width
note 5
tWEW
3 × DCK
−
−
ns
MS pulse width
note 6
tMSW
2 × DCK
−
−
ns
January 1987
26
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
PARAMETER
CONDITIONS
SAA5250
SYMBOL
MIN.
TYP.
MAX.
UNIT
Demodulator interface
(see SD and DCK D.C.
CHARACTERISTICS)
DCK LOW
Fig.14
conversion
rate < 7,5 MHz
tDCKL
55
−
−
ns
conversion
rate < 7,5 MHz
tDCKH
55
−
−
ns
Serial data set-up time
tSSD
0
−
−
ns
Serial data hold time
tHSD
30
−
−
ns
Validation signal set-up time
tSVALI
50
−
−
ns
Validation signal hold time
tHVALI
50
−
−
ns
tWCBB
0
−
63
DCK
tWVAL
X
12
X
DCK
tDVAL
0
−
127
DCK
DCK HIGH
Other I/O signals
Fig.15
User definable width as a
multiple of DCK period
Validation signal width
note 7
User definable delay as a
multiple of DCK period
Notes to the characteristics
1. Unless R7 = 00 the value given is unacceptable.
2. When CBI signal is maintained at 0 V (R7 = 00) and if SD input signal is correctly referenced to ground, no coupling
capacitor is required.
3. DCK + 50 is the DCK period plus 50 ns.
4. 3 × DCK − 110 is 3 × DCK period − 110 ns.
5. 3 × DCK is 3 × DCK period.
6. 2 × DCK is 2 × DCK period.
7. X = irrelevant.
January 1987
27
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
READ CYCLE
handbook, full pagewidth
SAA5250
tCY
ALE
tAHRD
tLHLL
tRL
tALRD
RD
WR
CS
tASL
tAHL
tDR
tRD
ADDRESS
BUS
D OUT
WRITE CYCLE
tCY
ALE
tAHRD
tLHLL
tALRD
tWL
WR
tAHRD
RD
CS
tASL
BUS
tAHL
ADDRESS
tDW
tWD
D IN
MGH087
Fig.11 Timing diagram for microcontroller interface (Intel).
January 1987
28
January 1987
29
read cycle
write cycle
CS
R/W
(pin WR)
AS
(pin ALE)
DS
(pin RD)
tAHRD
handbook, full pagewidth
BUS
BUS
tRWS
(1)
tAHL (1)
tAHL
tRD
D IN
tDW
(1) ALE, CS, RD, WR and DB7 to DB0
tCY
D OUT
MGH085
tDR
tWD
tRWH
tAHRD
Interface for data acquisition and control
(for multi-standard teletext systems)
Fig.12 Timing diagram for microcontroller interface (Motorola).
tASL
tASL
tLHLL
tALRD
Philips Semiconductors
Product specification
SAA5250
January 1987
30
D7 to D0
tAV
tMSH
tMSW
tWEW
tAV
tDWH
READ ADDRESS
tAD
tMSL
tWEH
DATA IN
DATA OUT
WRITE ADDRESS
MGH086
Interface for data acquisition and control
(for multi-standard teletext systems)
Fig.13 Timing diagram for memory interface.
DATA OUT
tDWL
WRITE ADDRESS
tMSL
tWEL
handbook, full pagewidth
A10 to A0
MS
WE
DCK
character
period
Philips Semiconductors
Product specification
SAA5250
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
tDCKL
handbook, full pagewidth
DCK
tDCKH
SD
tSSD
tHSD
tSVALI
tHVALI
VAL IN/
SYNC
MGH079
Fig.14 Timing diagram for demodulator interface.
handbook, full pagewidth
VAL, CBB
DCK
VAL IN /
SYNC
CLOCK SYNCHRONIZATION
BITS
SD
tDVAL
FRAMING
CODE
PREFIX AND DATA BYTES
tWVAL
VAL OUT
tWCBB
CBB
MGH078
Fig.15 Timing diagram for all other I/O signals.
January 1987
31
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
PACKAGE OUTLINES
seating plane
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
21
40
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.7
0.51
4.0
1.70
1.14
0.53
0.38
0.36
0.23
52.50
51.50
inches
0.19
0.020
0.16
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
D
(1)
e
e1
L
ME
MH
w
Z (1)
max.
14.1
13.7
2.54
15.24
3.60
3.05
15.80
15.24
17.42
15.90
0.254
2.25
0.56
0.54
0.10
0.60
0.14
0.12
0.62
0.60
0.69
0.63
0.01
0.089
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT129-1
051G08
MO-015AJ
January 1987
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-14
32
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
VSO40: plastic very small outline package; 40 leads
SOT158-1
D
E
A
X
c
y
HE
v M A
Z
40
21
Q
A2
A
(A 3)
A1
θ
pin 1 index
Lp
L
1
detail X
20
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
2.70
0.3
0.1
2.45
2.25
0.25
0.42
0.30
0.22
0.14
15.6
15.2
7.6
7.5
0.762
12.3
11.8
2.25
1.7
1.5
1.15
1.05
0.2
0.1
0.1
0.6
0.3
0.012 0.096
0.017 0.0087 0.61
0.010
0.004 0.089
0.012 0.0055 0.60
0.30
0.29
0.03
0.48
0.46
0.067
0.089
0.059
inches
0.11
0.045
0.024
0.008 0.004 0.004
0.041
0.012
θ
7o
0o
Notes
1. Plastic or metal protrusions of 0.4 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-01-24
SOT158-1
January 1987
EUROPEAN
PROJECTION
33
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO and
VSO packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO and VSO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO and
VSO packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
January 1987
SAA5250
34
Philips Semiconductors
Product specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
January 1987
35