INTEGRATED CIRCUITS DATA SHEET TDA4887PS 160 MHz bus-controlled monitor video preamplifier Product specification File under Integrated Circuits, IC02 2001 Oct 19 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier CONTENTS TDA4887PS 10 CHARACTERISTICS 11 I2C-BUS PROTOCOL 12 TEST AND APPLICATION INFORMATION Test board Application board with monolithic post amplifier Building the application board Application hints 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 12.1 12.2 12.3 12.4 6 PINNING 13 INTERNAL CIRCUITRY 7 FUNCTIONAL DESCRIPTION 14 PACKAGE OUTLINE SOLDERING 15.1 Introduction to soldering through-hole mount packages Soldering by dipping or by solder wave Manual soldering Suitability of through-hole mount IC packages for dipping and wave soldering methods 7.9 7.10 Signal input stage Electronic potentiometer stages Output stage Pedestal blanking Output clamping and feedback references Clamping and blanking pulses On Screen Display insertion and OSD contrast Subcontrast adjustment, contrast modulation and beam current limiting I2C-bus control I2C-bus data buffer 15 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 2001 Oct 19 15.2 15.3 15.4 2 16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS 19 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 1 TDA4887PS FEATURES • 160 MHz pixel rate • 2.7 ns rise time, 3.6 ns fall time • I2C-bus control • I2C-bus data buffer for synchronization of adjustments • 8-bit Digital-to-Analog Converters (DACs) 2 • 200 ns input clamping pulse The TDA4887PS is a monolithic integrated RGB preamplifier for colour monitor systems (e.g. 15" and 17") with I2C-bus control and OSD. In addition to bus control, beam current limiting and contrast modulation are possible. The IC offers brightness control with or without grey scale tracking for easy alignment. The signals are amplified to drive commonly used video modules or discrete solutions. A choice can be made between individual black level control with negative feedback from the cathode (DC coupling), or black level control with positive feedback and three DAC outputs for external cut-off control (AC coupling). • 4.6 V (p-p) output signal • Brightness control with grey scale tracking for user-friendly performance (4 dB more than TDA4885 and TDA4886) • Brightness control without grey scale tracking for easy alignment • On Screen Display (OSD) mixing with 50 MHz pixel rate • OSD contrast • Negative feedback for DC-coupled cathodes • Especially for AC-coupled cathodes GENERAL DESCRIPTION The circuit can be used with special advantages in conjunction with the TDA485x monitor deflection IC family. – Bus controlled black level adaptable to post amplifier type – Internal positive feedback – DAC outputs for black level restoration • Integrated black level storage capacitors • Beam current limiting • Subcontrast/contrast modulation • Adjustable pedestal blanking • Sync clipping. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA4887PS 2001 Oct 19 SDIP24 DESCRIPTION plastic shrink dual in-line package; 24 leads (400 mil) 3 VERSION SOT234-1 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 4 TDA4887PS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP supply voltage (pin 7) 7.6 8.0 8.8 V IP supply current (pin 7) − 25 30 mA VP(n) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) 7.6 8.0 8.8 V IP(n) supply current; channels 1, 2 and 3 (pins 21, 18 and 15) − 20 25 mA Vi(n)(b-w) input voltage; channels 1, 2 and 3 (pins 6, 8 and 10) (black-to-white value) − 0.7 1.0 V Vo(n)(b-w)(max) maximum output voltage swing (black-to-white value); channels 1, 2 and 3 (pins 22, 19 and 16) 4.6 4.9 V Vo(n) output voltage level (pins 22, 19 and 16) 0.1 − VP(n) − 1 V Io(n)(source)(M) peak output source current (pins 22, 19 and 16) during fast positive signal transients −40 − − mA Io(n)(sink)(M) peak output sink current (pins 22, 19 and 16) during fast negative signal transients − − 20 mA Vbl(n)(ref) black level reference voltage (pins 22, 19 and 16) typical values maximum contrast; 4.2 maximum gain; Vi(n)(b-w) = 0.7 V; RL = 2 kΩ DC coupling control bit FPOL = 0 0.5 − 2.0 V AC coupling control bit FPOL = 1; no pedestal blanking 0.53 − 1.89 V tr(n) rise time of fast transients at signal outputs (pins 22, 19 and 16) − 2.7 − ns tf(n) fall time of fast transients at signal outputs (pins 22, 19 and 16) − 3.6 − ns δVo(n) overshoot/undershoot at signal outputs (pins 22, 19 and 16) input rise/fall times = 1 ns; maximum colour signal − − 10 % αct(f) crosstalk suppression by frequency f = 50 MHz 25 − − dB δC contrast control: colour signal related to maximum colour signal −45 − 0 dB ∆Gtrack tracking of output colour signals of channels 1, 2 and 3 − 0 0.5 dB δG gain control related to maximum gain −13.5 − 0 dB ∆Vbl(n) brightness control (difference between video black level and reference black level at signal outputs related to maximum colour signal) control bit BRI = 0 −10 − +33 % ∆VDA(n) brightness control range (DAC output voltages for AC coupling or internal feedback reference voltage for DC coupling) from maximum to minimum; control bit BRI = 1 −1.4 − 0 V 2001 Oct 19 contrast control from maximum to minimum 4 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier SYMBOL PARAMETER TDA4887PS CONDITIONS MIN. TYP. MAX. UNIT VFB/Rn DAC output voltage range without brightness control (for black level restoration) (pins 23, 20 and 17) control bit FPOL = 1; control bit BRI = 0 3.95 − 5.75 V VOSDn(max) maximum OSD colour signal related to maximum colour signal (pins 22, 19 and 16) maximum OSD contrast; maximum gain − 96 − % δOC OSD colour signal related to maximum OSD colour signal OSD contrast control from maximum to minimum −12 − 0 dB 2001 Oct 19 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... LIM I2C-BUS 8 4 8 8 8 8 2 3 8 8 8 8-BIT DAC 4-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 2-BIT DAC 3-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC SUBCONTRAST CONTRAST MODULATION LIMITING 24 BRIGHTNESS SWITCH AC BLACK LEVEL BRI VI1 6 22 OSD CONTRAST PEDESTAL BLANKING CHANNEL 1 REFERENCE FPOL VI2 8 CONTRAST 18 FPOL 6 PEDESTAL BLANKING FPOL FPOL 16 OSD CONTRAST PEDESTAL BLANKING TDA4887PS FPOL blanking DISO 2 3 4 BLANKING OUTPUT CLAMPING 5 11 14 DISV SUPPLY 7 9 MHB943 FBL OSD1 OSD2 OSD3 CLI HFB Fig.1 Block diagram. VP GND GNDX Product specification 1 FPOL output clamping blanking FB/R3 TDA4887PS INPUT CLAMPING VERTICAL BLANKING OSD INPUT VO3 CHANNEL 3 REFERENCE 17 input clamping VP3 BRIGHTNESS BRIGHTNESS BLANKING fast blanking FB/R2 GAIN CONTRAST INPUT CLAMPING BLANKING VO2 CHANNEL 2 REFERENCE 15 10 VP2 BRIGHTNESS 20 VI3 FB/R1 GAIN 19 OSD CONTRAST VO1 BRIGHTNESS 23 INPUT CLAMPING BLANKING VP1 GAIN CONTRAST INPUT CLAMPING BLANKING 21 Philips Semiconductors DISO DISV FPOL BRI 160 MHz bus-controlled monitor video preamplifier 13 BLOCK DIAGRAM 12 4 REGISTER 5 book, full pagewidth 2001 Oct 19 SDA SCL Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 6 TDA4887PS PINNING SYMBOL PIN DESCRIPTION FBL 1 fast blanking input for OSD insertion OSD1 2 OSD input, channel 1 OSD2 3 OSD input, channel 2 OSD3 4 OSD input, channel 3 CLI 5 input clamping and vertical blanking input VI1 6 signal input, channel 1 VP 7 supply voltage OSD1 2 23 FB/R1 VI2 8 signal input, channel 2 OSD2 3 22 VO1 GND 9 ground OSD3 4 21 VP1 VI3 10 signal input, channel 3 HFB 11 output clamping and blanking input SDA 12 I2C-bus serial data input/output SCL 13 I2C-bus clock input GNDX 14 ground signal, channels 1, 2 and 3 VP3 15 supply voltage, channel 3 VO3 16 signal output, channel 3 FB/R3 17 feedback input/reference voltage output channel 3 VP2 18 supply voltage, channel 2 VO2 19 signal output, channel 2 FB/R2 20 feedback input/reference voltage output, channel 2 VP1 21 supply voltage, channel 1 VO1 22 signal output, channel 1 FB/R1 23 feedback input/reference voltage output, channel 1 LIM 24 subcontrast adjustment, contrast modulation and beam current limiting input 2001 Oct 19 handbook, halfpage 24 LIM FBL 1 20 FB/R2 CLI 5 19 VO2 VI1 6 TDA4887PS VP 7 18 VP2 VI2 8 17 FB/R3 GND 9 16 VO3 VI3 10 15 VP3 HFB 11 14 GNDX SDA 12 13 SCL MHB919 Fig.2 Pin configuration. 7 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 7 The brightness setting is also valid for OSD signals. During blanking and output clamping the video black level will be blanked to the reference black level (brightness blanking). The brightness information is inserted before the gain potentiometers, background colour temperature will not change with brightness setting (grey scale tracking). FUNCTIONAL DESCRIPTION Refer also to block diagram (Fig.1) and definitions of levels and signals (Chapter 10). 7.1 Signal input stage The RGB input signals are capacitively coupled into the TDA4887PS from a low-ohmic source (75 Ω recommended) and actively clamped to the internal reference black level during signal black level. The signal amplitude is 0.7Vi(b-w) and should not exceed 1 V. The high-ohmic input impedance of the TDA4887PS allows the coupling capacitor to be relatively small (10 nF recommended). The coupling capacitor also functions as a storage capacitor between clamping pulses. Very small input currents will discharge the coupling capacitor resulting in black output signals for missing input clamping pulses. 7.2.2.2 The brightness information will be mixed with the DAC outputs for external black level restoration (FPOL = 1, AC-coupled cathodes) or internal feedback reference voltages (FPOL = 0, DC-coupled cathodes). This allows a simple bus-controlled brightness setting without grey scale tracking. With AC-coupled cathodes this is equivalent to brightness control via grid G1. 7.2.3 Gain control is used for white point adjustment (correction for different voltage-to-light amplification of the three colour channels) and therefore individually for R, G and B. The video signals related to the reference black level can be gain-controlled within a range of 14 dB (typical). This range is large enough to accommodate the maximum output amplitude for different applications. The nominal setting is maximum gain. The gain setting is also valid for OSD signals and brightness shift (BRI = 0), therefore the complete ‘grey scale’ is effected by gain control. Electronic potentiometer stages CONTRAST CONTROL The contrast control is driven by an 8-bit DAC via the I2C-bus. The input signals related to the internal reference black level can be adjusted simultaneously by contrast control with a control range of 32 dB (typical). The nominal setting is for maximum contrast. 7.2.2 7.2.2.1 7.3 Output stage In the output stage the nominal input signal will be amplified to provide a 4.6 V (typical) output colour signal at maximum contrast and maximum gain settings. Reference or pedestal black levels are adjusted by output clamping. In order to achieve fast rise and fall times of the output signals with minimum crosstalk between the channels, each signal stage has its own supply voltage pin. BRIGHTNESS CONTROL Brightness control with grey scale tracking The brightness control is driven by an 8-bit DAC via the I2C-bus; brightness control with grey scale tracking is selected when control bit BRI = 0. With brightness control, the video black level is shifted in relation to the reference black level simultaneously for all three channels. With a negative setting (up to 10% of the maximum signal amplitude) dark signal parts will be lost in ultra black; for positive settings (up to 33% of the maximum signal amplitude) the background will alter from black to grey. At nominal brightness setting (40H) there is no shift. 2001 Oct 19 GAIN CONTROL AND GREY SCALE TRACKING The gain control is driven by an 8-bit DAC via the I2C-bus. A fast signal blanking circuit included in the input stage is driven by several blanking pulses (see Section 7.6) and control bit DISV = 1. During the off condition the internal reference black level is inserted instead of the input signals. 7.2.1 Brightness control without grey scale tracking Brightness control without grey scale tracking is selected when control bit BRI = 1. Composite signals will not disturb normal operation because a clipping circuit cuts all signal parts below black level. 7.2 TDA4887PS 8 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 7.4 For correct operation it is necessary that there is enough headroom for ultra black signals (negative brightness setting and pedestal blanking). Any clipping with the video supply voltage at the cathode can disturb the signal rise/fall times or the black level stabilization. Pedestal blanking The pedestal blanking is driven by a 2-bit DAC via the I2C-bus. Pedestal blanking inserts a negative output level related to the reference black level (should always correspond to the ‘extended cut-off voltage’ at the cathode) during blanking and output clamping. In this way retrace lines during vertical flyback are suppressed (blanking to spot cut-off). The depth of pedestal blanking (voltage difference between reference black level and pedestal black level) is bus-controlled (2 bits, 0 to 13.5% of the maximum colour signal) and does not change with any other control or adjustment. The pedestal blanking level is used for output clamping instead of the reference black level (see Section 7.5). If the pedestal blanking level is the most negative output signal and if the application is for AC-coupled cathodes, a very simple black level restoration with a DC diode clamp can be used. 7.5 After power-on, the control bit FPOL is set to logic 1 and all alignment registers are set to logic 0 resulting in the reference black level at its lowest level (0.53 V) with no output signal. Normal operation starts after all data registers have been refreshed via the I2C-bus. Brightness control with grey scale tracking (control bit BRI = 0) can be used as well as brightness control without grey scale tracking (control bit BRI = 1) using the mixing function of bus-controlled brightness offset (0 to −1.4 V) to feedback reference voltages (see Section 7.2). 2. AC-coupled cathodes (control bit FPOL = 1) Output clamping and feedback references For applications with AC-coupled cathodes the signal outputs are fed back internally. During the output clamping pulse they are compared with a bus controlled feedback reference voltage (0.5 to 1.9 V). These values ensure a good adaptability to both discrete and integrated post amplifiers. The aim of the output clamping is to set the reference black level of the signal outputs to a value which corresponds to the ‘extended cut-off voltage’ of the CRT cathodes. With missing output clamping pulses the integrated storage capacitors will be discharged resulting in output signals going to switch-off voltage. If using pedestal blanking, the pedestal black level will be controlled by output clamping (see Fig.5). It is therefore not allowed to change the pedestal depth after black level adjustment of the monitor. For black level restoration, the DAC outputs (FB/R1, FB/R2 and FB/R3) with a range of approximately 3.95 to 5.75 V can be used. Pedestal blanking is recommended because it allows use of a simple restoration circuit. After power-on, the DAC outputs will be at maximum output voltage (register value logic 0), so when using a non-inverting amplifier for the reference voltages the monitor will start with black. Feedback references are driven via the I2C-bus and controlled by an 8-bit DAC for DC feedback references or by a 3-bit DAC for AC feedback references: 1. DC-coupled cathodes (control bit FPOL = 0) Brightness control with grey scale tracking (control bit BRI = 0) can be used as well as simple brightness control without grey scale tracking (control bit BRI = 1) using the mixing function of bus controlled brightness offset (0 to −1.4 V) to DAC output voltages (see Section 7.2). The cathode voltage is divided by a voltage divider and fed back to the IC (pins FB/R1, FB/R2 and FB/R3). During the output clamping pulse it is compared with a bus-controlled feedback reference voltage with a range of approximately 5.75 to 3.95 V. Any difference will lead to a reference black level correction (subaddress 0BH = 00H) or pedestal black level correction (subaddress 0BH ≠ 00H) by charging or discharging the integrated capacitors that store the black level information between the output clamping pulses. The DC voltages of the output stages should be designed in such a way that the reference black level/pedestal black level is within the range of 0.5 to 2.4 V at the preamplifier output. 2001 Oct 19 TDA4887PS 9 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 7.6 TDA4887PS 7.7 Clamping and blanking pulses On Screen Display insertion and OSD contrast There are two pins for clamping and blanking purposes (pins CLI and HFB): On Screen Display (OSD) insertion and OSD contrast are controlled by a 4-bit DAC driven via the I2C-bus. 1. Pin CLI (input clamping, vertical blanking) If the fast blanking input signal at pin FBL exceeds the threshold (typically 1.4 V) the input signals are blanked (signal blanking) and OSD signals are enabled. Then, any signal at pins OSD1, OSD2 or OSD3 exceeding the same threshold will create an insertion signal with an amplitude of 100% of the maximum colour signal. The amplitude can be controlled by OSD contrast (driven via the I2C-bus) with a range of 12 dB. The OSD signals are inserted at the same point as the contrast-controlled input signals and will be treated with brightness and gain control as with normal input signals. The pin CLI of TDA4887PS can be connected directly to pin CLBL of e.g. TDA4855 sync processor for input clamping pulses and vertical blanking pulses. Input clamping pulses and blanking pulses are completely separated from the sandcastle input, that means there is normally (outside detected vertical blanking) no blanking during input clamping and the clamping pulse is not suppressed during vertical blanking. The input pulse is scanned with two thresholds: Identical pulses at OSD signal input pins and FBL have to be handled very carefully. Each difference in pulse delay at the inputs will produce glitches at pulse edges at signal outputs. a) 1.4 V (typical) for vertical blanking b) 3 V (typical) for input clamping. In order to separate the vertical blanking pulse from the sandcastle pulse it is necessary that the input clamping pulse has rise/fall times faster than 75 ns/V during the transition from 1.2 to 3.5 V and vice versa. The leading edge of the internal vertical blanking pulse is delayed by typically 270 ns (after the end of an input clamping pulse or the beginning of a separate blanking pulse), the trailing edge is delayed by typically 115 ns. When control bit DISO = 1 the OSD signal insertion and fast blanking (pin FBL) are disabled. 7.8 The pin LIM is a linear contrast control pin which allows subcontrast setting, contrast modulation and beam current limiting. The maximum contrast is defined by the actual I2C-bus setting. Input signals at pin LIM act on video and OSD signals and do not affect the contrast bit resolution. If the pin is not used it should be decoupled with a capacitor or tied to the supply voltage. During the vertical blanking pulse signal blanking, brightness blanking and pedestal blanking will be activated. In buffered mode, the leading edge of the internal vertical blanking pulse is used to synchronize data transmitted via the I2C-bus (see Section 7.10.1). For correct input clamping the input signals have to be at black level during the input clamping pulse. 7.8.1 2. Pin HFB (output clamping and blanking) BEAM CURRENT LIMITING The open-circuit voltage is approximately 5 V, contrast reduction starts at input voltages <4.4 V (typical) and signal amplification will be reduced with descending input voltages. The input resistance of pin LIM is very high to make it possible to choose a time constant sufficient for the open-circuit voltage to recover through the application. The input pulse (e.g. horizontal flyback pulse) is scanned with two thresholds. If the input pulse exceeds the first threshold (typically 1.4 V) signal blanking, brightness blanking and pedestal blanking will be activated. If the input pulse exceeds the second threshold (typically 3 V) output clamping will be activated additionally. 7.8.2 Especially for applications with DC-coupled cathodes (FPOL = 0), it is useful that the leading edge of the (internal) clamping pulse is slightly delayed with respect to the leading edge of the (internal) blanking pulse in order to avoid initial misclamping due to the delay of the feedback signal from the cathodes. 2001 Oct 19 Subcontrast adjustment, contrast modulation and beam current limiting SUBCONTRAST In order to fit the maximum signal amplification to the post amplifier gain, an input voltage of <4.4 V can be used. 7.8.3 CONTRAST MODULATION To achieve brightness uniformity over the screen, scan dependent contrast modulation is possible. The nominal input voltage should be <4.4 V having enough margin for positive and negative modulation. 10 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 7.9 I2C-bus control TDA4887PS 7.10 The TDA4887PS contains an I2C-bus receiver for several control functions: 7.10.1 I2C-bus data buffer BUFFERED MODE Adjustments via the I2C-bus are synchronized with vertical blanking pulse at CLI: • Contrast register with control bits BRI, FPOL, DISV and DISO • Most significant bit (MSB) of subaddress is set to logic 1 • Brightness control with 8-bit DAC • OSD contrast control with 4-bit DAC • Only one I2C-bus transmission in buffered mode is accepted before the start of the vertical blanking pulse; following transmissions receive no acknowledge • Gain control for each channel with 8-bit DAC • Received data is stored in one internal 8-bit buffer • Internal feedback reference and external reference voltage control for each channel with 8-bit DAC • Adjustments will take effect with detection of the first vertical blanking pulse after the end of the acknowledged I2C-bus transmission • Contrast control with 8-bit DAC • Black level for AC coupling with 3-bit DAC • Depth of pedestal blanking with 2-bit DAC. • Waiting for vertical blanking pulse in buffered mode can be interrupted by Power-on reset After power-up and after internal power-on reset of the I2C-bus, the registers are set to the following values (for most applications these settings guarantee a black screen after power-up): • Auto-increment is not possible • Buffered mode should be used for user adjustments such as contrast, OSD contrast and brightness when a picture is visible on the monitor. • Control bit FPOL set to logic 1 • Control bits BRI, DISV and DISO set to logic 0 7.10.2 • All other alignment registers set to logic 0 (minimum value for control registers). Adjustments via the I2C-bus take effect immediately: DIRECT MODE • Most significant bit (MSB) of subaddress is set to logic 0 After an intermediate power dip, all registers are set to their initial values and an internal Power-on reset bit will be set with the consequence that the device will give no acknowledge on the data byte after being first addressed. The Power-on reset bit will be reset if the control register is addressed. It is recommended to then refresh all registers by using the auto-increment function. • Number of I2C-bus transmissions in direct mode is unlimited • Adjustments take effect directly at the end of each I2C-bus transmission • Direct mode can be used for all adjustments but large changes of control values may appear as visual disturbances in the picture on the monitor • Auto-increment is possible • Vertical blanking pulse is not necessary. 2001 Oct 19 11 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage (pin 7) 0 8.8 V VP(n) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) 0 8.8 V Vi(n) input voltage; channels 1, 2 and 3 (pins 6, 8 and 10) −0.1 VP V Vext external DC voltage applied to pins 1 to 4 −0.1 VP V pins 5 and 11 −0.1 VP + 0.7 V pins 12 and 13 −0.1 VP V pins 23, 20 and 17 −0.1 VP + 0.7 V pins 22, 19 and 16 note 1 note 1 pin 24 −0.1 VP V Io(n)(av) average output current; channels 1, 2 and 3 (pins 22, 19 and 16) − 20 mA Io(n)(M) peak output current channels 1, 2 and 3 (pins 22, 19 and 16) − 50 mA Ptot total power dissipation − 1400 mW Tstg storage temperature −25 +150 °C Tamb ambient temperature −20 +70 °C Tj junction temperature −25 +150 °C VESD electrostatic handling voltage for all pins machine model note 2 −250 +250 V human body model note 3 −3000 +3000 V Notes 1. No external voltages. 2. Equivalent to discharging a 200 pF capacitor via a 0.75 µH inductance (“SNW-FQ-302B” ). 3. Equivalent to discharging a 100 pF capacitor via a 1500 Ω series resistor (“SNW-FQ-302A” ). 9 THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth(j-a) thermal resistance from junction to ambient Rth(j-c) thermal resistance from junction to case 2001 Oct 19 CONDITIONS in free air 12 VALUE UNIT 55 K/W 5 K/W Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 10 CHARACTERISTICS All voltages and currents are measured in a dedicated test circuit (see Fig.17) optimized for best high frequency performance; all voltages are measured with respect to GND (pins 9 and 14); VP = VP1,2,3 = 8 V (pins 7, 21, 18 and 15); Tamb = 25 °C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; maximum colour signals at signal outputs (pins 22, 19 and 16); reference black level (Vbl(ref)) approximately 0.7 V; nominal setting for brightness; maximum settings for OSD contrast, contrast and gain; no subcontrast, modulation of contrast or limiting (VLIM ≥ 5 V); no OSD fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP supply voltage (pin 7) 7.6 8.0 8.8 V VP(SO) supply voltage threshold at note 1 pin 7 at which signal outputs are switched off 6.8 7.0 7.2 V IP supply current (pin 7) − 25 30 mA VP(n) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) 7.6 8.0 8.8 V IP(n) supply current; channels 1, pins 22, 19 and 16 2 and 3 (pins 21, 18 and 15) open-circuit; Vbl(n)(ref) = 0.7 V; notes 4 and 5 − 20 25 mA note 4 Input clamping and vertical blanking input, validation of buffered I2C-bus data (CLI; pin 5) VCLI ICLI input clamping and vertical blanking input signal input current notes 6 and 7 no vertical blanking, no input clamping −0.1 − +1.2 V vertical blanking, no input clamping 1.6 − 2.6 V input clamping, no vertical blanking 3.5 − VP V VCLI = 1 V − −0.2 − µA pin 5 connected to ground; note 8 −80 −45 −30 µA VCLI = −0.1 V; note 8 −250 −135 −100 µA note 6; see Fig.7 − − 75 ns/V 200 − − ns tr/f5 rise/fall time for input clamping pulse; disable for vertical blanking tW(CLI) width of input clamping pulse tW(I2C)(valid) width of vertical blanking pulse for validation of buffered I2C-bus data leading and trailing edge threshold VCLI = 1.4 V; note 7 10 − − µs td(I2C)(valid) delay between leading edge of vertical blanking pulse and validation of buffered I2C-bus data I2C-bus buffered mode transmission completed; leading edge threshold VCLI = 1.4 V; note 7; see Fig.7 − − 2 µs 2001 Oct 19 13 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier SYMBOL PARAMETER TDA4887PS CONDITIONS MIN. TYP. MAX. UNIT tdead(I2C) I2C-bus receiver dead time after synchronizing vertical blanking pulse following a completed I2C-bus buffered mode transmission leading edge threshold VCLI = 1.4 V; note 7 15 − − µs tdl5 delay between leading edges of vertical blanking input pulse and signal blanking at signal outputs VHFB < 0.8 V; input pulse rising and falling edges = 50 ns/V; threshold for vertical blanking with rising edge VCLI = 1.4 V; threshold for vertical blanking with falling edge VCLI = 3 V; see Fig.7 − 270 − ns tdt5 delay between trailing edges of vertical blanking input pulse and signal blanking at signal outputs VHFB < 0.8 V; input pulse falling edge = 50 ns/V; threshold VCLI = 1.4 V; see Fig.7 − 115 − ns no blanking, no output clamping −0.1 − +0.8 V blanking, no output clamping 2 − 2.6 V blanking, output clamping 3.5 − VP V Output clamping and blanking input (HFB; pin 11) VHFB IHFB tW(HFB) output clamping and blanking input signal input current width of output clamping pulse note 9 VHFB = 0.8 V − −0.4 − µA pin 11 connected to ground; note 8 −80 −45 −30 µA VHFB = −0.1 V; note 8 −250 −135 −100 µA VHFB = 3 V 1 − − µs − 0.7 1.0 V no input clamping; Vi(n) = Vi(n)(clamp); Tamb = −20 to +70 °C 0.02 0.20 0.35 µA during input clamping; Vi(n) = Vi(n)(clamp) ±0.7 V ±350 ±420 ±500 µA control bit DISV = 1; f = 80 MHz 20 − − dB control bit DISV = 1; f = 120 MHz 10 − − dB Video signal inputs; channels 1, 2 and 3 (pins 6, 8 and 10) Vi(n)(b-w) input voltage; black-to-white value (pins 6, 8 and 10) Ii(n) DC input current (pins 6, 8 and 10) Signal blanking αct(blank) 2001 Oct 19 crosstalk suppression from input to output during blanking 14 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier SYMBOL PARAMETER TDA4887PS CONDITIONS MIN. TYP. MAX. UNIT Clipping of negative input signals (measured at signal outputs) ∆Vclipp Vi(n) = Vi(n)(clamp); sync amplitude = 0.3 V; note 10; see Fig.3 − 0.6 1.2 % colour signal related to maximum colour signal FFH (maximum) − 0 − dB 00H (minimum) − −45 − dB tracking of output colour signals of channels 1, 2 and 3 FFH to 40H; note 12 − 0 0.5 dB offset during sync clipping related to maximum colour signal Contrast control; see Fig.8 and note 11 δC ∆Gtrack Fast blanking (pin 1) and OSD signal insertion; channels 1, 2 and 3 (pins 2, 3 and 4); note 13 VFBL VOSDn fast blanking input signal (pin 1) OSD input signal (pins 2, 3 and 4) no video signal blanking; OSD signal insertion disabled 0 − 1.1 V video signal blanking; OSD signal insertion enabled 1.7 − VP V no internal OSD signal insertion 0 − 1.1 V internal OSD signal insertion 1.7 − VP V VFBL > 1.7 V tr(OSDn) rise time of OSD colour signals (pins 22, 19 and 16) 10 to 90% amplitude; pulse leading edge = 1.2 ns/V − 3 4 ns tf(OSDn) fall time of OSD colour signals (pins 22, 19 and 16) 90 to 10% amplitude; pulse falling edge = 1.2 ns/V − 4 7 ns tg(n)(CO) width of (negative going) OSD signal insertion glitch, leading edge (pins 22, 19 and 16) identical pulses at fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4) 0 4 6 ns tg(n)(OC) width of (negative going) OSD signal insertion glitch, trailing edge (pins 22, 19 and 16) identical pulses at fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4) 0 5 6 ns δVOSDn overshoot/undershoot of OSD colour signal related to actual OSD output pulse amplitude (pins 22, 19 and 16) pulse with 1.2 ns/V at OSD signal inputs (pins 2, 3 and 4) − 6 10 % VOSDn(max) maximum OSD colour signal maximum OSD contrast; related to maximum colour maximum gain signal (pins 22, 19 and 16) 90 96 110 % 2001 Oct 19 15 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier SYMBOL PARAMETER TDA4887PS CONDITIONS MIN. TYP. MAX. UNIT OSD contrast control; see Fig.9 and note 14 δOC OSD colour signal related to 0FH (maximum) maximum OSD colour signal 00H (minimum) − 0 − dB −14 −12 −10 dB Subcontrast adjustment, contrast modulation and beam current limiting (pin 24); see Fig.8 and note 15 VLIM(nom) nominal input voltage VLIM(start) starting voltage for linear contrast and OSD contrast reduction VLIM(stop) stop voltage for linear contrast and OSD contrast reduction BLIM ILIM(max) pin 24 open-circuit 4.7 5.0 5.3 V 4.2 4.4 4.8 V −40 dB below maximum colour signal (contrast setting FFH) 1.5 2.0 2.5 V bandwidth of contrast modulation −3 dB 4 − − MHz maximum input current VLIM = 0 V −1 − +1 µA Brightness control; see Figs 10, 12 and 14 and notes 16 and 17 ∆Vbl(n) ∆VDA(n) difference between video black level and reference black level at signal outputs related to maximum colour signal FFH (maximum); BRI = 0 28 33 38 % 40H (nominal); BRI = 0 −2 0 +2 % 00H (minimum); BRI = 0 −12 −10 −8 % DAC output voltage shift (pins 23, 20 and 17) FPOL = 1, see DAC output voltages for AC coupling or feedback reference voltage shift; FPOL = 0, see internal feedback reference voltage for DC coupling FFH (maximum); BRI = 1 − −1.4 − V 00H (minimum); BRI = 1 − 0 − V FFH (maximum) − 0 − dB 00H (minimum) −15 −13.5 −12.5 dB 03H (maximum) −12 −13.5 − % 02H −8 −9 − % 01H −4 −4.5 − % 00H (minimum) − 0 − % Gain control; see Fig.11 and note 18 δG video signal related to video signal at maximum gain Pedestal blanking; see Fig.5 and note 19 ∆Vbl(n)(PED-VID) 2001 Oct 19 difference between pedestal black level and video black level at nominal brightness, measured at signal outputs (pins 22, 19 and 16) related to maximum colour signal 16 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier SYMBOL PARAMETER TDA4887PS CONDITIONS MIN. TYP. MAX. UNIT Signal outputs; channels 1, 2 and 3 (pins 22; 19 and 16) Vo(n)(min) minimum output voltage level (pins 22, 19 and 16) 0.01 0.05 0.1 V Vo(n)(max) maximum output voltage level (pins 22, 19 and 16) VP(n) − 2 − VP(n) − 1 V Io(n)(source)(max) maximum output source current (pins 22, 19 and 16) −15 − − mA Ro(n) output resistance (pins 22, 19 and 16) 65 75 90 Ω Vo(n)(b-w)(max) maximum output voltage maximum contrast; swing (black-to-white value); maximum gain; channels 1, 2 and 3 Vi(n)(b-w) = 0.7 V; RL = 2 kΩ (pins 22, 19 and 16) 4.2 4.6 4.9 V Io(n)(source)(M) peak output source current (pins 22, 19 and 16) during fast positive signal transients −40 − − mA Io(n)(sink)(M) peak output sink current (pins 22, 19 and 16) during fast negative signal transients − − 20 mA S/N signal-to-noise ratio note 20 48 − − dB arbitrary input signals, contrast, brightness and gain adjustments; without load Frequency response at signal outputs; channels 1, 2 and 3 (pins 22, 19 and 16) tr(n) tf(n) 2001 Oct 19 rise time of fast transients (pins 22, 19 and 16) fall time of fast transients (pins 22, 19 and 16) input rise time = 1 ns; 10 to 90% amplitude; RL = 10 kΩ; notes 21, 22 and 23; 2.8 V (p-p) signal amplitude; CL = 5 pF − 2.7 3.8 ns 4.5 V (p-p) signal amplitude; CL = 5 pF − 3.2 4.2 ns 4.5 V (p-p) signal amplitude; CL = 11 pF − 3.8 4.5 ns 2.8 V (p-p) signal amplitude; CL = 5 pF − 3.6 4.5 ns 4.5 V (p-p) signal amplitude; CL = 5 pF − 3.6 4.5 ns 4.5 V (p-p) signal amplitude; CL = 11 pF − 5 6 ns input fall time = 1 ns; 90 to 10% amplitude; RL = 10 kΩ; notes 21, 22 and 23; 17 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier SYMBOL δVo(n) PARAMETER TDA4887PS CONDITIONS MIN. TYP. MAX. UNIT overshoot of output signal pulse related to actual output pulse amplitude (pins 22, 19 and 16) input rise time = 1 ns; maximum colour signal − − 10 % undershoot of output signal pulse related to actual output pulse amplitude (pins 22, 19 and 16) input fall time = 1 ns; maximum colour signal − − 10 % Crosstalk at signal outputs; channels 1, 2 and 3 (pins 22, 19 and 16) αct(tr)(n) transient crosstalk suppression (pins 22, 19 and 16) input rise/fall time = 1 ns; note 24 10 − − dB αct(f) crosstalk suppression by frequency f = 50 MHz; note 25 25 − − dB f = 100 MHz; note 25 10 − − dB internal reference voltage for FFH; FPOL = 0; BRI = 0 negative feedback polarity 00H; FPOL = 0; BRI = 0 (without brightness control) 3.7 3.95 4.1 V 5.6 5.75 5.9 V internal reference voltage for negative feedback polarity (with brightness control, see also brightness control ∆VDA(n)) FFH; FPOL = 0; BRI = 1; maximum brightness 2.3 2.55 2.7 V 00H; FPOL = 0; BRI = 1; minimum brightness 5.6 5.75 5.9 V Internal feedback reference voltage for DC coupling; see Fig.12 and note 26 Vref(DC) Output clamping, feedback inputs for DC coupling; FB/R1, FB/R2 and FB/R3 (pins 23, 20 and 17) IFB/Rn(max) maximum input current (pins 23, 20 and 17) during output clamping; −500 VHFB > 3.5 V; VFB/Rn = 0.5 V; FPOL = 0 −200 −60 nA Vbl(n)(ref)(min) minimum reference black level/minimum pedestal black level (pins 22, 19 and 16) VHFB > 3.5 V; FPOL = 0 0.01 0.1 0.5 V Vbl(n)(ref)(max) maximum reference black level/maximum pedestal black level (pins 22, 19 and 16) VHFB > 3.5 V; FPOL = 0 2.0 2.8 4.0 V ∆Vbl(CRT) black level variation at CRT FPOL = 0; note 27 − − 200 mV ∆Vbl(n)(lf) black level decrease between clamping pulses related to maximum colour signal (pins 22, 19 and 16) FPOL = 0; fline = 60 kHz; δ = 10% − 0.1 − % 2001 Oct 19 18 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier SYMBOL PARAMETER TDA4887PS CONDITIONS MIN. TYP. MAX. UNIT Output clamping; internal feedback (of signal outputs) reference voltage for AC coupling; see Fig.13 and note 28 Vbl(n)(ref) reference black level voltage/pedestal black level voltage (pins 22, 19 and 16) VHFB > 3.5 V; FPOL = 1 00H (minimum) 0.47 0.53 0.59 V 0FH (maximum) 1.83 1.89 1.95 V DAC output voltages for AC coupling; FB/R1, FB/R2 and FB/R3 (pins 23, 20 and 17); see Fig.14 and note 29 DAC output voltage (without brightness control) FFH; FPOL = 1; BRI = 0 3.7 3.95 4.1 V 00H; FPOL = 1; BRI = 0 5.6 5.75 5.9 V DAC output voltage (with brightness control, see also brightness control ∆VDA(n)) FFH; FPOL = 1; BRI = 1; maximum brightness 2.3 2.55 2.7 V 00H; FPOL = 1; BRI = 1; minimum brightness 5.6 5.75 5.9 V RFB/Rn output resistance FPOL = 1 − 100 − Ω IFB/Rn(sink)(max) maximum sink current FPOL = 1 − − 400 µA IFB/Rn(source)(max) maximum source current FPOL = 1 − −200 − µA VFB/Rn I2C-bus inputs; SDA (pin 12), SCL (pin 13); note 30 fSCL SCL clock frequency − − 100 kHz VIL LOW-level input voltage 0 − 1.5 V VIH HIGH-level input voltage 3 − 5 V IIL LOW-level input current VIL = 0 V −10 − − µA IIH HIGH-level input current VIH = 5 V −10 − − µA VOL LOW-level output voltage during acknowledge 0 − 0.4 V ISDA(ack) SDA output current (pin 12) during acknowledge VOL = 0.4 V 3 − − mA VOL = 0.6 V 6 − − mA to(f) output fall time VSDA = 3 to 1.5 V; bus capacitance CSDA = 400 pF − − 250 ns Vth(POR)(r) threshold for Power-on reset on rising supply voltage − 1.5 2.0 V falling supply voltage − 3.5 − V Vth(POR)(f) threshold for Power-on reset off rising supply voltage − − 7 V falling supply voltage − 1.5 − V 2001 Oct 19 19 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS Notes to the characteristics 1. Definition of levels (see Figs 3 to 5) Reference black level: this is the level to which the input level is clamped during the input clamping pulse (VCLI > 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs: a) When the input is at black and the brightness setting is nominal (subaddress 01H = 40H) or control bit BRI = 1 b) During output blanking and clamping (VHFB > 3.5 V) if the pedestal blanking depth is set to zero (subaddress 0BH = 00H). Video black level: this is the black level of the actual video. At the input it is still equal to the reference black level. At the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level unaltered . Gain setting biases the video black level due to its influence on brightness. This is important for correct grey scale tracking. It can be observed at the outputs when the input is at black outside output blanking and clamping pulses (VHFB < 0.8 V). Pedestal black level: this is an ultra black level which deviates from the reference black level by a bus controlled amount. It can be observed at the output during output blanking and clamping (VHFB > 3.5 V; subaddress 0BH ≠ 00H). Switch-off voltage: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the internal black level storage capacitors if the supply voltage is less than VP(SO). It can be observed at the outputs when the input is at black, the brightness setting is nominal and VP < 6.8 V (subaddress 01H = 40H). Blanking level: this level equals reference black (subaddress 0BH 1= 00H) or pedestal black. It can be observed at the outputs during output blanking and clamping (VHFB > 3.5 V). 2. Explanation to black level adjustment: The three reference black levels are aligned correctly when they are made equal to the ‘extended cut-off levels’ of the three cathodes. Full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying a negative pulse to the grid G1. Negative feedback for DC-coupled cathodes (control bit FPOL = 0): the actual blanking level on the outputs depends on the external feedback application for output clamping. The loop will function correctly only if it is within the control range of Vbl(n)(ref)(min) to Vbl(n)(ref)(max) at pins 22, 19 and 16. It should be noted that changing pedestal blanking in a given application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black levels). Positive feedback for AC-coupled cathodes (control bit FPOL = 1): the feedback loop for output clamping is closed internally. The actual blanking level is bus controlled between 0.53 and 1.89 V (subaddress 0AH). It should be noted that changing pedestal blanking will not affect the blanking level, but instead shifts the video (and re-alignment of the three black levels is needed). 3. Definition of output signals (see Fig.6): Colour signal: all positive voltages are referenced to black level at signal outputs. Maximum colour signal: colour signal with nominal input signal 0.7Vi(b-w), maximum contrast setting and maximum gain setting. Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the superimposing of the brightness information (∆Vbl) and the colour signal. 4. The total supply current IP(tot) = IP + IP1 + IP2 + IP3 depends on the supply voltage with a factor of approximately 4.4 mA/V and varies in the temperature range from −20 to +70 °C by approximately ±5% (VO(n) = 0.7 V). 5. The channel supply current IP1, IP2, IP3 depends on the signal output current IO1, IO2, IO3, the channel supply voltage VP1, VP2, VP3 and the signal output voltage VO1, VO2, VO3. With IPx = IP(n) at IO(n) = 0, VP(n) = 8 V and VO(n) = 0.7 V: I P(n) ≈ I Px + I O(n) + 4.4 mA/V × ( V P(n) – 8 V ) – 1 mA/V × ( V O(n) – 0.7 V ) 2001 Oct 19 20 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and pedestal blanking). With a fast clamping pulse (transition between VCLI = 1.2 to 3.5 V and 3.5 to 1.2 V in less than 75 ns/V) no blanking will occur during input clamping. For 75 ns/V < tr/f5 ≤ 280 ns/V the generation of the internal blanking pulse is uncertain. For tr/f5 > 280 ns/V the internal blanking pulse will be generated. If pin 5 is open-circuit, it will activate permanent input clamping and undefined blanking. 7. Pin 5 can be used to synchronize all adjustments via the I2C-bus (one by one). With a completed I2C-bus transmission in buffered mode, only the leading edge of a vertical blanking pulse activates an adjustment (see also Section 7.10). After the adjustment has been activated (validation of buffered I2C-bus data) the I2C-bus will be reset and further transmissions in direct or buffered mode are enabled. I2C-bus transmissions in direct mode need no synchronization pulses. 8. Input voltages less than −0.1 V can produce internal substrate currents which disturb the leakage currents at the signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or with negative voltage. Feeding clamping and blanking pulses via a resistor (several kΩ) protects the pin from negative voltages. 9. Pin 11 should be used for output clamping and/or blanking. If pin 11 is open-circuit, it will activate permanent blanking and output clamping. 10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below input reference black level (see Fig.3). 11. Contrast control acts on internal colour signals under I2C-bus control; subaddress 02H (bit resolution 0.4% of contrast range). A 1 A 20 12. ∆G track = 20 × maximum of log --------- × --------- A 10 A 2 A 1 A 30 log --------- × --------- A 10 A 3 A 2 A 30 log --------- × --------- dB A 20 A 3 An: colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting. An0: colour signal output amplitude in channel n = 1, 2 or 3 at maximum contrast setting and same gain setting. 13. When OSD fast blanking is active and OSD inputs OSD1, OSD2 and OSD3 are HIGH (VFBL > 1.7 V, VOSD(n) > 1.7 V) the OSD colour signals will be inserted in front of the gain potentiometers. This ensures a correct grey scale of all video signals. The amplitudes of the inserted OSD signals can be controlled simultaneously by OSD contrast via the I2C-bus. The inserted black level change (∆Vbl) due to brightness control is not affected by OSD fast blanking. 14. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution 6.7% of OSD contrast range). 15. This pin can be used for subcontrast adjustment, beam current limiting and contrast modulation. Both the video and OSD contrast are reduced simultaneously (see Figs 8 and 9). Because of the high-ohmic input impedance the pin should be tied to a voltage of more than 5 V or decoupled with a capacitor (several nF) if not used. 16. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution 0.4% of brightness range). When control bit BRI = 1 the internal gain dependent brightness control is switched off and the feedback reference voltages (control bit FPOL = 0) or DAC output voltages for DC restoration (control bit FPOL = 1) at the cathodes are shifted with brightness control. 17. The voltage difference between video black level and reference black level is related to the colour signal (see note 3) with nominal 0.7 V (p-p) input signal, at maximum contrast (subaddress 02H = FFH) and for any gain setting. This voltage difference (in Volts) is proportional to the gain setting (grey scale tracking). Therefore ∆Vbl (in percent) is constant for any gain setting. The given values of ∆Vbl are valid only for video black levels higher than the minimum output voltage level Vo(n)(min). 2001 Oct 19 21 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 18. Gain control acts on video signals and inserted OSD video signals under I2C-bus control; subaddress 04H (channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 0.4% of gain range respectively). 19. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative signal at the signal output pins. The pedestal depth can be selected by bus control, subaddress 0BH. The reference black level which should correspond to the ‘extended cut-off voltage’ at the cathodes is approximately ∆Vbl(n)(PED-VID) higher (see Fig.5). The use of pedestal blanking with AC-coupled cathodes (control bit FPOL = 1) allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit. 20. The signal-to-noise ratio is calculated using the formula (range 1 to 120 MHz): peak-to-peak value of the maximum signal output voltage S ---- = 20 × log -------------------------------------------------------------------------------------------------------------------------------------------------------- dB RMS value of the noise output voltage N 21. The following formula can be used to approximately determine the output rise/fall time for any input rise/fall time other 2 2 2 2 than 1 ns: t r/f, measured = t r/f (22,19,16) + ( t r/f, input – [ 1 ns ] ) 22. The relationship between pixel rate and signal bandwidth is f−3dB = 0.75 × fpixel, which is a compromise between excellent and acceptable video performance. The calculation of the pixel-related rise and fall times can be done using 0.35 0.35 the formula t r/f = ------------ = ----------------------------- . Although this formula is valid for low-pass filters of first order only it is used 0.75 × f pixel f –3dB 0.35 in most cases for simplified estimations. The pixel rate f pixel = --------------------- is a good approximation for many filter types. 0.75 × t r 23. Rise and fall times depend on signal amplitude, temperature, external load, black level and supply voltage. The rise time is affected if the top level of the signal pulse approaches the maximum output voltage level (high black level, large signal amplitude or low supply voltage). The fall time depends on the black level (increase with decreasing black level) and on large capacitive loads. Low-ohmic pull-down loads at the outputs helps towards smaller fall times. Rise and fall times increase with increasing ambient (or crystal) temperature. At maximum operating temperature, rise and fall times are approximately 0.4 ns longer than at Tamb = 25 °C. 24. Transient crosstalk between any two output pins: a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other two channels (channels B) are capacitively coupled to ground. Gain setting at maximum (FFH). Contrast setting at maximum (FFH). No limiting/modulation of contrast (VLIM ≥ 4.8 V) b) Output conditions: black level set to approximately 0.7 V for each channel at signal outputs. Output signals are VA and VB respectively VA c) Transient crosstalk suppression: α ct(tr) = 20 × log ------- dB VB 25. Crosstalk by frequency between any two output pins: a) Input conditions: any channel (channel A) with 0.2 V (p-p) sinusoidal input signal, DC-coupled to approximately 4.3 V, no input clamping. The inputs of the other two channels (channels B) are capacitively coupled to ground. Gain setting at maximum (FFH). Contrast setting at maximum (FFH). No limiting/modulation of contrast (VLIM ≥ 4.8 V) b) Output conditions: control bit FPOL = 1, subaddress 0AH set to 01H, no pedestal blanking, nominal brightness setting. Output signals are VA and VB respectively VA c) Crosstalk suppression: α ct(f) = 20 × log ------- dB VB 2001 Oct 19 22 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 26. Control bit FPOL = 0: the internal feedback reference voltages for DC control act under I2C-bus control; subaddress 07H (channel 1), 08H (channel 2) and 09H (channel 3); bit resolution 0.4% of voltage range. Rising values of the data bytes, e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs (pins 22, 19 and 16). The internal feedback reference voltages can be measured at feedback inputs (pins 23, 20 and 17) during output clamping (VHFB > 3.5 V) in closed feedback loop. The feedback loop remains operative at reference black levels between the specified values of Vo(n)bl(ref)(min) and Vo(n)bl(ref)(max). Control bit BRI = 1: the internal feedback reference voltages can be shifted under I2C-bus control which allows easy brightness control without grey scale tracking (see Section 7.2.2.2); subaddress 01H (bit resolution 0.4% of voltage shift range). The superimposition of internal feedback reference and brightness control leads to a voltage output range of 5.8 to 2.5 V. 27. Slow variations of video supply voltage VCRT will be suppressed at the CRT cathode by the clamping feedback loop. A change of VCRT with 5 V leads to a specified change of the cathode voltage. 28. To adapt to different types of post amplifier, the internal feedback reference voltage for AC coupling (control bit FPOL = 1) acts under I2C-bus control; subaddress 0AH (bit resolution 14.29%). The internal feedback reference voltage can be measured at signal outputs (pins 22, 19 and 16) during output clamping (VHFB > 3.5 V); reference black level or pedestal black level. 29. The DAC output voltages act under I2C-bus control for control bit FPOL = 1; subaddress 07H (FB/R1), 08H (FB/R2) and 09H (FB/R3); bit resolution 0.4% of voltage range respectively. Using an inverting amplifier for DC restoration, rising values of the data bytes, e.g. 00H to FFH, correspond to changing the light output from dark to bright. With control bit BRI = 1 the DAC output voltages can be shifted under I2C-bus control which allows easy brightness control without grey scale tracking (see Section 7.2.2.2); subaddress 01H (bit resolution 0.4% of voltage shift range). The superimposition of black level control and brightness control leads to a voltage output range of 5.8 to 2.5 V. 30. All adjustments via the I2C-bus can be synchronized with vertical blanking pulse at pin CLI. This is called I2C-bus transmission in buffered mode. Conversely the adjustments via the I2C-bus will take effect immediately in direct mode. The timing of I2C-bus transmissions in buffered mode is related to the vertical blanking. See Section 7.6 and note 7 for specification of vertical blanking input (pin 5). 2001 Oct 19 23 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS handbook, full pagewidth input video signal with sync pulses at pins 6, 8 and 10 input reference black level the sync pulses are clipped to reference black level internally input clamping pulses at pin 5 output clamping and blanking input pulses at pin 11 MHA344 The input video signals have to be at black level during input clamping. Fig.3 Definition of input signals. 2001 Oct 19 24 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS handbook, full pagewidth output clamping and blanking input pulses at pin 11 signal outputs at pins 22, 19 and 16 (1) maximum gain setting, maximum contrast setting, maximum/nominal/minimum brightness setting (2) (3) video black levels at maximum brightness nominal brightness minimum brightness reference black level switch-off voltage ground (1) maximum gain setting, maximum brightness setting, maximum/minimum contrast setting (3) video black level (maximum brightness) reference black level switch-off voltage ground maximum brightness setting, maximum contrast setting, maximum/minimum gain setting (1) (3) video black levels (maximum brightness) reference black level switch-off voltage ground MHB920 (1) Maximum. (2) Nominal. (3) Minimum. Fig.4 Definition of levels and functions of brightness, contrast and gain with no pedestal blanking. 2001 Oct 19 25 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS handbook, full pagewidth output clamping and blanking input pulses at pin 11 signal outputs at pins 22, 19 and 16 no pedestal blanking maximum gain setting, maximum contrast setting, maximum/minimum brightness setting (1) (2) video black levels at maximum brightness minimum brightness reference black level switch-off voltage ground pedestal blanking maximum gain setting, maximum contrast setting, maximum/minimum brightness setting (1) (2) video black levels at maximum brightness minimum brightness reference black level pedestal black level switch-off voltage ground MHB921 (1) Maximum. (2) Minimum. Fig.5 Output signals with and without pedestal blanking. 2001 Oct 19 26 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier handbook, full pagewidth TDA4887PS video signals colour signals (1) (2) reference black level video black levels at maximum brightness minimum brightness MHB922 (1) Maximum brightness setting. (2) Minimum brightness setting. Fig.6 Definition of output signals at pins 22, 19 and 16: maximum gain setting, maximum contrast setting and no pedestal blanking. handbook, full pagewidth 3V t r/f5 ≤ 75 ns/V input pulses at pin 5 1.4 V internal pulse for input clamping vertical blanking pulses at signal outputs (brightness blanking at maximum brightness setting) t dl5 t dl5 t dl5 reference black level MHB944 Fig.7 Timing of pulses at pin 5 and derived pulses at maximum brightness setting. 2001 Oct 19 video black level 27 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier handbook, full pagewidth TDA4887PS MHB945 0 colour signal amplitude with respect to maximum colour signal amplitude −3 (dB) (1) contrast modulation range −6 (2) − 12 (3) − 45 00H 20H 40H 80H 60H A0H C0H E0H FFH contrast control data byte (1) No contrast reduction. (2) Partial contrast reduction by subcontrast, limiting or contrast modulation. (3) Full contrast reduction by subcontrast, limiting or contrast modulation. Fig.8 Contrast control characteristic with subcontrast, limiting or contrast modulation. MHB946 handbook, full pagewidth maximum OSD signal amplitude 96 OSD signal amplitude with respect to maximum colour signal amplitude (%) maximum colour signal amplitude (1) (2) 24 (3) 00H 0FH OSD contrast control data byte (1) No OSD contrast reduction. (2) Partial OSD contrast reduction by subcontrast, limiting or contrast modulation. (3) Full OSD contrast reduction by subcontrast, limiting or contrast modulation. Fig.9 OSD contrast control characteristic with subcontrast, limiting or contrast modulation. 2001 Oct 19 28 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier handbook, full pagewidth TDA4887PS MHB947 33 difference of video black level and reference black level with respect to maximum colour signal amplitude (%) (1) 0 (2) −10 00H 20H 40H 80H 60H A0H C0H E0H FFH brightness control data byte (1) Nominal adjustment. (2) Nominal brightness reference black level. Fig.10 Brightness control characteristic; control bit BRI = 0. handbook, full pagewidth MHB948 100 video signal gain with respect to maximum video signal gain (%) 20 00H 20H 40H 80H 60H A0H Fig.11 Gain control characteristic. 2001 Oct 19 29 E0H FFH C0H gain control data byte Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS MHB949 handbook, full pagewidth 5.75 internal feedback reference voltage (V) 4.35 3.95 (1) brightness control; 8-bit DAC subaddress 01H (2) 2.55 0 00H 20H 40H 80H 60H A0H C0H E0H FFH negative feedback reference data byte (1) Control bit BRI = 0 or control bit BRI = 1 and minimum brightness setting (subaddress 01H at 00H). (2) Control bit BRI = 1 and maximum brightness setting (subaddress 01H at FFH). Fig.12 Internal feedback reference voltages for negative feedback (FPOL = 0). handbook, full pagewidth 1.89 internal feedback reference voltage 1.70 (V) 1.50 1.31 1.11 0.92 0.72 0.53 0 01H 02H 03H 04H 05H 06H 07H positive feedback reference data byte MHB950 Fig.13 Internal feedback reference voltages for positive feedback (FPOL = 1). 2001 Oct 19 30 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS MHB951 handbook, full pagewidth 5.75 DAC output voltage pins 23, 20, 17 (V) 4.35 (1) 3.95 brightness control; 8-bit DAC subaddress 01H (2) 2.55 0 00H 20H 40H 80H 60H A0H C0H E0H feedback reference data byte; subaddresses 07H, 08H and 09H (1) Control bit BRI = 0 or control bit BRI = 1 and minimum brightness setting (subaddress 01H at 00H). (2) Control bit BRI = 1 and maximum brightness setting (subaddress 01H at FFH). Fig.14 DAC output voltages (control bit FPOL = 1). 2001 Oct 19 31 FFH Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 11 I2C-BUS PROTOCOL Table 1 Slave address A6(1) A5(1) A4(1) A3(1) A2(1) A1(1) A0(1) W(2) 1 0 0 0 1 0 0 0 Notes 1. Address bit. 2. Write bit. Table 2 Slave receiver format S(1) SLAVE ADDRESS A(2) SUBADDRESS(3) A DATA BYTE(4) A P(5) Notes 1. START condition. 2. A = acknowledge. After an intermediate power dip all registers are set to their initial values (see note 3 at Table 4) and an internal power-on reset bit will be set with the consequence that the device will give no acknowledge on the data byte after a first addressing. The power-on reset bit will be reset if the control register is addressed. It is recommended to then refresh all registers by using the auto-increment function. 3. All subaddresses within the range 00H to 0BH are automatically incremented. The subaddress counter wraps around from 0BH to 00H. For subaddresses within the range 80H to 8FH no auto-increment takes place. Subaddresses outside the ranges 00H to 0BH and 80H to 8BH are acknowledged by the device but no auto-increment or any other internal operation takes place. 4. Single data byte in case of no auto-increment of subaddresses. More than one data byte with auto-increment of subaddresses. 5. STOP condition. 2001 Oct 19 32 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier Table 3 TDA4887PS Subaddress byte format SUBADDRESS(1) FUNCTION DIRECT MODE SUBADDRESS BYTE BUFFERED S7(2) S6(2) S5(2) S4(2) S3(2) S2(2) S1(2) S0(2) MODE Control register 00H 80H B(3) 0 0 0 0 0 0 0 Brightness control 01H 81H B(3) 0 0 0 0 0 0 1 82H B(3) 0 0 0 0 0 1 0 Contrast control 02H OSD contrast control 03H 83H B(3) 0 0 0 0 0 1 1 Gain control channel 1 04H 84H B(3) 0 0 0 0 1 0 0 85H B(3) 0 0 0 0 1 0 1 86H B(3) 0 0 0 0 1 1 0 Gain control channel 2 Gain control channel 3 05H 06H Black level reference channel 1 07H 87H B(3) 0 0 0 0 1 1 1 Black level reference channel 2 08H 88H B(3) 0 0 0 1 0 0 0 89H B(3) 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 Black level reference channel 3 09H Black level for AC coupling 0AH 8AH B(3) Depth of pedestal blanking 0BH 8BH B(3) 0CH to 0FH 8CH to 8FH not used Notes 1. The most significant bit (MSB) of the subaddress enables an I2C-bus transmission in direct or in buffered mode (see note 3). Subaddresses outside the ranges 00H to 0FH and 80H to 8FH are not used. 2. Subaddress bit. 3. Most significant bit of subaddress byte. I2C-bus transmission in direct mode: B = 0. I2C-bus transmission in buffered mode: B = 1. 2001 Oct 19 33 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier Table 4 TDA4887PS Subaddress and data byte format SUBADDRESS(1) FUNCTION DATA BYTE(2) DIRECT BUFFERED D7(4) D6(4) D5(4) MODE MODE D4(4) D3(4) D2(4) D1(4) D0(4) NOMINAL VALUE(3) X(5) 08H Control register 00H 80H X(5) BRI X(5) X(5) Brightness control 01H 81H A17 A16 A15 A14 A13 A12 A11 A10 40H Contrast control 02H 82H A27 A26 A25 A24 A23 A22 A21 A20 FFH X(5) X(5) X(5) A33 A32 A31 A30 0FH FPOL DISV DISO OSD contrast control 03H 83H X(5) Gain control channel 1 04H 84H A47 A46 A45 A44 A43 A42 A41 A40 FFH Gain control channel 2 05H 85H A57 A56 A55 A54 A53 A52 A51 A50 FFH Gain control channel 3 06H 86H A67 A66 A65 A64 A63 A62 A61 A60 FFH Black level reference channel 1 07H 87H A77 A76 A75 A74 A73 A72 A71 A70 − Black level reference channel 2 08H 88H A87 A86 A85 A84 A83 A82 A81 A80 − Black level reference channel 3 09H 89H A97 A96 A95 A94 A93 A92 A91 A90 − Black level for AC coupling 0AH 8AH X(5) X(5) X(5) X(5) X(5) AA2 AA1 AA0 − Depth of pedestal blanking 0BH 8BH X(5) X(5) X(5) X(5) X(5) X(5) AB1 AB0 00 Notes 1. See Table 3 (Subaddress byte format). 2. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0). 3. Under certain conditions the nominal values lead to nominal colour signals, etc. (see notes 1 and 3 of Chapter “Characteristics” and Figs 4 to 6). After power-up and after internal Power-on reset of the I2C-bus the registers are set to the following values: a) Control bit FPOL to logic 1. b) Control bits DISV, DISO and BRI to logic 0. c) All other alignment registers to logic 0 (minimum value for control registers). 4. Data bit. 5. X means don’t care but the bits are preferably set to logic 0 for software compatibility with other video ICs that have the same slave address. 2001 Oct 19 34 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier Table 5 TDA4887PS Control register BIT FUNCTION DISO = 0 OSD signals enabled DISO = 1 OSD signals disabled DISV = 0 video signals enabled DISV = 1 video signals disabled FPOL = 0 negative feedback polarity; pins 23, 20 and 17 as feedback inputs; no external DAC voltage outputs FPOL = 1 positive feedback polarity; pins 23, 20 and 17 as external DAC voltage outputs; internal feedback of signal outputs BRI = 0 internal brightness control with grey scale tracking BRI = 1 Brightness control without grey scale tracking. With FPOL = 0 the brightness information is combined with the internal feedback reference voltages. With FPOL = 1 the brightness information is combined with the DAC output voltages for DC restoration at the cathodes. 2001 Oct 19 35 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier handbook, full pagewidth TDA4887PS START LOAD PRESET CONTROL BITS FPOL, BRI DISV = 1 DISO = 1 load from program ROM code or EEPROM LOAD FACTORY SETTINGS GAIN (CHANNEL 1, 2, 3) BLACK LEVEL REFERENCES (CHANNEL 1, 2, 3) OR EXTERNAL DAC VOLTAGES AC BLACK LEVEL PEDESTAL DEPTH load from EEPROM LOAD USER PRESET VALUES load from EEPROM CONTRAST BRIGHTNESS OSD CONTRAST DEFLECTION CONTROL IC LOCKED no yes DISV = 0 DISO = 0 DISPLAY NEW MODE(1) DISO = 1 USER INPUT no yes DISO = 0 RESPONSE TO USER INPUTS(2) (CONTRAST, BRIGHTNESS, OSD CONTRAST) DISO = 1 DEFLECTION CONTROL IC LOCKED (1) Only synchronized video should be displayed. Each new mode can be displayed by OSD. (2) Data transmission should be synchronized with vertical blanking of the monitor. no DISV = 1 yes Fig.15 I2C-bus control flow chart. 2001 Oct 19 36 MHB932 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 12 TEST AND APPLICATION INFORMATION contrast modulation input handbook, full pagewidth limiting input subcontrast setting fast blanking OSD inputs signal inputs 1 24 2 23 3 22 Application with integrated post amplifier, DC-coupled cathode and negative feedback. to cathode 90 V 4 21 5 20 BLACK LEVEL RESTORATION channel 1 19 6 TDA4887PS 7 18 8 17 9 16 10 15 11 14 12 13 70 V to cathode Application with integrated post amplifier, AC-coupled cathode and black level restoration cicuit. channel 2 90 V channel 3 Application with discrete post amplifier, DC-coupled cathode and negative feedback. to cathode 8V pull-up resistors 5V MHB933 I2C-BUS output clamping blanking input clamping vertical blanking Fig.16 Basic applications for different kinds of post amplifiers with DC or AC coupling. 12.1 Test board shows the test circuit and Figs 18 and 19 show the layout and mounting of the double-sided printed-circuit board. Most components are SMD-type. Short HF loops and minimum crosstalk between channels and between signal inputs and outputs are achieved by using properly shaped ground areas. For high frequency measurements, a special test board with only a few external components can be built. It utilizes the internal positive feedback of the output signals during output clamping with control bit FPOL = 1. Figure 17 2001 Oct 19 37 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 1 kΩ handbook, full pagewidth 5.6 Ω FBL FBL 50 Ω OSD1 OSD1 50 Ω 1 24 2 23 LIM FB/R1 FB/R1 solder pin channel 1 OSD2 OSD2 50 Ω 50 Ω VO1 4 21 50 Ω 5 20 100 nF 0.47 µF (63 V) FB/R2 solder pin channel 2 VI1 VI1 6 5 kΩ 19 VO2 VO2 3.3 pF TDA4887PS VP J1 0.47 µF (63 V) 10 nF 100 nF 7 18 100 pF VI2 8 17 100 nF 0.47 µF (63 V) FB/R3 FB/R3 solder pin 5 kΩ channel 3 GND J2 9 16 VO3 VO3 3.3 pF 10 nF VI3 VI3 50 Ω 150 pF 10 kΩ 5.6 Ω VP2 150 pF VI2 50 Ω 150 pF 10 kΩ FB/R2 10 nF 50 Ω 150 pF 3.3 pF 5.6 Ω VP1 150 pF CLI CLI 22 1 kΩ OSD3 OSD3 3 VO1 10 15 5.6 Ω VP3 150 pF 5 kΩ HFB J3 11 14 12 13 10 kΩ 100 nF 0.47 µF (63 V) GNDX HFB 50 Ω 150 pF SDA 10 nF SCL 10 nF VPX LIMAC VP1 sense 50 Ω 10 kΩ VP sense 10 kΩ 10 nF SDA 5V VP GND 10 kΩ VINDC SCL LIM 5V MHB934 Fig.17 Test board utilizing internal positive feedback only (FPOL = 1). 2001 Oct 19 38 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 103 handbook, full pagewidth 81 CLI OSD3 OSD2 OSD1 5.6 Ω FBL 1 kΩ 50 Ω 50 Ω 50 Ω 50 Ω 10 nF 10 nF 100 nF 150 pF 5 kΩ 150 pF 5 kΩ + 100 nF 150 pF 10 kΩ TDA4887PS − 150 pF J3 100 nF 50 Ω 10 nF 10 kΩ VO3 3.3 pF 5 kΩ 150 pF 1 kΩ U19 5.6 Ω VO2 0.47 µF 50 Ω 50 Ω − + 0.47 µF 150 pF 10 kΩ 3.3 pF 10 nF HFB VO1 J1 J2 VI2 50 Ω VI3 50 Ω 3.3 pF 50 Ω VI1 10 kΩ − 0.47 µF + − + 5.6 Ω 0.47 µF 5.6 Ω 10 kΩ 10 kΩ 10 nF SDA SCL LIMAC MHB935 Dimensions are in mm. Fig.18 Printed-circuit top view shown with and without components mounted (for bottom view, see Fig.19). 2001 Oct 19 39 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier handbook, full pagewidth TDA4887PS 103 81 100 pF 100 nF 100 nF 100 pF MHB217 Dimensions are in mm. Fig.19 Printed-circuit bottom view shown with and without components mounted (for top view, see Fig.18). 2001 Oct 19 40 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 12.2 80 V supply and use of I2C-bus controlled external brightness setting. The 8 V supply voltage of the preamplifier is made from 12 V on this board. Connectors for video, sync, I2C-bus, OSD, clamping pulses, beam current limiting and supply voltages are provided. Application board with monolithic post amplifier Figure 20 shows the application circuit of TDA4887PS with a modern monolithic video post amplifier and AC-coupled CRT. The black level restoration circuit is designed for 2001 Oct 19 TDA4887PS 41 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS Vg2 handbook, full pagewidth BEAM CUR LIM V2 80 V V1 12 V CLAMPING BLANKING Vff Vff GND Vg1 GROUND HOR SYNC VERT SYNC AQUADAG A 1 L1 10 µH 2 3 1Ω R16/H D E R3 5.6 Ω 6 8 F 9 7808 C2 330 nF 10 G 100 Ω R4 R14 2.2 Ω 1 kΩ 4 GND SCL 1 24 2 23 H R106 3 2 22 I 10 Ω R104 1 R6 1 kΩ R302 1 kΩ R202 1 kΩ 4 21 5 20 C102 100 nF R102 1 kΩ R9 100 Ω I 2C-BUS C9 22 nF 3 8V +5 V 8V R12 1 kΩ SDA C6 100 µF 12 14 FBL C3 100 nF 11 n.c. CH 3 2.7 kΩ R2 1Ω 7 R5 OSD 1.5 nF 2.7 kΩ R15/H 5 13 CH 2 B C12 C 4 n.c. CH 1 L2 10 µH R1 J R206 4 6 3 19 TDA4887PS D1 5.1 V 2 5.6 Ω C1 100 nF R7 R8 10 kΩ 10 kΩ R204 7 18 8 17 C202 100 nF C7 22 nF 1 K 10 Ω 5.6 Ω L R306 9 16 M 10 Ω R304 10 15 11 14 12 13 C302 100 nF VERT SYNC R10 HOR SYNC 100 Ω 5.6 Ω R11 100 Ω C101 R103 R101 75 Ω 22 nF 33 Ω C201 R203 R201 75 Ω 22 nF 33 Ω C301 R303 R301 75 Ω 22 nF 33 Ω CH 1 VIDEO INPUT CH 2 CH 3 MHB966 Fig.20 Application board with LM2435 (drawing is continued in Fig. 20). 2001 Oct 19 42 N Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS handbook, full pagewidth A B C EHT D E C5 1 nF (2 kV) C11 1 nF (2 kV) 6 8 11 C10 1.5 nF F R318/H 68 Ω R218/H 68 Ω R118/H 68 Ω 10 9 5 7 1 R13 G 4.7 Ω C8 C15 100 nF D109 BAV103 R107 L108 22 Ω 0.22 µH R207 L208 22 Ω 0.22 µH R307 L308 22 Ω 0.22 µH D110 BAV103 C106 R119 1 µF (63 V) 1 MΩ 47 µF H C4 1 47 µF 2 C14 D209 BAV103 D210 BAV103 3 I C206 R219 1 µF (63 V) 1 MΩ 4 2 × 100 nF 5 LM2435 6 J D309 BAV103 D310 BAV103 7 C306 R319 1 µF (63 V) 1 MΩ 8 K D303 BAW62 9 R317 10 kΩ 8V L R305 M TR301 10 Ω R316 68 kΩ 2× BC546 R315 150 kΩ C305 1 µF (100 V) TR302 C304 2.2 nF R313 270 Ω R314 12 kΩ D203 BAW62 N R217 10 kΩ 8V R205 TR201 10 Ω R216 68 kΩ 2× BC546 R215 150 kΩ C205 1 µF (100 V) TR202 C204 2.2 nF R213 270 Ω R214 12 kΩ D103 BAW62 R117 10 kΩ 8V R105 TR101 10 Ω C104 2.2 nF R116 68 kΩ 2× BC546 R115 150 kΩ C105 1 µF (100 V) TR102 R113 270 Ω R114 12 kΩ MHB967 Fig.21 Application board with LM2435 (drawing continued from Fig. 20). 2001 Oct 19 43 Vfoc Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 12.3 12.4.1.2 Building the application board 12.3.1 • Double-sided board • Short HF loops by large ground plane on the rear • SMD components with minimum parasitics. VOLTAGE OUTPUTS • Capacitive loads as small as possible • Be aware of internal output resistance (typically 75 Ω). 12.3.3 12.4.1.3 SUPPLY VOLTAGES • Use electrolytic capacitors with small serial resistance and inductance. For a better understanding, discrete values for luminance, video and feedback gain have been taken (these values should be regarded as examples). For special applications actual values have to be taken instead. FLASHOVER High electric field strength is present between the gun electrodes of picture tubes. In case of a flashover large transient currents and voltages may damage electronic components. It is therefore important to provide protective circuits with spark gaps, series resistors and protection diodes. Be aware that not only electronic components that are directly connected to the tube socket are endangered if interconnection lines on the application board are unfavourably routed. 12.4 White point must be aligned at maximum luminance (e.g. at 102.8 cd/m2) with maximum contrast and nominal brightness. It is recommended to use only a small white square for white point alignment, to prevent variations of the voltage at grid G1 (Vg1) and grid G2 (Vg2) and to prevent unwanted activation of the automatic beam limiter (ABL). For practical reasons, alignment of the R, G, B reference black levels must be done with a small amount of drive for obtaining a luminance level of approximately 2.4 cd/m2. This drive can be simulated by setting the brightness to a certain value. Assuming 102.8 cd/m2 luminance with full white video (100% drive) and a cathode characteristic with gamma = 2.25, the drive for black level adjustment can be shown as: Application hints 12.4.1 ALIGNMENT RECOMMENDATIONS USING BRIGHTNESS CONTROL WITH GREY SCALE TRACKING 12.4.1.1 Introduction (philosophy of TDA4887PS) With the TDA4887PS the user may change contrast, brightness and even colour temperature (R, G, B gains) or any combination at will. The ‘x,y’ colour point will remain stable for the full grey scale. This feature is achieved in the following way: 2.4 -------------------------- × 100 = 18.8% drive 1/2.25 102.8 which corresponds to a brightness setting of B8H. A change of brightness will cause a change of black level which is proportional to the actual gain setting After black level adjustment for L = 2.4 cd/m2, the cathode voltages are fixed and the cut-off voltages are set with equal gain condition in all channels. During white point adjustment the gains will be changed. In the factory procedure for single pass adjustment, the luminance level for black level alignment (2.4 cd/m2) is kept constant while adjusting the gain settings. To achieve this, the black level references are compensated by software and an alignment computer (this compensation is for factory alignment only and is not needed for any user change of R, G, B gain). Conversely, a change of gain setting will cause a change of black level that is proportional to the deviation of brightness from its nominal setting. To benefit fully from this colour tracking feature, the reference black levels of the video amplifiers must match exactly to the cut-off points of the cathodes. Re-adjustments of black level settings by the end user should be avoided, because this will upset the tracking feature. 2001 Oct 19 Considerations for a single-pass factory alignment The nominal brightness setting is 40H. In this condition the black level equals reference black level and must match to the CRT cut-off. • Capacitors as near as possible to the pins 12.3.4 Difficulty during monitor production The factory cut-off alignment is done at a quite high level (e.g. 2.4 cd/m2). As a consequence it is not certain that the reference black level will match the cut-off exactly after a first black level adjustment. If then the R, G, B gains are adjusted for the (x, y) white point at e.g. 102.8 cd/m2, the white balance at 2.4 cd/m2 will have changed. So two or more alignment cycles may be needed to achieve good results. GENERAL 12.3.2 TDA4887PS 44 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier Calculation of compensation (see Fig.22): TDA4887PS 3. The black level adjustment range (at feedback inputs) is 1.9 V in 255 steps, which is 7.45 mV per step (∆ black level of 97 mV at the cathode with feedback gain = 1⁄13). It follows that the optimum compensation 1. Gain adjustment is in 255 steps from 20 to 100% which equates to 4.6 V per step at maximum contrast. 0.8 × 4.6 V One step = ---------------------------- = 14.4 mV which is equal to 255 187 mV at the cathode with video gain = 13 for the white area. 97 is one step black level for ------ = 2.8 or approximately 35 three steps of gain. 2. For 18.8% drive (used for black level adjustment) the output changes only 2.7 mV (35 mV at the cathode) per gain step. handbook, full pagewidth FIXED MAXIMUM GAIN 4.6/0.7 V 0.7 V (nom.) CONTRAST −40 dB (0.5/100%) 255 steps BRIGHTNESS −10/30% of 4.6 V 255 steps 3 × GAIN 20/100% 255 steps 3 × BLACK REFERENCES range 1.9 V 255 steps PREAMPLIFIER 4.6 V (max.) 5.75 to 3.95 V VIDEO GAIN ≈ 13 FEEDBACK GAIN ≈ 1/13 signal amplitude 60 V (max.) CRT ≈ 25 V cut-off level variation MHB953 Fig.22 Signal amplification and feedback references. 12.4.1.4 Example of automatic factory alignment 2. Vg2 and black levels This procedure shows a realization of the alignment description, it depends on disposable equipment. a) Set brightness to 18.8% drive (B8H, subaddress 01H, control bit BRI=0) Gamma = 2.25, maximum luminance = 102.8 cd/m2, video gain = 13, feedback gain = 1⁄13, white D; see Fig.23. b) Apply black video 1. Initialization d) Activate the alignment computer c) Increase Vg2 manually until one colour appears e) The computer will continuously adjust the R, G, B black levels to meet the following three conditions: x = 0.131 y = 0.329 the centre of the min/max setting remains at 80H (this will leave some margin for the compensation steps that follow) a) Set grid 2 voltage to minimum b) Set R, G, B gains to the centre values (80H, subaddresses 04H, 05H, 06H) c) Set R, G, B black references to centre values (80H, subaddresses 07H, 08H, 09H) d) Set contrast to maximum (FFH, subaddress 02H). f) Fine tuning of Vg2 (or Vg1) until Y = 2.4 cd/m2 with the computer still active. 2001 Oct 19 45 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier The effect on cathode voltages is demonstrated in Fig.23. After step 2 the voltages at 18.8% drive are correct but not those at 100% drive (white) and 0% (black). After step 3 the voltages at 18.8% drive have not changed but white as well as black voltages are correct now. Any brightness setting (−10 to +30%) relates to the individual maximum video amplitude (black-to-white). 3. R, G, B gains (white point) a) Set brightness at nominal (40H) b) Apply full video white area (700 mV) c) Activate the computer d) The computer will adjust the R, G, B gains to meet the following three conditions: x = 0.313 y = 0.329 Y = 102.8 cd/m2 For each 3 (2.8) gain increments, the computer will decrement the black references by one step. handbook, full pagewidth TDA4887PS This alignment procedure is adaptable to DC-coupled as well as AC-coupled cathodes. 80 cathode voltage (V) 70 cut-off voltage range from black level references (13 × 5.75 to 13 × 3.95) black 60 18.8% 50 40 30 20 10 white step 1: Black level references and gain set to 80H. step 2: Black level references adjusted with 18.8% drive and gain set to 80H. 0 MHB954 Fig.23 Automatic factory alignment. 2001 Oct 19 step 3: Gain adjustment at 100% white with automatic black level reference correction. Cathode voltages for 18.8% drive left unchanged. 46 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 12.4.2 BLACK LEVEL RESTORATION The upper circuit has much less temperature dependence on clamp voltage and, in the event of an I2C-bus Power-on reset in TDA4887PS, all clamp voltages go to black. Figure 24 shows two simple circuits for black level restoration for applications with AC-coupled cathodes. The output signal of the post amplifier is coupled via a 1 µF capacitor and a 68 Ω resistor to the cathode. The cathode voltage is clamped (peak responding) to the DC voltage Vcl = Vb + VBE via diode D1. The voltage Vb is derived from the bus controlled reference voltage Vref (pin FB/R(n) of TDA4887PS) by resistor network R1 to R2. For correct clamping, a well-defined top level of Vsig is necessary (pedestal black level has to be the most positive voltage). When using internal brightness control, pedestal blanking (subaddress 0BH) has to be larger than minimum possible brightness setting (10% of maximum signal swing if the complete range is used). With 40 V maximum signal swing and 15% pedestal blanking, the clamping voltage Vcl has to be 6 V higher than the extended cut-off voltage. R1 + R2 V b = V a × --------------------- for the upper circuit. R1 R2 V b = V p1 – ( V a1 – V be ) × ------- for the lower circuit. R1 handbook, full pagewidth TDA4887PS Without using internal brightness control, at least 5% pedestal blanking is recommended. Vp1 90 V BAV21 VIDEO BOOSTER amplification ≈ 13 1 MΩ cathode BAW62 Vb R2 150 kΩ 2× BC546 amplification ≈ 13.5 Va Re 560 Ω Vp1 68 Ω Vcl 8V Vref 1 µF R1 12 kΩ 100 V BAV21 VIDEO BOOSTER amplification ≈ 13 Rc 22 kΩ D1 Vp2 TDA4887PS 1 µF Vsig Vsig 1 µF R2 150 kΩ 1 MΩ 68 Ω Vcl D1 cathode BAW62 Vb TDA4887PS amplification ≈ − 15 BC546 Vref 1 µF Va1 R1 10 kΩ MHB955 Fig.24 Black level restoration circuits. 2001 Oct 19 47 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier 12.4.3 AVOIDING NEGATIVE INPUT VOLTAGES AT BLANKING TDA4887PS combination with an external resistor protects the pins from negative voltages (see Fig.25). AND CLAMPING INPUT PINS Negative voltages on any input pin causes ESD protection diodes and other internal junctions will become open-circuit resulting in substrate current injection. Substrate currents can generate parasitic effects that are not completely predictable. Signal inputs (pins 6 and 10) are neighbouring clamping inputs (pins 5 and 11) and can therefore suffer from larger leakage currents during negative clamping pulse glitches. An internal circuit in At pin voltages near to ground level, the voltage difference between the internal reference voltage Vref and the base voltage of TR1, which is 2VBE higher than the pin voltage, generates a current through R1 which is amplified to the output by transistor TR1. The voltage drop at the external resistor Rext stabilizes voltage Vpin near ground. The recommended value for Rext is 1 kΩ. handbook, full pagewidth Vref = 2VBE R1 6 kΩ VP 8V TR1 TDA4887PS TR3 ground TR2 Rext clamping pulse Vi Vpin junctions from pin to substrate MHB956 Fig.25 Protection circuit at pins CLI and HFB. 2001 Oct 19 48 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 SYMBOL AND DESCRIPTION FBL; fast blanking input for OSD insertion CHARACTERISTIC WAVEFORM open-circuit base EQUIVALENT CIRCUIT 50 µA 5V 50 µA 50 µA 50 µA VP signal blanking 0V MHA653 OSD1 blanking OSD2 blanking OSD3 blanking 1 1 kΩ MHA928 2 OSD1; OSD input channel 1 open-circuit base 5V VP 50 µA VP 0V signal blanking MHA653 1 kΩ 2 disable OSD 49 1 kΩ FBL 3 OSD2; OSD input channel 2 open-circuit base 5V Philips Semiconductors PIN 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 13 INTERNAL CIRCUITRY MHB197 VP 50 µA VP 0V signal blanking MHA653 3 1 kΩ disable OSD 1 kΩ FBL MHB198 Product specification TDA4887PS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... OSD3; OSD input channel 3 CHARACTERISTIC WAVEFORM open-circuit base EQUIVALENT CIRCUIT 5V VP 50 µA VP 0V signal blanking MHA653 1 kΩ 4 disable OSD 1 kΩ FBL 5 CLI; vertical blanking input, input clamping input VCLI > 0.2 V: open-circuit base VCLI ≤ 0.2 V: source current rising with decreasing voltage 5V 2.5 V 0V 2VBE VP 6 kΩ 10 kΩ MHB199 26 µA MHA651 3 V + VBE 50 VP Philips Semiconductors 4 SYMBOL AND DESCRIPTION 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN 1 kΩ 5 10 kΩ power on/down MHA619 Product specification TDA4887PS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VI1; signal input channel 1 CHARACTERISTIC outside clamping pulse: open-circuit base with base current compensation II1 during clamping: −420 to +420 µA WAVEFORM EQUIVALENT CIRCUIT 4.7 V dbook, halfpage black shoulder MIRROR 1:1 VP VP video signal sync 4V 3.7 V 6 input clamping (pin 5) MHA652 700 Ω 1.8 V + VBE signal 420 µA 240 µA 220 µA 0 µA MHB926 7 51 VP; supply voltage IP = 25 mA (typical) 7 Philips Semiconductors 6 SYMBOL AND DESCRIPTION 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN MHA621 Product specification TDA4887PS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VI2; signal input channel 2 CHARACTERISTIC outside clamping pulse: open-circuit base with base current compensation II2 during clamping: −420 to +420 µA WAVEFORM EQUIVALENT CIRCUIT 4.7 V book, halfpage black shoulder MIRROR 1:1 VP VP video signal sync 4V 3.7 V 8 input clamping (pin 5) MHA652 700 Ω 1.8 V + VBE signal 420 µA 240 µA 220 µA 0 µA MHB927 9 GND; ground 52 9 Philips Semiconductors 8 SYMBOL AND DESCRIPTION 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN MHA623 10 VI3; signal input channel 3 outside clamping pulse: open-circuit base with base current compensation II3 during clamping: −420 to +420 µA 4.7 V book, halfpage black shoulder MIRROR 1:1 VP VP video signal sync 4V 3.7 V 10 input clamping (pin 5) MHA652 700 Ω 420 µA 240 µA 220 µA 0 µA MHB923 Product specification signal TDA4887PS 1.8 V + VBE This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... HFB; output clamping input, blanking input CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT VHFB > 0.2 V: open-circuit base VHFB ≤ 0.2 V: source current rising with decreasing voltage 5V 2VBE VP 0V 27 µA 27 µA clamping blanking 12 kΩ 10 kΩ 6 kΩ MHA649 VP 1.7 V 3 V + VBE 10 kΩ 1 kΩ 11 power on/down 12 SDA; I2C-bus serial data input/output no acknowledge: open-circuit base 53 during acknowledge: ISDA > 3 mA 5V halfpage 6 µA 70 µA 19 µA 0V MHA647 10 kΩ 2.46 V + VBE 12 MHB924 acknowledge 13 SCL; I2C-bus clock input open-circuit base 5V alfpage MHA625 Philips Semiconductors 11 SYMBOL AND DESCRIPTION 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN 19 µA 0V 1 kΩ 2.46 V + VBE MHB925 Product specification 13 TDA4887PS MHA648 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 15 CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT GNDX; ground signal channels 1, 2 and 3 VP3; supply voltage channel 3 14 MHB205 IP3 = 20 mA (typical) 15 MHB206 16 reference black level VO3; signal output channel 3 voltage 0.1 to 2.8 V MHA655 VP brightness 2 kΩ VP 54 reference black level during output clamping 16 control bit PEDST = 0 60 fF 1 kΩ Philips Semiconductors 14 SYMBOL AND DESCRIPTION 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN 8 kΩ 75 Ω 1.5 kΩ pedestal black level voltage 0.1 to 2.8 V MHA656 1 kΩ 3.5 pF brightness 10 µA pedestal black level during output clamping MHB957 control bit PEDST = 1 Product specification TDA4887PS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... CHARACTERISTIC FB/R3; feedback open-circuit base input/ reference voltage output channel 3 WAVEFORM age EQUIVALENT CIRCUIT feedback reference 5.75 to 2.55 V VP 27 I PEDST = 0 2I 100 Ω 17 PEDST = 1 5.75 to 2.55 V MHB931 1 kΩ control bit FPOL = 0 IFB/R3: −200 to +200 µA VFB/R3: 5.75 to 2.55 V 1.7 kΩ control bit FPOL = 1 I 10 µA 10 µA Philips Semiconductors 17 SYMBOL AND DESCRIPTION 55 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN 15 kΩ Vs1 15 kΩ Vs2 1 kΩ MHB928 5.75 to 2.55 V DC coupling (control bit FPOL = 0): Vs1 = 0 V; Vs2 = 1 V; I = 0 AC coupling (control bit FPOL = 1): Vs1 = 1 V; Vs2 = 0 V; I = 7.5 µA 18 I18 = 20 mA (typical) 18 Product specification MHB218 TDA4887PS VP2; supply voltage channel 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... CHARACTERISTIC WAVEFORM VO2; signal reference black level output channel 2 voltage 0.1 to 2.8 V EQUIVALENT CIRCUIT MHA655 VP brightness 2 kΩ VP reference black level during output clamping 19 control bit PEDST = 0 60 fF 1 kΩ 8 kΩ 75 Ω 1.5 kΩ pedestal black level voltage 0.1 to 2.8 V MHA656 1 kΩ 3.5 pF brightness 10 µA pedestal black level during output clamping MHB958 Philips Semiconductors 19 SYMBOL AND DESCRIPTION 56 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN control bit PEDST = 1 Product specification TDA4887PS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... CHARACTERISTIC FB/R2; feedback open-circuit base input/reference voltage output channel 2 WAVEFORM age EQUIVALENT CIRCUIT feedback reference 5.75 to 2.55 V VP 27 I PEDST = 0 2I 100 Ω 20 PEDST = 1 5.75 to 2.55 V MHB931 1 kΩ control bit FPOL = 0 IFB/R2: −200 to +200 µA VFB/R2: 5.75 to 2.55 V 1.7 kΩ control bit FPOL = 1 I 10 µA 10 µA Philips Semiconductors 20 SYMBOL AND DESCRIPTION 57 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN 15 kΩ Vs1 15 kΩ Vs2 1 kΩ MHB929 5.75 to 2.55 V DC coupling (control bit FPOL = 0): Vs1 = 0; Vs2 = 1 V; I = 0 AC coupling (control bit FPOL = 1): Vs1 = 1 V; Vs2 = 0; I = 7.5 µA 21 IP1 = 20 mA (typical) 21 Product specification MHB211 TDA4887PS VP1; supply voltage channel 1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... CHARACTERISTIC WAVEFORM VO1; signal reference black level output channel 1 voltage 0.1 to 2.8 V EQUIVALENT CIRCUIT MHA655 VP brightness 2 kΩ VP reference black level during output clamping 22 control bit PEDST = 0 60 fF 1 kΩ 8 kΩ 75 Ω 1.5 kΩ pedestal black level voltage 0.1 to 2.8 V MHA656 1 kΩ 3.5 pF brightness 10 µA pedestal black level during output clamping MHB959 Philips Semiconductors 22 SYMBOL AND DESCRIPTION 58 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN control bit PEDST = 1 Product specification TDA4887PS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... CHARACTERISTIC FB/R1; feedback open-circuit base input/reference voltage output channel 1 WAVEFORM age EQUIVALENT CIRCUIT feedback reference 5.75 to 2.55 V VP 27 I PEDST = 0 2I 100 Ω 23 PEDST = 1 5.75 to 2.55 V MHB931 1 kΩ control bit FPOL = 0 IFB/R1: −200 to +200 µA VFB/R1: 5.75 to 2.55 V 1.7 kΩ control bit FPOL = 1 I 10 µA 10 µA Philips Semiconductors 23 SYMBOL AND DESCRIPTION 59 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN 15 kΩ Vs1 15 kΩ Vs2 1 kΩ 5.75 to 2.55 V MHB930 DC coupling (control bit FPOL = 0): Vs1 = 0; Vs2 = 1 V; I = 0 AC coupling (control bit FPOL = 1): Vs1 = 1 V; Vs2 = 0; I = 7.5 µA Product specification TDA4887PS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... LIM; subcontrast adjustment, contrast modulation, beam current limiting input CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT open-circuit voltage VLIM = 5 V VLIM < 4.4 V: open-circuit base VP 24 21 µA 1 kΩ 5.0 V 10 kΩ MHB214 Philips Semiconductors 24 SYMBOL AND DESCRIPTION 60 160 MHz bus-controlled monitor video preamplifier 2001 Oct 19 PIN Product specification TDA4887PS Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 14 PACKAGE OUTLINE SDIP24: plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 ME seating plane D A2 A A1 L c e Z b1 (e 1) w M MH b 13 24 pin 1 index E 1 12 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.8 1.3 0.8 0.53 0.40 0.32 0.23 22.3 21.4 9.1 8.7 1.778 10.16 3.2 2.8 10.7 10.2 12.2 10.5 0.18 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT234-1 2001 Oct 19 EUROPEAN PROJECTION 61 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier The total contact time of successive solder waves must not exceed 5 seconds. 15 SOLDERING 15.1 Introduction to soldering through-hole mount packages The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 15.2 15.3 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. 15.4 TDA4887PS Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 2001 Oct 19 62 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 16 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective specification Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary specification Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product specification Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 17 DEFINITIONS 18 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2001 Oct 19 63 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier TDA4887PS 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Oct 19 64 Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier NOTES 2001 Oct 19 65 TDA4887PS Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier NOTES 2001 Oct 19 66 TDA4887PS Philips Semiconductors Product specification 160 MHz bus-controlled monitor video preamplifier NOTES 2001 Oct 19 67 TDA4887PS Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA73 © Koninklijke Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/01/pp68 Date of release: 2001 Oct 19 Document order number: 9397 750 08393