PHILIPS PSMN130-200D

DISCRETE SEMICONDUCTORS
DATA SHEET
PSMN130-200D
N-channel TrenchMOS(TM)
transistor
Product specification
August 1999
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
FEATURES
SYMBOL
PSMN130-200D
QUICK REFERENCE DATA
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
d
VDSS = 200 V
ID = 20 A
g
RDS(ON) ≤ 130 mΩ
s
GENERAL DESCRIPTION
SiliconMAX products use the latest
Philips Trench technology to
achieve the lowest possible
on-state resistance in each
package at each voltage rating.
Applications:• d.c. to d.c. converters
• switched mode power supplies
PINNING
PIN
SOT428 (DPAK)
DESCRIPTION
1
gate
2
drain1
3
source
tab
2
tab
drain
1
3
The PSMN130-200D is supplied in
the SOT428 (Dpak) surface
mounting package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
MIN.
MAX.
UNIT
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
- 55
200
200
± 20
20
14
80
150
175
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
1 It is not possible to make connection to pin 2 of the SOT428 package.
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS
Non-repetitive avalanche
energy
IAS
Non-repetitive avalanche
current
CONDITIONS
MIN.
MAX.
UNIT
-
252
mJ
-
20
A
Unclamped inductive load, IAS = 19 A;
tp = 100 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer
to fig;15
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
SOT428 package, pcb mounted, minimum
footprint
TYP. MAX. UNIT
-
-
1
K/W
-
50
-
K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
RDS(ON)
IGSS
IDSS
Drain-source on-state
VGS = 10 V; ID = 25 A
resistance
Gate source leakage current VGS = ±10 V; VDS = 0 V
Zero gate voltage drain
VDS = 150 V; VGS = 0 V;
current
Tj = 175˚C
Tj = 175˚C
MIN.
TYP. MAX. UNIT
200
178
2
1
-
3
120
0.02
0.05
-
4
6
130
377
100
10
500
V
V
V
V
V
mΩ
mΩ
nA
µA
µA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 20 A; VDD = 160 V; VGS = 10 V
-
65
10
22
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 100 V; RD = 4.7 Ω;
VGS = 10 V; RG = 5.6 Ω
Resistive load
-
15
46
50
38
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from source lead to source
bond pad
-
3.5
7.5
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
2470
207
90
-
pF
pF
pF
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
IF = 25 A; VGS = 0 V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IS
ISM
August 1999
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 25 V
4
TYP. MAX. UNIT
-
-
20
A
-
-
80
A
-
0.95
1.2
V
-
124
0.74
-
ns
µC
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
Normalised Power Derating, PD (%)
Transient thermal impedance, Zth j-mb (K/W)
10
100
90
80
1
D = 0.5
70
0.2
60
0.1
0.05
0.1
50
40
P
D
0.02
30
D = tp/T
tp
0.01
single pulse
20
T
10
0.001
1E-06
0
0
25
50
75
100
125
150
Mounting Base temperature, Tmb (C)
175
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A)
20
Normalised Current Derating, ID (%)
Tj = 25 C
100
90
6V
VGS = 10V
18
5.4 V
8V
16
80
14
70
60
12
50
10
40
8
30
6
20
5.2 V
5V
4.8 V
4
10
4.6 V
2
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
4.4 V
0
175
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); VGS ≥ 10 V
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Peak Pulsed Drain Current, IDM (A)
100
0.3
RDS(on) = VDS/ ID
Drain-Source On Resistance, RDS(on) (Ohms)
4.4 V 4.6 V 4.8 V
tp = 10 us
Tj = 25 C
5V
0.25
100 us
10
0.2
5.2 V
D.C.
1 ms
0.15
5.4 V
10 ms
1
100 ms
6V
0.1
8V
0.05
0.1
VGS = 10V
0
1
10
100
Drain-Source Voltage, VDS (V)
1000
0
4
6
8
10
12
Drain Current, ID (A)
14
16
18
20
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
August 1999
2
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
Drain current, ID (A)
4.5
20
VDS > ID X RDS(ON)
18
Threshold Voltage, VGS(TO) (V)
4
16
3.5
14
3
12
typical
2.5
175 C
10
maximum
minimum
2
8
Tj = 25 C
1.5
6
4
1
2
0.5
0
0
0
1
2
3
4
5
6
-60
-40
-20
Gate-source voltage, VGS (V)
40
60
80
100 120 140 160 180
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
VDS > ID X RDS(ON)
20
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
30
0
1.0E-01
Drain current, ID (A)
Tj = 25 C
25
1.0E-02
20
175 C
minimum
1.0E-03
15
typical
1.0E-04
10
maximum
1.0E-05
5
1.0E-06
0
0
2
4
6
8
10
12
14
Drain current, ID (A)
16
18
0
20
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
0.5
1
1.5
2
2.5
3
3.5
Gate-source voltage, VGS (V)
4
4.5
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
10000
Capacitances, Ciss, Coss, Crss (pF)
Ciss
1000
Coss
100
Crss
10
-60
-40
-20
0
20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
0.1
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
August 1999
1
10
Drain-Source Voltage, VDS (V)
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
Maximum Avalanche Current, IAS (A)
100
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID = 20A
Tj = 25 C
10
25 C
VDD = 40 V
VDD = 160 V
0
5
10
15
20 25 30 35 40
Gate charge, QG (nC)
45
50
1
55
0.1
0.001
60
Tj prior to avalanche = 150 C
0.01
0.1
1
10
Avalanche time, tAV (ms)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Source-Drain Diode Current, IF (A)
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
VGS = 0 V
175 C
0
0.1
0.2
0.3
0.4
0.5
0.6
Tj = 25 C
0.7
0.8
0.9
1
1.1
1.2
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
E
A2
A
A1
b2
D1
mounting
base
E1
D
HE
L2
2
L1
L
1
3
b1
w M A
b
c
e
e1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max. A1(1)
mm
2.38
2.22
0.65
0.45
A2
b
b1
max.
b2
c
0.89
0.71
0.89
0.71
1.1
0.9
5.36
5.26
0.4
0.2
D1
E
D
max. max. max.
E1
min.
6.22
5.98
4.0
4.81
4.45
6.73
6.47
e
e1
2.285 4.57
HE
max.
L
L1
min.
L2
w
y
max.
10.4
9.6
2.95
2.55
0.5
0.7
0.5
0.2
0.2
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
SOT428
EUROPEAN
PROJECTION
ISSUE DATE
98-04-07
Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
8
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
1.5
2.5
4.57
Fig.17. SOT428 : soldering pattern for surface mounting.
August 1999
9
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
10
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
NOTES
August 1999
11
Rev 1.000
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SCA 69
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
603502/300/03/pp12
Date of release: August
1999
Document order number:
9397 750 09675